Prior art

To identify the most relevant prior art for US Patent 9275982, I will examine the "Citations" section of the patent as provided by the Google Patents document, as these are the references deemed relevant by the patent examiner during prosecution. The current date is April 26, 2026.

Here are the citations listed in US Patent 9275982, along with their details and potential relevance to the claims:

Prior Art Analysis for US Patent 9275992

1. US20030080408A1 (Farnworth Warren M.)

• Full Citation: US20030080408A1, "Method for fabricating semiconductor components and interconnects with contacts on opposing sides"
• Publication Date: 2003-05-01
• Filing Date: 1997-12-18
• Brief Description: This publication describes methods for fabricating semiconductor components with interconnects and contacts on opposing sides. It focuses on creating through-wafer interconnects, often involving etching holes and filling them with conductive material, and forming pads on either side of the wafer.
• Potential Anticipation (35 U.S.C. § 102):
  • Claim 1: This reference appears to anticipate several elements of Claim 1, including "providing a first semiconductor device having a first side and a second side opposite to the first side," "forming a via-hole through the first semiconductor device," and the concept of "forming a via structure in the via-hole." The concept of forming contacts/pads on opposing sides for through-wafer interconnects is central to Farnworth. Depending on the specific details of pad and via formation and sequencing, it could anticipate the steps of "forming a first pad covering the first opening" and "forming a via structure in the via-hole subsequent to forming the first pad" if similar processes are disclosed. The broader concept of vertically integrating semiconductor devices with such through-substrate vias is also generally known in the art, potentially anticipating "substantially vertically integrating the first semiconductor device with a second semiconductor device".

2. JP2004128177A (Hitachi Cable Ltd)

• Full Citation: JP2004128177A, "Method for manufacturing wiring board, wiring board, and semiconductor device"
• Publication Date: 2004-04-22
• Filing Date: 2002-10-02
• Brief Description: This patent describes a method for manufacturing a wiring board and semiconductor device, likely involving interconnections within the structure.
• Potential Anticipation (35 U.S.C. § 102): Without the full text, a precise assessment is difficult. However, given its title and classification, it likely pertains to methods of forming conductive paths and connections within semiconductor packages. It could potentially anticipate the steps related to forming via-holes, pads, and via structures in Claim 1, depending on the specific techniques and sequences disclosed.

3. US20040080023A1 (Alps Electric Co., Ltd.)

• Full Citation: US20040080023A1, "Thin-film capacitor element with reduced inductance component"
• Publication Date: 2004-04-29
• Filing Date: 2002-10-28
• Brief Description: This publication relates to thin-film capacitor elements and reducing inductance. While it's a semiconductor device, its focus on capacitors might make it less directly relevant to the specific method of forming via-holes and pads for general interconnection as claimed in US9275982, unless the interconnections described are directly analogous to those in the present patent.
• Potential Anticipation (35 U.S.C. § 102): Unlikely to anticipate the core method steps of Claim 1 directly, as its primary focus is on capacitor structure and inductance reduction, not generic through-hole interconnection formation. However, specific sub-elements or materials used in forming parts of the capacitor might overlap with general semiconductor processing steps.

4. US20060186441A1 (Semiconductor Energy Laboratory Co., Ltd.)

• Full Citation: US20060186441A1, "Light-emitting device, liquid-crystal display device and method for manufacturing same"
• Publication Date: 2006-08-24
• Filing Date: 2002-03-26
• Brief Description: This patent describes light-emitting and liquid-crystal display devices and their manufacturing methods. The focus here is on display technologies.
• Potential Anticipation (35 U.S.C. § 102): Similar to US20040080023A1, its primary focus on display devices makes it less likely to directly anticipate the generic method of forming through-substrate interconnections for package structures as defined in Claim 1 of US9275982.

5. US20060226415A1 (Nishijima Masaaki)

• Full Citation: US20060226415A1, "Semiconductor integrated circuit device and vehicle-mounted radar system using the same"
• Publication Date: 2006-10-12
• Filing Date: 2004-11-22
• Brief Description: This publication discusses semiconductor integrated circuit devices, particularly in the context of vehicle-mounted radar systems.
• Potential Anticipation (35 U.S.C. § 102): This reference might be relevant if it discloses specific interconnection structures or fabrication methods within the integrated circuit device for the radar system. Without further detail, it's hard to ascertain direct anticipation of Claim 1's method steps, but the broad category of "semiconductor integrated circuit device" could potentially encompass various interconnection techniques.

6. US20070027699A1 (Koninklijke Philips Electronics N.V.)

• Full Citation: US20070027699A1, "Method of manufacturing recyclable electronic products and electronic products obtained by the method"
• Publication Date: 2007-02-01
• Filing Date: 2003-05-16
• Brief Description: This patent focuses on manufacturing recyclable electronic products.
• Potential Anticipation (35 U.S.C. § 102): This reference seems less likely to directly anticipate the specific method of forming an interconnection structure of a package structure outlined in Claim 1, as its emphasis is on recyclability rather than the fundamental physical construction of interconnections.

7. US20070194436A1 (Advanced Semiconductor Engineering, Inc.)

• Full Citation: US20070194436A1, "Ball grid array package"
• Publication Date: 2007-08-23
• Filing Date: 2006-02-17
• Brief Description: This publication describes a ball grid array (BGA) package, which is a common type of semiconductor package.
• Potential Anticipation (35 U.S.C. § 102): This reference is highly relevant to "package structures" and likely discusses various interconnection methods within such packages. It could potentially anticipate elements of Claim 1 related to vertically integrating semiconductor devices and the overall package structure, depending on whether it details the specific sequence of forming via-holes, pads, and via structures as claimed. Many BGA packages utilize through-substrate vias or similar vertical interconnections.

8. US7312400B2 (Fujikura Ltd.)

• Full Citation: US7312400B2, "Multilayer wiring board, base for multilayer wiring board, printed wiring board and its manufacturing method"
• Publication Date: 2007-12-25
• Filing Date: 2002-02-22
• Brief Description: This patent concerns multilayer wiring boards and their manufacturing methods.
• Potential Anticipation (35 U.S.C. § 102): Multilayer wiring boards often incorporate vias and pads for interconnections between layers. Therefore, this reference could potentially anticipate some steps of Claim 1 related to forming conductive paths and pads, especially if it describes methods for forming through-holes and filling them with conductive material in a sequential manner.

9. US7528475B2 (Alps Electric Co., Ltd.)

• Full Citation: US7528475B2, "Thin-film capacitor element with reduced inductance component"
• Publication Date: 2009-05-05
• Filing Date: 2003-07-18
• Brief Description: This patent is a granted version of US20040080023A1, focusing on thin-film capacitor elements.
• Potential Anticipation (35 U.S.C. § 102): As with its application counterpart, this reference is less likely to directly anticipate the general method of forming interconnection structures for package structures.

Key Observation on Anticipation (35 U.S.C. § 102):
For a prior art reference to anticipate a claim under 35 U.S.C. § 102, it must disclose every element of the claim, arranged as claimed, either explicitly or inherently. Given the commonality of through-silicon vias (TSVs) and stacked packaging in semiconductor technology, references like US20030080408A1 and US20070194436A1 are highly pertinent. The distinguishing feature highlighted in US9275982's specification is often the sequence of forming the first pad before the via structure via electroplating without a vacuum seed layer, which potentially reduces cost. Any prior art disclosing this specific sequence, particularly the "forming a via structure in the via-hole subsequent to forming the first pad" and the use of the first pad as a seed layer for electroplating without a vacuum step, would be most impactful for anticipation. [cite: an electroplating process is performed using the first pad 130 as a seed layer to deposit a via structure 132 which fills the via-hole 126 ., the method for forming the interconnection structure of the invention forms the via structure using electroplating with the first pad as a seed layer, and no vacuum environment is required for forming the interconnect structure. Therefore, the method of the invention can produce semiconductor devices at a lower cost.]