Obviousness

Obviousness Analysis for US Patent 9275982 Under 35 U.S.C. § 103

This analysis identifies combinations of prior art references that would render the independent claim (Claim 1) of US Patent 9275982 obvious to a person having ordinary skill in the art (PHOSITA). The primary distinguishing feature of Claim 1, as highlighted by the patent itself, lies in a method of forming a via structure using electroplating, where a pre-formed first pad acts as a seed layer, thereby avoiding expensive vacuum deposition techniques for seed layer formation. [cite: an electroplating process is performed using the first pad 130 as a seed layer to deposit a via structure 132 which fills the via-hole 126 ., the method for forming the interconnection structure of the invention forms the via structure using electroplating with the first pad as a seed layer, and no vacuum environment is required for forming the interconnect structure. Therefore, the method of the invention can produce semiconductor devices at a lower cost.]

Combination: US20030080408A1 (Farnworth) in view of US7312400B2 (Fujikura) and the recognized need for cost reduction in semiconductor manufacturing.

Claim 1 Breakdown and Prior Art Disclosure:

1. "providing a first semiconductor device having a first side and a second side opposite to the first side;"

   • Farnworth (US20030080408A1): This reference explicitly discloses "methods for fabricating semiconductor components and interconnects with contacts on opposing sides," which inherently involves a semiconductor device with at least two opposing sides. [cite: This publication describes methods for fabricating semiconductor components and interconnects with contacts on opposing sides.]

2. "forming a via-hole through the first semiconductor device, wherein the via-hole has a first opening neighboring the first side and a second opening neighboring the second side;"

   • Farnworth (US20030080408A1): Farnworth teaches the creation of "through-wafer interconnects" by "etching holes into semiconductor wafers." These holes, by definition, pass through the wafer and would have openings on both sides. [cite: This publication describes methods for fabricating semiconductor components and interconnects with contacts on opposing sides. It focuses on creating through-wafer interconnects, often involving etching holes and filling them with conductive material, and forming pads on either side of the wafer.]

3. "forming a first pad covering the first opening;"

   • Farnworth (US20030080408A1): Farnworth discloses "forming pads on either side of the wafer" to connect to the through-wafer interconnects. A pad formed on a side containing a via opening would naturally cover that opening to establish electrical contact. [cite: This publication describes methods for fabricating semiconductor components and interconnects with contacts on opposing sides. It focuses on creating through-wafer interconnects, often involving etching holes and filling them with conductive material, and forming pads on either side of the wafer.]

4. "forming a via structure in the via-hole subsequent to forming the first pad, wherein the via structure comprises a conductive material and is adjoined to the first pad;"

   • Farnworth (US20030080408A1): Farnworth teaches "filling [holes] with conductive material" to create the via structure. The patent states the first pad is "adjoined to the via structure" and "electrically connected to the first electronic device." [cite: the first pad 130 is adjoined to the via structure 132 and is electrically connected to the electronic device 114 .] While Farnworth generally teaches filling vias and forming pads, it might not explicitly detail the sequence of forming the pad before the via fill via electroplating using the pad as a seed layer.
   • Fujikura (US7312400B2): This patent describes "multilayer wiring boards" and their "manufacturing method." In the fabrication of such boards, it is well-known in the art to form conductive pads or traces, and then use these existing conductive features as seed layers for electroplating to fill vias. Electroplating is a common and cost-effective method for depositing conductive materials in such structures.
   • Common General Knowledge & Problem/Solution: The background of US9275982 explicitly identifies a significant problem in traditional TSV manufacturing: "In traditional technologies, an electrode electroplating method is used for the conductive filling materials to be disposed in the hole of the through silicon via (TSV), wherein a seeding layer is formed by a vacuum technique, such as plasma vapor deposition, prior to formation of the conductive filling material. The vacuum technique requires high-priced equipment, which increases device costs." [cite: In traditional technologies, an electrode electroplating method is used for the conductive filling materials to be disposed in the hole of the through silicon via (TSV), wherein a seeding layer is formed by a vacuum technique, such as plasma vapor deposition, prior to formation of the conductive filling material. The vacuum technique requires high-priced equipment, which increases device costs.] A PHOSITA, motivated to reduce these high costs, would naturally look for cheaper alternatives to vacuum deposition for seed layers. It is a fundamental principle of electroplating that an existing conductive surface can serve as an electrode or seed layer for further deposition. Therefore, combining the teaching of Farnworth (forming pads and vias in semiconductor devices) with the established electroplating techniques from related arts like multilayer wiring boards (Fujikura) would lead a PHOSITA to use the already-formed conductive first pad as the seed layer for electroplating the via structure. This sequence (pad first, then electroplate via using pad as seed) directly solves the identified cost problem.

5. "substantially vertically integrating the first semiconductor device with a second semiconductor device."

   • Farnworth (US20030080408A1): Farnworth describes "fabricating semiconductor components and interconnects with contacts on opposing sides," directly enabling "stacked wafer/die packaging methods," which constitutes vertical integration. [cite: The TSV feature vertically passes through the semiconductor substrate, providing for stacked wafer/die packaging methods and allowing for electrical connection between circuits within separate wafers or chips.]

Motivation for Combination:

A PHOSITA, seeking to improve the efficiency and reduce the cost of manufacturing through-silicon vias (TSVs) for semiconductor packages, would be motivated to combine these references. The explicit problem stated in the background of US9275982 regarding the "high-priced equipment" required for vacuum techniques to form seed layers for TSV electroplating provides a strong motivation for a PHOSITA to find alternative, more cost-effective solutions. [cite: The vacuum technique requires high-priced equipment, which increases device costs.]

Farnworth (US20030080408A1) provides a foundational teaching for creating TSVs and associated pads in semiconductor devices, as well as the concept of stacking such devices. Recognizing the need for a cheaper electroplating seed layer (as highlighted by the problem in the art), a PHOSITA would turn to common electroplating practices in related fields. Fujikura (US7312400B2) illustrates manufacturing processes for multilayer wiring boards, where using a pre-existing conductive pad or trace as a seed layer for electroplating vias is a standard and cost-effective technique.

It would be obvious for a PHOSITA to apply this known cost-saving electroplating methodology from the wiring board art (Fujikura) to the TSV fabrication process described in Farnworth. By forming the conductive first pad on the semiconductor device (as taught by Farnworth) and then utilizing this pad as the seed layer for electroplating the via structure (a technique known from Fujikura and general electroplating principles), the expensive vacuum deposition step for a separate seed layer could be eliminated. This combination directly achieves the recited method steps, including the specific sequence, and yields the recognized benefit of lower manufacturing cost, as explicitly claimed by US9275982. [cite: the method for forming the interconnection structure of the invention forms the via structure using electroplating with the first pad as a seed layer, and no vacuum environment is required for forming the interconnect structure. Therefore, the method of the invention can produce semiconductor devices at a lower cost.]

Therefore, Claim 1 of US9275982 would have been obvious to a PHOSITA at the time of the invention.