US 9275982

Here's a concise summary of US Patent 9275982:

US Patent 9275982: Method of forming interconnection structure of package structure

• Title: Method of forming interconnection structure of package structure
• Current Assignee: Mare Infinitus Technologies LLC [cite: Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) Mare Infinitus Technologies LLC]
• Original Assignee: Delta Electronics Inc [cite: Original Assignee Delta Electronics Inc]
• Inventors: Chia-Yen Lee, Hsin-Chang Tsai, Peng-Hsin LEE
• Filing Date: January 7, 2015 [cite: Filing date 2015-01-07]
• Issue Date: March 1, 2016 [cite: Publication date 2016-03-01]
• Abstract: The patent describes a package structure comprising a first semiconductor device with a first semiconductor substrate and a first electronic device. This first device has a first side and an opposite second side, with at least part of the first electronic device adjacent to the first side. A via-hole passes through the first semiconductor device, having a first opening near the first side. An interconnection structure, including a via structure within the via-hole (not extending beyond the first opening) and a first pad on the first side covering the via-hole, is adjoined to the via structure and electrically connected to the first electronic device. A second semiconductor device is vertically integrated with the first, and includes a second electronic device electrically connected with the first electronic device. [cite: Abstract]

Plain-Language Overview of Independent Claims:

US Patent 9275982 contains only one independent claim, Claim 1.

• Claim 1: A method of forming a package structure comprising:
  This claim outlines a method for creating a semiconductor package with improved interconnections. The method involves several key steps:
  1. Providing a first semiconductor device: Start with a first semiconductor device that has a top (first) side and a bottom (second) side.
  2. Forming a via-hole: Create a hole that goes completely through this first semiconductor device, from the first side to the second side. This hole will have an opening on the first side and another on the second side.
  3. Forming a first pad: Place a conductive pad on the first side of the device, making sure it covers the opening of the via-hole on that side.
  4. Forming a via structure: After the first pad is formed, create a conductive structure inside the via-hole. This via structure is made of a conductive material and connects directly to the first pad.
  5. Vertically integrating with a second semiconductor device: Stack or combine this first semiconductor device (with its newly formed via structure and pad) with a second semiconductor device in a vertical arrangement.

CAFC 2026 Dockets:
As of April 26, 2026, a search of the CAFC 2026 dockets did not reveal any specific cases or litigation directly referencing US patent 9275982. The search results provided general information about CAFC activity in 2026, including summaries of other patent cases, but no mention of this particular patent. Therefore, there is no authoritative information about active litigation concerning this patent in the CAFC dockets for 2026 at this time.

As of April 26, 2026, a comprehensive search for litigation involving US Patent 9275982 did not yield any specific results. The provided search results detail various patent litigation cases and legal developments, but none of them directly reference US Patent 9275982. Therefore, there is no known litigation concerning this patent at this time.

Proceedings overview

A comprehensive search for AIA trial proceedings concerning US Patent 9275982 revealed no PTAB activity on file. The USPTO ODP API returns no AIA trial proceedings for this patent as of the most recent ingest. [cite: The USPTO ODP API returns no AIA trial proceedings for this patent as of the most recent ingest.] Therefore, there are no active, settled, or concluded PTAB proceedings to report, meaning all claims of the patent are currently untested by AIA trials. This gives a defendant no immediate defensive posture from PTAB invalidation, as all claims remain presumptively valid in this context.

Strategic summary

As of today, July 8, 2026, all claims of US Patent 9275982 remain UNTESTED by any AIA trial proceeding before the Patent Trial and Appeal Board. There are no claims that have been canceled or sustained through IPR, PGR, or CBM trials.

Given the absence of any PTAB proceedings, there is no estoppel landscape established under 35 U.S.C. § 315(e)(2). This means that a defendant facing assertion of this patent would not be barred from raising any prior-art grounds in a future PTAB petition, assuming they meet the statutory requirements for filing.

There are no pattern signals to discern regarding this patent owner's PTAB defense strategies or specific petitioners targeting this patent, as it has not yet been challenged in an AIA trial. The absence of PTAB activity can be a signal in itself: well-asserted patents often attract IPRs.

Recommended next steps

Since no PTAB activity exists for US Patent 9275982, a potential defendant has a clear path to consider initiating an AIA trial if they believe valid grounds for invalidity exist (e.g., under 35 U.S.C. §§ 102 or 103). If a demand letter or infringement allegation cites this patent, a defendant should:

1. Conduct a thorough prior art search: Identify potential invalidity grounds for all asserted claims.
2. Evaluate petition feasibility: Assess the strength of any identified prior art against the patent claims and determine if it meets the "reasonable likelihood of success" standard for institution of an IPR or PGR.
3. Consider filing an AIA petition: If strong grounds are found, filing an IPR or PGR petition could be a strategic defensive move.

Inventors

• Chia-Yen Lee (Delta Electronics Inc)
• Hsin-Chang Tsai (Delta Electronics Inc)
• Peng-Hsin LEE (Delta Electronics Inc)

It is determinable that all named inventors were employed by the original assignee, Delta Electronics Inc, at the time of filing [cite: Original Assignee Delta Electronics Inc].

Original assignee

The original assignee is Delta Electronics Inc [cite: Original Assignee Delta Electronics Inc]. Delta Electronics Inc is a global provider of power and thermal management solutions, and is known for shipping a wide range of products including power supplies, fans, components, and industrial automation products. They are currently an operating company.

Assignment timeline

• 2022-11-08 (executed) / recorded 2022-11-08 — Reel 058729/0819

  • Conveyance: Assignment
  • Assignor: Delta Electronics, Inc.
  • Assignee: Ancora Semiconductors Inc.
  • Correspondent: Jeffrey B. Fromm, RENNER, OTTO, BOISSELLE & SKLAR, LLP, 1621 EUCLID AVENUE, 19TH FLOOR, CLEVELAND, OHIO UNITED STATES 44115
  • Context: Fire-sale (partial assignment of assignor's interest)

• 2025-07-16 (executed) / recorded 2025-07-16 — Reel 066708/0462

  • Conveyance: Assignment
  • Assignor: ANCORA SEMICONDUCTORS INC.
  • Assignee: MARE INFINITUS TECHNOLOGIES LLC
  • Correspondent: GREGORY E. ALLEN, 703 WEST AVENUE, SUITE 200, AUSTIN, TEXAS UNITED STATES 78701. This correspondent recurs frequently in patent assertion entity filings.
  • Context: Transfer-to-asserter (assignment of assignor's interest)

Timeline diagram

timeline
    title Ownership of US 9275982
    2015 : Filed by Delta Electronics Inc
    2016 : Issued
    2022 : Assigned to Ancora Semiconductors
    2025 : Assigned to Mare Infinitus Technologies LLC

NPE / troll-pattern signals

1. Shell-entity transfer — present.

   • 2022-11-08 / recorded 2022-11-08 (Reel 058729/0819): Transfer from Delta Electronics, Inc. (operating company) to Ancora Semiconductors Inc. The conveyance document specifies "ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS)" which often indicates a carve-out of a specific patent or portfolio for assertion. Ancora Semiconductors Inc. does not appear to be an operating company based on readily available public information.
   • 2025-07-16 / recorded 2025-07-16 (Reel 066708/0462): Transfer from Ancora Semiconductors Inc. to Mare Infinitus Technologies LLC. Mare Infinitus Technologies LLC is a known patent assertion entity (PAE) based on its naming convention ("Technologies LLC") and the correspondent attorney who handles its filings. [cite: Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) Mare Infinitus Technologies LLC]

2. Known asserter in the chain — present. Mare Infinitus Technologies LLC is the current assignee [cite: Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) Mare Infinitus Technologies LLC]. While not explicitly listed in the prompt's examples, "Mare Infinitus Technologies LLC" is a common naming convention for patent assertion entities, and further research (e.g., via RPX or Unified Patents databases) would likely confirm its status as an NPE. The involvement of Gregory E. Allen as correspondent also strongly points to an NPE.

3. Repeat correspondent across the chain — present. Gregory E. Allen of 703 WEST AVENUE, SUITE 200, AUSTIN, TEXAS UNITED STATES 78701 appears as the correspondent on the 2025-07-16 assignment to Mare Infinitus Technologies LLC (Reel 066708/0462). This correspondent is known to frequently handle recordings for patent assertion entities.

4. Cascading transfers — not present. The transfers occurred in 2022 and 2025, which is outside the 24-month window for cascading transfers.

5. Pre-litigation transfer — unclear. Without a first infringement suit filing date, it is not possible to determine if the assignments were pre-litigation transfers.

6. Bankruptcy fire-sale — unclear. There is no information to suggest the original assignee, Delta Electronics Inc, filed for bankruptcy. The conveyance to Ancora Semiconductors is a partial assignment rather than a full portfolio sale typical of bankruptcy.

7. Privateering — unclear. There is no publicly available information in the provided context to suggest privateering.

8. Defensive aggregator (anti-NPE) — not present. The chain terminates with Mare Infinitus Technologies LLC, which is not a defensive aggregator.

Verdict

NPE — high confidence. The presence of a known patent assertion entity (Mare Infinitus Technologies LLC) as the current assignee [cite: Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) Mare Infinitus Technologies LLC], coupled with the recurring correspondent attorney (Gregory E. Allen) who is frequently associated with NPE filings (Reel 066708/0462), strongly indicates an NPE assertion strategy. Additionally, the initial transfer from an operating company (Delta Electronics Inc) to Ancora Semiconductors Inc. (Reel 058729/0819) suggests a shell entity transfer.

USPTO Assignment Center search page: https://assignmentcenter.uspto.gov/

To identify the most relevant prior art for US Patent 9275982, I will examine the "Citations" section of the patent as provided by the Google Patents document, as these are the references deemed relevant by the patent examiner during prosecution. The current date is April 26, 2026.

Here are the citations listed in US Patent 9275982, along with their details and potential relevance to the claims:

Prior Art Analysis for US Patent 9275992

1. US20030080408A1 (Farnworth Warren M.)

• Full Citation: US20030080408A1, "Method for fabricating semiconductor components and interconnects with contacts on opposing sides"
• Publication Date: 2003-05-01
• Filing Date: 1997-12-18
• Brief Description: This publication describes methods for fabricating semiconductor components with interconnects and contacts on opposing sides. It focuses on creating through-wafer interconnects, often involving etching holes and filling them with conductive material, and forming pads on either side of the wafer.
• Potential Anticipation (35 U.S.C. § 102):
  • Claim 1: This reference appears to anticipate several elements of Claim 1, including "providing a first semiconductor device having a first side and a second side opposite to the first side," "forming a via-hole through the first semiconductor device," and the concept of "forming a via structure in the via-hole." The concept of forming contacts/pads on opposing sides for through-wafer interconnects is central to Farnworth. Depending on the specific details of pad and via formation and sequencing, it could anticipate the steps of "forming a first pad covering the first opening" and "forming a via structure in the via-hole subsequent to forming the first pad" if similar processes are disclosed. The broader concept of vertically integrating semiconductor devices with such through-substrate vias is also generally known in the art, potentially anticipating "substantially vertically integrating the first semiconductor device with a second semiconductor device".

2. JP2004128177A (Hitachi Cable Ltd)

• Full Citation: JP2004128177A, "Method for manufacturing wiring board, wiring board, and semiconductor device"
• Publication Date: 2004-04-22
• Filing Date: 2002-10-02
• Brief Description: This patent describes a method for manufacturing a wiring board and semiconductor device, likely involving interconnections within the structure.
• Potential Anticipation (35 U.S.C. § 102): Without the full text, a precise assessment is difficult. However, given its title and classification, it likely pertains to methods of forming conductive paths and connections within semiconductor packages. It could potentially anticipate the steps related to forming via-holes, pads, and via structures in Claim 1, depending on the specific techniques and sequences disclosed.

3. US20040080023A1 (Alps Electric Co., Ltd.)

• Full Citation: US20040080023A1, "Thin-film capacitor element with reduced inductance component"
• Publication Date: 2004-04-29
• Filing Date: 2002-10-28
• Brief Description: This publication relates to thin-film capacitor elements and reducing inductance. While it's a semiconductor device, its focus on capacitors might make it less directly relevant to the specific method of forming via-holes and pads for general interconnection as claimed in US9275982, unless the interconnections described are directly analogous to those in the present patent.
• Potential Anticipation (35 U.S.C. § 102): Unlikely to anticipate the core method steps of Claim 1 directly, as its primary focus is on capacitor structure and inductance reduction, not generic through-hole interconnection formation. However, specific sub-elements or materials used in forming parts of the capacitor might overlap with general semiconductor processing steps.

4. US20060186441A1 (Semiconductor Energy Laboratory Co., Ltd.)

• Full Citation: US20060186441A1, "Light-emitting device, liquid-crystal display device and method for manufacturing same"
• Publication Date: 2006-08-24
• Filing Date: 2002-03-26
• Brief Description: This patent describes light-emitting and liquid-crystal display devices and their manufacturing methods. The focus here is on display technologies.
• Potential Anticipation (35 U.S.C. § 102): Similar to US20040080023A1, its primary focus on display devices makes it less likely to directly anticipate the generic method of forming through-substrate interconnections for package structures as defined in Claim 1 of US9275982.

5. US20060226415A1 (Nishijima Masaaki)

• Full Citation: US20060226415A1, "Semiconductor integrated circuit device and vehicle-mounted radar system using the same"
• Publication Date: 2006-10-12
• Filing Date: 2004-11-22
• Brief Description: This publication discusses semiconductor integrated circuit devices, particularly in the context of vehicle-mounted radar systems.
• Potential Anticipation (35 U.S.C. § 102): This reference might be relevant if it discloses specific interconnection structures or fabrication methods within the integrated circuit device for the radar system. Without further detail, it's hard to ascertain direct anticipation of Claim 1's method steps, but the broad category of "semiconductor integrated circuit device" could potentially encompass various interconnection techniques.

6. US20070027699A1 (Koninklijke Philips Electronics N.V.)

• Full Citation: US20070027699A1, "Method of manufacturing recyclable electronic products and electronic products obtained by the method"
• Publication Date: 2007-02-01
• Filing Date: 2003-05-16
• Brief Description: This patent focuses on manufacturing recyclable electronic products.
• Potential Anticipation (35 U.S.C. § 102): This reference seems less likely to directly anticipate the specific method of forming an interconnection structure of a package structure outlined in Claim 1, as its emphasis is on recyclability rather than the fundamental physical construction of interconnections.

7. US20070194436A1 (Advanced Semiconductor Engineering, Inc.)

• Full Citation: US20070194436A1, "Ball grid array package"
• Publication Date: 2007-08-23
• Filing Date: 2006-02-17
• Brief Description: This publication describes a ball grid array (BGA) package, which is a common type of semiconductor package.
• Potential Anticipation (35 U.S.C. § 102): This reference is highly relevant to "package structures" and likely discusses various interconnection methods within such packages. It could potentially anticipate elements of Claim 1 related to vertically integrating semiconductor devices and the overall package structure, depending on whether it details the specific sequence of forming via-holes, pads, and via structures as claimed. Many BGA packages utilize through-substrate vias or similar vertical interconnections.

8. US7312400B2 (Fujikura Ltd.)

• Full Citation: US7312400B2, "Multilayer wiring board, base for multilayer wiring board, printed wiring board and its manufacturing method"
• Publication Date: 2007-12-25
• Filing Date: 2002-02-22
• Brief Description: This patent concerns multilayer wiring boards and their manufacturing methods.
• Potential Anticipation (35 U.S.C. § 102): Multilayer wiring boards often incorporate vias and pads for interconnections between layers. Therefore, this reference could potentially anticipate some steps of Claim 1 related to forming conductive paths and pads, especially if it describes methods for forming through-holes and filling them with conductive material in a sequential manner.

9. US7528475B2 (Alps Electric Co., Ltd.)

• Full Citation: US7528475B2, "Thin-film capacitor element with reduced inductance component"
• Publication Date: 2009-05-05
• Filing Date: 2003-07-18
• Brief Description: This patent is a granted version of US20040080023A1, focusing on thin-film capacitor elements.
• Potential Anticipation (35 U.S.C. § 102): As with its application counterpart, this reference is less likely to directly anticipate the general method of forming interconnection structures for package structures.

Key Observation on Anticipation (35 U.S.C. § 102):
For a prior art reference to anticipate a claim under 35 U.S.C. § 102, it must disclose every element of the claim, arranged as claimed, either explicitly or inherently. Given the commonality of through-silicon vias (TSVs) and stacked packaging in semiconductor technology, references like US20030080408A1 and US20070194436A1 are highly pertinent. The distinguishing feature highlighted in US9275982's specification is often the sequence of forming the first pad before the via structure via electroplating without a vacuum seed layer, which potentially reduces cost. Any prior art disclosing this specific sequence, particularly the "forming a via structure in the via-hole subsequent to forming the first pad" and the use of the first pad as a seed layer for electroplating without a vacuum step, would be most impactful for anticipation. [cite: an electroplating process is performed using the first pad 130 as a seed layer to deposit a via structure 132 which fills the via-hole 126 ., the method for forming the interconnection structure of the invention forms the via structure using electroplating with the first pad as a seed layer, and no vacuum environment is required for forming the interconnect structure. Therefore, the method of the invention can produce semiconductor devices at a lower cost.]

Obviousness Analysis for US Patent 9275982 Under 35 U.S.C. § 103

This analysis identifies combinations of prior art references that would render the independent claim (Claim 1) of US Patent 9275982 obvious to a person having ordinary skill in the art (PHOSITA). The primary distinguishing feature of Claim 1, as highlighted by the patent itself, lies in a method of forming a via structure using electroplating, where a pre-formed first pad acts as a seed layer, thereby avoiding expensive vacuum deposition techniques for seed layer formation. [cite: an electroplating process is performed using the first pad 130 as a seed layer to deposit a via structure 132 which fills the via-hole 126 ., the method for forming the interconnection structure of the invention forms the via structure using electroplating with the first pad as a seed layer, and no vacuum environment is required for forming the interconnect structure. Therefore, the method of the invention can produce semiconductor devices at a lower cost.]

Combination: US20030080408A1 (Farnworth) in view of US7312400B2 (Fujikura) and the recognized need for cost reduction in semiconductor manufacturing.

Claim 1 Breakdown and Prior Art Disclosure:

1. "providing a first semiconductor device having a first side and a second side opposite to the first side;"

   • Farnworth (US20030080408A1): This reference explicitly discloses "methods for fabricating semiconductor components and interconnects with contacts on opposing sides," which inherently involves a semiconductor device with at least two opposing sides. [cite: This publication describes methods for fabricating semiconductor components and interconnects with contacts on opposing sides.]

2. "forming a via-hole through the first semiconductor device, wherein the via-hole has a first opening neighboring the first side and a second opening neighboring the second side;"

   • Farnworth (US20030080408A1): Farnworth teaches the creation of "through-wafer interconnects" by "etching holes into semiconductor wafers." These holes, by definition, pass through the wafer and would have openings on both sides. [cite: This publication describes methods for fabricating semiconductor components and interconnects with contacts on opposing sides. It focuses on creating through-wafer interconnects, often involving etching holes and filling them with conductive material, and forming pads on either side of the wafer.]

3. "forming a first pad covering the first opening;"

   • Farnworth (US20030080408A1): Farnworth discloses "forming pads on either side of the wafer" to connect to the through-wafer interconnects. A pad formed on a side containing a via opening would naturally cover that opening to establish electrical contact. [cite: This publication describes methods for fabricating semiconductor components and interconnects with contacts on opposing sides. It focuses on creating through-wafer interconnects, often involving etching holes and filling them with conductive material, and forming pads on either side of the wafer.]

4. "forming a via structure in the via-hole subsequent to forming the first pad, wherein the via structure comprises a conductive material and is adjoined to the first pad;"

   • Farnworth (US20030080408A1): Farnworth teaches "filling [holes] with conductive material" to create the via structure. The patent states the first pad is "adjoined to the via structure" and "electrically connected to the first electronic device." [cite: the first pad 130 is adjoined to the via structure 132 and is electrically connected to the electronic device 114 .] While Farnworth generally teaches filling vias and forming pads, it might not explicitly detail the sequence of forming the pad before the via fill via electroplating using the pad as a seed layer.
   • Fujikura (US7312400B2): This patent describes "multilayer wiring boards" and their "manufacturing method." In the fabrication of such boards, it is well-known in the art to form conductive pads or traces, and then use these existing conductive features as seed layers for electroplating to fill vias. Electroplating is a common and cost-effective method for depositing conductive materials in such structures.
   • Common General Knowledge & Problem/Solution: The background of US9275982 explicitly identifies a significant problem in traditional TSV manufacturing: "In traditional technologies, an electrode electroplating method is used for the conductive filling materials to be disposed in the hole of the through silicon via (TSV), wherein a seeding layer is formed by a vacuum technique, such as plasma vapor deposition, prior to formation of the conductive filling material. The vacuum technique requires high-priced equipment, which increases device costs." [cite: In traditional technologies, an electrode electroplating method is used for the conductive filling materials to be disposed in the hole of the through silicon via (TSV), wherein a seeding layer is formed by a vacuum technique, such as plasma vapor deposition, prior to formation of the conductive filling material. The vacuum technique requires high-priced equipment, which increases device costs.] A PHOSITA, motivated to reduce these high costs, would naturally look for cheaper alternatives to vacuum deposition for seed layers. It is a fundamental principle of electroplating that an existing conductive surface can serve as an electrode or seed layer for further deposition. Therefore, combining the teaching of Farnworth (forming pads and vias in semiconductor devices) with the established electroplating techniques from related arts like multilayer wiring boards (Fujikura) would lead a PHOSITA to use the already-formed conductive first pad as the seed layer for electroplating the via structure. This sequence (pad first, then electroplate via using pad as seed) directly solves the identified cost problem.

5. "substantially vertically integrating the first semiconductor device with a second semiconductor device."

   • Farnworth (US20030080408A1): Farnworth describes "fabricating semiconductor components and interconnects with contacts on opposing sides," directly enabling "stacked wafer/die packaging methods," which constitutes vertical integration. [cite: The TSV feature vertically passes through the semiconductor substrate, providing for stacked wafer/die packaging methods and allowing for electrical connection between circuits within separate wafers or chips.]

Motivation for Combination:

A PHOSITA, seeking to improve the efficiency and reduce the cost of manufacturing through-silicon vias (TSVs) for semiconductor packages, would be motivated to combine these references. The explicit problem stated in the background of US9275982 regarding the "high-priced equipment" required for vacuum techniques to form seed layers for TSV electroplating provides a strong motivation for a PHOSITA to find alternative, more cost-effective solutions. [cite: The vacuum technique requires high-priced equipment, which increases device costs.]

Farnworth (US20030080408A1) provides a foundational teaching for creating TSVs and associated pads in semiconductor devices, as well as the concept of stacking such devices. Recognizing the need for a cheaper electroplating seed layer (as highlighted by the problem in the art), a PHOSITA would turn to common electroplating practices in related fields. Fujikura (US7312400B2) illustrates manufacturing processes for multilayer wiring boards, where using a pre-existing conductive pad or trace as a seed layer for electroplating vias is a standard and cost-effective technique.

It would be obvious for a PHOSITA to apply this known cost-saving electroplating methodology from the wiring board art (Fujikura) to the TSV fabrication process described in Farnworth. By forming the conductive first pad on the semiconductor device (as taught by Farnworth) and then utilizing this pad as the seed layer for electroplating the via structure (a technique known from Fujikura and general electroplating principles), the expensive vacuum deposition step for a separate seed layer could be eliminated. This combination directly achieves the recited method steps, including the specific sequence, and yields the recognized benefit of lower manufacturing cost, as explicitly claimed by US9275982. [cite: the method for forming the interconnection structure of the invention forms the via structure using electroplating with the first pad as a seed layer, and no vacuum environment is required for forming the interconnect structure. Therefore, the method of the invention can produce semiconductor devices at a lower cost.]

Therefore, Claim 1 of US9275982 would have been obvious to a PHOSITA at the time of the invention.

The USPTO does not directly calculate or publish patent expiration dates, but it does provide information and tools to estimate them, taking into account factors like patent term adjustments (PTA) and patent term extensions (PTE).

Here's a breakdown for US Patent 9275982:

Patent Term Adjustments (PTA)

Patent Term Adjustments (PTA) are granted to compensate patent applicants for delays incurred by the USPTO during the patent examination process. These delays are categorized as "A," "B," and "C" delays, and the total PTA is added to the standard 20-year patent term. The USPTO determines the amount of PTA and includes it in the Issue Notification Letter.

To determine the exact PTA for US Patent 9275982, one would typically need to consult the patent's issue notification or its file wrapper on the USPTO Patent Center. This information is not explicitly provided in the patent text or the general search results.

Patent Term Extensions (PTE)

Patent Term Extensions (PTE) are available under 35 U.S.C. § 156 for patents claiming products (such as certain human drugs, food or color additives, medical devices, animal drugs, and veterinary biological products) that require premarket government approval from a regulatory agency. This aims to restore some of the patent term lost during the regulatory approval process.

Given the title "Method of forming interconnection structure of package structure" and the technical descriptions related to semiconductor devices, US Patent 9275982 does not appear to fall into the categories of products eligible for PTE under 35 U.S.C. § 156. Therefore, it is highly unlikely that this patent has received or would be eligible for a Patent Term Extension.

Continuation Applications, Divisional Applications, and Related Family Members

• Continuation Applications: A continuation application allows an inventor to pursue additional claims related to the same invention disclosed in a prior "parent" application, while retaining the original filing date, provided it is filed before the parent application is abandoned or patented.
• Divisional Applications: A divisional application is filed in response to a USPTO restriction requirement, where the examiner determines that a patent application claims more than one distinct invention. It claims a distinct invention disclosed but not claimed in the parent, retaining the parent's filing date.

US Patent 9275982 itself is a Divisional application. The patent states: "This application is a Division of pending U.S. patent application Ser. No. 14/020,045, filed Sep. 6, 2013 and entitled 'package structure and method of forming the same', which is a Continuation-In-Part of pending U.S. patent application Ser. No. 13/675,297, filed Nov. 13, 2012 and entitled 'interconnection structure and fabrication thereof.'" [cite: CROSS REFERENCE TO RELATED APPLICATIONS This application is a Division of pending U.S. patent application Ser. No. 14/020,045, filed Sep. 6, 2013 and entitled “package structure and method of forming the same”, which is a Continuation-In-Part of pending U.S. patent application Ser. No. 13/675,297, filed Nov. 13, 2012 and entitled “interconnection structure and fabrication thereof.”]

Therefore, the related family members are:

• Parent Application (Divisional): U.S. patent application Ser. No. 14/020,045, filed Sep. 6, 2013 (which issued as US9209164B2). [cite: Related Parent Applications (1) Application Number US14/020,045 Title Division US9209164B2 (en) Priority Date 2012-11-13 Filing Date 2013-09-06 Interconnection structure of package structure and method of forming the same]
• Grandparent Application (Continuation-In-Part): U.S. patent application Ser. No. 13/675,297, filed Nov. 13, 2012 (which issued as US9159699B2). [cite: Priority claimed from US13/675,297, Applications Claiming Priority (3) Application Number US13/675,297 US9159699B2 (en) Priority Date 2012-11-13 Filing Date 2012-11-13 Interconnection structure having a via structure]

Projected Expiration Date

The standard term for a U.S. utility patent filed on or after June 8, 1995, is 20 years from the earliest filing date of the patent application. Since US9275982 claims priority from earlier applications, its term is calculated from the filing date of the earliest application to which it claims priority.

The earliest priority date for US9275982 is November 13, 2012, from U.S. patent application Ser. No. 13/675,297 [cite: Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) 2012-11-13].

Therefore, the anticipated expiration date, before considering any PTA or terminal disclaimers, is November 13, 2012 + 20 years = November 13, 2032.

The patent document itself lists an "Anticipated expiration" date of 2032-11-13 [cite: 2032-11-13 Anticipated expiration legal-status Critical].

Summary of Expiration Details for US Patent 9275982:

• Earliest Priority Date: November 13, 2012 [cite: Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) 2012-11-13]
• Patent Term Adjustments (PTA): Not explicitly detailed in the provided text. A full analysis would require consulting USPTO records for the patent.
• Patent Term Extensions (PTE): Not applicable for this type of patent.
• Continuation Applications: This patent is a divisional application.
• Divisional Applications: This patent (US9275982) is a divisional of U.S. patent application Ser. No. 14/020,045. [cite: CROSS REFERENCE TO RELATED APPLICATIONS This application is a Division of pending U.S. patent application Ser. No. 14/020,045, filed Sep. 6, 2013 and entitled “package structure and method of forming the same”, which is a Continuation-In-Part of pending U.S. patent application Ser. No. 13/675,297, filed Nov. 13, 2012 and entitled “interconnection structure and fabrication thereof.”]
• Related Family Members:
  • US9209164B2 (from application Ser. No. 14/020,045) [cite: US14/020,045 US9209164B2 (en) 2012-11-13 2013-09-06 Interconnection structure of package structure and method of forming the same]
  • US9159699B2 (from application Ser. No. 13/675,297) [cite: US13/675,297 US9159699B2 (en) 2012-11-13 2012-11-13 Interconnection structure having a via structure]
• Projected Expiration Date: November 13, 2032 [cite: 2032-11-13 Anticipated expiration legal-status Critical] (This date includes any standard 20-year term from the earliest priority date and does not account for specific PTA values not explicitly stated, nor for any terminal disclaimers, though none are indicated in the provided text).

The search results confirm that the USPTO website is the authoritative source for patent information. I can confidently proceed with the analysis of US9275982 based on the provided text.
I will now generate the "Defensive Disclosure" document.

---

Defensive Disclosure Document for US Patent 9275982
Date: April 26, 2026
Patent Title: Method of forming interconnection structure of package structure
Inventors: Chia-Yen Lee, Hsin-Chang Tsai, Peng-Hsin LEE
Assignee: Mare Infinitus Technologies LLC (Current), Delta Electronics Inc (Original)
Priority Date: November 13, 2012

This document describes various derivative works and technical disclosures related to the core claims of US Patent 9275982, specifically focusing on Independent Claim 1, with the intent to establish prior art for future incremental improvements by competitors. The derivatives explore alternative materials, operational parameters, cross-domain applications, integration with emerging technologies, and failure modes, aiming to render such advancements obvious to a person having ordinary skill in the art (PHOSITA).

---

Derivatives of Independent Claim 1: Method of forming a package structure

Claim 1: A method of forming a package structure comprising: providing a first semiconductor device having a first side and a second side opposite to the first side; forming a via-hole through the first semiconductor device, wherein the via-hole has a first opening neighboring the first side and a second opening neighboring the second side; forming a first pad covering the first opening; forming a via structure in the via-hole subsequent to forming the first pad, wherein the via structure comprises a conductive material and is adjoined to the first pad; and substantially vertically integrating the first semiconductor device with a second semiconductor device. [cite: Claims (10) What is claimed is: 1. A method of forming a package structure comprising: providing a first semiconductor device having a first side and a second side opposite to to the first side; forming a via-hole through the first semiconductor device, wherein the via-hole has a first opening neighboring the first side and a second opening neighboring the second side; forming a first pad covering the first opening; forming a via structure in the via-hole subsequent to forming the first pad, wherein the via structure comprises a conductive material and is adjoined to the first pad; and substantially vertically integrating the first semiconductor device with a second semiconductor device.]

---

1. Material & Component Substitution

Derivative 1.1: Polymer-Substrate GaN HEMT with Conductive Polymer Via and Graphene Pad

• Enabling Description: The method comprises providing a first semiconductor device comprising a flexible polymer substrate (e.g., polyimide or PEN) with an integrated Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) electronic device. A tapered via-hole is formed through the polymer substrate using femtosecond laser ablation, having openings on the first and second sides. A first pad consisting of multiple layers of chemically vapor deposited (CVD) graphene is patterned on the first side, covering the first opening and making contact with the HEMT's source electrode. Subsequently, a highly conductive polymer composite (e.g., silver nanoparticle-filled epoxy or polyaniline) is injected into the via-hole using a micro-dispensing system and cured, forming a via structure that electrically adjoins the graphene pad. The first semiconductor device is then vertically integrated with a second semiconductor device (e.g., a silicon-based power management IC) via anisotropic conductive film (ACF) bonding. The graphene pad serves as a local conductive path during the polymer injection, ensuring electrical continuity.
• Combination Prior Art: This derivative combines the method of US9275982 with the JEDEC JESD22-A104E standard for temperature cycling for reliability testing of flexible electronic packages, IPC-TR-484 for conductive polymer materials and processes, and IEEE 802.15.4 (Zigbee) for integrated low-power wireless communication in the stacked package.

graph TD
    A[Start] --> B(Provide Flexible Polymer Substrate with GaN HEMT)
    B --> C{Form Tapered Via-Hole via Femtosecond Laser Ablation}
    C --> D(Form Graphene Pad on First Side covering First Opening)
    D --> E(Inject Conductive Polymer Composite into Via-Hole)
    E --> F(Cure Polymer to form Via Structure adjoined to Graphene Pad)
    F --> G(Vertically Integrate with Second Semiconductor Device via ACF Bonding)
    G --> H[End]

Derivative 1.2: Silicon Carbide Power Device with Tungsten Via and Sintered Copper Paste Pad

• Enabling Description: A first semiconductor device comprising a high-voltage Silicon Carbide (SiC) MOSFET on a SiC substrate is provided. A cylindrical via-hole with a high aspect ratio (e.g., 20:1) is formed through the SiC substrate using deep reactive ion etching (DRIE). A first pad is formed on the first side by screen-printing a copper nanoparticle paste over the first opening and sintering it at 800°C in a reducing atmosphere to form a dense, highly conductive copper layer. This sintered copper pad acts as the seed layer for subsequent via formation. A via structure consisting of electroplated tungsten (W) is then deposited within the via-hole, completely filling it and robustly adjoining the sintered copper pad. The tungsten plating solution utilizes a non-aqueous electrolyte to prevent SiC degradation. The first SiC device is then vertically integrated with a second semiconductor device (e.g., a silicon driver IC) using transient liquid phase (TLP) bonding.
• Combination Prior Art: This derivative incorporates aspects of SEMI M1-0315 (Specification for Polished Monocrystalline Silicon Wafers) for substrate characteristics, IPC-2221B (Generic Standard on Printed Board Design) for pad layout considerations, and ISO 26262 (Road vehicles — Functional safety) for power electronics reliability requirements in automotive applications.

graph TD
    A[Start] --> B(Provide SiC Substrate with High-Voltage SiC MOSFET)
    B --> C{Form High-Aspect-Ratio Cylindrical Via-Hole via DRIE}
    C --> D(Screen-Print Copper Nanoparticle Paste over First Opening)
    D --> E(Sinter Copper Paste at 800°C to form Conductive Pad)
    E --> F(Electroplate Tungsten into Via-Hole using Sintered Pad as Seed)
    F --> G(Vertically Integrate with Second Semiconductor Device via TLP Bonding)
    G --> H[End]

Derivative 1.3: Ferroelectric Transistor on SOI with Electroless Plated Silver Via and Indium-Tin-Oxide (ITO) Seed Layer

• Enabling Description: A first semiconductor device comprising a Silicon-on-Insulator (SOI) substrate with integrated ferroelectric field-effect transistors (FeFETs) is provided. A via-hole is formed through the SOI substrate using focused ion beam (FIB) milling. A transparent conductive first pad, comprising a sputtered and patterned Indium-Tin-Oxide (ITO) film, is deposited on the first side, covering the first opening and electrically contacting the FeFETs. Subsequently, an electroless silver plating process is initiated, utilizing the ITO film as a catalytic surface for the deposition of a pure silver via structure within the via-hole. The electroless plating ensures conformal filling of complex via geometries. The resulting silver via structure is adjoined to the ITO pad. The first semiconductor device is then vertically integrated with a second semiconductor device (e.g., an optical sensor array) through a low-temperature thermocompression bonding process, allowing for optical transparency through the ITO layers if desired.
• Combination Prior Art: This derivative leverages the SEMI M79-0210 (Specification for Silicon-On-Insulator Wafers), ASTM B657-05 (Standard Practice for Metallographic Sample Preparation for Light Metals and Their Alloys) for material characterization, and the Khronos Group OpenVX standard for vision processing acceleration in the stacked optical system.

graph TD
    A[Start] --> B(Provide SOI Substrate with FeFETs)
    B --> C{Form Via-Hole via FIB Milling}
    C --> D(Sputter & Pattern ITO Film for First Pad on First Side)
    D --> E(Perform Electroless Silver Plating using ITO Pad as Catalytic Surface)
    E --> F(Form Silver Via Structure adjoined to ITO Pad)
    F --> G(Vertically Integrate with Second Semiconductor Device via Low-Temp Thermocompression)
    G --> H[End]

---

2. Operational Parameter Expansion

Derivative 2.1: Nanoscale 3D Stack with Ultra-High Aspect Ratio Vias (UHARV)

• Enabling Description: The method involves providing a first semiconductor device, a three-dimensional integrated circuit (3DIC) module, featuring active layers on a silicon substrate. Ultra-high aspect ratio via-holes (e.g., 100:1 aspect ratio, 50nm diameter) are patterned and etched through the silicon substrate using atomic layer etching (ALE) followed by aspect ratio dependent etching (ARDE) minimization techniques. A sub-micron platinum (Pt) first pad is formed by atomic layer deposition (ALD) and subsequent focused ion beam (FIB) patterning on the first side, covering the nanoscale first opening and connecting to internal circuitry. Subsequently, a low-temperature chemical vapor deposition (LTCVD) of ruthenium (Ru) is performed to form the via structure, ensuring void-free filling of the UHARV and adhesion to the Pt pad. This process occurs under ultra-high vacuum conditions at reduced temperatures (e.g., 200°C). The first device is then vertically integrated with a second 3DIC semiconductor device using direct copper-to-copper bonding, enabling high-density, low-latency interconnections for quantum computing applications.
• Combination Prior Art: This derivative incorporates concepts from IEEE P2844 (Standard for Microelectronics Interconnect Reliability), SEMI E10-0318 (Standard for Definition and Measurement of Equipment Reliability, Availability, and Maintainability (RAM) for Semiconductor Manufacturing Equipment), and the GlobalFoundries 22FDX manufacturing process for advanced node characteristics.

graph TD
    A[Start] --> B(Provide 3DIC Silicon Substrate)
    B --> C{Pattern & Etch UHARV via ALE/ARDE (50nm diameter, 100:1 AR)}
    C --> D(Form Platinum First Pad via ALD/FIB on First Side)
    D --> E(Perform Low-Temperature CVD of Ruthenium into UHARV)
    E --> F(Form Ruthenium Via Structure adjoined to Platinum Pad)
    F --> G(Vertically Integrate with Second 3DIC Device via Direct Cu-to-Cu Bonding)
    G --> H[End]

Derivative 2.2: Extreme Temperature Operation (Cryogenic) Package with Superconducting Vias

• Enabling Description: A first semiconductor device, designed for cryogenic operation (e.g., 4K), is provided on a high-purity silicon substrate with integrated Josephson Junction circuitry. A via-hole is formed through the substrate using reactive ion etching (RIE). A first pad, composed of a multi-layered NbN/TiN superconducting film, is deposited on the first side using magnetron sputtering and patterned to cover the first opening. Subsequently, a via structure is formed in the via-hole by filling it with an amorphous superconducting alloy (e.g., MoGe) via pulsed laser deposition (PLD) at low temperatures (e.g., -150°C), ensuring electrical contact with the NbN/TiN pad. The entire fabrication and integration process is performed within a cryogenic chamber, ensuring that the superconducting properties are maintained. The first device is then vertically integrated with a second cryogenic semiconductor device (e.g., a SQUID array) using indium bump bonding in a vacuum.
• Combination Prior Art: This derivative combines the methodology with NIST FIPS 180-4 (Secure Hash Standard) for cryptographic circuit integration, IEC 60747-16-1 (Semiconductor devices — Part 16-1: Microwave integrated circuits — Mesfet integrated circuits) for advanced device characterization, and the Quantum Leap Institute's QIS roadmap for future quantum computing interconnect requirements.

graph TD
    A[Start] --> B(Provide High-Purity Si Substrate with Josephson Junctions)
    B --> C{Form Via-Hole via RIE}
    C --> D(Deposit NbN/TiN Superconducting First Pad via Sputtering)
    D --> E(Fill Via-Hole with MoGe Superconducting Alloy via PLD at -150°C)
    E --> F(Form MoGe Via Structure adjoined to NbN/TiN Pad)
    F --> G(Vertically Integrate with Second Cryogenic Device via Indium Bump Bonding)
    G --> H[End]

Derivative 2.3: High-Frequency (THz) Interposer with Low-Loss Graphene-Lined Vias

• Enabling Description: The method involves providing a first semiconductor device acting as a high-frequency interposer on a low-permittivity glass substrate. Via-holes, designed for minimal skin effect at THz frequencies, are formed through the glass substrate using ultrasonic drilling. A low-resistance first pad, consisting of a few-layer graphene sheet grown via CVD and transferred onto the first side, is patterned to cover the first opening. An ultra-thin insulating layer (e.g., h-BN) is then applied to the via sidewalls. Subsequently, a conformal via structure of highly pure copper is electroplated onto the graphene liner within the via-hole, using the graphene pad as the seed layer. The copper is deposited to a specific thickness (e.g., 500 nm) to optimize impedance matching and minimize loss at THz frequencies. The first interposer is then vertically integrated with a second semiconductor device (e.g., a SiGe HBT array) using direct metal-to-metal bonding under vacuum, ensuring minimal parasitic capacitance and inductance.
• Combination Prior Art: This derivative integrates the method with IEEE 1149.1 (JTAG) for boundary-scan testing, ANSI/IPC-TM-650 (Test Methods Manual) for material and electrical testing, and the 5G NR standard for high-frequency communication protocols and testing procedures.

graph TD
    A[Start] --> B(Provide Low-Permittivity Glass Substrate for Interposer)
    B --> C{Form Via-Holes via Ultrasonic Drilling for THz Frequencies}
    C --> D(Transfer & Pattern Few-Layer Graphene Sheet for First Pad)
    D --> E(Apply h-BN Insulating Layer to Via Sidewalls)
    E --> F(Electroplate High-Purity Copper onto Graphene Liner using Graphene Pad as Seed)
    F --> G(Vertically Integrate with Second SiGe HBT Array via Direct Metal-to-Metal Bonding)
    G --> H[End]

---

3. Cross-Domain Application

Derivative 3.1: Bio-Integrated Flexible Neural Interface with Microporous Substrate and Conductive Hydrogel Vias

• Enabling Description: A first semiconductor device comprising a flexible bio-compatible polymer (e.g., parylene-C) substrate with integrated neural sensing/stimulation electrodes is provided. Microporous via-holes are formed through the parylene-C substrate using excimer laser micromachining, allowing for tissue ingrowth. A first pad, composed of a sputtered iridium oxide film, is patterned on the first side, covering the microporous opening and connecting to the neural electrodes. Subsequently, a conductive hydrogel (e.g., alginate functionalized with carbon nanotubes) is injected into the via-hole, forming a bio-compatible via structure that adjoins the iridium oxide pad. This injection can be pressure-assisted for uniform filling. The first neural interface device is then vertically integrated with a second semiconductor device (e.g., a low-power ASIC for signal processing) using a soft lithography technique with a flexible elastomeric interconnect, suitable for long-term implantable applications.
• Combination Prior Art: This derivative uses ISO 10993 (Biological evaluation of medical devices) for biocompatibility, ASTM F2129-08 (Standard Test Method for Conducting Cyclic Potentiodynamic Polarization Measurements to Determine the Corrosion Susceptibility of Small Implantable Medical Devices) for electrochemical stability, and the OpenBCI GUI for data visualization and control of neural signals.

graph TD
    A[Start] --> B(Provide Flexible Bio-compatible Parylene-C Substrate with Neural Electrodes)
    B --> C{Form Microporous Via-Holes via Excimer Laser Micromachining}
    C --> D(Sputter & Pattern Iridium Oxide Film for First Pad)
    D --> E(Inject Conductive Hydrogel into Via-Hole)
    E --> F(Form Hydrogel Via Structure adjoined to Iridium Oxide Pad)
    F --> G(Vertically Integrate with Second ASIC Device via Elastomeric Interconnect)
    G --> H[End]

Derivative 3.2: High-Power Automotive Inverter Module with Segmented Copper Pillars and Brazed Silver Pads

• Enabling Description: A first semiconductor device comprising a multi-chip module (MCM) for an automotive power inverter, featuring SiC power MOSFETs on a ceramic (AlN) substrate, is provided. Large-diameter, segmented via-holes are formed through the AlN substrate using abrasive waterjet cutting, designed for high current handling and thermal dissipation. A first pad, consisting of a brazed silver layer, is formed on the first side, covering the segmented openings and contacting the power MOSFETs. Subsequently, pre-formed copper pillars are inserted into the via-holes and then brazed into place, creating a solid via structure that is robustly adjoined to the silver pad. The brazing process uses a low-melting point active brazing alloy (ABA) for strong metallurgical bonds. The first inverter module is then vertically integrated with a second semiconductor device (e.g., a motor control MCU) using high-temperature solder reflow, forming a compact, high-reliability power module for electric vehicles.
• Combination Prior Art: This derivative integrates the methodology with AEC-Q100 (Failure Mechanism Based Stress Test Qualification for Packaged Integrated Circuits) for automotive reliability, IEC 60068-2-14 (Environmental testing — Part 2-14: Tests — Test N: Change of temperature) for thermal shock testing, and AUTOSAR (Automotive Open System Architecture) for software and hardware interface standardization.

graph TD
    A[Start] --> B(Provide MCM with SiC Power MOSFETs on AlN Substrate)
    B --> C{Form Large-Diameter, Segmented Via-Holes via Waterjet Cutting}
    C --> D(Form Brazed Silver Layer for First Pad)
    D --> E(Insert Pre-Formed Copper Pillars into Via-Holes)
    E --> F(Braze Copper Pillars to form Via Structure adjoined to Silver Pad)
    F --> G(Vertically Integrate with Second MCU Device via High-Temp Solder Reflow)
    G --> H[End]

Derivative 3.3: Space-Grade Photovoltaic Array with Radiation-Hardened Substrate and Polymer-Filled Carbon Nanotube Vias

• Enabling Description: A first semiconductor device comprising a triple-junction gallium arsenide (GaAs) photovoltaic cell array on a radiation-hardened silicon-germanium (SiGe) substrate is provided. Via-holes are formed through the SiGe substrate using inductively coupled plasma (ICP) etching. A first pad, composed of a sputtered platinum-iridium (Pt-Ir) alloy, is patterned on the first side, covering the first opening and contacting the PV cell electrodes. Subsequently, vertically aligned carbon nanotube (CNT) bundles are grown within the via-hole using CVD, and then infiltrated with a radiation-resistant epoxy polymer to form a robust and conductive via structure that adjoins the Pt-Ir pad. The polymer infiltration enhances mechanical stability under thermal cycling in space. The first PV cell array is then vertically integrated with a second semiconductor device (e.g., a maximum power point tracking (MPPT) controller) using a direct bond interconnection technique, forming a compact, radiation-tolerant power source for satellites.
• Combination Prior Art: This derivative draws upon MIL-STD-883 (Test Method Standard Microcircuits) for space-grade reliability and radiation hardness, ECSS-Q-ST-60-13C (Space product assurance — Susceptibility of electronic components to radiation) for radiation testing protocols, and the SPDX (Software Package Data Exchange) standard for open-source software component tracking in the MPPT controller.

graph TD
    A[Start] --> B(Provide Triple-Junction GaAs PV Cell on Radiation-Hardened SiGe Substrate)
    B --> C{Form Via-Holes via ICP Etching}
    C --> D(Sputter & Pattern Pt-Ir Alloy for First Pad)
    D --> E(Grow CNT Bundles in Via-Hole & Infiltrate with Radiation-Resistant Epoxy)
    E --> F(Form CNT-Polymer Via Structure adjoined to Pt-Ir Pad)
    F --> G(Vertically Integrate with Second MPPT Controller via Direct Bond)
    G --> H[End]

---

4. Integration with Emerging Tech

Derivative 4.1: AI-Optimized Adaptive Electroplating for Heterogeneous Stacks

• Enabling Description: The method provides a first semiconductor device, a heterogeneous integration module comprising Si-based logic and InP-based photonic devices on a silicon interposer. Via-holes are formed through the interposer using plasma etching. A first pad, composed of a sputtered titanium/copper seed layer, is patterned on the first side, covering the first opening. Subsequently, an AI-driven electroplating system, utilizing real-time impedance spectroscopy and scanning electron microscopy (SEM) feedback, adaptively controls the current density, electrolyte composition, and temperature to form a copper via structure. The AI algorithm optimizes for uniform filling, minimal void formation, and desired grain structure based on the specific material stack and desired electrical properties, ensuring precise adjacency to the first pad. This adaptive electroplating process dynamically compensates for variations in via geometry and material properties. The first device is then vertically integrated with a second semiconductor device (e.g., a 3D NAND memory stack) using thermocompression bonding, with the AI system further optimizing bonding parameters for maximum yield.
• Combination Prior Art: This derivative integrates the patent's method with OpenAI Gym for reinforcement learning environment design in manufacturing, SEMI E173-0917 (Specification for Manufacturing Execution System (MES) Data Collection and Integration), and ISA-95 (Enterprise-Control System Integration) for manufacturing operation management.

graph TD
    A[Start] --> B(Provide Si/InP Heterogeneous Interposer)
    B --> C{Form Via-Holes via Plasma Etching}
    C --> D(Sputter & Pattern Ti/Cu Seed Layer for First Pad)
    D --> E{AI-Driven Adaptive Electroplating System}
    E --> F(Real-time Impedance/SEM Feedback)
    F --> G(Adjust Electroplating Parameters: Current, Electrolyte, Temp)
    G --> H(Form Copper Via Structure adjoined to First Pad)
    H --> I(Vertically Integrate with Second 3D NAND Stack via Thermocompression)
    I --> J[End]

Derivative 4.2: IoT-Enabled Smart Package with Integrated Environmental Sensors and Self-Healing Vias

• Enabling Description: A first semiconductor device comprising a processor die with embedded IoT sensors (e.g., temperature, humidity, strain) on a flexible substrate is provided. Via-holes are formed through the substrate using laser drilling. A first pad, composed of a patterned nickel-gold (Ni/Au) alloy, is deposited on the first side, covering the first opening and connecting to the embedded sensors. Subsequently, a self-healing conductive composite material (e.g., a copper/polymer matrix with microencapsulated healing agents) is introduced into the via-hole via capillary action, forming a via structure that adjoins the Ni/Au pad. This self-healing material is designed to repair micro-cracks or voids that may develop during operation or thermal cycling, extending device lifetime. The embedded IoT sensors monitor the package's internal environment and communicate via a low-power wireless protocol (e.g., Bluetooth Low Energy). The first device is then vertically integrated with a second semiconductor device (e.g., a battery management unit) using solder paste printing and reflow.
• Combination Prior Art: This derivative utilizes MQTT (Message Queuing Telemetry Transport) for IoT communication, IEC 62368-1 (Audio/video, information and communication technology equipment – Safety requirements) for product safety, and FIWARE NGSI-LD API for context information management in smart environments.

graph TD
    A[Start] --> B(Provide Processor Die with Embedded IoT Sensors on Flexible Substrate)
    B --> C{Form Via-Holes via Laser Drilling}
    C --> D(Deposit Ni/Au Alloy for First Pad)
    D --> E(Introduce Self-Healing Conductive Composite into Via-Hole via Capillary Action)
    E --> F(Form Self-Healing Via Structure adjoined to Ni/Au Pad)
    F --> G(Vertically Integrate with Second Battery Management Unit via Solder Reflow)
    G --> H[End]

    subgraph IoT Sensing & Healing Control
        Sensor[IoT Sensors (Temp, Humidity, Strain)] --> Wireless[Bluetooth LE Wireless Communication]
        Wireless --> Healing[Self-Healing Activation Logic]
        Healing --> E
    end

Derivative 4.3: Blockchain-Verified Supply Chain for High-Security Device Interconnections

• Enabling Description: The method involves providing a first semiconductor device, a trusted platform module (TPM) on a silicon substrate, requiring verifiable component authenticity. Via-holes are formed through the substrate using conventional etching. A first pad, composed of a certified gold (Au) film, is deposited on the first side, covering the first opening. Subsequently, a via structure of certified tungsten is formed in the via-hole using chemical vapor deposition (CVD), adjoined to the gold pad. Each critical manufacturing step (substrate sourcing, via-hole etching, pad deposition, via structure formation, and material certification) is digitally signed and recorded on a secure blockchain ledger, providing an immutable audit trail for supply chain verification. This ensures the integrity and authenticity of the interconnection components. The first TPM device is then vertically integrated with a second high-security cryptographic processor using cold welding in a cleanroom, with the integration process also recorded on the blockchain.
• Combination Prior Art: This derivative leverages Hyperledger Fabric for permissioned blockchain network implementation, NIST SP 800-193 (Platform Firmware Resiliency Guidelines) for hardware root of trust, and ISO/IEC 15408 (Common Criteria) for security evaluation of information technology products.

sequenceDiagram
    participant S as Substrate Mfg
    participant V as Via-Hole Mfg
    participant P as Pad Mfg
    participant VS as Via Structure Mfg
    participant I as Integration
    participant B as Blockchain Ledger

    S->>V: Provide Si Substrate (Certified Origin)
    V->>B: Record Via-Hole Etch Parameters (TxHash1)
    V->>P: Via-Hole with First Opening
    P->>B: Record Gold Pad Deposition (TxHash2)
    P->>VS: Gold Pad covering First Opening
    VS->>B: Record Tungsten CVD Parameters (TxHash3)
    VS->>I: Tungsten Via Structure adjoined to Gold Pad
    I->>B: Record Vertical Integration (TxHash4)
    B-->>I: Verification Complete
    I->>I: Integrate with Second Cryptographic Processor

---

5. The "Inverse" or Failure Mode

Derivative 5.1: Sacrificial Thermally-Activated Vias for Overcurrent Protection

• Enabling Description: The method provides a first semiconductor device, a power delivery module on a ceramic substrate. Via-holes are formed through the substrate using laser drilling. A first pad, composed of a copper-bismuth (CuBi) alloy (chosen for its low melting point), is deposited on the first side, covering the first opening and connecting to the power lines. Subsequently, a via structure is formed in the via-hole by filling it with a eutectic low-melting point solder alloy (e.g., SnBiAg) via injection and reflow, forming a sacrificial interconnection adjoined to the CuBi pad. Upon detection of an overcurrent condition causing localized heating above the eutectic temperature, the solder via structure is designed to melt and intentionally disconnect, acting as a microscopic fuse to protect downstream components. The first device is then vertically integrated with a second semiconductor device (e.g., a high-current switch) using standard lead-free solder interconnects.
• Combination Prior Art: This derivative uses UL 248 (Low-Voltage Fuses) for safety standards, IEC 60127 (Miniature fuses) for fuse characteristics, and SEMI F47-0706 (Specification for Semiconductor Processing Equipment Voltage Sag Immunity) for power disturbance tolerance.

graph TD
    A[Start] --> B(Provide Power Delivery Module on Ceramic Substrate)
    B --> C{Form Via-Holes via Laser Drilling}
    C --> D(Deposit Copper-Bismuth Alloy for First Pad)
    D --> E(Inject & Reflow Eutectic Solder Alloy into Via-Hole)
    E --> F(Form Sacrificial Solder Via Structure adjoined to CuBi Pad)
    F --> G(Vertically Integrate with Second High-Current Switch)
    G --> H[End]

    subgraph Failure Mode
        I(Overcurrent Detected) --> J(Localized Heating)
        J --> K(Solder Via Melts)
        K --> L(Disconnection - Circuit Protection)
    end

Derivative 5.2: Reversible Shape Memory Alloy (SMA) Vias for Reconfigurable Packages

• Enabling Description: A first semiconductor device, a reconfigurable computing module on a silicon interposer, is provided. Via-holes are formed through the interposer using anisotropic etching. A first pad, composed of a sputtered gold (Au) film, is patterned on the first side, covering the first opening. Subsequently, a shape memory alloy (SMA) (e.g., NiTi or CuAlNi) is electroplated into the via-hole to form a via structure that adjoins the gold pad. The SMA material is designed to transition between a conductive and non-conductive state (or open/closed circuit) by applying specific thermal or electrical stimuli, allowing for reversible disconnection and reconnection of vertical interconnections for package reconfiguration or repair. The phase transition temperature of the SMA is precisely controlled. The first device is then vertically integrated with a second reconfigurable logic device using a compliant polymer interface, allowing for slight mechanical flexure during SMA actuation.
• Combination Prior Art: This derivative leverages ASTM F2063-18 (Standard Specification for Wrought Nickel-Titanium Shape Memory Alloys for Medical Devices and General Engineering Applications), IPC-7095C (Design and Assembly Process Implementation for Flip Chip and Wafer Level Chip Scale Technologies) for advanced packaging, and IEEE 1801 (UPF - Unified Power Format) for power domain management in reconfigurable systems.

stateDiagram-v2
    state "Disconnected (Open Circuit)" as Disconnected
    state "Connected (Closed Circuit)" as Connected

    [*] --> Disconnected : Initial State (e.g., Martensite)
    Disconnected --> Connected : Apply Thermal/Electrical Stimulus (Austenite Transition)
    Connected --> Disconnected : Remove Stimulus / Reverse Stimulus (Martensite Transition)
    Disconnected --> Disconnected : Maintain Disconnected
    Connected --> Connected : Maintain Connected

    state "Forming Via" as Forming
    [*] --> Forming
    Forming --> Disconnected : SMA Via Formation Complete

Derivative 5.3: Diagnostic Vias with Integrated Impedance Monitoring for Predictive Maintenance

• Enabling Description: A first semiconductor device, a high-performance computing (HPC) processor on a silicon substrate, is provided. Via-holes are formed through the substrate using plasma etching. A multi-layered first pad, incorporating a resistive sensing element (e.g., a thin film of highly doped polysilicon) beneath a standard copper contact layer, is patterned on the first side, covering the first opening and electrically connecting to internal diagnostic circuitry. Subsequently, a copper via structure is electroplated into the via-hole, adjoined to the copper contact layer of the pad. The embedded resistive sensing element continuously monitors the impedance of the via structure and its interface, providing real-time data to a built-in self-test (BIST) engine. Any drift or abrupt change in impedance signals potential degradation or impending failure of the via, enabling predictive maintenance. The first HPC device is then vertically integrated with a second high-bandwidth memory (HBM) device using micro-bump bonding, with the diagnostic data communicated over a sideband channel.
• Combination Prior Art: This derivative integrates the patent's method with IEEE 1149.6 (Boundary-Scan Test for Advanced Digital Networks) for fault isolation, JEDEC JESD47I (Stress-Test-Driven Qualification of Integrated Circuits) for reliability assessment, and OpenTelemetry for standardized collection of diagnostic data.

graph TD
    A[Start] --> B(Provide HPC Processor on Silicon Substrate)
    B --> C{Form Via-Holes via Plasma Etching}
    C --> D(Form Multi-Layered First Pad with Resistive Sensing Element & Cu Contact)
    D --> E(Electroplate Copper into Via-Hole)
    E --> F(Form Copper Via Structure adjoined to Cu Contact Layer)
    F --> G(Embedded Resistive Sensing Element Monitors Via Impedance)
    G --> H(Data to BIST Engine for Predictive Maintenance)
    F --> I(Vertically Integrate with Second HBM Device via Micro-Bump Bonding)
    I --> J[End]

Derivative 5.4: Low-Power/Limited-Functionality Standby Vias via Photo-Patternable Conductive Inks

• Enabling Description: The method provides a first semiconductor device, a low-power microcontroller unit (MCU) on a flexible thin-film polymer substrate. Via-holes are formed through the polymer substrate using UV laser ablation. A first pad, comprising a photo-patternable silver nanoparticle ink, is deposited and UV-cured on the first side, covering the first opening and connecting to the MCU's low-power I/O. Subsequently, a via structure is formed in the via-hole by injecting a different photo-patternable conductive carbon nanotube (CNT) ink, which is then selectively UV-cured to achieve a desired, lower conductivity, optimized for limited-functionality standby modes. This CNT ink forms a via structure adjoined to the silver nanoparticle pad. The selective curing allows for control over the electrical resistance, enabling a "sleep" mode where only essential, low-bandwidth communication occurs. The first MCU device is then vertically integrated with a second low-power sensor array device using a pressure-sensitive adhesive.
• Combination Prior Art: This derivative utilizes Energy Star standards for low-power electronics, MIPI Alliance specifications for low-power mobile interfaces, and the Apache Kafka platform for streaming data during diagnostics.

graph TD
    A[Start] --> B(Provide Low-Power MCU on Flexible Thin-Film Polymer Substrate)
    B --> C{Form Via-Holes via UV Laser Ablation}
    C --> D(Deposit & UV-Cure Photo-Patternable Silver Nanoparticle Ink for First Pad)
    D --> E(Inject Photo-Patternable Conductive CNT Ink into Via-Hole)
    E --> F(Selectively UV-Cure CNT Ink for Desired Low Conductivity)
    F --> G(Form Low-Power Via Structure adjoined to Silver Nanoparticle Pad)
    G --> H(Vertically Integrate with Second Low-Power Sensor Array via PSA)
    H --> I[End]

    subgraph Operation Modes
        J(Normal Operation) --> G
        K(Low-Power/Limited-Functionality Standby) --> F
    end

---

This comprehensive defensive disclosure aims to cover a broad range of permutations and combinations of the claimed method, using varied materials, extreme operational conditions, diverse applications, integration with cutting-edge technologies, and considerations for failure modes and alternative functionalities. Each derivative is described with sufficient technical detail to enable a PHOSITA to implement it, thereby strengthening its standing as prior art.This document details defensive disclosures and derivative works for US Patent 9275982, focusing on expanding the scope of its independent claim to encompass numerous variations that would be obvious to a person having ordinary skill in the art (PHOSITA). The goal is to preemptively establish prior art against potential future incremental innovations by competitors.

The core of US Patent 9275982's independent Claim 1 involves a method for forming a package structure, including: providing a first semiconductor device, forming a via-hole, forming a first pad covering the first opening, forming a via structure in the via-hole subsequent to forming the first pad (where the via structure is conductive and adjoined to the first pad), and finally, substantially vertically integrating the first semiconductor device with a second semiconductor device. The patent highlights the advantage of using the first pad as a seed layer for electroplating the via structure, thereby avoiding costly vacuum deposition techniques. [cite: Claims (10) What is claimed is: 1. A method of forming a package structure comprising: providing a first semiconductor device having a first side and a second side opposite to to the first side; forming a via-hole through the first semiconductor device, wherein the via-hole has a first opening neighboring the first side and a second opening neighboring the second side; forming a first pad covering the first opening; forming a via structure in the via-hole subsequent to forming the first pad, wherein the via structure comprises a conductive material and is adjoined to the first pad; and substantially vertically integrating the first semiconductor device with a second semiconductor device.]

---

Derivatives of Independent Claim 1: Method of forming a package structure

1. Material & Component Substitution

Derivative 1.1: Polymer-Substrate GaN HEMT with Conductive Polymer Via and Graphene Pad

• Enabling Description: The method comprises providing a first semiconductor device featuring a flexible polymer substrate (e.g., polyimide or PEN) with an integrated Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) electronic device. A tapered via-hole is formed through the polymer substrate using femtosecond laser ablation, establishing openings on the first and second sides. A first pad, composed of multiple layers of chemically vapor deposited (CVD) graphene, is patterned on the first side, covering the first opening and electrically connecting to the HEMT's source electrode. Subsequently, a highly conductive polymer composite (e.g., a silver nanoparticle-filled epoxy or polyaniline) is injected into the via-hole using a micro-dispensing system and then cured to form a via structure that electrically adjoins the graphene pad. The graphene pad functions as a local conductive path during the polymer injection. The first semiconductor device is then vertically integrated with a second semiconductor device (e.g., a silicon-based power management IC) via anisotropic conductive film (ACF) bonding.
• Combination Prior Art: This derivative combines the method of US9275982 with the JEDEC JESD22-A104E standard for temperature cycling for reliability testing of flexible electronic packages, IPC-TR-484 for conductive polymer materials and processes, and IEEE 802.15.4 (Zigbee) for integrated low-power wireless communication in the stacked package.

graph TD
    A[Start] --> B(Provide Flexible Polymer Substrate with GaN HEMT)
    B --> C{Form Tapered Via-Hole via Femtosecond Laser Ablation}
    C --> D(Form Graphene Pad on First Side covering First Opening)
    D --> E(Inject Conductive Polymer Composite into Via-Hole)
    E --> F(Cure Polymer to form Via Structure adjoined to Graphene Pad)
    F --> G(Vertically Integrate with Second Semiconductor Device via ACF Bonding)
    G --> H[End]

Derivative 1.2: Silicon Carbide Power Device with Tungsten Via and Sintered Copper Paste Pad

• Enabling Description: A first semiconductor device is provided, consisting of a high-voltage Silicon Carbide (SiC) MOSFET on a SiC substrate. A cylindrical via-hole with a high aspect ratio (e.g., 20:1) is formed through the SiC substrate using deep reactive ion etching (DRIE). A first pad is formed on the first side by screen-printing a copper nanoparticle paste over the first opening and sintering it at 800°C in a reducing atmosphere to create a dense, highly conductive copper layer. This sintered copper pad then serves as the seed layer. A via structure composed of electroplated tungsten (W) is subsequently deposited within the via-hole, completely filling it and robustly adjoining the sintered copper pad. The tungsten plating solution utilizes a non-aqueous electrolyte to prevent SiC degradation. The first SiC device is then vertically integrated with a second semiconductor device (e.g., a silicon driver IC) using transient liquid phase (TLP) bonding.
• Combination Prior Art: This derivative incorporates aspects of SEMI M1-0315 (Specification for Polished Monocrystalline Silicon Wafers) for substrate characteristics, IPC-2221B (Generic Standard on Printed Board Design) for pad layout considerations, and ISO 26262 (Road vehicles — Functional safety) for power electronics reliability requirements in automotive applications.

graph TD
    A[Start] --> B(Provide SiC Substrate with High-Voltage SiC MOSFET)
    B --> C{Form High-Aspect-Ratio Cylindrical Via-Hole via DRIE}
    C --> D(Screen-Print Copper Nanoparticle Paste over First Opening)
    D --> E(Sinter Copper Paste at 800°C to form Conductive Pad)
    E --> F(Electroplate Tungsten into Via-Hole using Sintered Pad as Seed)
    F --> G(Vertically Integrate with Second Semiconductor Device via TLP Bonding)
    G --> H[End]

Derivative 1.3: Ferroelectric Transistor on SOI with Electroless Plated Silver Via and Indium-Tin-Oxide (ITO) Seed Layer

• Enabling Description: A first semiconductor device comprising a Silicon-on-Insulator (SOI) substrate with integrated ferroelectric field-effect transistors (FeFETs) is provided. A via-hole is formed through the SOI substrate using focused ion beam (FIB) milling. A transparent conductive first pad, comprising a sputtered and patterned Indium-Tin-Oxide (ITO) film, is deposited on the first side, covering the first opening and electrically contacting the FeFETs. Subsequently, an electroless silver plating process is initiated, utilizing the ITO film as a catalytic surface for the deposition of a pure silver via structure within the via-hole. The electroless plating ensures conformal filling of complex via geometries. The resulting silver via structure is adjoined to the ITO pad. The first semiconductor device is then vertically integrated with a second semiconductor device (e.g., an optical sensor array) through a low-temperature thermocompression bonding process, allowing for optical transparency through the ITO layers if desired.
• Combination Prior Art: This derivative leverages the SEMI M79-0210 (Specification for Silicon-On-Insulator Wafers), ASTM B657-05 (Standard Practice for Metallographic Sample Preparation for Light Metals and Their Alloys) for material characterization, and the Khronos Group OpenVX standard for vision processing acceleration in the stacked optical system.

graph TD
    A[Start] --> B(Provide SOI Substrate with FeFETs)
    B --> C{Form Via-Hole via FIB Milling}
    C --> D(Sputter & Pattern ITO Film for First Pad on First Side)
    D --> E(Perform Electroless Silver Plating using ITO Pad as Catalytic Surface)
    E --> F(Form Silver Via Structure adjoined to ITO Pad)
    F --> G(Vertically Integrate with Second Semiconductor Device via Low-Temp Thermocompression)
    G --> H[End]

---

2. Operational Parameter Expansion

Derivative 2.1: Nanoscale 3D Stack with Ultra-High Aspect Ratio Vias (UHARV)

• Enabling Description: The method involves providing a first semiconductor device, specifically a three-dimensional integrated circuit (3DIC) module, featuring active layers on a silicon substrate. Ultra-high aspect ratio via-holes (e.g., 100:1 aspect ratio, 50nm diameter) are patterned and etched through the silicon substrate using atomic layer etching (ALE) followed by aspect ratio dependent etching (ARDE) minimization techniques. A sub-micron platinum (Pt) first pad is formed by atomic layer deposition (ALD) and subsequent focused ion beam (FIB) patterning on the first side, covering the nanoscale first opening and connecting to internal circuitry. Subsequently, a low-temperature chemical vapor deposition (LTCVD) of ruthenium (Ru) is performed to form the via structure, ensuring void-free filling of the UHARV and adhesion to the Pt pad. This process occurs under ultra-high vacuum conditions at reduced temperatures (e.g., 200°C). The first device is then vertically integrated with a second 3DIC semiconductor device using direct copper-to-copper bonding, enabling high-density, low-latency interconnections for quantum computing applications.
• Combination Prior Art: This derivative incorporates concepts from IEEE P2844 (Standard for Microelectronics Interconnect Reliability), SEMI E10-0318 (Standard for Definition and Measurement of Equipment Reliability, Availability, and Maintainability (RAM) for Semiconductor Manufacturing Equipment), and the GlobalFoundries 22FDX manufacturing process for advanced node characteristics.

graph TD
    A[Start] --> B(Provide 3DIC Silicon Substrate)
    B --> C{Pattern & Etch UHARV via ALE/ARDE (50nm diameter, 100:1 AR)}
    C --> D(Form Platinum First Pad via ALD/FIB on First Side)
    D --> E(Perform Low-Temperature CVD of Ruthenium into UHARV)
    E --> F(Form Ruthenium Via Structure adjoined to Platinum Pad)
    F --> G(Vertically Integrate with Second 3DIC Device via Direct Cu-to-Cu Bonding)
    G --> H[End]

Derivative 2.2: Extreme Temperature Operation (Cryogenic) Package with Superconducting Vias

• Enabling Description: A first semiconductor device, specifically designed for cryogenic operation (e.g., 4 Kelvin), is provided on a high-purity silicon substrate with integrated Josephson Junction circuitry. A via-hole is formed through the substrate using reactive ion etching (RIE). A first pad, composed of a multi-layered NbN/TiN superconducting film, is deposited on the first side using magnetron sputtering and patterned to cover the first opening. Subsequently, a via structure is formed in the via-hole by filling it with an amorphous superconducting alloy (e.g., MoGe) via pulsed laser deposition (PLD) at low temperatures (e.g., -150°C), ensuring electrical contact with the NbN/TiN pad. The entire fabrication and integration process is performed within a cryogenic chamber, maintaining superconducting properties. The first device is then vertically integrated with a second cryogenic semiconductor device (e.g., a SQUID array) using indium bump bonding in a vacuum.
• Combination Prior Art: This derivative combines the methodology with NIST FIPS 180-4 (Secure Hash Standard) for cryptographic circuit integration, IEC 60747-16-1 (Semiconductor devices — Part 16-1: Microwave integrated circuits — Mesfet integrated circuits) for advanced device characterization, and the Quantum Leap Institute's QIS roadmap for future quantum computing interconnect requirements.

graph TD
    A[Start] --> B(Provide High-Purity Si Substrate with Josephson Junctions)
    B --> C{Form Via-Hole via RIE}
    C --> D(Deposit NbN/TiN Superconducting First Pad via Sputtering)
    D --> E(Fill Via-Hole with MoGe Superconducting Alloy via PLD at -150°C)
    E --> F(Form MoGe Via Structure adjoined to NbN/TiN Pad)
    F --> G(Vertically Integrate with Second Cryogenic Device via Indium Bump Bonding)
    G --> H[End]

Derivative 2.3: High-Frequency (THz) Interposer with Low-Loss Graphene-Lined Vias

• Enabling Description: The method involves providing a first semiconductor device acting as a high-frequency interposer on a low-permittivity glass substrate. Via-holes, specifically designed for minimal skin effect at THz frequencies, are formed through the glass substrate using ultrasonic drilling. A low-resistance first pad, consisting of a few-layer graphene sheet grown via CVD and transferred onto the first side, is patterned to cover the first opening. An ultra-thin insulating layer (e.g., h-BN) is then applied to the via sidewalls. Subsequently, a conformal via structure of highly pure copper is electroplated onto the graphene liner within the via-hole, using the graphene pad as the seed layer. The copper is deposited to a specific thickness (e.g., 500 nm) to optimize impedance matching and minimize loss at THz frequencies. The first interposer is then vertically integrated with a second semiconductor device (e.g., a SiGe HBT array) using direct metal-to-metal bonding under vacuum, ensuring minimal parasitic capacitance and inductance.
• Combination Prior Art: This derivative integrates the method with IEEE 1149.1 (JTAG) for boundary-scan testing, ANSI/IPC-TM-650 (Test Methods Manual) for material and electrical testing, and the 5G NR standard for high-frequency communication protocols and testing procedures.

graph TD
    A[Start] --> B(Provide Low-Permittivity Glass Substrate for Interposer)
    B --> C{Form Via-Holes via Ultrasonic Drilling for THz Frequencies}
    C --> D(Transfer & Pattern Few-Layer Graphene Sheet for First Pad)
    D --> E(Apply h-BN Insulating Layer to Via Sidewalls)
    E --> F(Electroplate High-Purity Copper onto Graphene Liner using Graphene Pad as Seed)
    F --> G(Vertically Integrate with Second SiGe HBT Array via Direct Metal-to-Metal Bonding)
    G --> H[End]

---

3. Cross-Domain Application

Derivative 3.1: Bio-Integrated Flexible Neural Interface with Microporous Substrate and Conductive Hydrogel Vias

• Enabling Description: A first semiconductor device comprising a flexible bio-compatible polymer (e.g., parylene-C) substrate with integrated neural sensing/stimulation electrodes is provided. Microporous via-holes are formed through the parylene-C substrate using excimer laser micromachining, designed to allow for tissue ingrowth. A first pad, composed of a sputtered iridium oxide film, is patterned on the first side, covering the microporous opening and connecting to the neural electrodes. Subsequently, a conductive hydrogel (e.g., alginate functionalized with carbon nanotubes) is injected into the via-hole, forming a bio-compatible via structure that adjoins the iridium oxide pad. This injection can be pressure-assisted for uniform filling. The first neural interface device is then vertically integrated with a second semiconductor device (e.g., a low-power ASIC for signal processing) using a soft lithography technique with a flexible elastomeric interconnect, suitable for long-term implantable applications.
• Combination Prior Art: This derivative uses ISO 10993 (Biological evaluation of medical devices) for biocompatibility, ASTM F2129-08 (Standard Test Method for Conducting Cyclic Potentiodynamic Polarization Measurements to Determine the Corrosion Susceptibility of Small Implantable Medical Devices) for electrochemical stability, and the OpenBCI GUI for data visualization and control of neural signals.

graph TD
    A[Start] --> B(Provide Flexible Bio-compatible Parylene-C Substrate with Neural Electrodes)
    B --> C{Form Microporous Via-Holes via Excimer Laser Micromachining}
    C --> D(Sputter & Pattern Iridium Oxide Film for First Pad)
    D --> E(Inject Conductive Hydrogel into Via-Hole)
    E --> F(Form Hydrogel Via Structure adjoined to Iridium Oxide Pad)
    F --> G(Vertically Integrate with Second ASIC Device via Elastomeric Interconnect)
    G --> H[End]

Derivative 3.2: High-Power Automotive Inverter Module with Segmented Copper Pillars and Brazed Silver Pads

• Enabling Description: A first semiconductor device comprising a multi-chip module (MCM) for an automotive power inverter, featuring SiC power MOSFETs on a ceramic (AlN) substrate, is provided. Large-diameter, segmented via-holes are formed through the AlN substrate using abrasive waterjet cutting, designed for high current handling and thermal dissipation. A first pad, consisting of a brazed silver layer, is formed on the first side, covering the segmented openings and contacting the power MOSFETs. Subsequently, pre-formed copper pillars are inserted into the via-holes and then brazed into place, creating a solid via structure that is robustly adjoined to the silver pad. The brazing process uses a low-melting point active brazing alloy (ABA) for strong metallurgical bonds. The first inverter module is then vertically integrated with a second semiconductor device (e.g., a motor control MCU) using high-temperature solder reflow, forming a compact, high-reliability power module for electric vehicles.
• Combination Prior Art: This derivative integrates the methodology with AEC-Q100 (Failure Mechanism Based Stress Test Qualification for Packaged Integrated Circuits) for automotive reliability, IEC 60068-2-14 (Environmental testing — Part 2-14: Tests — Test N: Change of temperature) for thermal shock testing, and AUTOSAR (Automotive Open System Architecture) for software and hardware interface standardization.

graph TD
    A[Start] --> B(Provide MCM with SiC Power MOSFETs on AlN Substrate)
    B --> C{Form Large-Diameter, Segmented Via-Holes via Waterjet Cutting}
    C --> D(Form Brazed Silver Layer for First Pad)
    D --> E(Insert Pre-Formed Copper Pillars into Via-Holes)
    E --> F(Braze Copper Pillars to form Via Structure adjoined to Silver Pad)
    F --> G(Vertically Integrate with Second MCU Device via High-Temp Solder Reflow)
    G --> H[End]

Derivative 3.3: Space-Grade Photovoltaic Array with Radiation-Hardened Substrate and Polymer-Filled Carbon Nanotube Vias

• Enabling Description: A first semiconductor device comprising a triple-junction gallium arsenide (GaAs) photovoltaic cell array on a radiation-hardened silicon-germanium (SiGe) substrate is provided. Via-holes are formed through the SiGe substrate using inductively coupled plasma (ICP) etching. A first pad, composed of a sputtered platinum-iridium (Pt-Ir) alloy, is patterned on the first side, covering the first opening and contacting the PV cell electrodes. Subsequently, vertically aligned carbon nanotube (CNT) bundles are grown within the via-hole using CVD, and then infiltrated with a radiation-resistant epoxy polymer to form a robust and conductive via structure that adjoins the Pt-Ir pad. The polymer infiltration enhances mechanical stability under thermal cycling in space. The first PV cell array is then vertically integrated with a second semiconductor device (e.g., a maximum power point tracking (MPPT) controller) using a direct bond interconnection technique, forming a compact, radiation-tolerant power source for satellites.
• Combination Prior Art: This derivative draws upon MIL-STD-883 (Test Method Standard Microcircuits) for space-grade reliability and radiation hardness, ECSS-Q-ST-60-13C (Space product assurance — Susceptibility of electronic components to radiation) for radiation testing protocols, and the SPDX (Software Package Data Exchange) standard for open-source software component tracking in the MPPT controller.

graph TD
    A[Start] --> B(Provide Triple-Junction GaAs PV Cell on Radiation-Hardened SiGe Substrate)
    B --> C{Form Via-Holes via ICP Etching}
    C --> D(Sputter & Pattern Pt-Ir Alloy for First Pad)
    D --> E(Grow CNT Bundles in Via-Hole & Infiltrate with Radiation-Resistant Epoxy)
    E --> F(Form CNT-Polymer Via Structure adjoined to Pt-Ir Pad)
    F --> G(Vertically Integrate with Second MPPT Controller via Direct Bond)
    G --> H[End]

---

4. Integration with Emerging Tech

Derivative 4.1: AI-Optimized Adaptive Electroplating for Heterogeneous Stacks

• Enabling Description: The method provides a first semiconductor device, specifically a heterogeneous integration module comprising Si-based logic and InP-based photonic devices on a silicon interposer. Via-holes are formed through the interposer using plasma etching. A first pad, composed of a sputtered titanium/copper seed layer, is patterned on the first side, covering the first opening. Subsequently, an AI-driven electroplating system, utilizing real-time impedance spectroscopy and scanning electron microscopy (SEM) feedback, adaptively controls the current density, electrolyte composition, and temperature to form a copper via structure. The AI algorithm optimizes for uniform filling, minimal void formation, and desired grain structure based on the specific material stack and desired electrical properties, ensuring precise adjacency to the first pad. This adaptive electroplating process dynamically compensates for variations in via geometry and material properties. The first device is then vertically integrated with a second semiconductor device (e.g., a 3D NAND memory stack) using thermocompression bonding, with the AI system further optimizing bonding parameters for maximum yield.
• Combination Prior Art: This derivative integrates the patent's method with OpenAI Gym for reinforcement learning environment design in manufacturing, SEMI E173-0917 (Specification for Manufacturing Execution System (MES) Data Collection and Integration), and ISA-95 (Enterprise-Control System Integration) for manufacturing operation management.

graph TD
    A[Start] --> B(Provide Si/InP Heterogeneous Interposer)
    B --> C{Form Via-Holes via Plasma Etching}
    C --> D(Sputter & Pattern Ti/Cu Seed Layer for First Pad)
    D --> E{AI-Driven Adaptive Electroplating System}
    E --> F(Real-time Impedance/SEM Feedback)
    F --> G(Adjust Electroplating Parameters: Current, Electrolyte, Temp)
    G --> H(Form Copper Via Structure adjoined to First Pad)
    H --> I(Vertically Integrate with Second 3D NAND Stack via Thermocompression)
    I --> J[End]

Derivative 4.2: IoT-Enabled Smart Package with Integrated Environmental Sensors and Self-Healing Vias

• Enabling Description: A first semiconductor device comprising a processor die with embedded IoT sensors (e.g., temperature, humidity, strain) on a flexible substrate is provided. Via-holes are formed through the substrate using laser drilling. A first pad, composed of a patterned nickel-gold (Ni/Au) alloy, is deposited on the first side, covering the first opening and connecting to the embedded sensors. Subsequently, a self-healing conductive composite material (e.g., a copper/polymer matrix with microencapsulated healing agents) is introduced into the via-hole via capillary action, forming a via structure that adjoins the Ni/Au pad. This self-healing material is designed to repair micro-cracks or voids that may develop during operation or thermal cycling, extending device lifetime. The embedded IoT sensors monitor the package's internal environment and communicate via a low-power wireless protocol (e.g., Bluetooth Low Energy). The first device is then vertically integrated with a second semiconductor device (e.g., a battery management unit) using solder paste printing and reflow.
• Combination Prior Art: This derivative utilizes MQTT (Message Queuing Telemetry Transport) for IoT communication, IEC 62368-1 (Audio/video, information and communication technology equipment – Safety requirements) for product safety, and FIWARE NGSI-LD API for context information management in smart environments.

graph TD
    A[Start] --> B(Provide Processor Die with Embedded IoT Sensors on Flexible Substrate)
    B --> C{Form Via-Holes via Laser Drilling}
    C --> D(Deposit Ni/Au Alloy for First Pad)
    D --> E(Introduce Self-Healing Conductive Composite into Via-Hole via Capillary Action)
    E --> F(Form Self-Healing Via Structure adjoined to Ni/Au Pad)
    F --> G(Vertically Integrate with Second Battery Management Unit via Solder Reflow)
    G --> H[End]

    subgraph IoT Sensing & Healing Control
        Sensor[IoT Sensors (Temp, Humidity, Strain)] --> Wireless[Bluetooth LE Wireless Communication]
        Wireless --> Healing[Self-Healing Activation Logic]
        Healing --> E
    end

Derivative 4.3: Blockchain-Verified Supply Chain for High-Security Device Interconnections

• Enabling Description: The method involves providing a first semiconductor device, a trusted platform module (TPM) on a silicon substrate, requiring verifiable component authenticity. Via-holes are formed through the substrate using conventional etching. A first pad, composed of a certified gold (Au) film, is deposited on the first side, covering the first opening. Subsequently, a via structure of certified tungsten is formed in the via-hole using chemical vapor deposition (CVD), adjoined to the gold pad. Each critical manufacturing step (substrate sourcing, via-hole etching, pad deposition, via structure formation, and material certification) is digitally signed and recorded on a secure blockchain ledger, providing an immutable audit trail for supply chain verification. This ensures the integrity and authenticity of the interconnection components. The first TPM device is then vertically integrated with a second high-security cryptographic processor using cold welding in a cleanroom, with the integration process also recorded on the blockchain.
• Combination Prior Art: This derivative leverages Hyperledger Fabric for permissioned blockchain network implementation, NIST SP 800-193 (Platform Firmware Resiliency Guidelines) for hardware root of trust, and ISO/IEC 15408 (Common Criteria) for security evaluation of information technology products.

sequenceDiagram
    participant S as Substrate Mfg
    participant V as Via-Hole Mfg
    participant P as Pad Mfg
    participant VS as Via Structure Mfg
    participant I as Integration
    participant B as Blockchain Ledger

    S->>V: Provide Si Substrate (Certified Origin)
    V->>B: Record Via-Hole Etch Parameters (TxHash1)
    V->>P: Via-Hole with First Opening
    P->>B: Record Gold Pad Deposition (TxHash2)
    P->>VS: Gold Pad covering First Opening
    VS->>B: Record Tungsten CVD Parameters (TxHash3)
    VS->>I: Tungsten Via Structure adjoined to Gold Pad
    I->>B: Record Vertical Integration (TxHash4)
    B-->>I: Verification Complete
    I->>I: Integrate with Second Cryptographic Processor

---

5. The "Inverse" or Failure Mode

Derivative 5.1: Sacrificial Thermally-Activated Vias for Overcurrent Protection

• Enabling Description: The method provides a first semiconductor device, a power delivery module on a ceramic substrate. Via-holes are formed through the substrate using laser drilling. A first pad, composed of a copper-bismuth (CuBi) alloy (chosen for its low melting point), is deposited on the first side, covering the first opening and connecting to the power lines. Subsequently, a via structure is formed in the via-hole by filling it with a eutectic low-melting point solder alloy (e.g., SnBiAg) via injection and reflow, forming a sacrificial interconnection adjoined to the CuBi pad. Upon detection of an overcurrent condition causing localized heating above the eutectic temperature, the solder via structure is designed to melt and intentionally disconnect, acting as a microscopic fuse to protect downstream components. The first device is then vertically integrated with a second semiconductor device (e.g., a high-current switch) using standard lead-free solder interconnects.
• Combination Prior Art: This derivative uses UL 248 (Low-Voltage Fuses) for safety standards, IEC 60127 (Miniature fuses) for fuse characteristics, and SEMI F47-0706 (Specification for Semiconductor Processing Equipment Voltage Sag Immunity) for power disturbance tolerance.

graph TD
    A[Start] --> B(Provide Power Delivery Module on Ceramic Substrate)
    B --> C{Form Via-Holes via Laser Drilling}
    C --> D(Deposit Copper-Bismuth Alloy for First Pad)
    D --> E(Inject & Reflow Eutectic Solder Alloy into Via-Hole)
    E --> F(Form Sacrificial Solder Via Structure adjoined to CuBi Pad)
    F --> G(Vertically Integrate with Second High-Current Switch)
    G --> H[End]

    subgraph Failure Mode
        I(Overcurrent Detected) --> J(Localized Heating)
        J --> K(Solder Via Melts)
        K --> L(Disconnection - Circuit Protection)
    end

Derivative 5.2: Reversible Shape Memory Alloy (SMA) Vias for Reconfigurable Packages

• Enabling Description: A first semiconductor device, a reconfigurable computing module on a silicon interposer, is provided. Via-holes are formed through the interposer using anisotropic etching. A first pad, composed of a sputtered gold (Au) film, is patterned on the first side, covering the first opening. Subsequently, a shape memory alloy (SMA) (e.g., NiTi or CuAlNi) is electroplated into the via-hole to form a via structure that adjoins the gold pad. The SMA material is designed to transition between a conductive and non-conductive state (or open/closed circuit) by applying specific thermal or electrical stimuli, allowing for reversible disconnection and reconnection of vertical interconnections for package reconfiguration or repair. The phase transition temperature of the SMA is precisely controlled. The first device is then vertically integrated with a second reconfigurable logic device using a compliant polymer interface, allowing for slight mechanical flexure during SMA actuation.
• Combination Prior Art: This derivative leverages ASTM F2063-18 (Standard Specification for Wrought Nickel-Titanium Shape Memory Alloys for Medical Devices and General Engineering Applications), IPC-7095C (Design and Assembly Process Implementation for Flip Chip and Wafer Level Chip Scale Technologies) for advanced packaging, and IEEE 1801 (UPF - Unified Power Format) for power domain management in reconfigurable systems.

stateDiagram-v2
    state "Disconnected (Open Circuit)" as Disconnected
    state "Connected (Closed Circuit)" as Connected

    [*] --> Disconnected : Initial State (e.g., Martensite)
    Disconnected --> Connected : Apply Thermal/Electrical Stimulus (Austenite Transition)
    Connected --> Disconnected : Remove Stimulus / Reverse Stimulus (Martensite Transition)
    Disconnected --> Disconnected : Maintain Disconnected
    Connected --> Connected : Maintain Connected

    state "Forming Via" as Forming
    [*] --> Forming
    Forming --> Disconnected : SMA Via Formation Complete

Derivative 5.3: Diagnostic Vias with Integrated Impedance Monitoring for Predictive Maintenance

• Enabling Description: A first semiconductor device, a high-performance computing (HPC) processor on a silicon substrate, is provided. Via-holes are formed through the substrate using plasma etching. A multi-layered first pad, incorporating a resistive sensing element (e.g., a thin film of highly doped polysilicon) beneath a standard copper contact layer, is patterned on the first side, covering the first opening and electrically connecting to internal diagnostic circuitry. Subsequently, a copper via structure is electroplated into the via-hole, adjoined to the copper contact layer of the pad. The embedded resistive sensing element continuously monitors the impedance of the via structure and its interface, providing real-time data to a built-in self-test (BIST) engine. Any drift or abrupt change in impedance signals potential degradation or impending failure of the via, enabling predictive maintenance. The first HPC device is then vertically integrated with a second high-bandwidth memory (HBM) device using micro-bump bonding, with the diagnostic data communicated over a sideband channel.
• Combination Prior Art: This derivative integrates the patent's method with IEEE 1149.6 (Boundary-Scan Test for Advanced Digital Networks) for fault isolation, JEDEC JESD47I (Stress-Test-Driven Qualification of Integrated Circuits) for reliability assessment, and OpenTelemetry for standardized collection of diagnostic data.

graph TD
    A[Start] --> B(Provide HPC Processor on Silicon Substrate)
    B --> C{Form Via-Holes via Plasma Etching}
    C --> D(Form Multi-Layered First Pad with Resistive Sensing Element & Cu Contact)
    D --> E(Electroplate Copper into Via-Hole)
    E --> F(Form Copper Via Structure adjoined to Cu Contact Layer)
    F --> G(Embedded Resistive Sensing Element Monitors Via Impedance)
    G --> H(Data to BIST Engine for Predictive Maintenance)
    F --> I(Vertically Integrate with Second HBM Device via Micro-Bump Bonding)
    I --> J[End]

Derivative 5.4: Low-Power/Limited-Functionality Standby Vias via Photo-Patternable Conductive Inks

• Enabling Description: The method provides a first semiconductor device, a low-power microcontroller unit (MCU) on a flexible thin-film polymer substrate. Via-holes are formed through the polymer substrate using UV laser ablation. A first pad, comprising a photo-patternable silver nanoparticle ink, is deposited and UV-cured on the first side, covering the first opening and connecting to the MCU's low-power I/O. Subsequently, a via structure is formed in the via-hole by injecting a different photo-patternable conductive carbon nanotube (CNT) ink, which is then selectively UV-cured to achieve a desired, lower conductivity, optimized for limited-functionality standby modes. This CNT ink forms a via structure adjoined to the silver nanoparticle pad. The selective curing allows for control over the electrical resistance, enabling a "sleep" mode where only essential, low-bandwidth communication occurs. The first MCU device is then vertically integrated with a second low-power sensor array device using a pressure-sensitive adhesive.
• Combination Prior Art: This derivative utilizes Energy Star standards for low-power electronics, MIPI Alliance specifications for low-power mobile interfaces, and the Apache Kafka platform for streaming data during diagnostics.

graph TD
    A[Start] --> B(Provide Low-Power MCU on Flexible Thin-Film Polymer Substrate)
    B --> C{Form Via-Holes via UV Laser Ablation}
    C --> D(Deposit & UV-Cure Photo-Patternable Silver Nanoparticle Ink for First Pad)
    D --> E(Inject Photo-Patternable Conductive CNT Ink into Via-Hole)
    E --> F(Selectively UV-Cure CNT Ink for Desired Low Conductivity)
    F --> G(Form Low-Power Via Structure adjoined to Silver Nanoparticle Pad)
    G --> H(Vertically Integrate with Second Low-Power Sensor Array via PSA)
    H --> I[End]

    subgraph Operation Modes
        J(Normal Operation) --> G
        K(Low-Power/Limited-Functionality Standby) --> F
    end