Derivative works — US Patent 9275982

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Defensive Disclosure Document for US Patent 9275982
Date: April 26, 2026
Patent Title: Method of forming interconnection structure of package structure
Inventors: Chia-Yen Lee, Hsin-Chang Tsai, Peng-Hsin LEE
Assignee: Mare Infinitus Technologies LLC (Current), Delta Electronics Inc (Original)
Priority Date: November 13, 2012

This document describes various derivative works and technical disclosures related to the core claims of US Patent 9275982, specifically focusing on Independent Claim 1, with the intent to establish prior art for future incremental improvements by competitors. The derivatives explore alternative materials, operational parameters, cross-domain applications, integration with emerging technologies, and failure modes, aiming to render such advancements obvious to a person having ordinary skill in the art (PHOSITA).

Derivatives of Independent Claim 1: Method of forming a package structure

Claim 1: A method of forming a package structure comprising: providing a first semiconductor device having a first side and a second side opposite to the first side; forming a via-hole through the first semiconductor device, wherein the via-hole has a first opening neighboring the first side and a second opening neighboring the second side; forming a first pad covering the first opening; forming a via structure in the via-hole subsequent to forming the first pad, wherein the via structure comprises a conductive material and is adjoined to the first pad; and substantially vertically integrating the first semiconductor device with a second semiconductor device. [cite: Claims (10) What is claimed is: 1. A method of forming a package structure comprising: providing a first semiconductor device having a first side and a second side opposite to to the first side; forming a via-hole through the first semiconductor device, wherein the via-hole has a first opening neighboring the first side and a second opening neighboring the second side; forming a first pad covering the first opening; forming a via structure in the via-hole subsequent to forming the first pad, wherein the via structure comprises a conductive material and is adjoined to the first pad; and substantially vertically integrating the first semiconductor device with a second semiconductor device.]

1. Material & Component Substitution

Derivative 1.1: Polymer-Substrate GaN HEMT with Conductive Polymer Via and Graphene Pad

Enabling Description: The method comprises providing a first semiconductor device comprising a flexible polymer substrate (e.g., polyimide or PEN) with an integrated Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) electronic device. A tapered via-hole is formed through the polymer substrate using femtosecond laser ablation, having openings on the first and second sides. A first pad consisting of multiple layers of chemically vapor deposited (CVD) graphene is patterned on the first side, covering the first opening and making contact with the HEMT's source electrode. Subsequently, a highly conductive polymer composite (e.g., silver nanoparticle-filled epoxy or polyaniline) is injected into the via-hole using a micro-dispensing system and cured, forming a via structure that electrically adjoins the graphene pad. The first semiconductor device is then vertically integrated with a second semiconductor device (e.g., a silicon-based power management IC) via anisotropic conductive film (ACF) bonding. The graphene pad serves as a local conductive path during the polymer injection, ensuring electrical continuity.
Combination Prior Art: This derivative combines the method of US9275982 with the JEDEC JESD22-A104E standard for temperature cycling for reliability testing of flexible electronic packages, IPC-TR-484 for conductive polymer materials and processes, and IEEE 802.15.4 (Zigbee) for integrated low-power wireless communication in the stacked package.

graph TD
    A[Start] --> B(Provide Flexible Polymer Substrate with GaN HEMT)
    B --> C{Form Tapered Via-Hole via Femtosecond Laser Ablation}
    C --> D(Form Graphene Pad on First Side covering First Opening)
    D --> E(Inject Conductive Polymer Composite into Via-Hole)
    E --> F(Cure Polymer to form Via Structure adjoined to Graphene Pad)
    F --> G(Vertically Integrate with Second Semiconductor Device via ACF Bonding)
    G --> H[End]

Derivative 1.2: Silicon Carbide Power Device with Tungsten Via and Sintered Copper Paste Pad

Enabling Description: A first semiconductor device comprising a high-voltage Silicon Carbide (SiC) MOSFET on a SiC substrate is provided. A cylindrical via-hole with a high aspect ratio (e.g., 20:1) is formed through the SiC substrate using deep reactive ion etching (DRIE). A first pad is formed on the first side by screen-printing a copper nanoparticle paste over the first opening and sintering it at 800°C in a reducing atmosphere to form a dense, highly conductive copper layer. This sintered copper pad acts as the seed layer for subsequent via formation. A via structure consisting of electroplated tungsten (W) is then deposited within the via-hole, completely filling it and robustly adjoining the sintered copper pad. The tungsten plating solution utilizes a non-aqueous electrolyte to prevent SiC degradation. The first SiC device is then vertically integrated with a second semiconductor device (e.g., a silicon driver IC) using transient liquid phase (TLP) bonding.
Combination Prior Art: This derivative incorporates aspects of SEMI M1-0315 (Specification for Polished Monocrystalline Silicon Wafers) for substrate characteristics, IPC-2221B (Generic Standard on Printed Board Design) for pad layout considerations, and ISO 26262 (Road vehicles — Functional safety) for power electronics reliability requirements in automotive applications.

graph TD
    A[Start] --> B(Provide SiC Substrate with High-Voltage SiC MOSFET)
    B --> C{Form High-Aspect-Ratio Cylindrical Via-Hole via DRIE}
    C --> D(Screen-Print Copper Nanoparticle Paste over First Opening)
    D --> E(Sinter Copper Paste at 800°C to form Conductive Pad)
    E --> F(Electroplate Tungsten into Via-Hole using Sintered Pad as Seed)
    F --> G(Vertically Integrate with Second Semiconductor Device via TLP Bonding)
    G --> H[End]

Derivative 1.3: Ferroelectric Transistor on SOI with Electroless Plated Silver Via and Indium-Tin-Oxide (ITO) Seed Layer

Enabling Description: A first semiconductor device comprising a Silicon-on-Insulator (SOI) substrate with integrated ferroelectric field-effect transistors (FeFETs) is provided. A via-hole is formed through the SOI substrate using focused ion beam (FIB) milling. A transparent conductive first pad, comprising a sputtered and patterned Indium-Tin-Oxide (ITO) film, is deposited on the first side, covering the first opening and electrically contacting the FeFETs. Subsequently, an electroless silver plating process is initiated, utilizing the ITO film as a catalytic surface for the deposition of a pure silver via structure within the via-hole. The electroless plating ensures conformal filling of complex via geometries. The resulting silver via structure is adjoined to the ITO pad. The first semiconductor device is then vertically integrated with a second semiconductor device (e.g., an optical sensor array) through a low-temperature thermocompression bonding process, allowing for optical transparency through the ITO layers if desired.
Combination Prior Art: This derivative leverages the SEMI M79-0210 (Specification for Silicon-On-Insulator Wafers), ASTM B657-05 (Standard Practice for Metallographic Sample Preparation for Light Metals and Their Alloys) for material characterization, and the Khronos Group OpenVX standard for vision processing acceleration in the stacked optical system.

graph TD
    A[Start] --> B(Provide SOI Substrate with FeFETs)
    B --> C{Form Via-Hole via FIB Milling}
    C --> D(Sputter & Pattern ITO Film for First Pad on First Side)
    D --> E(Perform Electroless Silver Plating using ITO Pad as Catalytic Surface)
    E --> F(Form Silver Via Structure adjoined to ITO Pad)
    F --> G(Vertically Integrate with Second Semiconductor Device via Low-Temp Thermocompression)
    G --> H[End]

2. Operational Parameter Expansion

Derivative 2.1: Nanoscale 3D Stack with Ultra-High Aspect Ratio Vias (UHARV)

Enabling Description: The method involves providing a first semiconductor device, a three-dimensional integrated circuit (3DIC) module, featuring active layers on a silicon substrate. Ultra-high aspect ratio via-holes (e.g., 100:1 aspect ratio, 50nm diameter) are patterned and etched through the silicon substrate using atomic layer etching (ALE) followed by aspect ratio dependent etching (ARDE) minimization techniques. A sub-micron platinum (Pt) first pad is formed by atomic layer deposition (ALD) and subsequent focused ion beam (FIB) patterning on the first side, covering the nanoscale first opening and connecting to internal circuitry. Subsequently, a low-temperature chemical vapor deposition (LTCVD) of ruthenium (Ru) is performed to form the via structure, ensuring void-free filling of the UHARV and adhesion to the Pt pad. This process occurs under ultra-high vacuum conditions at reduced temperatures (e.g., 200°C). The first device is then vertically integrated with a second 3DIC semiconductor device using direct copper-to-copper bonding, enabling high-density, low-latency interconnections for quantum computing applications.
Combination Prior Art: This derivative incorporates concepts from IEEE P2844 (Standard for Microelectronics Interconnect Reliability), SEMI E10-0318 (Standard for Definition and Measurement of Equipment Reliability, Availability, and Maintainability (RAM) for Semiconductor Manufacturing Equipment), and the GlobalFoundries 22FDX manufacturing process for advanced node characteristics.

graph TD
    A[Start] --> B(Provide 3DIC Silicon Substrate)
    B --> C{Pattern & Etch UHARV via ALE/ARDE (50nm diameter, 100:1 AR)}
    C --> D(Form Platinum First Pad via ALD/FIB on First Side)
    D --> E(Perform Low-Temperature CVD of Ruthenium into UHARV)
    E --> F(Form Ruthenium Via Structure adjoined to Platinum Pad)
    F --> G(Vertically Integrate with Second 3DIC Device via Direct Cu-to-Cu Bonding)
    G --> H[End]

Derivative 2.2: Extreme Temperature Operation (Cryogenic) Package with Superconducting Vias

Enabling Description: A first semiconductor device, designed for cryogenic operation (e.g., 4K), is provided on a high-purity silicon substrate with integrated Josephson Junction circuitry. A via-hole is formed through the substrate using reactive ion etching (RIE). A first pad, composed of a multi-layered NbN/TiN superconducting film, is deposited on the first side using magnetron sputtering and patterned to cover the first opening. Subsequently, a via structure is formed in the via-hole by filling it with an amorphous superconducting alloy (e.g., MoGe) via pulsed laser deposition (PLD) at low temperatures (e.g., -150°C), ensuring electrical contact with the NbN/TiN pad. The entire fabrication and integration process is performed within a cryogenic chamber, ensuring that the superconducting properties are maintained. The first device is then vertically integrated with a second cryogenic semiconductor device (e.g., a SQUID array) using indium bump bonding in a vacuum.
Combination Prior Art: This derivative combines the methodology with NIST FIPS 180-4 (Secure Hash Standard) for cryptographic circuit integration, IEC 60747-16-1 (Semiconductor devices — Part 16-1: Microwave integrated circuits — Mesfet integrated circuits) for advanced device characterization, and the Quantum Leap Institute's QIS roadmap for future quantum computing interconnect requirements.

graph TD
    A[Start] --> B(Provide High-Purity Si Substrate with Josephson Junctions)
    B --> C{Form Via-Hole via RIE}
    C --> D(Deposit NbN/TiN Superconducting First Pad via Sputtering)
    D --> E(Fill Via-Hole with MoGe Superconducting Alloy via PLD at -150°C)
    E --> F(Form MoGe Via Structure adjoined to NbN/TiN Pad)
    F --> G(Vertically Integrate with Second Cryogenic Device via Indium Bump Bonding)
    G --> H[End]

Derivative 2.3: High-Frequency (THz) Interposer with Low-Loss Graphene-Lined Vias

Enabling Description: The method involves providing a first semiconductor device acting as a high-frequency interposer on a low-permittivity glass substrate. Via-holes, designed for minimal skin effect at THz frequencies, are formed through the glass substrate using ultrasonic drilling. A low-resistance first pad, consisting of a few-layer graphene sheet grown via CVD and transferred onto the first side, is patterned to cover the first opening. An ultra-thin insulating layer (e.g., h-BN) is then applied to the via sidewalls. Subsequently, a conformal via structure of highly pure copper is electroplated onto the graphene liner within the via-hole, using the graphene pad as the seed layer. The copper is deposited to a specific thickness (e.g., 500 nm) to optimize impedance matching and minimize loss at THz frequencies. The first interposer is then vertically integrated with a second semiconductor device (e.g., a SiGe HBT array) using direct metal-to-metal bonding under vacuum, ensuring minimal parasitic capacitance and inductance.
Combination Prior Art: This derivative integrates the method with IEEE 1149.1 (JTAG) for boundary-scan testing, ANSI/IPC-TM-650 (Test Methods Manual) for material and electrical testing, and the 5G NR standard for high-frequency communication protocols and testing procedures.

graph TD
    A[Start] --> B(Provide Low-Permittivity Glass Substrate for Interposer)
    B --> C{Form Via-Holes via Ultrasonic Drilling for THz Frequencies}
    C --> D(Transfer & Pattern Few-Layer Graphene Sheet for First Pad)
    D --> E(Apply h-BN Insulating Layer to Via Sidewalls)
    E --> F(Electroplate High-Purity Copper onto Graphene Liner using Graphene Pad as Seed)
    F --> G(Vertically Integrate with Second SiGe HBT Array via Direct Metal-to-Metal Bonding)
    G --> H[End]

3. Cross-Domain Application

Derivative 3.1: Bio-Integrated Flexible Neural Interface with Microporous Substrate and Conductive Hydrogel Vias

Enabling Description: A first semiconductor device comprising a flexible bio-compatible polymer (e.g., parylene-C) substrate with integrated neural sensing/stimulation electrodes is provided. Microporous via-holes are formed through the parylene-C substrate using excimer laser micromachining, allowing for tissue ingrowth. A first pad, composed of a sputtered iridium oxide film, is patterned on the first side, covering the microporous opening and connecting to the neural electrodes. Subsequently, a conductive hydrogel (e.g., alginate functionalized with carbon nanotubes) is injected into the via-hole, forming a bio-compatible via structure that adjoins the iridium oxide pad. This injection can be pressure-assisted for uniform filling. The first neural interface device is then vertically integrated with a second semiconductor device (e.g., a low-power ASIC for signal processing) using a soft lithography technique with a flexible elastomeric interconnect, suitable for long-term implantable applications.
Combination Prior Art: This derivative uses ISO 10993 (Biological evaluation of medical devices) for biocompatibility, ASTM F2129-08 (Standard Test Method for Conducting Cyclic Potentiodynamic Polarization Measurements to Determine the Corrosion Susceptibility of Small Implantable Medical Devices) for electrochemical stability, and the OpenBCI GUI for data visualization and control of neural signals.

graph TD
    A[Start] --> B(Provide Flexible Bio-compatible Parylene-C Substrate with Neural Electrodes)
    B --> C{Form Microporous Via-Holes via Excimer Laser Micromachining}
    C --> D(Sputter & Pattern Iridium Oxide Film for First Pad)
    D --> E(Inject Conductive Hydrogel into Via-Hole)
    E --> F(Form Hydrogel Via Structure adjoined to Iridium Oxide Pad)
    F --> G(Vertically Integrate with Second ASIC Device via Elastomeric Interconnect)
    G --> H[End]

Derivative 3.2: High-Power Automotive Inverter Module with Segmented Copper Pillars and Brazed Silver Pads

Enabling Description: A first semiconductor device comprising a multi-chip module (MCM) for an automotive power inverter, featuring SiC power MOSFETs on a ceramic (AlN) substrate, is provided. Large-diameter, segmented via-holes are formed through the AlN substrate using abrasive waterjet cutting, designed for high current handling and thermal dissipation. A first pad, consisting of a brazed silver layer, is formed on the first side, covering the segmented openings and contacting the power MOSFETs. Subsequently, pre-formed copper pillars are inserted into the via-holes and then brazed into place, creating a solid via structure that is robustly adjoined to the silver pad. The brazing process uses a low-melting point active brazing alloy (ABA) for strong metallurgical bonds. The first inverter module is then vertically integrated with a second semiconductor device (e.g., a motor control MCU) using high-temperature solder reflow, forming a compact, high-reliability power module for electric vehicles.
Combination Prior Art: This derivative integrates the methodology with AEC-Q100 (Failure Mechanism Based Stress Test Qualification for Packaged Integrated Circuits) for automotive reliability, IEC 60068-2-14 (Environmental testing — Part 2-14: Tests — Test N: Change of temperature) for thermal shock testing, and AUTOSAR (Automotive Open System Architecture) for software and hardware interface standardization.

graph TD
    A[Start] --> B(Provide MCM with SiC Power MOSFETs on AlN Substrate)
    B --> C{Form Large-Diameter, Segmented Via-Holes via Waterjet Cutting}
    C --> D(Form Brazed Silver Layer for First Pad)
    D --> E(Insert Pre-Formed Copper Pillars into Via-Holes)
    E --> F(Braze Copper Pillars to form Via Structure adjoined to Silver Pad)
    F --> G(Vertically Integrate with Second MCU Device via High-Temp Solder Reflow)
    G --> H[End]

Derivative 3.3: Space-Grade Photovoltaic Array with Radiation-Hardened Substrate and Polymer-Filled Carbon Nanotube Vias

Enabling Description: A first semiconductor device comprising a triple-junction gallium arsenide (GaAs) photovoltaic cell array on a radiation-hardened silicon-germanium (SiGe) substrate is provided. Via-holes are formed through the SiGe substrate using inductively coupled plasma (ICP) etching. A first pad, composed of a sputtered platinum-iridium (Pt-Ir) alloy, is patterned on the first side, covering the first opening and contacting the PV cell electrodes. Subsequently, vertically aligned carbon nanotube (CNT) bundles are grown within the via-hole using CVD, and then infiltrated with a radiation-resistant epoxy polymer to form a robust and conductive via structure that adjoins the Pt-Ir pad. The polymer infiltration enhances mechanical stability under thermal cycling in space. The first PV cell array is then vertically integrated with a second semiconductor device (e.g., a maximum power point tracking (MPPT) controller) using a direct bond interconnection technique, forming a compact, radiation-tolerant power source for satellites.
Combination Prior Art: This derivative draws upon MIL-STD-883 (Test Method Standard Microcircuits) for space-grade reliability and radiation hardness, ECSS-Q-ST-60-13C (Space product assurance — Susceptibility of electronic components to radiation) for radiation testing protocols, and the SPDX (Software Package Data Exchange) standard for open-source software component tracking in the MPPT controller.

graph TD
    A[Start] --> B(Provide Triple-Junction GaAs PV Cell on Radiation-Hardened SiGe Substrate)
    B --> C{Form Via-Holes via ICP Etching}
    C --> D(Sputter & Pattern Pt-Ir Alloy for First Pad)
    D --> E(Grow CNT Bundles in Via-Hole & Infiltrate with Radiation-Resistant Epoxy)
    E --> F(Form CNT-Polymer Via Structure adjoined to Pt-Ir Pad)
    F --> G(Vertically Integrate with Second MPPT Controller via Direct Bond)
    G --> H[End]

4. Integration with Emerging Tech

Derivative 4.1: AI-Optimized Adaptive Electroplating for Heterogeneous Stacks

Enabling Description: The method provides a first semiconductor device, a heterogeneous integration module comprising Si-based logic and InP-based photonic devices on a silicon interposer. Via-holes are formed through the interposer using plasma etching. A first pad, composed of a sputtered titanium/copper seed layer, is patterned on the first side, covering the first opening. Subsequently, an AI-driven electroplating system, utilizing real-time impedance spectroscopy and scanning electron microscopy (SEM) feedback, adaptively controls the current density, electrolyte composition, and temperature to form a copper via structure. The AI algorithm optimizes for uniform filling, minimal void formation, and desired grain structure based on the specific material stack and desired electrical properties, ensuring precise adjacency to the first pad. This adaptive electroplating process dynamically compensates for variations in via geometry and material properties. The first device is then vertically integrated with a second semiconductor device (e.g., a 3D NAND memory stack) using thermocompression bonding, with the AI system further optimizing bonding parameters for maximum yield.
Combination Prior Art: This derivative integrates the patent's method with OpenAI Gym for reinforcement learning environment design in manufacturing, SEMI E173-0917 (Specification for Manufacturing Execution System (MES) Data Collection and Integration), and ISA-95 (Enterprise-Control System Integration) for manufacturing operation management.

graph TD
    A[Start] --> B(Provide Si/InP Heterogeneous Interposer)
    B --> C{Form Via-Holes via Plasma Etching}
    C --> D(Sputter & Pattern Ti/Cu Seed Layer for First Pad)
    D --> E{AI-Driven Adaptive Electroplating System}
    E --> F(Real-time Impedance/SEM Feedback)
    F --> G(Adjust Electroplating Parameters: Current, Electrolyte, Temp)
    G --> H(Form Copper Via Structure adjoined to First Pad)
    H --> I(Vertically Integrate with Second 3D NAND Stack via Thermocompression)
    I --> J[End]

Derivative 4.2: IoT-Enabled Smart Package with Integrated Environmental Sensors and Self-Healing Vias

Enabling Description: A first semiconductor device comprising a processor die with embedded IoT sensors (e.g., temperature, humidity, strain) on a flexible substrate is provided. Via-holes are formed through the substrate using laser drilling. A first pad, composed of a patterned nickel-gold (Ni/Au) alloy, is deposited on the first side, covering the first opening and connecting to the embedded sensors. Subsequently, a self-healing conductive composite material (e.g., a copper/polymer matrix with microencapsulated healing agents) is introduced into the via-hole via capillary action, forming a via structure that adjoins the Ni/Au pad. This self-healing material is designed to repair micro-cracks or voids that may develop during operation or thermal cycling, extending device lifetime. The embedded IoT sensors monitor the package's internal environment and communicate via a low-power wireless protocol (e.g., Bluetooth Low Energy). The first device is then vertically integrated with a second semiconductor device (e.g., a battery management unit) using solder paste printing and reflow.
Combination Prior Art: This derivative utilizes MQTT (Message Queuing Telemetry Transport) for IoT communication, IEC 62368-1 (Audio/video, information and communication technology equipment – Safety requirements) for product safety, and FIWARE NGSI-LD API for context information management in smart environments.

graph TD
    A[Start] --> B(Provide Processor Die with Embedded IoT Sensors on Flexible Substrate)
    B --> C{Form Via-Holes via Laser Drilling}
    C --> D(Deposit Ni/Au Alloy for First Pad)
    D --> E(Introduce Self-Healing Conductive Composite into Via-Hole via Capillary Action)
    E --> F(Form Self-Healing Via Structure adjoined to Ni/Au Pad)
    F --> G(Vertically Integrate with Second Battery Management Unit via Solder Reflow)
    G --> H[End]

    subgraph IoT Sensing & Healing Control
        Sensor[IoT Sensors (Temp, Humidity, Strain)] --> Wireless[Bluetooth LE Wireless Communication]
        Wireless --> Healing[Self-Healing Activation Logic]
        Healing --> E
    end

Derivative 4.3: Blockchain-Verified Supply Chain for High-Security Device Interconnections

Enabling Description: The method involves providing a first semiconductor device, a trusted platform module (TPM) on a silicon substrate, requiring verifiable component authenticity. Via-holes are formed through the substrate using conventional etching. A first pad, composed of a certified gold (Au) film, is deposited on the first side, covering the first opening. Subsequently, a via structure of certified tungsten is formed in the via-hole using chemical vapor deposition (CVD), adjoined to the gold pad. Each critical manufacturing step (substrate sourcing, via-hole etching, pad deposition, via structure formation, and material certification) is digitally signed and recorded on a secure blockchain ledger, providing an immutable audit trail for supply chain verification. This ensures the integrity and authenticity of the interconnection components. The first TPM device is then vertically integrated with a second high-security cryptographic processor using cold welding in a cleanroom, with the integration process also recorded on the blockchain.
Combination Prior Art: This derivative leverages Hyperledger Fabric for permissioned blockchain network implementation, NIST SP 800-193 (Platform Firmware Resiliency Guidelines) for hardware root of trust, and ISO/IEC 15408 (Common Criteria) for security evaluation of information technology products.

sequenceDiagram
    participant S as Substrate Mfg
    participant V as Via-Hole Mfg
    participant P as Pad Mfg
    participant VS as Via Structure Mfg
    participant I as Integration
    participant B as Blockchain Ledger

    S->>V: Provide Si Substrate (Certified Origin)
    V->>B: Record Via-Hole Etch Parameters (TxHash1)
    V->>P: Via-Hole with First Opening
    P->>B: Record Gold Pad Deposition (TxHash2)
    P->>VS: Gold Pad covering First Opening
    VS->>B: Record Tungsten CVD Parameters (TxHash3)
    VS->>I: Tungsten Via Structure adjoined to Gold Pad
    I->>B: Record Vertical Integration (TxHash4)
    B-->>I: Verification Complete
    I->>I: Integrate with Second Cryptographic Processor

5. The "Inverse" or Failure Mode

Derivative 5.1: Sacrificial Thermally-Activated Vias for Overcurrent Protection

Enabling Description: The method provides a first semiconductor device, a power delivery module on a ceramic substrate. Via-holes are formed through the substrate using laser drilling. A first pad, composed of a copper-bismuth (CuBi) alloy (chosen for its low melting point), is deposited on the first side, covering the first opening and connecting to the power lines. Subsequently, a via structure is formed in the via-hole by filling it with a eutectic low-melting point solder alloy (e.g., SnBiAg) via injection and reflow, forming a sacrificial interconnection adjoined to the CuBi pad. Upon detection of an overcurrent condition causing localized heating above the eutectic temperature, the solder via structure is designed to melt and intentionally disconnect, acting as a microscopic fuse to protect downstream components. The first device is then vertically integrated with a second semiconductor device (e.g., a high-current switch) using standard lead-free solder interconnects.
Combination Prior Art: This derivative uses UL 248 (Low-Voltage Fuses) for safety standards, IEC 60127 (Miniature fuses) for fuse characteristics, and SEMI F47-0706 (Specification for Semiconductor Processing Equipment Voltage Sag Immunity) for power disturbance tolerance.

graph TD
    A[Start] --> B(Provide Power Delivery Module on Ceramic Substrate)
    B --> C{Form Via-Holes via Laser Drilling}
    C --> D(Deposit Copper-Bismuth Alloy for First Pad)
    D --> E(Inject & Reflow Eutectic Solder Alloy into Via-Hole)
    E --> F(Form Sacrificial Solder Via Structure adjoined to CuBi Pad)
    F --> G(Vertically Integrate with Second High-Current Switch)
    G --> H[End]

    subgraph Failure Mode
        I(Overcurrent Detected) --> J(Localized Heating)
        J --> K(Solder Via Melts)
        K --> L(Disconnection - Circuit Protection)
    end

Derivative 5.2: Reversible Shape Memory Alloy (SMA) Vias for Reconfigurable Packages

Enabling Description: A first semiconductor device, a reconfigurable computing module on a silicon interposer, is provided. Via-holes are formed through the interposer using anisotropic etching. A first pad, composed of a sputtered gold (Au) film, is patterned on the first side, covering the first opening. Subsequently, a shape memory alloy (SMA) (e.g., NiTi or CuAlNi) is electroplated into the via-hole to form a via structure that adjoins the gold pad. The SMA material is designed to transition between a conductive and non-conductive state (or open/closed circuit) by applying specific thermal or electrical stimuli, allowing for reversible disconnection and reconnection of vertical interconnections for package reconfiguration or repair. The phase transition temperature of the SMA is precisely controlled. The first device is then vertically integrated with a second reconfigurable logic device using a compliant polymer interface, allowing for slight mechanical flexure during SMA actuation.
Combination Prior Art: This derivative leverages ASTM F2063-18 (Standard Specification for Wrought Nickel-Titanium Shape Memory Alloys for Medical Devices and General Engineering Applications), IPC-7095C (Design and Assembly Process Implementation for Flip Chip and Wafer Level Chip Scale Technologies) for advanced packaging, and IEEE 1801 (UPF - Unified Power Format) for power domain management in reconfigurable systems.

stateDiagram-v2
    state "Disconnected (Open Circuit)" as Disconnected
    state "Connected (Closed Circuit)" as Connected

    [*] --> Disconnected : Initial State (e.g., Martensite)
    Disconnected --> Connected : Apply Thermal/Electrical Stimulus (Austenite Transition)
    Connected --> Disconnected : Remove Stimulus / Reverse Stimulus (Martensite Transition)
    Disconnected --> Disconnected : Maintain Disconnected
    Connected --> Connected : Maintain Connected

    state "Forming Via" as Forming
    [*] --> Forming
    Forming --> Disconnected : SMA Via Formation Complete

Derivative 5.3: Diagnostic Vias with Integrated Impedance Monitoring for Predictive Maintenance

Enabling Description: A first semiconductor device, a high-performance computing (HPC) processor on a silicon substrate, is provided. Via-holes are formed through the substrate using plasma etching. A multi-layered first pad, incorporating a resistive sensing element (e.g., a thin film of highly doped polysilicon) beneath a standard copper contact layer, is patterned on the first side, covering the first opening and electrically connecting to internal diagnostic circuitry. Subsequently, a copper via structure is electroplated into the via-hole, adjoined to the copper contact layer of the pad. The embedded resistive sensing element continuously monitors the impedance of the via structure and its interface, providing real-time data to a built-in self-test (BIST) engine. Any drift or abrupt change in impedance signals potential degradation or impending failure of the via, enabling predictive maintenance. The first HPC device is then vertically integrated with a second high-bandwidth memory (HBM) device using micro-bump bonding, with the diagnostic data communicated over a sideband channel.
Combination Prior Art: This derivative integrates the patent's method with IEEE 1149.6 (Boundary-Scan Test for Advanced Digital Networks) for fault isolation, JEDEC JESD47I (Stress-Test-Driven Qualification of Integrated Circuits) for reliability assessment, and OpenTelemetry for standardized collection of diagnostic data.

graph TD
    A[Start] --> B(Provide HPC Processor on Silicon Substrate)
    B --> C{Form Via-Holes via Plasma Etching}
    C --> D(Form Multi-Layered First Pad with Resistive Sensing Element & Cu Contact)
    D --> E(Electroplate Copper into Via-Hole)
    E --> F(Form Copper Via Structure adjoined to Cu Contact Layer)
    F --> G(Embedded Resistive Sensing Element Monitors Via Impedance)
    G --> H(Data to BIST Engine for Predictive Maintenance)
    F --> I(Vertically Integrate with Second HBM Device via Micro-Bump Bonding)
    I --> J[End]

Derivative 5.4: Low-Power/Limited-Functionality Standby Vias via Photo-Patternable Conductive Inks

Enabling Description: The method provides a first semiconductor device, a low-power microcontroller unit (MCU) on a flexible thin-film polymer substrate. Via-holes are formed through the polymer substrate using UV laser ablation. A first pad, comprising a photo-patternable silver nanoparticle ink, is deposited and UV-cured on the first side, covering the first opening and connecting to the MCU's low-power I/O. Subsequently, a via structure is formed in the via-hole by injecting a different photo-patternable conductive carbon nanotube (CNT) ink, which is then selectively UV-cured to achieve a desired, lower conductivity, optimized for limited-functionality standby modes. This CNT ink forms a via structure adjoined to the silver nanoparticle pad. The selective curing allows for control over the electrical resistance, enabling a "sleep" mode where only essential, low-bandwidth communication occurs. The first MCU device is then vertically integrated with a second low-power sensor array device using a pressure-sensitive adhesive.
Combination Prior Art: This derivative utilizes Energy Star standards for low-power electronics, MIPI Alliance specifications for low-power mobile interfaces, and the Apache Kafka platform for streaming data during diagnostics.

graph TD
    A[Start] --> B(Provide Low-Power MCU on Flexible Thin-Film Polymer Substrate)
    B --> C{Form Via-Holes via UV Laser Ablation}
    C --> D(Deposit & UV-Cure Photo-Patternable Silver Nanoparticle Ink for First Pad)
    D --> E(Inject Photo-Patternable Conductive CNT Ink into Via-Hole)
    E --> F(Selectively UV-Cure CNT Ink for Desired Low Conductivity)
    F --> G(Form Low-Power Via Structure adjoined to Silver Nanoparticle Pad)
    G --> H(Vertically Integrate with Second Low-Power Sensor Array via PSA)
    H --> I[End]

    subgraph Operation Modes
        J(Normal Operation) --> G
        K(Low-Power/Limited-Functionality Standby) --> F
    end

This comprehensive defensive disclosure aims to cover a broad range of permutations and combinations of the claimed method, using varied materials, extreme operational conditions, diverse applications, integration with cutting-edge technologies, and considerations for failure modes and alternative functionalities. Each derivative is described with sufficient technical detail to enable a PHOSITA to implement it, thereby strengthening its standing as prior art.This document details defensive disclosures and derivative works for US Patent 9275982, focusing on expanding the scope of its independent claim to encompass numerous variations that would be obvious to a person having ordinary skill in the art (PHOSITA). The goal is to preemptively establish prior art against potential future incremental innovations by competitors.

The core of US Patent 9275982's independent Claim 1 involves a method for forming a package structure, including: providing a first semiconductor device, forming a via-hole, forming a first pad covering the first opening, forming a via structure in the via-hole subsequent to forming the first pad (where the via structure is conductive and adjoined to the first pad), and finally, substantially vertically integrating the first semiconductor device with a second semiconductor device. The patent highlights the advantage of using the first pad as a seed layer for electroplating the via structure, thereby avoiding costly vacuum deposition techniques. [cite: Claims (10) What is claimed is: 1. A method of forming a package structure comprising: providing a first semiconductor device having a first side and a second side opposite to to the first side; forming a via-hole through the first semiconductor device, wherein the via-hole has a first opening neighboring the first side and a second opening neighboring the second side; forming a first pad covering the first opening; forming a via structure in the via-hole subsequent to forming the first pad, wherein the via structure comprises a conductive material and is adjoined to the first pad; and substantially vertically integrating the first semiconductor device with a second semiconductor device.]