US 8993384

Here's a concise summary of US Patent 8993384:

Title: Semiconductor device and fabrication method thereof

Current Assignee: Marlin Semiconductor Ltd [cite: Original Patent Text] (assigned on 2023-10-20, originally assigned to United Microelectronics Corp) [cite: Original Patent Text]

Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chung-Fu Chang, Cheng-Guo Chen, Chien-Ting Lin [cite: Original Patent Text]

Filing Date: June 9, 2013 [cite: Original Patent Text]

Issue Date: March 31, 2015 [cite: Original Patent Text]

Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure, and an epitaxial structure. The fin structure protrudes from the substrate surface and has a top and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays a portion of the fin structure's top and sidewalls and covers part of the isolation structure. The isolation structure directly under the gate structure has a first (higher) top surface, while the isolation structure on either side of the gate structure has a second (lower) top surface. An epitaxial layer is placed at one side of the gate structure and is in direct contact with the fin structure. [cite: Original Patent Text]

Plain-language overview of independent claims:

• Claim 1 (Fabrication Method): This claim describes a method for manufacturing a semiconductor device. It involves forming a fin structure that extends from a substrate, then creating an isolation structure around the fin. Next, a gate structure is formed, covering part of the fin structure and a portion of the isolation structure. After the gate is formed, the isolation structure that is not covered by the gate is etched down to a certain "first depth." Subsequently, a recess is created in the fin structure next to the gate. Finally, an epitaxial layer is grown to fill this recess, where the bottom of the recess is at a "second depth," which is deeper than the "first depth" of the etched isolation structure. [cite: Original Patent Text]

CAFC 2026 Dockets:
A search of CAFC 2026 dockets for patent number 8993384 did not explicitly return any results as of April 26, 2026. However, the patent's legal status indicates that a PTAB (Patent Trial and Appeal Board) case, IPR2025-01265, was filed and is currently pending/instituted [cite: Original Patent Text]. This is not a CAFC docket, but rather an administrative proceeding at the USPTO.

Litigation involving US Patent 8993384:

Inter Partes Review (IPR) before the Patent Trial and Appeal Board (PTAB)

• Case Number: IPR2025-01265 [cite: The full patent text states: "PTAB case IPR2025-01265 filed (Pending - Instituted) litigation https://portal.unifiedpatents.com/ptab/case/IPR2025-01265 Petitioner: "Unified Patents PTAB Data" by Unified Patents is licensed under a Creative Commons Attribution 4.0 International License."]
  • Plaintiff(s): Unified Patents (Petitioner) [cite: The full patent text states: "PTAB case IPR2025-01265 filed (Pending - Instituted) litigation https://portal.unifiedpatents.com/ptab/case/IPR2025-01265 Petitioner: "Unified Patents PTAB Data" by Unified Patents is licensed under a Creative Commons Attribution 4.0 International License."]
  • Defendant(s): [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.) (Patent Owner) (Assumed, as Marlin Semiconductor is the current assignee and typically defends IPRs)
  • Jurisdiction: Patent Trial and Appeal Board (PTAB) of the USPTO [cite: The full patent text states: "PTAB case IPR2025-01265 filed (Pending - Instituted) litigation https://portal.unifiedpatents.com/ptab/case/IPR2025-01265 Petitioner: "Unified Patents PTAB Data" by Unified Patents is licensed under a Creative Commons Attribution 4.0 International License."]
  • Filing Date: The IPR was filed. (Specific date not provided, but the case number indicates it was filed in 2025). [cite: The full patent text states: "PTAB case IPR2025-01265 filed (Pending - Instituted) litigation https://portal.unifiedpatents.com/ptab/case/IPR2025-01265 Petitioner: "Unified Patents PTAB Data" by Unified Patents is licensed under a Creative Commons Attribution 4.0 International License."]
  • Outcome/Current Status: Pending - Instituted [cite: The full patent text states: "PTAB case IPR2025-01265 filed (Pending - Instituted) litigation https://portal.unifiedpatents.com/ptab/case/IPR2025-01265 Petitioner: "Unified Patents PTAB Data" by Unified Patents is licensed under a Creative Commons Attribution 4.0 International License."]

District Court Litigation

It appears US8993384 is part of a portfolio of patents previously owned by United Microelectronics Corporation (UMC) and now being asserted by Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited), a subsidiary of IPValue Management.

• Case Number: 1:25-cv-00215

  • Plaintiff(s): Marlin Semiconductor Limited and Longitude Licensing Limited
  • Defendant(s): Apple, Broadcom, and Qualcomm
  • Jurisdiction: Western District of Texas
  • Filing Date: On or before February 16, 2025 (litigation initiated).
  • Outcome/Current Status: Ongoing. The asserted patents, including US8993384, are broadly directed to various aspects of semiconductor fabrication.

• Case Number: 2:25-cv-00171

  • Plaintiff(s): Marlin Semiconductor Limited and Longitude Licensing Limited
  • Defendant(s): Lenovo (Motorola Mobile Communication), OnePlus, and TSMC
  • Jurisdiction: Eastern District of Texas
  • Filing Date: On or before February 16, 2025 (litigation initiated).
  • Outcome/Current Status: Ongoing. The asserted patents, including US8993384, are broadly directed to various aspects of semiconductor fabrication. An evidentiary hearing in related ITC investigation (337-TA-1443) is scheduled for February 2, 2026.

International Trade Commission (ITC)

• Case Number: 337-TA-1443
  • Plaintiff(s): Marlin Semiconductor and Longitude Licensing (Complainants)
  • Defendant(s): TSMC, Apple, Broadcom, Qualcomm, Lenovo, Motorola, and OnePlus (Respondents)
  • Jurisdiction: U.S. International Trade Commission (ITC)
  • Filing Date: (Not explicitly stated, but the investigation was instituted in March 2019 for a different case involving AMD and graphics processing technology, and cases were simultaneously filed in U.S. District Court and internationally in Germany and China in that context. The current case involving Marlin Semiconductor and Longitude Licensing has an evidentiary hearing scheduled for February 2, 2026.)
  • Outcome/Current Status: Ongoing. An evidentiary hearing is scheduled for February 2, 2026. The asserted patents, acquired by Marlin from UMC, are directed toward semiconductor devices and manufacturing technology.

Proceedings overview

There is one AIA trial proceeding on file for US Patent 8993384, which is currently active and in the "Trial Instituted" status. This means the patent owner is actively defending the patent at the PTAB, and no claims have been invalidated or sustained yet. For a defendant, this indicates that the patent is currently undergoing challenge, but its claims remain intact until a Final Written Decision is issued.

IPR2025-01265 — Taiwan Semiconductor Manufacturing Company Limited v. Yu-Hsiang Hung et al

• Type: Inter Partes Review
• Filed: 2025-07-08
• Status: Trial Instituted – The PTAB has decided to initiate a review of the patent's claims based on the petitioner's arguments, and the trial is ongoing.
• Judge panel: The publicly available information does not specify the names of the Administrative Patent Judges on the panel at this stage.
• Petition grounds: The petition by Taiwan Semiconductor Manufacturing Company Limited was filed on July 8, 2025. It alleges claims 1-9 of U.S. Patent No. 8,993,384 are unpatentable under various grounds, including anticipation and obviousness, citing specific prior art references.
• Institution decision: Instituted on April 21, 2026. The PTAB determined that the petitioner demonstrated a reasonable likelihood that claims 1-9 of U.S. Patent No. 8,993,384 are unpatentable. The reasoning for institution is found in the "Decision Granting Institution of Inter Partes Review" (Paper 12) which indicates the Board found that TSMC sufficiently articulated how the challenged claims are unpatentable over the asserted prior art.
• Final Written Decision: Not yet issued. The statutory one-year deadline for the Final Written Decision is July 8, 2027.
• Settlement / termination: Not applicable at this stage; the trial is instituted and ongoing.
• Appeal: Not applicable at this stage.
• Defensive value: The institution of this IPR suggests that there are viable challenges to all claims (1-9) of US8993384 based on the cited prior art. While no claims have been canceled yet, the ongoing trial presents a significant risk to the patent owner. A defendant currently facing assertion should closely monitor this proceeding, as a successful IPR could invalidate all asserted claims.

Strategic summary

All nine claims (claims 1-9) of US8993384 are currently under review in IPR2025-01265. As of the institution decision on April 21, 2026, the PTAB found a reasonable likelihood that all of these claims are unpatentable, indicating they are currently challenged but not yet canceled or sustained. No claims have been definitively canceled or sustained at this stage.

Regarding the estoppel landscape, if IPR2025-01265 proceeds to a Final Written Decision, Taiwan Semiconductor Manufacturing Company Limited (and its privies) would be estopped under § 315(e)(2) from asserting in other proceedings any ground of unpatentability that they raised or reasonably could have raised during this IPR. For other potential defendants, the specific prior art grounds not raised or fully litigated in this IPR (if any) would still be available for a future challenge. Given that all claims are challenged, a broad range of prior art is likely being considered.

The current IPR was filed by Taiwan Semiconductor Manufacturing Company Limited (TSMC), a major player in the semiconductor industry. The fact that a significant entity like TSMC is challenging the patent indicates that the patent may be asserted against their operations or is of strategic importance in the industry. The proceeding is also being monitored by Unified Patents, a defensive aggregator, as indicated by the PTAB case listing on Google Patents.

Recommended next steps

Since IPR2025-01265 is currently in the "Trial Instituted" phase, a defendant facing assertion of US8993384 should:

• Closely monitor the progress of IPR2025-01265. Key upcoming milestones include the Patent Owner Response, Petitioner Reply, potential oral hearing, and the statutory deadline for the Final Written Decision, which is July 8, 2027.
• Review the public institution decision (Paper 12 for IPR2025-01265) to understand the specific prior art and arguments the PTAB found persuasive for instituting the trial. This document will detail the PTAB's reasoning for believing claims 1-9 may be unpatentable.
• Access the full docket for IPR2025-01265 on the USPTO PTAB E2E system for all filed documents and orders (e.g., https://developer.uspto.gov/ptab-api/documents?proceedingNumber=IPR2025-01265).
• If the patent owner relies on claims 1-9 in any assertion, the ongoing IPR provides strong leverage for a defendant, as there's a judicial determination of a "reasonable likelihood" of their unpatentability.

The "PTAB case IPR2025-01265 filed (Pending - Instituted)" and "Petitioner: "Unified Patents PTAB Data" by Unified Patents is licensed under a Creative Commons Attribution 4.0 International License" are listed in the Google Patents information for US89933384.

Inventors

• Yu-Hsiang Hung: United Microelectronics Corp [cite: Original Patent Text]
• Ssu-I Fu: United Microelectronics Corp [cite: Original Patent Text]
• Chung-Fu Chang: United Microelectronics Corp [cite: Original Patent Text]
• Cheng-Guo Chen: United Microelectronics Corp [cite: Original Patent Text]
• Chien-Ting Lin: United Microelectronics Corp [cite: Original Patent Text]

All inventors were employed by United Microelectronics Corp at the time of filing.

Original assignee

The original assignee on the issued patent was United Microelectronics Corp (UMC). [cite: Original Patent Text] UMC is a major Taiwanese semiconductor foundry company that manufactures integrated circuits for various applications, indicating they ship products embodying the claims. UMC is currently operating.

Assignment timeline

USPTO Assignment Center search results for US8993384:

• 2013-06-09 (executed) / recorded 2013-06-09 — Reel 030573/0820

  • Conveyance: Assignment of Assignors Interest
  • Assignor: Hung, Yu-Hsiang; Fu, Ssu-I; Chang, Chung-Fu; Chen, Cheng-Guo; Lin, Chien-Ting (all inventors)
  • Assignee: UNITED MICROELECTRONICS CORP., TAIWAN
  • Correspondent: Not specified in the provided text.
  • Context: Original assignment from inventors to the initial corporate assignee.

• 2023-10-13 (executed) / recorded 2023-10-20 — Reel 065294/0055

  • Conveyance: Assignment of Assignors Interest
  • Assignor: UNITED MICROELECTRONICS CORPORATION
  • Assignee: MARLIN SEMICONDUCTOR LIMITED, IRELAND
  • Correspondent: Not specified in the provided text.
  • Context: Transfer of patent ownership from original assignee to a new entity.

Timeline diagram

timeline
    title Ownership of US 8993384
    2013 : Inventors assign to UMC
    2015 : Patent issued
    2023 : UMC assigns to Marlin Semiconductor

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The assignment on 2023-10-13 from UNITED MICROELECTRONICS CORPORATION to MARLIN SEMICONDUCTOR LIMITED, IRELAND [cite: Original Patent Text] suggests a shell entity transfer. [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.) is listed as the current assignee. [cite: Original Patent Text] Without evidence of Marlin Semiconductor Ltd. being an operating company that produces products, and given its name and country of incorporation (Ireland, a common jurisdiction for patent holding companies), this is a strong indicator.

2. Known asserter in the chain — Unclear. Marlin Semiconductor Ltd is the current assignee, and while a PTAB case (IPR2025-01265) has been filed against this patent [cite: Original Patent Text], the provided information does not definitively identify Marlin Semiconductor Ltd as a "known asserter" from standard NPE lists (Acacia Research, Marathon Patent Group, etc.).

3. Repeat correspondent across the chain — Not present. The provided USPTO assignment records do not specify correspondent attorney information for either assignment.

4. Cascading transfers — Not present. There are only two assignments recorded, with a 10-year gap between them.

5. Pre-litigation transfer — Unclear. A PTAB case (IPR2025-01265) was filed, but the transfer to Marlin Semiconductor Ltd occurred in October 2023, while the PTAB case was filed in 2025 [cite: Original Patent Text]. This gap is longer than the typical 6-month window for a "pre-litigation transfer" signal.

6. Bankruptcy fire-sale — Not present. There is no indication in the provided information that United Microelectronics Corp (UMC) filed for bankruptcy.

7. Privateering — Unclear. There is no information in the provided text or the search results to suggest a privateering arrangement.

8. Defensive aggregator (anti-NPE) — Not present. The current assignee, Marlin Semiconductor Ltd, is not a known defensive aggregator.

Verdict

NPE — moderate confidence

The transfer from United Microelectronics Corporation, an operating company, to Marlin Semiconductor Limited, an entity without a readily apparent product line and incorporated in Ireland, is a strong indicator of a shell-entity transfer [cite: Original Patent Text]. While there are no repeat correspondents or cascading transfers to further solidify the NPE classification, the nature of the assignee change strongly suggests an assertion-focused strategy.

To identify the most relevant prior art for US Patent 8993384, I will examine the "Cited By" and "Citations" sections of the patent, focusing on the patents listed as prior art. "Prior art" refers to information publicly available before the effective filing date of a patent application, which for US8993384 is June 9, 2013 [cite: Original Patent Text, 3].

I will now list the patent citations for US8993384, providing the full citation, publication/filing date, a brief description, and which claims it potentially anticipates under 35 U.S.C. § 102.

Cited Prior Art for US Patent 8993384:

1. US6043138A

   • Full Citation: US6043138A - Multi-step polysilicon deposition process for boron penetration inhibition [cite: Original Patent Text]
   • Priority Date: September 16, 1996 [cite: Original Patent Text]
   • Publication Date: March 28, 2000 [cite: Original Patent Text]
   • Brief Description: This patent describes a multi-step polysilicon deposition process aimed at inhibiting boron penetration in semiconductor devices. This is relevant to the general field of semiconductor fabrication and gate structures. [cite: Original Patent Text]
   • Potentially Anticipates: This patent broadly relates to gate formation and semiconductor processing. Given its early filing date and general nature, it could potentially anticipate aspects of Claim 1, particularly steps involving "forming a gate structure" and general semiconductor device fabrication, though it does not describe FinFETs or epitaxial recess structures.

2. US6492216B1

   • Full Citation: US6492216B1 - Method of forming a transistor with a strained channel [cite: Original Patent Text]
   • Priority Date: February 7, 2002 [cite: Original Patent Text]
   • Publication Date: December 10, 2002 [cite: Original Patent Text]
   • Brief Description: This patent focuses on methods for forming transistors with strained channels to improve performance, which is a key objective of US8993384. It describes inducing biaxial tensile strain in an epitaxial silicon layer due to lattice constant differences. [cite: Original Patent Text]
   • Potentially Anticipates: This patent is highly relevant to US8993384, specifically regarding the use of strained channels and epitaxial layers. It directly relates to the concept of forming an epitaxial layer to impose stress on channel regions (as mentioned in the background of US8993384). It could potentially anticipate the "forming an epitaxial layer to fill up the recess" step of Claim 1, especially the underlying purpose of applying stress.

3. US20040195624A1

   • Full Citation: US20040195624A1 - Strained silicon fin field effect transistor [cite: Original Patent Text]
   • Priority Date: April 4, 2003 [cite: Original Patent Text]
   • Publication Date: October 7, 2004 [cite: Original Patent Text]
   • Brief Description: This publication describes a strained silicon fin field effect transistor (FinFET). This is highly pertinent as US8993384 specifically addresses FinFETs and strained epitaxial structures. [cite: Original Patent Text]
   • Potentially Anticipates: This patent directly relates to "fin structures" and "strained silicon," central elements of US8993384. It could potentially anticipate the "forming a fin structure" step and the general concept of a FinFET with a strained region, as outlined in Claim 1.

4. US20050051825A1

   • Full Citation: US20050051825A1 - Semiconductor device and manufacturing method thereof [cite: Original Patent Text]
   • Priority Date: September 9, 2003 [cite: Original Patent Text]
   • Publication Date: March 10, 2005 [cite: Original Patent Text]
   • Brief Description: This patent discusses a semiconductor device and its manufacturing method, broadly covering the field. [cite: Original Patent Text]
   • Potentially Anticipates: Without a more specific description from the patent text, it's difficult to pinpoint exact claims. However, it generally relates to the fabrication method (Claim 1) and the semiconductor device itself.

5. US6921963B2

   • Full Citation: US6921963B2 - Narrow fin FinFET [cite: Original Patent Text]
   • Priority Date: January 23, 2003 [cite: Original Patent Text]
   • Publication Date: July 26, 2005 [cite: Original Patent Text]
   • Brief Description: This patent describes a FinFET with narrow fins, addressing a specific architectural detail of FinFETs. [cite: Original Patent Text]
   • Potentially Anticipates: This patent could potentially anticipate the "forming a fin structure" step of Claim 1, specifically regarding the geometry of the fin.

6. US20060099830A1

   • Full Citation: US20060099830A1 - Plasma implantation using halogenated dopant species to limit deposition of surface layers [cite: Original Patent Text]
   • Priority Date: November 5, 2004 [cite: Original Patent Text]
   • Publication Date: May 11, 2006 [cite: Original Patent Text]
   • Brief Description: This publication relates to plasma implantation techniques for doping, specifically using halogenated dopant species to limit surface layer deposition. [cite: Original Patent Text]
   • Potentially Anticipates: This patent is less directly related to the core innovation of US8993384 (epitaxial layer with recessed isolation) but broadly falls under semiconductor fabrication methods. It might be relevant to doping processes that could occur during or after the formation of fin structures or epitaxial layers, potentially anticipating some implied or optional steps in Claim 1.

7. US7087477B2

   • Full Citation: US7087477B2 - FinFET SRAM cell using low mobility plane for cell stability and method for forming [cite: Original Patent Text]
   • Priority Date: December 4, 2001 [cite: Original Patent Text]
   • Publication Date: August 8, 2006 [cite: Original Patent Text]
   • Brief Description: This patent describes a FinFET SRAM cell design and its fabrication method, focusing on cell stability. [cite: Original Patent Text]
   • Potentially Anticipates: This patent is relevant to FinFET structures and their fabrication (Claim 1), particularly the "forming a fin structure" step and the overall integration of FinFETs into circuits.

8. US7091551B1

   • Full Citation: US7091551B1 - Four-bit FinFET NVRAM memory device [cite: Original Patent Text]
   • Priority Date: April 13, 2005 [cite: Original Patent Text]
   • Publication Date: August 15, 2006 [cite: Original Patent Text]
   • Brief Description: This patent describes a four-bit FinFET NVRAM memory device, again focusing on FinFET applications. [cite: Original Patent Text]
   • Potentially Anticipates: Similar to US7087477B2, this patent broadly anticipates the "forming a fin structure" step and the general concept of FinFET devices in Claim 1.

9. US20060286729A1

   • Full Citation: US20060286729A1 - Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate [cite: Original Patent Text]
   • Priority Date: June 21, 2005 [cite: Original Patent Text]
   • Publication Date: December 21, 2006 [cite: Original Patent Text]
   • Brief Description: This publication describes CMOS integrated circuits utilizing raised source/drain regions and replacement metal gates. US8993384 also mentions a "high-k last replacement metal gate (RMG) process." [cite: Original Patent Text]
   • Potentially Anticipates: This patent is relevant to the "forming a gate structure" step (Claim 1) and the subsequent "removing the gate structure to leave a trench" and "forming a conductive layer to fill up the trench" steps (Claim 9), particularly concerning the use of replacement metal gates and raised source/drain areas.

10. US20070108528A1

    • Full Citation: US20070108528A1 - Sram cell [cite: Original Patent Text]
    • Priority Date: November 15, 2005 [cite: Original Patent Text]
    • Publication Date: May 17, 2007 [cite: Original Patent Text]
    • Brief Description: This publication describes an SRAM cell. [cite: Original Patent Text]
    • Potentially Anticipates: Broadly relevant to semiconductor devices, potentially to the context in which FinFETs (as in Claim 1) might be used.

11. US20070158756A1

    • Full Citation: US20070158756A1 - Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement [cite: Original Patent Text]
    • Priority Date: January 12, 2006 [cite: Original Patent Text]
    • Publication Date: July 12, 2007 [cite: Original Patent Text]
    • Brief Description: This publication describes a production method for a FinFET transistor arrangement. [cite: Original Patent Text]
    • Potentially Anticipates: Highly relevant to the "forming a fin structure" and "forming a gate structure" steps of Claim 1, as it directly concerns FinFET fabrication methods.

12. US7247887B2

    • Full Citation: US7247887B2 - Segmented channel MOS transistor [cite: Original Patent Text]
    • Priority Date: July 1, 2005 [cite: Original Patent Text]
    • Publication Date: July 24, 2007 [cite: Original Patent Text]
    • Brief Description: This patent describes a segmented channel MOS transistor. [cite: Original Patent Text]
    • Potentially Anticipates: While not explicitly a FinFET, it pertains to MOS transistor channel design, which is a fundamental aspect of the fin structure and gate structure of Claim 1.

13. US7250658B2

    • Full Citation: US7250658B2 - Hybrid planar and FinFET CMOS devices [cite: Original Patent Text]
    • Priority Date: June 26, 2003 [cite: Original Patent Text]
    • Publication Date: July 31, 2007 [cite: Original Patent Text]
    • Brief Description: This patent describes hybrid planar and FinFET CMOS devices, showing the co-existence and fabrication of both types of transistors. [cite: Original Patent Text]
    • Potentially Anticipates: This is highly relevant to the context of US8993384, which also discusses FinFETs and even mentions that planar FETs could be formed. It could anticipate the "forming a fin structure" and "forming a gate structure" steps of Claim 1, as well as the overall semiconductor device.

14. US7309626B2

    • Full Citation: US7309626B2 - Quasi self-aligned source/drain FinFET process [cite: Original Patent Text]
    • Priority Date: November 15, 2005 [cite: Original Patent Text]
    • Publication Date: December 18, 2007 [cite: Original Patent Text]
    • Brief Description: This patent describes a quasi self-aligned source/drain FinFET process. [cite: Original Patent Text]
    • Potentially Anticipates: This is relevant to the overall FinFET fabrication method (Claim 1), particularly the formation of source/drain regions which would be adjacent to the gate and where epitaxial structures are formed.

15. US7352034B2

    • Full Citation: US7352034B2 - Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures [cite: Original Patent Text]
    • Priority Date: August 25, 2005 [cite: Original Patent Text]
    • Publication Date: April 1, 2008 [cite: Original Patent Text]
    • Brief Description: This patent details semiconductor structures integrating damascene-body FinFETs and planar devices on a common substrate, along with their formation methods. [cite: Original Patent Text]
    • Potentially Anticipates: Similar to US7250658B2, this patent is relevant to the overall fabrication method (Claim 1) and the integration of FinFETs on a substrate.

16. US20080157208A1

    • Full Citation: US20080157208A1 - Stressed barrier plug slot contact structure for transistor performance enhancement [cite: Original Patent Text]
    • Priority Date: December 29, 2006 [cite: Original Patent Text]
    • Publication Date: July 3, 2008 [cite: Original Patent Text]
    • Brief Description: This publication describes a stressed barrier plug slot contact structure for enhancing transistor performance. [cite: Original Patent Text]
    • Potentially Anticipates: This patent relates to performance enhancement through stress, similar to the goal of US8993384. It could potentially anticipate the use of stressed materials around the transistor, although the specific structure (barrier plug slot contact) differs from the epitaxial recess of US8993384.

17. US7470570B2

    • Full Citation: US7470570B2 - Process for fabrication of FinFETs [cite: Original Patent Text]
    • Priority Date: November 14, 2006 [cite: Original Patent Text]
    • Publication Date: December 30, 2008 [cite: Original Patent Text]
    • Brief Description: This patent describes a process for the fabrication of FinFETs. [cite: Original Patent Text]
    • Potentially Anticipates: This is broadly anticipatory of the fabrication method of Claim 1, specifically the initial steps of "forming a fin structure" and "forming a gate structure" in a FinFET context.

18. US7525160B2

    • Full Citation: US7525160B2 - Multigate device with recessed strain regions [cite: Original Patent Text]
    • Priority Date: December 27, 2005 [cite: Original Patent Text]
    • Publication Date: April 28, 2009 [cite: Original Patent Text]
    • Brief Description: This patent describes a multigate device with recessed strain regions. This is directly relevant to the concept of forming a recess for a strained epitaxial layer in US8993384. [cite: Original Patent Text]
    • Potentially Anticipates: This patent is highly relevant to Claim 1, particularly the "forming a recess in the fin structure at a side of the gate structure" and "forming an epitaxial layer to fill up the recess" steps, as it describes similar features for strain enhancement in multigate devices.

19. US7531437B2

    • Full Citation: US7531437B2 - Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material [cite: Original Patent Text]
    • Priority Date: September 30, 2004 [cite: Original Patent Text]
    • Publication Date: May 12, 2009 [cite: Original Patent Text]
    • Brief Description: This patent details a method for forming metal gate electrodes using sacrificial materials. This is similar to the "gate-last for high-k last process" described in US8993384. [cite: Original Patent Text]
    • Potentially Anticipates: This patent could anticipate the "forming a gate structure" step of Claim 1, and more specifically the process of replacing a dummy gate with a metal gate as described in Claim 9.

20. US20090124097A1

    • Full Citation: US20090124097A1 - Method of forming narrow fins in FinFET devices with reduced spacing therebetween [cite: Original Patent Text]
    • Priority Date: November 9, 2007 [cite: Original Patent Text]
    • Publication Date: May 14, 2009 [cite: Original Patent Text]
    • Brief Description: This publication describes methods for forming narrow fins in FinFET devices with reduced spacing. [cite: Original Patent Text]
    • Potentially Anticipates: This is relevant to the "forming a fin structure" step of Claim 1, specifically regarding the dimensions and density of the fins.

21. US7569857B2

    • Full Citation: US7569857B2 - Dual crystal orientation circuit devices on the same substrate [cite: Original Patent Text]
    • Priority Date: September 29, 2006 [cite: Original Patent Text]
    • Publication Date: August 4, 2009 [cite: Original Patent Text]
    • Brief Description: This patent discusses dual crystal orientation circuit devices on the same substrate. [cite: Original Patent Text]
    • Potentially Anticipates: Broadly relevant to semiconductor devices and substrates, potentially influencing the material choices for the fin structure in Claim 1.

22. US20090242964A1

    • Full Citation: US20090242964A1 - Non-volatile memory device [cite: Original Patent Text]
    • Priority Date: April 26, 2006 [cite: Original Patent Text]
    • Publication Date: October 1, 2009 [cite: Original Patent Text]
    • Brief Description: This publication describes a non-volatile memory device. [cite: Original Patent Text]
    • Potentially Anticipates: Broadly relevant to semiconductor devices, potentially to the context in which FinFETs (as in Claim 1) might be used.

23. US20090269916A1

    • Full Citation: US20090269916A1 - Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges [cite: Original Patent Text]
    • Priority Date: April 28, 2008 [cite: Original Patent Text]
    • Publication Date: October 29, 2009 [cite: Original Patent Text]
    • Brief Description: This publication describes methods for fabricating memory cells with fin structures having specific top surface and corner profiles. [cite: Original Patent Text]
    • Potentially Anticipates: This is relevant to the "forming a fin structure" step of Claim 1, specifically regarding the shape and profile of the fin.

24. US20100048027A1

    • Full Citation: US20100048027A1 - Smooth and vertical semiconductor fin structure [cite: Original Patent Text]
    • Priority Date: August 21, 2008 [cite: Original Patent Text]
    • Publication Date: February 25, 2010 [cite: Original Patent Text]
    • Brief Description: This publication describes a smooth and vertical semiconductor fin structure. [cite: Original Patent Text]
    • Potentially Anticipates: This is relevant to the "forming a fin structure" step of Claim 1, specifically concerning the quality and orientation of the fin.

25. US20100072553A1

    • Full Citation: US20100072553A1 - METAL GATE STRESS FILM FOR MOBILITY ENHANCEMENT IN FinFET DEVICE [cite: Original Patent Text]
    • Priority Date: September 23, 2008 [cite: Original Patent Text]
    • Publication Date: March 25, 2010 [cite: Original Patent Text]
    • Brief Description: This publication describes a metal gate stress film for mobility enhancement in FinFET devices. This relates to using stress to improve FinFET performance. [cite: Original Patent Text]
    • Potentially Anticipates: This is highly relevant to the objective of US8993384 to increase carrier mobility through stress. It could potentially anticipate the functional aspect of "stress imposed on the channel region" (Claim 1) and the use of materials to achieve this.

26. US20100144121A1

    • Full Citation: US20100144121A1 - Germanium FinFETs Having Dielectric Punch-Through Stoppers [cite: Original Patent Text]
    • Priority Date: December 5, 2008 [cite: Original Patent Text]
    • Publication Date: June 10, 2010 [cite: Original Patent Text]
    • Brief Description: This publication describes Germanium FinFETs with dielectric punch-through stoppers. [cite: Original Patent Text]
    • Potentially Anticipates: This is relevant to the "forming a fin structure" step of Claim 1 (specifically if the fin material is Germanium or includes it), and the overall FinFET architecture.

27. US20100167506A1

    • Full Citation: US20100167506A1 - Inductive plasma doping [cite: Original Patent Text]
    • Priority Date: December 31, 2008 [cite: Original Patent Text]
    • Publication Date: July 1, 2010 [cite: Original Patent Text]
    • Brief Description: This publication describes inductive plasma doping. [cite: Original Patent Text]
    • Potentially Anticipates: Similar to US20060099830A1, this broadly relates to doping processes that might be part of the fabrication method in Claim 1.

28. US20120193713A1

    • Full Citation: US20120193713A1 - FinFET device having reduce capacitance, access resistance, and contact resistance [cite: Original Patent Text]
    • Priority Date: January 31, 2011 [cite: Original Patent Text]
    • Publication Date: August 2, 2012 [cite: Original Patent Text]
    • Brief Description: This publication describes a FinFET device designed to reduce capacitance, access resistance, and contact resistance. [cite: Original Patent Text]
    • Potentially Anticipates: This patent is relevant to the overall FinFET device structure and performance optimization, which would include elements of Claim 1, particularly concerning the fin and gate structures.

29. US8765533B2

    • Full Citation: US8765533B2 - Fin-like field effect transistor (FinFET) channel profile engineering method and associated device [cite: Original Patent Text]
    • Priority Date: December 4, 2012 [cite: Original Patent Text]
    • Publication Date: July 1, 2014 [cite: Original Patent Text]
    • Brief Description: This patent describes a FinFET channel profile engineering method and associated device. [cite: Original Patent Text]
    • Potentially Anticipates: This patent's filing date (December 4, 2012) is prior to US8993384's filing date (June 9, 2013). It directly addresses FinFET channel profiles, making it highly relevant to the "fin structure" and potentially the "recess" formation in Claim 1, as the profile of the channel would be influenced by these steps.

Most Relevant Prior Art:

Based on the descriptions, the following prior art references appear most relevant to the distinct features of US8993384, particularly the combination of FinFET structures with strained epitaxial layers and recessed isolation:

• US6492216B1 (Method of forming a transistor with a strained channel): Directly addresses forming strained channels using epitaxial layers for performance improvement, a core concept of US8993384. [cite: Original Patent Text]
• US20040195624A1 (Strained silicon fin field effect transistor): Combines the concepts of FinFETs and strained silicon, both central to US8993384. [cite: Original Patent Text]
• US7525160B2 (Multigate device with recessed strain regions): Explicitly mentions "recessed strain regions" in a multigate device context, which directly parallels the "recess in the fin structure" filled with an epitaxial layer in Claim 1 of US8993384. [cite: Original Patent Text]
• US20100072553A1 (METAL GATE STRESS FILM FOR MOBILITY ENHANCEMENT IN FinFET DEVICE): Directly addresses mobility enhancement in FinFETs through stress, aligning with the objective of US8993384. [cite: Original Patent Text]
• US8765533B2 (Fin-like field effect transistor (FinFET) channel profile engineering method and associated device): Its priority date is before US8993384, and it addresses FinFET channel profile engineering, which would impact the fin and recess structures of Claim 1. [cite: Original Patent Text]

These patents collectively show that the individual components of FinFETs, strained channels, and even recessed regions for strain were known in the prior art. The novelty of US8993384 likely lies in the specific combination of these elements and the detailed method for forming the epitaxial layer in the recess while addressing void defects, particularly the relationship between the depth of the isolation structure etch and the depth of the fin recess.

To assess the obviousness of US patent 8993384 under 35 U.S.C. § 103, we will analyze combinations of prior art references that would render the independent claim (Claim 1) obvious to a person having ordinary skill in the art (POSA).

Claim 1 of US8993384 (Fabrication Method):

1. Forming a fin structure, protruding from a surface of a substrate, wherein the fin structure comprises a top surface and two side surfaces;
2. Forming an isolation structure to surround the fin structure;
3. Forming a gate structure, overlaying the top surface and the two side surfaces of a portion of the fin structure, and covering a portion of the isolation structure;
4. After the step of forming the gate structure, etching the isolation structure exposed from the gate structure until a top surface of the isolation structure is etched down to a first depth;
5. Forming a recess in the fin structure at a side of the gate structure; and
6. Forming an epitaxial layer to fill up the recess, wherein a bottom surface of the recess has a second depth, and the second depth is deeper than the first depth. [cite: Original Patent Text]

Hypothetical Person Having Ordinary Skill in the Art (POSA):
A POSA in the field of semiconductor device fabrication would typically possess a Bachelor's degree in electrical engineering, materials science, or a related field, along with several years of experience in semiconductor process development, particularly involving FinFETs, strain engineering, and epitaxial growth techniques. Such a person would be familiar with common challenges in these processes, such as defect formation.

Prior Art References and their Relevance:
The patent itself lists several prior art documents, some of which are particularly relevant to FinFETs, strained channels, and recessed structures.

1. US20040195624A1 (Strained silicon fin field effect transistor): This reference discloses the fundamental concept of a FinFET device and the use of strained silicon to enhance performance. It provides the context for steps 1, 2, 3 (forming fin, isolation, and gate structures in a FinFET) and the general idea of an epitaxial layer for strain (step 6). [cite: Original Patent Text]
2. US7525160B2 (Multigate device with recessed strain regions): This patent explicitly teaches forming "recessed strain regions" in a multigate device. This directly implies creating recesses in the active semiconductor body (e.g., a fin structure) and filling these recesses with strain-inducing epitaxial material. This reference thus anticipates steps 5 (forming a recess in the fin structure) and 6 (filling the recess with an epitaxial layer) within a multigate context similar to a FinFET. [cite: Original Patent Text]

Differences Between the Prior Art and Claim 1:
The primary distinguishing feature of Claim 1 of US8993384 lies in the specific etching of the isolation structure (step 4) to a "first depth" and the subsequent formation of a recess in the fin structure (step 5) where the "bottom surface of the recess has a second depth, and the second depth is deeper than the first depth" (step 6). This defines a specific geometric relationship where the bottom of the fin recess is physically lower than the top surface of the adjacent, etched isolation structure.

Motivation to Combine and Obviousness Analysis:
The background section of US8993384 clearly articulates a known problem in the field: "due to the continuous shrinkage in the size of the semiconductor devices, the aspect ratio of the epitaxial layer also gets higher, which often incur unwanted defects, such as void defects in the epitaxial layer." It further states, "These defects inside the epitaxial layer reduce the stress required to be imposed onto the corresponding channel region. As a result, how to prevent the formation of the defects inside the epitaxial layer is an important issue." [cite: Original Patent Text]

A POSA, familiar with FinFETs incorporating strained regions (as taught by US20040195624A1 and US7525160B2), would undoubtedly encounter this common and acknowledged problem of void defects during the epitaxial growth process, especially when forming deep recesses for strain in increasingly smaller devices.

To address this known problem of voids and facilitate robust epitaxial filling, a POSA would be motivated to optimize the geometry of the surrounding structures. The patent itself highlights the solution: "Since the process for etching the isolation structure is optionally carried out prior to and/or after the formation of the recess, the height of the isolation structure at two sides of the gate structure may be reduced. In this way, the epitaxial layer may be filled into the corresponding recess easily during the epitaxial growth process. Furthermore, since the epitaxial structure is not sealed during the epitaxial growth process, the void defects may be also avoided as a result." [cite: Original Patent Text]

This motivation directly points to reducing the height of the isolation structure adjacent to the epitaxial growth region (Claim 1, step 4) as an obvious engineering solution to improve the aspect ratio for filling and prevent premature sealing, thereby avoiding void defects. The specific geometric outcome described in Claim 1—where the bottom surface of the fin recess (second depth) is deeper than the top surface of the etched isolation structure (first depth) (as visually confirmed by Figures 8 and 11 of US8993384)—would be a natural and routine design choice for a POSA attempting to ensure complete and defect-free epitaxial growth into the deeper fin recesses. By reducing the height of the isolation structure, even if its top surface remains above the deepest part of the fin recess, the overall constraint on epitaxial material flow into the recess is alleviated. The exact depths would be a matter of routine optimization to achieve the desired defect-free growth.

Conclusion:
A combination of US20040195624A1 and US7525160B2, combined with the common general knowledge in the art regarding the challenges of void formation in high-aspect-ratio epitaxial growth (as explicitly stated in the background of US8993384), would render Claim 1 obvious. A person having ordinary skill in the art would have been motivated to combine the teachings of FinFETs with strained regions and recessed epitaxial areas, and then, to overcome the known problem of epitaxial voids, would have found it obvious to reduce the height of the adjacent isolation structure to facilitate easier and more complete filling of the recesses.

To provide a comprehensive overview of US Patent 8993384, including its term adjustments, related applications, and projected expiration date, a direct search of the USPTO database is necessary.

As of April 26, 2026, a search for US Patent 8993384 on the USPTO's Patent Public Search portal would be the primary method to obtain the most accurate and up-to-date official information. The Google Patents entry provides some initial details that can be cross-referenced and expanded upon.

Here's the detailed information for US Patent 8993384:

• Patent Term Adjustments (PTA): The official USPTO record for US8993384, accessible through Patent Center or Patent Public Search, would provide the specific number of days, if any, granted for Patent Term Adjustment. PTA compensates patentees for delays caused by the USPTO during the patent examination process. Common delays include the USPTO failing to issue a first Official Action within 14 months of filing, failing to respond to an applicant's reply within four months, or failing to issue the patent within three years of the filing date. Without direct access to the specific file wrapper or the official PTA calculation for US8993384 on the USPTO website, the exact PTA amount cannot be stated here.

• Patent Term Extensions (PTE): Patent Term Extensions are generally granted for patents covering products (such as human drug products, medical devices, animal drug products, and food or color additive products) that require premarket regulatory approval from a government agency, like the FDA. The purpose is to restore patent term lost during the regulatory review period. Given that US8993384 pertains to "Semiconductor device and fabrication method thereof," it is unlikely to be eligible for a Patent Term Extension under 35 U.S.C. § 156, as it does not appear to cover a product subject to such regulatory review.

• Continuation and Divisional Applications:

  • Continuation Applications: The Google Patents record indicates that US8993384 (application number US13/913,511) has a "Priority to US13/913,511" on the same filing date of 2013-06-09, which is self-referential for the initial application. No other explicit "continuation" applications are immediately listed as directly deriving from this patent on Google Patents.
  • Divisional Applications: The Google Patents entry lists US9318609B2 as a "Priority Application" and also a "Related Child Application (Division)" of US8993384's underlying application US13/913,511. US9318609B2, titled "Semiconductor device with epitaxial structure," was filed on February 12, 2015, and claims priority from the same June 9, 2013, priority date as US8993384. [cite: Original Patent Text] This confirms US9318609B2 is a divisional application.

• Related Family Members:

  • US Family Applications:
    • US13/913,511 (US8993384B2) [cite: Original Patent Text]
    • US14/620,209 (US9318609B2) [cite: Original Patent Text]
  • Publications:
    • US20140361373A1 (publication of the original application) [cite: Original Patent Text]
    • US8993384B2 (granted patent) [cite: Original Patent Text]
    • US20150155386A1 (related publication)
    • US9318609B2 (granted divisional patent) [cite: Original Patent Text]

• Projected Expiration Date: The Google Patents record states an "Anticipated expiration" date of 2033-06-09. [cite: Original Patent Text] This date is typically 20 years from the earliest filing date of the application from which the patent claims priority, plus any Patent Term Adjustment (PTA). The filing date for US8993384 was June 9, 2013. Therefore, 20 years from this date would be June 9, 2033, suggesting that there might be no, or negligible, PTA, or the PTA calculation results in this specific end date.

Defensive Disclosure for US Patent 8993384

Current Date: April 26, 2026

Role: Senior Patent Strategist and Research Engineer specializing in Defensive Publishing.

This document details derivative variations of the core claims of US Patent 8993384, aimed at preemptively disclosing potential incremental improvements by competitors. The focus is on Claim 1, the independent method claim, as it defines the foundational fabrication process.

---

Derivations based on Claim 1: A fabrication method for a semiconductor device, comprising:

• forming a fin structure, protruding from a surface of a substrate, wherein the fin structure comprises a top surface and two side surfaces;
• forming an isolation structure to surround the fin structure;
• forming a gate structure, overlaying the top surface and the two side surfaces of a portion of the fin structure, and covering a portion of the isolation structure;
• after the step of forming the gate structure, etching the isolation structure exposed from the gate structure until a top surface of the isolation structure is etched down to a first depth;
• forming a recess in the fin structure at a side of the gate structure; and
• forming an epitaxial layer to fill up the recess, wherein a bottom surface of the recess has a second depth, and the second depth is deeper than the first depth. [cite: Original Patent Text]

---

Derivative 1.1: Material & Component Substitution - III-V FinFET with High-k/Metal Gate

Enabling Description:
A fabrication method for a semiconductor device comprising: forming a fin structure from a III-V semiconductor material, such as InGaAs, epitaxially grown on a GaAs-on-silicon substrate, wherein the fin structure comprises a (100) top surface and two (110) side surfaces. An isolation structure, specifically a deep trench isolation (DTI) using a spin-on dielectric (SOD) such as polysilazane, is formed to surround the InGaAs fin structure. A replacement high-k/metal gate (RMG) structure is then formed. Initially, a dummy polysilicon gate is fabricated, overlaying the top surface and two side surfaces of a portion of the InGaAs fin structure, and covering a portion of the DTI structure. After the dummy gate formation and spacer definition (e.g., using SiN), the SOD isolation structure exposed from the dummy gate and spacers is etched down to a first depth (e.g., 50 Å) using a CHF3/CF4 plasma etch. Subsequently, a recess is formed in the InGaAs fin structure at a side of the gate structure by selective wet etching using a citric acid/H2O2 solution at 50°C. Finally, a strained epitaxial layer of InAs is grown selectively within the recess via metal-organic chemical vapor deposition (MOCVD) using trimethylindium and arsine precursors, achieving a second depth (e.g., 150 Å) deeper than the first depth, thereby providing tensile strain to the InGaAs channel. The dummy gate is later removed and replaced with a high-k dielectric (e.g., HfO2 deposited by atomic layer deposition) and a metal gate electrode (e.g., TaN/TiN/W stack).

flowchart TD
    A[Form Fin Structure (InGaAs on GaAs/Si)] --> B{Form DTI Isolation (Polysilazane)};
    B --> C[Form Dummy Gate (Polysilicon) & SiN Spacers];
    C --> D[Etch Exposed DTI to First Depth (50Å) via CHF3/CF4 Plasma];
    D --> E[Form Recess in InGaAs Fin to Second Depth (150Å) via Citric Acid Wet Etch];
    E --> F[Grow Strained InAs Epitaxial Layer via MOCVD];
    F --> G[Replace Dummy Gate with High-k/Metal Gate];

---

Derivative 1.2: Operational Parameter Expansion - Ultra-High Aspect Ratio FinFET for Cryogenic Applications

Enabling Description:
A fabrication method for a semiconductor device intended for cryogenic computing, comprising: forming an ultra-high aspect ratio (AR > 10:1) silicon fin structure protruding from a bulk silicon-on-insulator (SOI) substrate. The fin structures are defined by electron beam lithography and deep reactive ion etching (DRIE) using a Bosch process. An isolation structure, specifically a sub-10nm feature size shallow trench isolation (STI) filled with a low-k dielectric such as a porous organosilicate glass (OSG), is formed to surround the silicon fin structure, with void-free filling achieved via supercritical CO2 drying. A gate-all-around (GAA) gate structure, utilizing a nanowire architecture, is formed, overlaying the top surface and all four side surfaces of a fully depleted portion of the silicon fin structure, and covering a portion of the OSG isolation structure. Post-gate and spacer formation (using a multi-layer SiN/SiO2 spacer), the exposed OSG isolation structure is etched down to a first depth (e.g., 20 Å) using a highly selective dry etch (e.g., C4F8/Ar plasma) optimized for maintaining fin integrity. Recesses are formed in the silicon fin structure at both source/drain sides of the gate structure to a second depth (e.g., 80 Å) using anisotropic cryogenic dry etching (e.g., SF6/O2 at -110°C) to maintain vertical sidewalls. These recesses are then filled with an epitaxially grown strained silicon-germanium (SiGe) layer (e.g., 50% Ge concentration, in-situ phosphorous doped) via low-temperature selective epitaxial growth (SEG) at 550°C, ensuring robust electrical contact and strain for enhanced carrier mobility at sub-4K operating temperatures. The critical dimensions for the fin width are below 5nm.

classDiagram
    class Substrate {
        +Silicon-on-Insulator (SOI)
        +Bulk Si
    }
    class FinStructure {
        +Material: Si
        +Aspect Ratio: >10:1 (Ultra-High)
        +Fabrication: E-beam Litho, DRIE (Bosch)
        +Width: <5nm
    }
    class IsolationStructure {
        +Type: STI
        +Material: Porous OSG (Low-k)
        +Fabrication: Supercritical CO2 drying
        +Recess Depth: First Depth (20Å)
    }
    class GateStructure {
        +Type: Gate-All-Around (GAA)
        +Architecture: Nanowire
        +Material: High-k/Metal (Post-RMG)
    }
    class Recess {
        +Location: Fin Source/Drain
        +Depth: Second Depth (80Å)
        +Fabrication: Cryogenic Dry Etch
    }
    class EpitaxialLayer {
        +Material: Strained SiGe (50% Ge, P-doped)
        +Fabrication: Low-Temp SEG (550°C)
    }
    Substrate --> FinStructure
    FinStructure --> IsolationStructure
    FinStructure --> GateStructure
    GateStructure --> IsolationStructure
    FinStructure <--> Recess
    Recess --> EpitaxialLayer

---

Derivative 1.3: Cross-Domain Application - FinFET-based Biosensor Array for Pathogen Detection

Enabling Description:
A fabrication method for a FinFET-based biosensor array, where the fin structure acts as the transducer surface for molecular binding. A silicon fin structure is formed protruding from a silicon-on-insulator (SOI) substrate, each fin tailored for a specific pathogen binding. An isolation structure, comprised of a biocompatible silicon nitride (SiNx) layer deposited by plasma-enhanced chemical vapor deposition (PECVD), surrounds each fin structure to electrically isolate individual sensor elements. A gate structure, consisting of a transparent indium tin oxide (ITO) electrode covered by a non-fouling hydrogel dielectric (e.g., polyethylene glycol diacrylate, PEGDA), is formed over a portion of the fin, leaving the active biosensing region of the fin exposed. After gate and spacer (SiO2) formation, the SiNx isolation structure not covered by the gate and spacers is selectively etched down to a first depth (e.g., 100 nm) using a dry etch, exposing additional fin sidewalls for functionalization. A recess is formed in the exposed silicon fin structure at a side of the gate structure to a second depth (e.g., 250 nm) using a KOH anisotropic wet etch, creating a larger surface area for analyte immobilization. This recess is then functionalized with specific antibodies (e.g., anti-Salmonella antibodies) via silane chemistry, and a "passive" epitaxial layer of SiO2 is deposited by atomic layer deposition (ALD) to backfill the remaining recess volume and passivate the non-functionalized surfaces, thereby forming the specific molecular binding sites on the fin surface. This design allows for label-free, real-time electrical detection of pathogen binding events.

graph TD
    A[Silicon Fin on SOI (Transducer)] --> B(Biocompatible SiNx Isolation);
    B --> C[Transparent ITO Gate + PEGDA Dielectric];
    C --> D[Etch Exposed SiNx Isolation (100nm)];
    D --> E[KOH Anisotropic Wet Etch for Fin Recess (250nm)];
    E --> F{Functionalize Recess with Antibodies};
    F --> G[ALD SiO2 Epitaxial Layer (Passivation)];
    G --> H(Real-time Electrical Detection);

---

Derivative 1.4: Integration with Emerging Tech - AI-Optimized FinFET Fabrication with IoT Monitoring and Blockchain Traceability

Enabling Description:
A fabrication method for a semiconductor device where process parameters are optimized by an AI-driven system and monitored in real-time via IoT sensors, with all process data recorded on a blockchain. Initially, a silicon fin structure is formed on a silicon substrate. The geometry of the fin (e.g., height, width, pitch) is dynamically adjusted based on AI feedback from simulated device performance models. An isolation structure, specifically a shallow trench isolation (STI) using flowable oxide (FOx) for gap fill, is formed, with its planarization (Chemical Mechanical Planarization - CMP) endpoint precisely controlled by IoT-enabled in-situ optical emission spectroscopy (OES) sensors. A gate structure (High-k/Metal Gate, RMG process) is formed over the fin. During the etching of the isolation structure exposed from the gate, the etch depth (first depth, 75 Å) is adjusted by an AI agent considering previous wafer data, real-time plasma etch uniformity sensors, and predicted device stress. All etching parameters (gas flow, RF power, pressure) are logged to a private blockchain for immutable process traceability. Recesses are formed in the fin structure at source/drain regions. The recess profile and depth (second depth, 200 Å) are continuously monitored by in-situ atomic force microscopy (AFM) and optical profilometry, with data streamed via IoT to the AI for closed-loop control of subsequent etching steps. An epitaxial layer (e.g., in-situ doped SiGe) is then grown in the recesses. The epitaxial growth parameters (temperature, precursor flow, pressure) are optimized in real-time by the AI to achieve target strain levels and dopant activation, with all growth metrics and source material batch IDs cryptographically linked on the blockchain for supply chain verification and quality assurance.

sequenceDiagram
    participant AI as AI Optimization System
    participant IoT as IoT Sensors (OES, Plasma, AFM, Profilometry)
    participant B as Blockchain Ledger
    participant Fab as Fabrication Tools

    Fab->>AI: Send simulated device performance data
    AI->>Fab: Dynamically adjust fin geometry
    Fab->>IoT: Stream CMP data (OES)
    IoT->>AI: Provide real-time CMP feedback
    AI->>Fab: Adjust CMP endpoint
    Fab->>B: Log CMP data & parameters
    Fab->>IoT: Stream plasma etch uniformity data
    IoT->>AI: Provide real-time etch feedback
    AI->>Fab: Adjust isolation etch parameters (First Depth)
    Fab->>B: Log etch parameters to blockchain
    Fab->>IoT: Stream recess profile data (AFM, Opt. Profilometry)
    IoT->>AI: Provide real-time recess feedback
    AI->>Fab: Adjust recess etch parameters (Second Depth)
    Fab->>B: Log recess parameters
    Fab->>AI: Send target strain, dopant activation
    AI->>Fab: Optimize epitaxial growth parameters
    Fab->>B: Log growth metrics & material batch IDs

---

Derivative 1.5: The "Inverse" or Failure Mode - Low-Power FinFET with Controlled Degradation

Enabling Description:
A fabrication method for a semiconductor device designed for low-power operation with predictable degradation characteristics, suitable for disposable or single-use applications. A fin structure is formed from a lightly doped p-type silicon (Si) on a bulk Si substrate. An isolation structure, specifically an STI filled with a deliberately porous low-density plasma-enhanced tetraethyl orthosilicate (PE-TEOS) oxide, is formed to surround the fin structure. This porous oxide is chosen for its higher moisture absorption and controlled dielectric degradation over time. A gate structure, composed of a sacrificial aluminum (Al) layer over a thin silicon dioxide (SiO2) gate dielectric, is formed. After gate and spacer (undoped SiO2) formation, the porous PE-TEOS isolation structure exposed from the gate and spacers is etched down to a first depth (e.g., 200 Å) using a buffered hydrofluoric acid (BHF) solution, specifically chosen to attack the porous oxide at a controlled rate, initiating a degradation mechanism. A shallow recess is formed in the silicon fin structure at the source/drain sides of the gate structure to a second depth (e.g., 300 Å), using a non-selective wet etch (e.g., NH4OH/H2O2) that creates a slightly rougher surface. This recess is then filled with a non-strained, intentionally defect-rich amorphous silicon (a-Si) layer via low-temperature plasma-enhanced chemical vapor deposition (PECVD). The a-Si layer is designed to have high trap densities and lower carrier mobility, contributing to the device's low-power characteristics and designed degradation profile (e.g., increasing leakage current over a predetermined operational lifespan due to trap-assisted tunneling and electromigration in the Al gate). This allows for predictable performance over a finite lifespan before transitioning to a limited-functionality or safe-fail mode.

stateDiagram
    [*] --> FinFormation
    FinFormation --> IsolationFormation
    IsolationFormation --> GateFormation
    GateFormation --> IsolationEtch_InitialDegradation
    IsolationEtch_InitialDegradation --> RecessFormation_DefectInduction
    RecessFormation_DefectInduction --> EpitaxialFill_LowPower
    EpitaxialFill_LowPower --> OperationalPhase
    OperationalPhase --> DegradationOnset : (Porous Oxide Degradation)
    DegradationOnset --> LimitedFunctionality : (Trap-assisted tunneling, Electromigration)
    LimitedFunctionality --> SafeFailMode
    SafeFailMode --> [*]

---

Combination Prior Art Scenarios

Here are at least three "Combination Prior Art" scenarios where US Patent 8993384 could be combined with existing open-source standards to make further developments obvious:

1. US8993384 + Open-Source Process Design Kit (PDK) Standards (e.g., OpenPDK or iPDK):

   • Scenario: A competitor claims a new method for integrating a strained epitaxial layer into a FinFET process where the recess formation and epitaxial growth parameters are optimized for a specific design rule and material stack defined within an open-source Process Design Kit (PDK).
   • Prior Art Argument: The core steps of forming a fin, isolation, gate, etching isolation to a first depth, forming a recess to a deeper second depth, and filling with an epitaxial layer (as taught by US8993384, Claim 1) are known. It would be obvious for a person skilled in the art, when implementing this known FinFET fabrication method using an open-source PDK (which provides standardized design rules, device models, and process flows for a given technology node), to optimize the specific etch depths, materials, and epitaxial growth parameters (e.g., temperature, pressure, precursor flow, dopant concentrations) to comply with or enhance the performance metrics defined within that open-source PDK. The selection and optimization of these parameters within a known framework like a PDK would be a routine engineering choice, not an inventive step. This combines the structural and methodological teachings of US8993384 with the publicly available and standardized constraints and guidance offered by an open-source PDK.

2. US8993384 + SEMI Standards for Wafer Fabrication Equipment & Materials:

   • Scenario: A competitor patents a method for forming a FinFET with enhanced epitaxial layer quality, where the specific gas delivery system for selective epitaxial growth (SEG) and the wafer handling robotics are compliant with certain SEMI standards (e.g., SEMI E10, SEMI E54, SEMI F19).
   • Prior Art Argument: US8993384 (Claim 1) clearly discloses the method of forming a fin, isolation, gate, etching isolation, forming a recess, and critically, forming an epitaxial layer to fill the recess. The enhancement of epitaxial layer quality (or any other process step) by utilizing manufacturing equipment and materials that adhere to widely adopted SEMI (Semiconductor Equipment and Materials International) standards is a well-known practice in the semiconductor industry. A person skilled in the art would understand that implementing the epitaxial growth step of US8993384 using commercially available, SEMI-compliant MOCVD or MBE equipment, which ensures standardized interfaces, contamination control, and consistent material delivery, would lead to improved process control and potentially higher quality epitaxial layers. Such compliance with industry standards, while leading to beneficial results, is a standard engineering implementation rather than an inventive modification of the core method.

3. US8993384 + Open-Source EDA Tools (e.g., OpenLane, Skywater PDK on GitHub):

   • Scenario: A competitor claims a method for fabricating FinFETs with improved electrical characteristics achieved by simulating the strained epitaxial region using an open-source Electronic Design Automation (EDA) tool flow (e.g., incorporating process simulation modules within a framework like OpenLane).
   • Prior Art Argument: The fundamental method for fabricating a FinFET with a strained epitaxial layer formed in a recess after differential etching of isolation (US8993384, Claim 1) is established. It would be obvious for a person skilled in the art to simulate and optimize the design and process parameters of such a device, including the geometry of the fin, the dimensions of the recess, and the characteristics of the epitaxial layer (e.g., composition, strain), using readily available open-source EDA tools. For example, using a tool flow like OpenLane (which integrates various open-source tools for ASIC design, including synthesis, placement, routing, and simulation, often leveraging open PDKs like Skywater 130nm) to model the structural and electrical impact of the epitaxial layer formation described in US8993384 would be a routine application of known computational methods to a known fabrication process. Any "improvement" derived from such simulation and optimization, when applied to the core method of US8993384, would be considered an obvious engineering refinement.