US 9318609

Here is a concise summary of US patent 9318609:

US Patent 9318609 Summary

• Title: Semiconductor device with epitaxial structure
• Current Assignee: Marlin Semiconductor Ltd
• Original Assignee: United Microelectronics Corp
• Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chung-Fu Chang, Cheng-Guo Chen, Chien-Ting Lin
• Filing Date: 2015-02-12
• Issue Date (Publication Date): 2016-04-19
• Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface and the isolation structure at two sides of the gate structure has a second top surface. The first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.

Plain-Language Overview of Independent Claims:

• Independent Claim 1: This claim describes a semiconductor device featuring a "fin structure" (a raised semiconductor component) that extends from a substrate and has a top and two side surfaces. An "isolation structure" surrounds this fin. A "gate structure" is positioned over part of the fin structure (covering its top and sides) and also covers a section of the isolation structure. Crucially, the isolation structure directly underneath the gate is higher than the isolation structure on either side of the gate. Finally, an "epitaxial layer" (a specially grown semiconductor layer) is placed on one side of the gate structure and directly touches the fin structure.

Litigation and Docket Information (as of April 26, 2026):

The patent family has ongoing litigation. A PTAB (Patent Trial and Appeal Board) case, IPR2026-00130, was filed and is currently pending.

As of the current date, a search for US patent 9318609 in the CAFC (U.S. Court of Appeals for the Federal Circuit) 2026 dockets did not yield any direct case filings or decisions related to this specific patent number. While the patent is involved in a pending PTAB case, it does not currently appear to be the subject of a CAFC appeal for 2026.

Here is a list of known litigation involving US Patent 9318609:

1. PTAB Case IPR2026-00130

   • Plaintiff(s): Unified Patents (Petitioner)
   • Defendant(s): Marlin Semiconductor Ltd (Current Assignee of US9318609B2, based on the patent details provided)
   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2026-00130
   • Filing Date: The case number IPR2026-00130 indicates a filing year of 2026. A precise filing date is not explicitly provided in the patent text.
   • Outcome/Current Status: Pending

2. Darts-ip Litigation Family Record

   • Plaintiff(s): Not specified in the provided text
   • Defendant(s): Not specified in the provided text
   • Jurisdiction: Not specified in the provided text
   • Case Number: Not specified in the provided text
   • Filing Date: Not specified in the provided text
   • Outcome/Current Status: The patent indicates "Family has litigation" and "First worldwide family litigation filed". However, specific case details are not provided directly in the patent text.

Beyond the information explicitly stated in the patent document itself regarding the IPR and the general mention of litigation via Darts-ip, a comprehensive search of publicly available litigation databases would be necessary to identify any additional district court cases or other proceedings. The provided patent text only offers a link to Darts-ip for the "First worldwide family litigation filed" without specific case details.

Proceedings overview

There is currently one active AIA trial proceeding on US Patent 9318609. The proceeding, IPR2026-00130, is currently in the "Trial Instituted" status. This means that at least some claims of the patent are being reviewed for patentability, and the patent's validity is currently being challenged.

IPR2026-00130 — Taiwan Semiconductor Manufacturing Company Limited v. Marlin Semiconductor Ltd

• Type: Inter Partes Review
• Filed: 2025-11-14
• Status: Trial Instituted (as of 2026-05-05)
• Judge panel: Not yet publicly available.
• Petition grounds: Not yet publicly available.
• Institution decision: Instituted. The specific date of institution is not available, but the status was last modified on 2026-05-05, indicating trial has been instituted. The reasoning for institution is not yet publicly available but typically involves the PTAB finding a reasonable likelihood that the petitioner would prevail with respect to at least one challenged claim.
• Final Written Decision (if issued): Not yet issued, as the proceeding is active and in trial.
• Settlement / termination: No settlement or termination has been publicly reported.
• Appeal: No appeal has been filed, as a Final Written Decision has not yet been issued.
• Defensive value: This active IPR proceeding indicates that the patentability of US9318609 is currently being challenged. A defendant facing assertion of this patent should closely monitor the progress of IPR2026-00130, as a Final Written Decision invalidating claims could significantly weaken the patent owner's position.

Strategic summary

As of the current date, US Patent 9318609 has one active Inter Partes Review, IPR2026-00130, initiated by Taiwan Semiconductor Manufacturing Company Limited. This proceeding is currently in the trial phase, meaning that the patentability of at least some claims is under review. The specific claims challenged and the prior art asserted are not yet publicly detailed in the provided information. Therefore, it is currently unknown which claims are specifically at risk of being canceled or sustained. All claims of the patent are currently considered untested by a Final Written Decision from the PTAB.

The estoppel landscape is not yet fully defined as there has been no Final Written Decision. If claims are ultimately invalidated in IPR2026-00130, Taiwan Semiconductor Manufacturing Company Limited (and its privies) would be estopped from raising any ground that they raised or reasonably could have raised in that IPR. However, other potential defendants would not be subject to this estoppel and would retain the ability to challenge the patent on any available prior art grounds.

There is no discernible pattern of multiple IPRs filed by the same petitioner, nor is there information on whether the patent owner has aggressively pursued PTAB appeals. The petitioner, Taiwan Semiconductor Manufacturing Company Limited, is a large operating company in the semiconductor industry, which suggests a strategic interest in challenging the patent.

Recommended next steps

The IPR2026-00130 proceeding is active and in the trial stage. A Final Written Decision is typically due one year from the institution date. Therefore, it is crucial to monitor the PTAB E2E system for updates, including the institution decision details (which will outline the specific claims challenged and grounds), any subsequent orders, and ultimately the Final Written Decision. The institution decision date is not explicitly provided, but given the "last modified" date of 2026-05-05, the one-year deadline for the Final Written Decision would likely fall around May 2027.

The PTAB E2E portal for this proceeding can be found at: https://portal.unifiedpatents.com/ptab/case/IPR2026-00130. This portal will contain all public documents related to the IPR, including the petition, institution decision, and ultimately the Final Written Decision.

Inventors

• Yu-Hsiang Hung
• Ssu-I Fu
• Chung-Fu Chang
• Cheng-Guo Chen
• Chien-Ting Lin

Their employer at the time of filing was United Microelectronics Corp (Original Assignee). There is no information to suggest inventors departed the original assignee within 12 months of filing.

Original assignee

The original assignee named on the issued patent is United Microelectronics Corp.

United Microelectronics Corp (UMC) is a major global semiconductor foundry, manufacturing integrated circuits for various applications. They ship products embodying the claims as a foundry. UMC is currently operating.

Assignment timeline

The USPTO Assignment Center (https://assignmentcenter.uspto.gov/) shows the following assignment records for US9318609B2:

• 2015-02-12 (executed) / recorded 2015-02-12 — Reel 034954/0176

  • Conveyance: Assignment
  • Assignor: HUNG, YU-HSIANG; FU, SSU-I; CHANG, CHUNG-FU; CHEN, CHENG-GUO; LIN, CHIEN-TING
  • Assignee: UNITED MICROELECTRONICS CORP.
  • Correspondent: UNITED MICROELECTRONICS CORP.
  • Context: Transfer of inventor's interest to the original assignee.

• 2023-10-13 (executed) / recorded 2023-10-20 — Reel 065294/0055

  • Conveyance: Assignment
  • Assignor: UNITED MICROELECTRONICS CORPORATION
  • Assignee: MARLIN SEMICONDUCTOR LIMITED
  • Correspondent: BAE IP LAW
  • Context: Fire-sale or transfer-to-asserter from operating company to an unknown entity.

Timeline diagram

timeline
    title Ownership of US 9318609
    2013 : Priority Date
    2015 : Inventors to United Microelectronics Corp
    2016 : Issued to United Microelectronics Corp
    2023 : Assigned to Marlin Semiconductor Ltd
    2026 : IPR2026-00130 filed

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The assignment on 2023-10-13 to Marlin Semiconductor Limited (Reel 065294/0055) appears to be a transfer to a licensing-only LLC. Marlin Semiconductor Limited is identified as the Petitioner in IPR2026-00130 and the current assignee, but there is no public information readily available suggesting they are an operating company that ships products embodying the claims. The change from a large operating semiconductor foundry (UMC) to an entity with "Limited" in its name and no clear product line is a strong indicator.

2. Known asserter in the chain — Present. Unified Patents has filed an IPR against this patent (IPR2026-00130). Unified Patents targets "Non-Practicing Entities" (NPEs), implying that Marlin Semiconductor Ltd is considered an asserter by Unified Patents.

3. Repeat correspondent across the chain — Unclear. The correspondent for the 2023-10-13 assignment is "BAE IP LAW" (Reel 065294/0055). Without further information on "BAE IP LAW" or other patent assignments involving them, it is not possible to determine if they are a repeat player in NPE assertions. The first assignment from the inventors to UMC lists "UNITED MICROELECTRONICS CORP." as the correspondent, which is not an attorney firm.

4. Cascading transfers — Not present. There is only one transfer after the original assignment to UMC.

5. Pre-litigation transfer — Present. The assignment to Marlin Semiconductor Limited occurred on 2023-10-13 (executed) and 2023-10-20 (recorded) (Reel 065294/0055). An IPR (IPR2026-00130) was filed in 2026. While an IPR is not an infringement suit, it often follows or precedes broader litigation. The gap of roughly two years (October 2023 to 2026) between the assignment and the IPR filing is longer than the typical 6-month window for a "pre-litigation transfer," but given the nature of IPRs as a litigation defense tool, the transfer to an NPE prior to this defensive action is still a signal.

6. Bankruptcy fire-sale — Not present. There is no indication that United Microelectronics Corporation filed for bankruptcy.

7. Privateering — Unclear. While UMC transferred the patent, and Marlin Semiconductor Ltd is now involved in litigation, there is no public information to confirm if Marlin Semiconductor Ltd is asserting the patent on UMC's behalf against UMC's competitors.

8. Defensive aggregator (anti-NPE) — Not present. The chain ends with Marlin Semiconductor Limited, which is not a known defensive aggregator.

Verdict

NPE — high confidence. The transfer of the patent from a large operating semiconductor foundry, United Microelectronics Corp, to Marlin Semiconductor Limited (Reel 065294/0055) is a strong signal. The subsequent filing of an IPR (IPR2026-00130) against Marlin Semiconductor Limited by Unified Patents, an organization specifically targeting NPEs, further reinforces this assessment. The lack of a clear product line for Marlin Semiconductor Limited and the timing of the transfer prior to the IPR also contribute to this conclusion.

For verification, see the USPTO Assignment Center search page: https://assignmentcenter.uspto.gov/ (search for patent number 9318609).

To identify the most relevant prior art for US patent 9318609, I will examine the "Citations" section of the patent itself, which lists prior art references cited by the examiner and/or third parties. This section is typically the most direct source of prior art considered during the patent's examination. I will then provide the requested information for each.

Here are the patent citations listed for US patent 9318609, along with their details:

Most Relevant Prior Art for US Patent 9318609

Below are the patent citations listed in US9318609B2, which represent prior art considered during its examination.

1. US6043138A

   • Full Citation: US6043138A - Multi-step polysilicon deposition process for boron penetration inhibition
   • Publication Date: 2000-03-28 (Priority Date: 1996-09-16)
   • Brief Description: This patent describes a multi-step polysilicon deposition process to inhibit boron penetration in semiconductor devices. While not directly detailing fin structures or recessed isolation, it pertains to fabrication processes and material properties in transistors.
   • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): Less likely to directly anticipate the structural claims of US9318609B2 (Claims 1, 5, 10) due to its focus on polysilicon deposition and impurity inhibition rather than the specific fin, isolation, and epitaxial layer geometry. It might be relevant to manufacturing aspects if those claims were broader, but given the specific structural elements claimed in US9318609B2, direct anticipation is unlikely. It could potentially serve as background art for general semiconductor fabrication.

2. US6492216B1

   • Full Citation: US6492216B1 - Method of forming a transistor with a strained channel
   • Publication Date: 2002-12-10 (Priority Date: 2002-02-07)
   • Brief Description: This patent describes a method for forming a transistor with a strained channel, which is relevant to the objective of US9318609B2 to increase carrier mobility through crystal strain technology using epitaxial layers.
   • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This patent is highly relevant as US9318609B2 explicitly mentions using strained silicon layers and epitaxial SiGe or SiC to improve device performance and carrier mobility, which is the core concept of US6492216B1. Claims 1, 5, 8, and 10 of US9318609B2, which describe the epitaxial layer and its function, could potentially be anticipated, especially regarding the broad concept of a strained channel formed by an epitaxial layer.

3. US20040195624A1

   • Full Citation: US20040195624A1 - Strained silicon fin field effect transistor
   • Publication Date: 2004-10-07 (Priority Date: 2003-04-04)
   • Brief Description: This publication describes a strained silicon fin field effect transistor (FinFET). This is highly relevant as US9318609B2 also describes a semiconductor device with a fin structure and an epitaxial structure designed to impart stress.
   • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This publication is extremely relevant, as it directly addresses "strained silicon fin field effect transistors." Claims 1, 5, 8, 9, and 10 of US9318609B2, which cover the fin structure, gate structure, isolation, epitaxial layer, and spacers, are highly susceptible to anticipation by this reference, particularly regarding the combination of finFET architecture with strained materials.

4. US20050051825A1

   • Full Citation: US20050051825A1 - Semiconductor device and manufacturing method thereof
   • Publication Date: 2005-03-10 (Priority Date: 2003-09-09)
   • Brief Description: This publication describes a semiconductor device and its manufacturing method, likely involving structures relevant to FinFETs or strained channels.
   • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): Without a more specific description of the device in US20050051825A1, it's difficult to pinpoint exact claim anticipation. However, given its publication date and general topic, it could potentially anticipate broader aspects of claims 1 and 5 relating to semiconductor device structures and manufacturing if it discloses similar fin, isolation, or epitaxial layer configurations.

5. US6921963B2

   • Full Citation: US6921963B2 - Narrow fin FinFET
   • Publication Date: 2005-07-26 (Priority Date: 2003-01-23)
   • Brief Description: This patent specifically describes a "narrow fin FinFET," directly addressing the fin structure aspect of US9318609B2.
   • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This patent is very relevant to Claim 1 of US9318609B2, which defines a semiconductor device with a fin structure. Depending on the specifics of the isolation structure and epitaxial layer in US6921963B2, it could anticipate elements of claims 1, 9, and 10.

6. US20060099830A1

   • Full Citation: US20060099830A1 - Plasma implantation using halogenated dopant species to limit deposition of surface layers
   • Publication Date: 2006-05-11 (Priority Date: 2004-11-05)
   • Brief Description: This publication focuses on plasma implantation techniques using specific dopant species to limit surface layer deposition. This is a manufacturing process detail.
   • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This patent is more focused on a specific fabrication technique (plasma implantation) rather than the overall device structure. It is unlikely to directly anticipate the structural claims of US9318609B2 (Claims 1, 5, 10). It could potentially be considered for method claims if US9318609B2 had any.

7. US7087477B2

   • Full Citation: US7087477B2 - FinFET SRAM cell using low mobility plane for cell stability and method for forming
   • Publication Date: 2006-08-08 (Priority Date: 2001-12-04)
   • Brief Description: This patent describes a FinFET SRAM cell and a method for forming it, utilizing a low mobility plane for cell stability. It involves FinFET architecture.
   • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This patent's discussion of FinFET SRAM cells and their formation is highly relevant to the FinFET aspects of US9318609B2. Claims 1, 9, and 10, which define the FinFET structure, could potentially be anticipated by this reference.

8. US7091551B1

   • Full Citation: US7091551B1 - Four-bit FinFET NVRAM memory device
   • Publication Date: 2006-08-15 (Priority Date: 2005-04-13)
   • Brief Description: This patent describes a four-bit FinFET NVRAM memory device. It further demonstrates the existence of FinFET technology prior to US9318609B2.
   • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): Similar to US7087477B2, this patent provides further evidence of FinFET technology. Claims 1, 9, and 10 of US9318609B2, relating to the FinFET structure, could be anticipated.

9. US20060286729A1

   • Full Citation: US20060286729A1 - Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate
   • Publication Date: 2006-12-21 (Priority Date: 2005-06-21)
   • Brief Description: This publication discusses a CMOS integrated circuit utilizing raised source/drain regions and a replacement metal gate process. US9318609B2 also mentions a replacement metal gate process.
   • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This reference is relevant to the "gate structure" aspect of US9318609B2, particularly if the gate structure is a metal gate (Claim 3) and if the epitaxial layer forms part of the source/drain regions. It could potentially anticipate Claim 3 and aspects of Claims 1, 5, and 10 if the raised source/drain regions are formed epitaxially.

10. US20070108528A1

    • Full Citation: US20070108528A1 - Sram cell
    • Publication Date: 2007-05-17 (Priority Date: 2005-11-15)
    • Brief Description: This publication generally describes an SRAM cell.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): Without further detail on the SRAM cell's specific construction, it's hard to assess direct anticipation. If the SRAM cell uses FinFETs with similar structural characteristics to US9318609B2, it could potentially anticipate elements of claims 1, 9, and 10.

11. US20070158756A1

    • Full Citation: US20070158756A1 - Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement
    • Publication Date: 2007-07-12 (Priority Date: 2006-01-12)
    • Brief Description: This publication directly concerns a "Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement," making it highly relevant to the FinFET device of US9318609B2.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This is a highly relevant reference. It could potentially anticipate most structural claims of US9318609B2, especially Claims 1, 5, 9, and 10, given its focus on FinFET arrangements and their production. The specific details of how the isolation structure and epitaxial layer are formed and their relative heights would be crucial for determining exact anticipation.

12. US7247887B2

    • Full Citation: US7247887B2 - Segmented channel MOS transistor
    • Publication Date: 2007-07-24 (Priority Date: 2005-07-01)
    • Brief Description: This patent describes a segmented channel MOS transistor.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): If the "segmented channel" involves structures akin to fin structures or if the segmentation impacts how strain is applied, this could be relevant to claims concerning the fin structure and epitaxial layer (Claims 1, 5, 10).

13. US7250658B2

    • Full Citation: US7250658B2 - Hybrid planar and FinFET CMOS devices
    • Publication Date: 2007-07-31 (Priority Date: 2003-06-26)
    • Brief Description: This patent describes hybrid planar and FinFET CMOS devices, showing the integration of both types of transistors.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This patent is relevant to the general field of FinFETs and their integration. Claims 1, 9, and 10 of US9318609B2, relating to the FinFET structure, could be anticipated depending on the specific FinFET configuration disclosed.

14. US7309626B2

    • Full Citation: US7309626B2 - Quasi self-aligned source/drain FinFET process
    • Publication Date: 2007-12-18 (Priority Date: 2005-11-15)
    • Brief Description: This patent details a "quasi self-aligned source/drain FinFET process," directly addressing FinFET fabrication and source/drain regions where epitaxial structures are typically formed.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This is a highly relevant reference, particularly to Claims 1, 5, 9, and 10 of US9318609B2, as it describes a FinFET process involving source/drain regions, which often incorporate epitaxial growth for strain. The specific arrangement of the isolation structure and epitaxial layer relative to the gate would be key to determining anticipation.

15. US7352034B2

    • Full Citation: US7352034B2 - Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
    • Publication Date: 2008-04-01 (Priority Date: 2005-08-25)
    • Brief Description: This patent focuses on integrating damascene-body FinFETs and planar devices on a common substrate.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This reference is relevant to FinFET structures and their integration. Claims 1, 9, and 10, which describe the FinFET structure, could be anticipated if the damascene-body FinFETs include similar isolation and epitaxial arrangements as claimed in US9318609B2.

16. US20080157208A1

    • Full Citation: US20080157208A1 - Stressed barrier plug slot contact structure for transistor performance enhancement
    • Publication Date: 2008-07-03 (Priority Date: 2006-12-29)
    • Brief Description: This publication describes a stressed barrier plug slot contact structure for enhancing transistor performance, which relates to stress application in transistors.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This reference is relevant to the concept of applying stress for performance enhancement, which is a goal of US9318609B2. Depending on how the stress is applied and its interaction with the fin and epitaxial structures, it could potentially anticipate aspects of claims 1, 5, 8, and 10.

17. US7470570B2

    • Full Citation: US7470570B2 - Process for fabrication of FinFETs
    • Publication Date: 2008-12-30 (Priority Date: 2006-11-14)
    • Brief Description: This patent explicitly covers a "Process for fabrication of FinFETs."
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This is a very relevant reference, as it describes FinFET fabrication. While US9318609B2 primarily claims a device, the described device is a product of a fabrication process. This reference could anticipate the structural features of Claims 1, 5, 9, and 10 if its FinFET fabrication process naturally leads to a device with the claimed characteristics.

18. US7525160B2

    • Full Citation: US7525160B2 - Multigate device with recessed strain regions
    • Publication Date: 2009-04-28 (Priority Date: 2005-12-27)
    • Brief Description: This patent describes a "multigate device with recessed strain regions." This is highly pertinent given US9318609B2's focus on fin structures (a type of multigate device) and epitaxial layers for strain.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This is a highly relevant reference. "Multigate device" encompasses FinFETs, and "recessed strain regions" directly relates to the epitaxial layer formed in recesses to induce strain as claimed in US9318609B2 (Claims 1, 5, 8, 10). The specific configuration of the recessed regions and how they interact with the isolation and gate structures would be critical for assessing direct anticipation of these claims.

19. US7531437B2

    • Full Citation: US7531437B2 - Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material
    • Publication Date: 2009-05-12 (Priority Date: 2004-09-30)
    • Brief Description: This patent describes a method for forming metal gate electrodes using sacrificial materials, which is consistent with the replacement metal gate (RMG) process mentioned in US9318609B2.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This reference is relevant to Claim 3 of US9318609B2, which specifies a metal gate structure. It could potentially anticipate the existence of a metal gate within a FinFET structure, particularly if the described method could be applied to FinFETs.

20. US20090124097A1

    • Full Citation: US20090124097A1 - Method of forming narrow fins in finfet devices with reduced spacing therebetween
    • Publication Date: 2009-05-14 (Priority Date: 2007-11-09)
    • Brief Description: This publication describes a method for forming narrow fins in FinFET devices with reduced spacing, directly related to the fin structure.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This is a relevant reference for FinFET fabrication, especially concerning the fin structure. It could potentially anticipate Claim 1 and related claims (9, 10) of US9318609B2, depending on the specific characteristics of the fins and their integration with other components.

21. US7569857B2

    • Full Citation: US7569857B2 - Dual crystal orientation circuit devices on the same substrate
    • Publication Date: 2009-08-04 (Priority Date: 2006-09-29)
    • Brief Description: This patent describes dual crystal orientation circuit devices, which can influence how strain is applied and its effects on carrier mobility.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This reference touches upon crystal orientation, which is fundamental to strain engineering in semiconductors. While not directly describing the FinFET structure of US9318609B2, it could be relevant to the underlying principles of applying stress for carrier mobility enhancement (Claims 8, 10) if the epitaxial layer's properties are linked to crystal orientation.

22. US20090242964A1

    • Full Citation: US20090242964A1 - Non-volatile memory device
    • Publication Date: 2009-10-01 (Priority Date: 2006-04-26)
    • Brief Description: This publication describes a non-volatile memory device.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): Without specific details of the non-volatile memory device's construction, it's difficult to assess direct anticipation. If it utilizes FinFET structures with elements similar to US9318609B2, it could potentially anticipate certain claims (e.g., 1, 9, 10).

23. US20090269916A1

    • Full Citation: US20090269916A1 - Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges
    • Publication Date: 2009-10-29 (Priority Date: 2008-04-28)
    • Brief Description: This publication describes methods for fabricating memory cells with fin structures having specific top surface and corner profiles.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This is a relevant reference for FinFET fabrication, specifically regarding the fin structure's geometry. It could potentially anticipate Claim 1 of US9318609B2 regarding the fin structure itself, particularly if the fin's shape impacts the integration of the isolation and epitaxial layers.

24. US20100048027A1

    • Full Citation: US20100048027A1 - Smooth and vertical semiconductor fin structure
    • Publication Date: 2010-02-25 (Priority Date: 2008-08-21)
    • Brief Description: This publication describes a smooth and vertical semiconductor fin structure, focusing on the quality and profile of the fin.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This reference focuses on the characteristics of the fin structure, directly relevant to Claim 1 of US9318609B2. It could potentially anticipate aspects of the fin structure's definition.

25. US20100072553A1

    • Full Citation: US20100072553A1 - METAL GATE STRESS FILM FOR MOBILITY ENHANCEMENT IN FinFET DEVICE
    • Publication Date: 2010-03-25 (Priority Date: 2008-09-23)
    • Brief Description: This publication describes a metal gate stress film for mobility enhancement in FinFET devices. This is highly relevant as it combines FinFETs, metal gates, and stress application.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This is a highly relevant reference. It combines several key elements of US9318609B2: FinFET devices, metal gates (Claim 3), and mobility enhancement through stress. It could potentially anticipate Claims 1, 3, 5, 8, 9, and 10 of US9318609B2, especially if the "stress film" functions similarly to the epitaxial layer in applying stress and its integration with the gate and fin is comparable.

26. US20100144121A1

    • Full Citation: US20100144121A1 - Germanium FinFETs Having Dielectric Punch-Through Stoppers
    • Publication Date: 2010-06-10 (Priority Date: 2008-12-05)
    • Brief Description: This publication describes Germanium FinFETs with dielectric punch-through stoppers, indicating the use of different semiconductor materials in FinFETs.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This reference is relevant for FinFETs using different materials, such as Germanium, which relates to the composition of the epitaxial layer (Claim 8). It could potentially anticipate the use of specific materials in FinFET structures, and elements of Claim 1, 5, and 10.

27. US20100167506A1

    • Full Citation: US20100167506A1 - Inductive plasma doping
    • Publication Date: 2010-07-01 (Priority Date: 2008-12-31)
    • Brief Description: This publication describes inductive plasma doping, a semiconductor manufacturing process.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): Similar to US20060099830A1, this reference is focused on a specific manufacturing technique. It is unlikely to directly anticipate the structural claims of US9318609B2 (Claims 1, 5, 10).

28. US20120193713A1

    • Full Citation: US20120193713A1 - FinFET device having reduce capacitance, access resistance, and contact resistance
    • Publication Date: 2012-08-02 (Priority Date: 2011-01-31)
    • Brief Description: This publication describes a FinFET device designed to reduce capacitance, access resistance, and contact resistance.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This is a relevant reference for FinFET device characteristics. It could potentially anticipate elements of Claim 1, 5, 9, and 10 of US9318609B2, particularly if the design features described to reduce resistance and capacitance involve similar fin, isolation, and contact structures.

29. US8765533B2

    • Full Citation: US8765533B2 - Fin-like field effect transistor (FinFET) channel profile engineering method and associated device
    • Publication Date: 2014-07-01 (Priority Date: 2012-12-04)
    • Brief Description: This patent describes a FinFET channel profile engineering method and the associated device, focusing on shaping the channel region of FinFETs.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This is a highly relevant reference, especially to Claim 1 of US9318609B2, as it focuses on FinFET channel profiles. The specific engineering of the channel could involve aspects of the fin structure and how it interfaces with the gate and potentially the epitaxial layer. It could also anticipate elements of Claims 5 and 10 depending on whether the channel profile engineering involves similar recessed regions or epitaxial growth.

To analyze the obviousness of US patent 9318609 under 35 U.S.C. § 103, it's necessary to consider the "person having ordinary skill in the art" (PHOSITA) and what would have been obvious to them at the time of the invention, given the prior art. The PHOSITA is a hypothetical person with ordinary skill, ordinary creativity, and ordinary knowledge in the relevant technical field, who is presumed to have known all relevant prior art at the time of the invention. This person is not a genius, nor are they an inventor; they are expected to follow conventional wisdom and apply known techniques in a predictable manner.

The stated objective of US9318609 is to provide a semiconductor device with an epitaxial layer such that stress imposed on the channel region can be increased, and to prevent the formation of void defects in the epitaxial layer by reducing the height of the isolation structure at the sides of the gate structure, thus preventing the epitaxial structure from being sealed during growth.

The patent itself lists 29 prior art documents. For a thorough obviousness analysis, each independent claim would need to be considered against combinations of these references. However, without a detailed breakdown of the specific teachings of each of the 29 cited prior art references, a complete obviousness analysis with specific combinations is not possible. The patent text only provides titles and publication details for these references, not their full content.

Therefore, this analysis will identify common themes in the prior art, and suggest how a PHOSITA might combine elements to achieve the claimed invention, based on the abstract and description of US9318609, and general knowledge in the field.

Level of Ordinary Skill in the Art (PHOSITA) for US9318609

For US9318609, the PHOSITA would be an individual with knowledge and experience in semiconductor device fabrication, particularly in the areas of FinFET technology, crystal strain engineering, and epitaxial growth processes. This would likely include:

• Educational Level: A bachelor's or master's degree in electrical engineering, materials science, or a related field, potentially with practical experience in semiconductor manufacturing or research.
• Technical Understanding: Familiarity with MOSFET and FinFET structures, shallow trench isolation (STI), gate-last processes (including high-k last), and the principles of applying strain to semiconductor channels to enhance carrier mobility.
• Process Knowledge: Understanding of various semiconductor fabrication techniques, including etching (wet and dry), deposition, photolithography, and epitaxial growth (e.g., MBE, selective epitaxial growth).
• Problem Solving: An awareness of common challenges in advanced semiconductor manufacturing, such as defect formation (e.g., void defects in epitaxial layers) and methods to mitigate them.

General Obviousness Considerations (based on common problems and solutions in the art)

The background of US9318609 explicitly states that "crystal strain technology has been developed" to improve device performance by increasing carrier mobility. It also acknowledges that "attempts have been made to use a strained silicon layer as a part of MOS transistors in which an epitaxial silicon germanium (SiGe) structure or an epitaxial silicon carbide (SiC) structure is formed". The core problem addressed by the patent is the formation of "void defects in the epitaxial layer" due to the high aspect ratio of epitaxial layers in continuously shrinking devices, which reduces the desired stress on the channel region. The solution proposed is to reduce the height of the isolation structure at the sides of the gate, preventing the epitaxial structure from being sealed during growth and thus avoiding voids.

Given this context, a PHOSITA would be motivated to address the problem of void defects in epitaxial layers used for strain engineering. If prior art references individually disclose elements of the claimed invention, and there's a recognized problem that the combination would solve, or if the combination simply yields predictable results, it could be considered obvious.

Potential Combinations of Prior Art (Hypothetical)

Without access to the full text of the 29 cited prior art references, it is difficult to identify precise combinations. However, based on the general descriptions and the problem/solution presented in US9318609, here are some hypothetical scenarios for obviousness, assuming typical disclosures in the cited prior art:

Assumption 1: Prior art discloses FinFETs with strained epitaxial source/drain regions, and separate prior art discloses recessed isolation structures.

• Scenario: Many of the cited prior art documents relate to FinFETs, strained channels, and semiconductor fabrication. For example, US20040195624A1 is titled "Strained silicon fin field effect transistor," US20060286729A1 is "Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate," and US7525160B2 is "Multigate device with recessed strain regions." It is highly probable that several of the cited references disclose the general concept of forming a fin structure, an isolation structure, a gate structure, and strained epitaxial regions in FinFETs to enhance performance.
• Combination: If a primary reference (e.g., US20040195624A1) discloses a FinFET device with a fin structure, an isolation structure, a gate structure, and an epitaxial layer for strain, but does not explicitly show the recessed isolation structure to prevent voids, a PHOSITA would look for solutions to common problems in epitaxial growth.
• Motivation: The problem of void defects in high-aspect-ratio epitaxial layers is explicitly stated in US9318609 as an "important issue". A PHOSITA, aware of this known problem, would be motivated to find ways to improve epitaxial growth quality. If other prior art references (not explicitly detailed here, but presumed to exist within the 29 cited) teach methods of recessing isolation structures to improve subsequent deposition or growth processes, or to alter the geometry for improved filling, a PHOSITA would be motivated to combine these teachings. For example, if a reference like US7531437B2 ("Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material") or other general fabrication method patents discuss modifying trench isolation or dielectric heights, a PHOSITA would understand the utility of such modifications for different subsequent steps. Reducing the height of the isolation structure to create a larger opening for epitaxial growth and prevent sealing would be a predictable modification to address the known void defect problem.
• Obviousness: The combination would be obvious because the primary reference provides the basic FinFET structure with epitaxial strain, and the secondary reference provides a known technique (recessing isolation structures) that a PHOSITA would apply to solve a recognized problem (void defects in epitaxial growth) in a predictable way.

Assumption 2: Prior art discusses the importance of avoiding sealing during epitaxial growth in other contexts.

• Scenario: The patent highlights that "since the epitaxial structure is not sealed during the epitaxial growth process, the void defects may be also avoided as a result". This suggests that avoiding sealing during epitaxial growth was a known desideratum in the art.
• Combination: If the prior art (e.g., some of the fabrication method patents listed like US6492216B1 "Method of forming a transistor with a strained channel" or US20050051825A1 "Semiconductor device and manufacturing method thereof") generally discusses epitaxial growth challenges and the importance of open geometries, even if not specifically in the context of recessed STI in FinFETs.
• Motivation: A PHOSITA, encountering the problem of void defects in FinFET epitaxial regions, would recognize that preventing the sealing of the growth area could solve this problem. If general epitaxial growth literature (which would be known to a PHOSITA) taught that open geometries prevent sealing and improve fill, the idea of recessing the adjacent isolation structure to achieve this would be a logical and predictable step for the PHOSITA.
• Obviousness: The combination would be obvious because the general principle of avoiding sealing during epitaxial growth is known, and applying a known structural modification (recessing the isolation) to achieve this known beneficial outcome in a FinFET context would be within the ordinary skill of the art.

Assumption 3: Prior art discloses variable height isolation structures for different purposes, and other prior art discloses epitaxial strain in FinFETs.

• Scenario: Claim 1 specifically states that "the isolation structure under the gate structure has a first top surface and the isolation structure at two sides of the gate structure has a second top surface, and the first top surface is higher than the second top surface." It's possible that prior art documents, such as those related to STI processes (e.g., some general semiconductor process patents), disclose varying the height of isolation structures for various reasons (e.g., to reduce capacitance, adjust stress, or facilitate subsequent processing steps).
• Combination: A PHOSITA would be aware of various methods for creating differential heights in isolation structures. When combined with the known need for strained epitaxial layers in FinFETs (from references like US20040195624A1 or US20100072553A1 "METAL GATE STRESS FILM FOR MOBILITY ENHANCEMENT IN FinFET DEVICE"), and the known problem of void defects, the PHOSITA would be motivated to combine these elements.
• Motivation: The motivation would stem from the recognized problem of void defects during epitaxial growth in high-aspect-ratio structures and the understanding that creating a more open geometry could alleviate this. Adjusting the isolation structure height is a known parameter in semiconductor fabrication, and a PHOSITA would predictably manipulate this to optimize epitaxial fill and stress, particularly in light of known issues like void formation.
• Obviousness: The combination would be obvious as it involves applying a known structural variation (differential isolation height) to a known device (FinFET with strained epitaxy) to solve a known problem (epitaxial voids) using a predictable approach (creating more open space for growth).

Conclusion

A definitive obviousness analysis requires full access to and detailed review of the 29 prior art references cited in US9318609. However, based on the problem statement and solution described in the patent, it is likely that a person having ordinary skill in the art would have been motivated to combine existing knowledge in FinFET fabrication, strain engineering, and epitaxial growth techniques. The core inventive step, as described, revolves around the specific geometry of recessing the isolation structure to prevent void defects during epitaxial growth. If prior art teaches FinFETs with strained epitaxial regions and also teaches methods for recessing isolation structures (perhaps for other purposes, but with recognizable benefits for deposition/growth), or if it broadly discusses avoiding sealing during epitaxial processes, then the combination to achieve the claimed invention would likely be considered obvious. The height difference between the first and second top surfaces of the isolation structure, ranging from 100 to 250 Angstroms (Claim 2), also appears to be a matter of routine optimization for a PHOSITA once the concept of recessing the isolation for void prevention is understood.

To accurately determine the patent term adjustments (PTA), patent term extensions (PTE), continuation/divisional applications, related family members, and the projected expiration date for US patent 9318609, a direct search of the USPTO database (specifically Patent Center or PAIR) for the patent is required. Information regarding PTA is calculated by the USPTO at the time of patent issuance and is included in the Issue Notification Letter. PTE is typically granted for patents on certain human drugs, food or color additives, medical devices, animal drugs, and veterinary biological products to compensate for time lost during premarket regulatory review.

Based on the information available from the patent text provided:

Patent Term Adjustment (PTA):
The patent document itself (US9318609B2) does not explicitly state the Patent Term Adjustment. This information is typically provided in the Issue Notification Letter by the USPTO. To get the precise PTA, one would need to access the official patent prosecution history via USPTO's Patent Center. PTA is an addition to the 20-year lifespan of a utility or plant patent and is intended to compensate for delays caused by the USPTO during the prosecution of the application.

Patent Term Extension (PTE):
There is no indication in the patent document (US9318609B2) that a Patent Term Extension (PTE) was applied for or granted. PTEs are generally reserved for patents covering products that undergo pre-market regulatory review, such as pharmaceuticals and medical devices, to restore patent term lost during that review period. Given the nature of this patent (semiconductor device), it is highly unlikely to be eligible for a PTE.

Continuation Applications:
US9318609B2 is listed as a divisional of U.S. application Ser. No. 13/913,511, filed on Jun. 9, 2013. This means that 13/913,511 is a parent application.

Divisional Applications:
The patent US9318609B2 itself is a divisional application of U.S. application Ser. No. 13/913,511.

Related Family Members:
The patent text explicitly states that US9318609B2 is a "division of U.S. application Ser. No. 13/913,511, filed on Jun. 9, 2013". U.S. application Ser. No. 13/913,511 eventually issued as US8993384B2. Therefore, US8993384B2 is a related family member (the parent patent). The "Priority date" for US9318609B2 is 2013-06-09, which aligns with the filing date of the parent application, US13/913,511.

Projected Expiration Date:
The anticipated expiration date stated in the patent information is 2033-06-09. This date is calculated as 20 years from the earliest effective filing date, which in this case is the priority date of 2013-06-09 (the filing date of its parent application US13/913,511), plus any Patent Term Adjustment (PTA). However, the patent explicitly notes "Anticipated expiration 2033-06-09" and states that this is an "assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed." To confirm the exact expiration date, including any PTA, one would need to consult the official USPTO records for the patent, as PTA can adjust the term.