US 8633537

I'll search for authoritative records on US 8633537 across USPTO and court dockets.

Let me search for the claim text and any court/CAFC docket activity.

Let me try to retrieve the actual granted claim text and any appellate docket activity.

Summary — US 8,633,537 B2

Caveat up front: I was able to confirm the bibliographic data and claim text for this patent's pre‑grant publication, but I was not able to retrieve the granted claim set verbatim from an authoritative source in this session, and I found no Federal Circuit 2026 docket activity for it. Details and discrepancies are flagged below rather than smoothed over.

Bibliographic data (as recorded)

Priority chain (per the patent's own cross‑reference): the '537 is a continuation‑in‑part of 13/288,919 (filed 2011‑11‑03), which is a divisional of 12/152,518 (filed 2008‑05‑13, now US 8,063,434), which claims benefit of provisional 60/940,160 (filed 2007‑05‑25). Continuations in the same family include US 9,093,318; 9,502,543; 9,929,240; 10,346,656; 10,446,656; 11,056,565; 11,456,365; 11,721,733; 12,009,401.

⚠️ Identifier discrepancy (flagged, not corrected): the specification text of US 9,502,543 describes its parent as "application No. 13/593,466, filed on Jul. 1, 2012, now Pat. No. 8,633,537." The '537 patent's own record, its publication (2013/0307053), Google Patents, and FreePatentsOnline all give 13/539,466. Both numbers appear in the public record for this family; I am reporting them literally rather than assuming which is correct.

Abstract (verbatim)

"A semiconductor devices including non-volatile memories and methods of fabricating the same to improve performance thereof are provided. Generally, the device includes a memory transistor comprising a polysilicon channel region electrically connecting a source region and a drain region formed in a substrate, an oxide-nitride-nitride-oxide (ONNO) stack disposed above the channel region, and a high work function gate electrode formed over a surface of the ONNO stack. In one embodiment the ONNO stack includes a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an oxygen-lean second nitride layer disposed above the first nitride layer. Other embodiments are also disclosed."

Independent claims — plain language

Important qualification on claim text. The following is the claim language from the pre‑grant publication US 2013/0307053 A1 (Justia record explicitly links that publication to grant 8633537, same application 13/539,466). The granted claims appear to have been renumbered/reordered during prosecution: the granted patent lists "recrystallized polysilicon" as claim 6, whereas in the pre‑grant publication that limitation is claim 3. So amendments clearly occurred, and I cannot vouch that the granted independent claims read exactly as below. Verify against USPTO Patent Center / Patent Public Search or the FPO record.

Published claim 1 — the primary independent claim (device):
A semiconductor device with two parts:

1. A memory transistor including:

• a channel region comprising polysilicon that electrically connects a source region and a drain region formed in a substrate;
• an oxide‑nitride‑nitride‑oxide (ONNO) stack above the channel region, the ONNO stack containing a multi‑layer charge‑trapping region with an oxygen‑rich first nitride layer and an oxygen‑lean second nitride layer disposed above the first nitride layer; and
• a high work function gate electrode formed over a surface of the ONNO stack; and

1. A MOS logic transistor on the same substrate, comprising a gate oxide and its own high work function gate electrode.

In plain terms: a SONOS‑type charge‑trap memory cell with a split (oxygen‑rich / oxygen‑lean) nitride storage layer and a high‑work‑function poly gate, co‑fabricated on one die with a logic transistor that also uses a high‑work‑function gate.

Two further independent claims appear in the related PCT application WO 2014/008166 A1 (PCT/US2013/048885, which claims priority to the '537) — these may or may not correspond one‑for‑one to granted independent claims:

• Claim 11 (ONONO variant): polysilicon channel region + an oxide‑nitride‑nitride‑oxide‑nitride‑oxide (ONONO) stack comprising a tunnel dielectric layer, a multi‑layer charge‑trapping region (oxygen‑rich first nitride / oxygen‑lean second nitride / oxide anti‑tunneling layer separating the two nitride layers), and a blocking dielectric layer; plus a high work function gate electrode above the ONONO stack.
• Claim 18 (vertical‑channel variant): a vertical polysilicon channel extending from a first diffusion region at the substrate surface to a second diffusion region above it; an ONNO stack disposed about the vertical channel (tunnel dielectric abutting the channel; multi‑layer charge‑trapping region with an oxygen‑rich nitride first layer and a silicon‑rich, oxygen‑lean nitride second layer; blocking dielectric layer); and a high work function gate electrode disposed about the stack, abutting the blocking dielectric.

Representative dependent claim themes: channel comprising a silicon nanowire; recrystallized (monocrystalline) polysilicon channel; the anti‑tunneling oxide layer (appearing as a dependent claim in the PCT set); N+ doped polysilicon gates → PMOS SONOS memory + NMOS logic; P+ doped polysilicon gates → NMOS SONOS memory + PMOS logic; and both gate electrodes formed from a single, patterned doped polysilicon layer.

"High work function" as defined in the spec: gate doping selected so the minimum energy to remove an electron is about 4.8 eV to about 5.3 eV, achieved e.g. by implanting boron (B+) or BF₂ at 5–100 keV and a dose of 1×10¹⁴–1×10¹⁶ cm⁻², in a poly layer 200–2000 Å thick.

Litigation / docket status

What the record shows (Google Patents "Family has litigation" block, sourced from Unified Patents and Darts‑ip):

• N.D. Cal. case 5:25‑cv‑02389 (US case filed in California Northern District Court) — 2025.
• C.D. Cal. case 8:25‑cv‑00119 (US case filed in California Central District Court) — 2025.
• First worldwide family litigation recorded under Darts‑ip family 49580624.
• **PTAB: Sandisk Technologies, Inc. v. Longitude Flash Memory Solutions Ltd., IPR2025‑01283**, filed 2025‑10‑14, terminated 2026‑02‑20 as settled pre‑institution (joint motion to dismiss; Patent Owner had filed a discretionary‑denial request on 2025‑12‑22). Note: that IPR challenged US 9,929,240 — a different, related family member, not the '537 itself.
• Public reporting indicates an IPValue affiliate (Longitude Flash Memory Solutions, Ltd.) granted SanDisk a worldwide, non‑exclusive license to the Cypress‑origin portfolio, resolving outstanding disputes.

Federal Circuit (2026): I found no CAFC docket or appeal in 2026 involving US 8,633,537. My searches were general web searches, not direct queries of the CAFC docket system (PACER/CM‑ECF or the Federal Circuit's own docket), so this is a negative finding from limited sources rather than a verified absence — treat it as uncertain.

Other uncertainty notes

• The "THUMB, Inc." current‑assignee entry on the Google Patents page corresponds to a 2012‑08‑01 change‑of‑name reassignment whose recorded assignor is "OPINIONAIDED, INC." — which does not obviously belong in this patent's chain of title. I am reporting it as recorded and not inferring its significance.
• Google Patents itself states the assignee list "may be inaccurate" and that it has performed no legal analysis.
• The specification excerpt I hold is truncated partway through the detailed description and does not include the printed claim set, which is why the claim discussion above rests on the pre‑grant publication and the related PCT rather than the granted text.

I'll research litigation involving US patent 8633537. Let me run several searches.

Let me search the specific case numbers and litigation portals.

I found significant results. Let me dig deeper into the specific cases and confirm the patent at issue.

I've gathered the available information. Here's my report on litigation involving US Patent No. 8,633,537.

Summary

US 8,633,537 ("Memory transistor with multiple charge storing layers and a high work function gate electrode") is a Cypress Semiconductor-origin patent, now held in the THUMB Inc. / Longitude Flash Memory Solutions Ltd. family. It has been drawn into a recently-filed patent dispute between IPValue Management / Longitude and Western Digital / SanDisk. Both cases are active; no judgment or final disposition is known as of the searches performed.

I could confirm two litigations. Note upfront: I was not able to independently open the dockets to verify the exact list of asserted patents in each case, so the linkage of this specific patent rests primarily on the Google Patents "Family has litigation" data for US 8,633,537 and on the RPX/RPX Empower reporting below. Treat case-status details as needing confirmation against PACER.

Case 1 — IPValue Management, Inc. et al. v. Western Digital Corporation

• Plaintiff(s): IPValue Management, Inc. and Longitude Flash Memory Solutions Ltd.
• Defendant(s): Western Digital Corporation (SanDisk Corporation added/also named via First Amended Complaint; served 4/18/2025)
• Jurisdiction / Court: U.S. District Court, Central District of California (Western Division)
• Case No.: 8:25-cv-00119 — now captioned 8:25-cv-00119-MWF (DFMx) after reassignment from Judge Christina A. Snyder to Judge Michael W. Fitzgerald
• Filing Date: January 22, 2025
• Nature: Patent infringement (35 U.S.C. § 271); jury demand noted. Per RPX Empower ("IPValue Sues Western Digital over Former Cypress Semiconductor Patents," Jan. 25, 2025), the complaint asserts five patents received from Cypress Semiconductor and accuses a wide array of products containing 3D NAND flash memory (embedded flash, HDDs, SSDs, USB flash drives, memory cards). The complaint indicates LFMS owns the patents, with IPValue possessing substantial rights including the right to enforce.
• Current status: Pending. Initial pleadings filed Jan. 22, 2025; a First Amended Complaint was filed adding SanDisk, and service on SanDisk was executed April 18, 2025 (answer originally due May 9, 2025). No outcome available.

Sources: Google Patents litigation link for the patent (California Central District Court, case 8:25-cv-00119); Docket via Justia — https://dockets.justia.com/docket/california/cacdce/8:2025cv00119/[954920](/patent/954920) ; PACER Monitor — https://www.pacermonitor.com/public/case/56601628/Ipvalue_Management,_Inc_et_al_v_Western_Digital_Corporation ; RPX Empower news — https://litigation.rpxcorp.com/news/84773-ipvalue-sues-western-digital-over-former-cypress-semiconductor-patents

Case 2 — SanDisk Corporation v. IPValue Management, Inc. et al.

• Plaintiff(s): SanDisk Corporation
• Defendant(s): IPValue Management, Inc. et al. (i.e., the Longitude/IPValue entities)
• Jurisdiction / Court: U.S. District Court, Northern District of California
• Case No.: 5:25-cv-02389
• Filing Date: March 7, 2025
• Nature: This appears to be a mirror-image / declaratory-judgment style action brought by SanDisk against the IPValue/Longitude group — logically related to the Central District infringement suit above (SanDisk is the affiliate of Western Digital). I could not retrieve the full docket text.
• Current status: Pending; docket updated on a daily basis per RPX Empower. No outcome available.

Sources: Google Patents litigation link for the patent (California Northern District Court, case 5:25-cv-02389); RPX Empower docket — https://litigation.rpxcorp.com/litigation/candce-[446095](/patent/446095)-sandisk-corporation-v-ipvalue-management-inc-et-al

The Google Patents record also references a Darts-IP entry for the "First worldwide family litigation" (https://patents.darts-ip.com/?family=49580624...), which is consistent with the same family dispute.

Important caveats / false matches I ruled out

1. Do not confuse with an unrelated "'353" patent. Some search results refer to a "'353 Patent" granted December 2, 2008 with claims 1, 33, 36, 43, 48, 51, 52, 58, 59, 66, 118, 138, 139, 149, 183, 252, 283, 317, owned by AI-Core Technologies, LLC (a SoftView-related NPE) and litigated across SoftView cases. That is a different patent (last three digits "353" but a different number, granted ~2008, with 300+ claims). It is not US 8,633,537 (granted January 21, 2014). I excluded it.
2. The "Longhorn Automotive Group" litigation table mentioning various patents is unrelated to US 8,633,537.
3. PTAB/IPR proceedings: I did not find any inter partes review or other PTAB post-grant proceeding specifically challenging US 8,633,537. If one exists, I could not confirm it — say so explicitly rather than assume.

Bottom line

Two known litigations involve US 8,633,537, both pending as of the last dockets retrieved (Jan. 2025 / Mar. 2025 data):

1. IPValue Management, Inc. et al. v. Western Digital Corp., C.D. Cal., 8:25-cv-00119 (filed Jan. 22, 2025) — infringement suit.
2. SanDisk Corp. v. IPValue Management, Inc. et al., N.D. Cal., 5:25-cv-02389 (filed Mar. 7, 2025) — related action.

No final outcomes are known. If you need the exact asserted-patent lists, current docket entries, or confirmation of any PTAB challenges, those should be pulled directly from PACER (and the USPTO PTAB docket) for these case numbers.

I'll verify whether any PTAB proceedings exist on this patent before drafting.

Let me dig specifically for any PTAB filings on this patent and the 2025 litigation.

Significant 2025–2026 activity is surfacing. Let me pin down which proceedings actually target the '537 patent itself versus its family members.

Proceedings overview

Total AIA trial proceedings naming U.S. Patent No. 8,633,537 as the challenged patent: 0. The USPTO ODP structured block states plainly that no AIA trial proceedings are on file for this patent as of the most recent ingest, and my independent web searches surfaced no IPR, PGR, or CBM petition ever filed against the '537 patent itself — so the breakdown is 0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution denials. Bottom line for a defendant: the '537 patent is entirely untested at the PTAB. No claim has been canceled, and no claim has been confirmed — there is no claim-level validity precedent of any kind. That cuts both ways: demanding-letter rhetoric that treats the patent as "hardened" is false, but so is any assumption that the claims are dead. What does exist is a rich, closely-related 2025–2026 PTAB and district-court record involving other patents in the same Cypress/Longitude charge-trap family, which I detail below because it is the practical proxy for what would happen if the '537 patent were challenged.

⚠️ Important caveat on identifications. Several search hits for "the '537 patent" refer to different patents: Cisco's U.S. Pat. No. 7,617,537 (router database subsystems, Fed. Cir. appeal in Cisco v. Arista), Illumina's U.S. Pat. No. 9,713,537 (nucleotide sequencing), and Micron's U.S. Pat. No. 6,324,537. None of those are this patent. I have excluded all of them. The proceedings below were verified against patent numbers, not party names alone.

IPR2025-01281 — Sandisk Technologies, Inc. et al. v. Longitude Flash Memory Solutions Ltd. et al.

(Challenged U.S. Pat. No. 11,456,365 — a continuation in the '537 family. The '537 patent itself appears only as evidence, not as the challenged patent.)

• Type: Inter Partes Review
• Filed: 2025-09-03
• Status: "Terminated-Settled" (terminated 2026-02-20, pre-institution — no institution decision ever issued)
• Judge panel: Not public in the sources I could access; no FWD issued, so no merits panel opinion exists.
• Petition grounds: Grounds are not itemized in the aggregator metadata I retrieved. The petition exhibit list (all filed 2025-09-03) is § 102/§ 103-shaped: Lee US 2012/0068255, KR 10-2011-0118961 (Lee), Fujiwara US 2006/0065919, Frohman-Bentchkowsky US 4,203,158, Kim US 2006/0255399, Nomoto US 2003/0122204, Levy US 2009/0179253, Heo US 2011/0045647, Ganguly US 2011/0281429, Wang US 2006/0113586, Yang US 6,897,533, Lue US 2006/0198189, Lai US 2009/0059676, Noguchi US 2005/0006696, Higuchi US 2010/0157680, Jung US 2008/0128790, Choi US 2003/0198106, Ou US 2009/0026460, Kim US 2010/0178759, Jeon US 2006/0118858, Shih US 2005/0237809, Yang US 2012/0276696, Jang US 2013/0270625, Lee US 2012/0068247, Lee US 2012/0299086, Kim US 2011/0316064, Zheng US 6,912,163, Sekine US 2010/0019312, Lai US 7,450,423, plus Arreghini, Tanaka (BiCS), Zhou, Sze, and Lukasiak & Jakubowski. I cannot state the precise statutory basis or claim-by-claim mapping without the petition text — do not treat this list as the grounds.
• Institution decision: None. The docket shows a Board "Director Discretionary Decision: Refer" on 2026-01-09 and termination on 2026-02-20 — i.e., the case ended before any institution decision.
• Final Written Decision: None issued.
• Settlement / termination: Joint motion to dismiss/terminate filed 2026-01-21 with a joint request to treat the Confidential Patent License Agreement as business confidential (terms not public). Exhibits filed with the motion were stipulations of dismissal in Sandisk Corp. v. IPValue Management, Inc., 5:25-cv-02389 (N.D. Cal.) and IPValue Management, Inc. v. Sandisk Corp., 8:25-cv-00119 (C.D. Cal.). Board termination decision: pre-DI settlement, 2026-02-20.
• Appeal: None. A pre-institution settlement termination is not appealable.
• Defensive value: Nothing directly for the '537 patent — the proceeding never reached institution, so no § 315(e)(2) estoppel attaches. Its real value is evidentiary: Sandisk had both U.S. Patent No. 8,633,537 and the '537 prosecution file history in its exhibit set (filed 2025-09-03 and 2025-12-16), meaning a sophisticated challenger has already built a family-level defense file covering the '537 patent. That work product is a starting point, not a shield.

IPR2025-01283 — Sandisk Technologies, Inc. v. Longitude Flash Memory Solutions Ltd.

(Challenged U.S. Pat. No. 9,929,240 — another '537-family continuation. The '537 patent itself is not the subject.)

• Type: Inter Partes Review
• Filed: 2025-10-14 (Tech Center 2800, Art Unit 2893)
• Status: "Terminated-Settled" (terminated 2026-02-20, pre-institution)
• Judge panel: Not public in my sources; no FWD.
• Petition grounds: Not retrievable from the metadata I had; exhibits included Lee US 2012/0068255, KR 10-2011-0118961, Fujiwara US 2006/0065919, Kim US 2006/0255399, Nomoto US 2003/0122204, Levy US 2009/0179253, Heo US 2011/0045647, Ganguly US 2011/0281429, Lue US 2006/0198189, Lai US 2009/0059676, and others — again a § 102/§ 103-style art set, but I will not assert the statutory basis I did not read.
• Institution decision: None. Patent Owner filed a Request for Discretionary Denial (2025-12-22); the Board terminated on 2026-02-20 before deciding institution.
• Final Written Decision: None issued.
• Settlement / termination: Joint motion to dismiss due to settlement, filed 2026-01-21; Board termination 2026-02-20.
• Appeal: None.
• Defensive value: Confirms the pattern — Longitude/IPValue's family patents are being counter-attacked with multiple parallel IPRs, and Longitude settles rather than litigates the PTAB to a merits ruling. No estoppel arises.

Unconfirmed siblings. Sandisk's September/October 2025 filings appear to have been a multi-patent batch (the -01281 through -01285 number neighborhood), and I saw passing references to other 2025 Sandisk/Longitude IPR numbers in that range. Because I could not verify their docket numbers, patents, or dispositions, I am not listing them and you should not cite any of them. Verify the complete set at PTAB E2E before relying on it.

Family litigation context (not PTAB, but material)

• 2025-01-22 — IPValue Management, Inc. et al. v. Western Digital Corp., No. 8:25-cv-00119 (C.D. Cal.), asserting five former Cypress patents against Western Digital/Sandisk products containing 3D NAND flash. Later amended to add Sandisk Corporation as a defendant.
• 2025-03-07 — Sandisk Corp. v. IPValue Management, Inc. et al., No. 5:25-cv-02389 (N.D. Cal.), declaratory judgment action.
• Both cases were stipulated dismissed on/around 2026-01-21 as part of the same global settlement that terminated IPR2025-01281 and IPR2025-01283.

Strategic summary

Claim status of the '537 patent: all claims UNTESTED. No claim of U.S. 8,633,537 has been canceled, confirmed, disclaimed, or even subjected to an institution decision. The patent remains in force per ODP with an adjusted expiration of 2028-09-26. If you are being accused under this patent, there is no claim-level PTAB holding to cite in either direction — you cannot point to a canceled independent claim, and plaintiff cannot point to a surviving one. Be wary of any demand letter that characterizes this patent as "previously upheld" or "validated": family-level settlement silence is not affirmance.

Estoppel landscape: essentially clean, which is the good news for a defendant. Section 315(e)(2) estoppel attaches only after a final written decision. There is no FWD on the '537 patent, and the two family IPRs (IPR2025-01281 and IPR2025-01283) terminated pre-institution by settlement — so neither Sandisk nor any privy is estopped from raising any ground against the '537 patent. Practically, that means the full prior-art universe remains available: you are free to run art Sandisk did not raise, art Sandisk raised elsewhere, and § 112 grounds (which cannot be raised in an IPR at all and are always reserved for district court or a PGR). The corollary: because no estoppel runs against you, you also get no free ride from Sandisk's work product.

Pattern signals. (i) The same petitioner — Sandisk Technologies, Inc. (with Sandisk GmbH in one filing) — filed at least two, and probably a batch of, IPRs against Longitude's charge-trap family in Sept–Oct 2025. (ii) The patent owner, Longitude Flash Memory Solutions Ltd. (with IPValue Management, Inc. as co-enforcer, and with Thumb Inc. appearing in the assignment record per ODP), did not pursue PTAB appeals or merits rulings — it settled globally in January 2026 and walked away from both IPRs and both district court cases. (iii) No defensive aggregator (e.g., Unified Patents) appears as a petitioner on this patent; the Unified Patents links in the Google Patents record are litigation data sources, not a party. (iv) The '537 patent was, however, already collected as an exhibit and its prosecution history pulled by a large petitioner — the defense bar is already aware of it.

One IPR-specific fragility worth developing. The '537 patent's priority claim runs back through U.S. App. No. 12/152,518 (filed 2008-05-13) to provisional 60/940,160 (filed 2007-05-25), and the application itself was filed 2012-07-01 as a CIP. CIP-versus-priority disputes of exactly this shape are a recurring IPR battleground, and Sandisk's exhibit list in IPR2025-01281 included both the '537 prosecution file history and the 60/940,160 provisional. If you contemplate your own petition, priority date (§ 102/§ 103 effective date) and the CIP's new-matter boundaries are the first places to look — but that is my analytic read of the exhibit list, not a finding by anyone.

Recommended next steps

1. Verify the negative. Pull PTAB E2E / USPTO PatentCenter for U.S. Pat. No. 8,633,537 and confirm zero proceedings. ODP ingest can lag newly filed petitions; if a '537 petition was filed in, say, August–September 2026, it may not yet appear. Check the Sandisk/Longitude docket neighborhood again before you rely on "no activity."
2. Do not cite IPR2025-01281 or IPR2025-01283 as adjudications of the '537 patent. They are not. They concern U.S. Pat. Nos. 11,456,365 and 9,929,240 respectively, both terminated pre-institution on 2026-02-20 without any merits ruling. If opposing counsel tries to leverage them, the accurate response is: no institution decision, no FWD, no estoppel, no preclusive effect.
3. Obtain the confidential license agreement's scope. A "Confidential Patent License Agreement" was filed as an exhibit supporting the January 2026 termination. If you or an affiliate were within its scope (e.g., as a Sandisk/Western Digital customer or contract manufacturer), you may have a license defense to any '537 assertion. This is the single highest-value document to chase.
4. No trial-stage milestones to track — there is no active proceeding. Re-engage on scheduling only if a petition is filed.
5. If you are a defendant today: the practical IPR path is open. There is no § 315(e)(2) bar, no prior FWD, no live proceeding to join, and no PTAB-sanctioned validity finding to overcome. The risks to weigh are ordinary ones — a 2014-issued patent with a 2007 priority date, a real § 325(d)/§ 314(a) discretionary-denial risk if you are in concurrent litigation, and the fact that the family's prior challenger chose to settle rather than litigate to judgment, which may indicate the art Sandisk used was not viewed as institution-proof.
6. If you do file, note that a settlement-terminated family IPR leaves the PTAB with no prior reasoned institution decision on closely related claims — so you cannot borrow claim-construction or priority rulings from the siblings. You will be building from scratch.
7. Flag for the file: the '537 patent is not in any defensive aggregator's challenge portfolio, and it has never been tested. A patent that is being asserted in 2025 litigation yet has attracted zero IPRs is an unusual posture — treat "untested" as untested, not as either strong or weak.

Sources consulted: USPTO ODP structured "PTAB proceedings on file" block (canonical, showing zero proceedings); Google Patents record for US8633537 (family, assignment, litigation links); IP Verse case dockets for IPR2025-01281 (https://ipverse.greyb.com/ptab-web/cases/case-details/IPR2025-01281) and IPR2025-01283 (https://sandbox.docketalarm.com/cases/PTAB/IPR2025-01283/Sandisk_Technologies_Inc._v._Longitude_Flash_Memory_Solutions_Ltd/); Justia dockets for 5:25-cv-02389 (https://dockets.justia.com/docket/california/candce/5:2025cv02389/[446095](/patent/446095)) and 8:25-cv-00119 (https://dockets.justia.com/docket/california/cacdce/8:2025cv00119/[954920](/patent/954920)); RPX litigation news (https://litigation.rpxcorp.com/news/84773-ipvalue-sues-western-digital-over-former-cypress-semiconductor-patents). Judge names, full grounds, and the settlement terms were not available in these sources and I have not supplied them.

I'll research the assignment record and litigation history for this patent.

Good — substantial findings. Let me dig into the specific assignment records and litigation details.

Let me find the specific reel/frame records and check the anomalous "THUMB, INC." entry.

I was able to pull substantial primary and secondary evidence, but note an important limitation up front: I could not retrieve the reel/frame numbers or correspondent-of-record fields themselves. The USPTO Assignment Center's per-record detail fields were not reachable through the search tooling available in this session, so everything below is built from (a) the authoritative Google Patents legal-events feed embedded in the patent text you supplied, and (b) contemporaneous reporting (RPX, BusinessWire/press releases, court dockets). No reel/frame or correspondent is invented below — where I don't have it, I say so. Verify at https://assignmentcenter.uspto.gov/ (search 8633537) or https://assignment.uspto.gov/patent/index.html.

Inventors

Pattern notes:

• All three inventors assigned their rights to Cypress Semiconductor Corporation — this was an employee-invention capture, not an inventor-started company. That is the normal operating-company pattern and argues against the "inventors depart and fire-sale the shell" tell.
• The application (US 13/539,466, filed 2012-07-01) is a continuation-in-part of 13/288,919 (filed 2011-11-03), itself a divisional of 12/152,518 (filed 2008-05-13, now US 8,063,434), claiming priority to provisional 60/940,160 (filed 2007-05-25). So the effective priority date is 2007-05-25 even though the patent issued 2014-01-21.
• Unclear: I found no evidence of when any inventor left Cypress or whether any joined an NPE/asserter. Do not read a fire-sale tell into this file.

Original assignee

Cypress Semiconductor Corporation (Delaware; principal place of business 198 Champion Court, San Jose, CA per Cypress's own pleadings).

• Line of business: Fabless/fab-lite semiconductor manufacturer — NOR flash, SRAM, USB controllers, PSoC programmable systems, and embedded non-volatile memory. This patent (multi-layer charge-trapping ONNO stack + high-work-function polysilicon gate) is squarely in Cypress's SONOS embedded-flash / charge-trap memory line, which Cypress did commercialize in embedded NVM. Caution: I could not map the claims to a specific shipping part number in this session, so "shipped a product embodying the claims" is highly probable but not documented here.
• Current status: Acquired. Cypress was acquired by Infineon Technologies AG, closing April 2020 (widely reported; consistent with IPValue's own statements that "the patents originated from Cypress Semiconductor, which was acquired by Infineon Technologies in 2020"). Cypress was not in bankruptcy — this matters for the fire-sale signal below.
• Earlier in the chain, Cypress itself had absorbed Spansion LLC (2015 merger), which is why Spansion appears as co-assignor on the Morgan Stanley security-interest records.

Assignment timeline

Disclosure: Reel/Frame numbers and correspondent names were not retrievable in this session. The entries below are the Google Patents legal-events records (which are derived from USPTO assignment data) plus external corroboration. Date semantics (executed vs. recorded) are not disambiguated in the Google feed — treat each date as "as indexed," not as a verified execution date. The 2015 and 2020 Morgan Stanley entries are security interests, not ownership transfers, and the 2019-05-07 entry is a release, not an assignment.

• 2012-07-19 (indexed) — Reel/Frame: not captured

  • Conveyance: Assignment of assignor's interest
  • Assignor: Levy, Sagy; Polishchuk, Igor; Ramkumar, Krishnaswamy
  • Assignee: Cypress Semiconductor Corporation
  • Correspondent: not captured (this would be Cypress's IP counsel of record — worth pulling, since Andrew J. Bateman, Reg. No. 45,573, Director of Intellectual Property, Cypress Semiconductor Corporation, appears as the 37 CFR 3.73(b) signatory on Cypress's related-file prosecution papers, suggesting Cypress typically recorded in-house)
  • Context: Standard employee-invention assignment to the operating company.

• 2012-08-01 (indexed) — Reel/Frame: not captured

  • Conveyance: Change of name
  • Assignor: OpinionAided, Inc.
  • Assignee: Thumb, Inc.
  • Correspondent: not captured
  • Context: Anomalous — flag for verification. This record is contaminated. OpinionAided, Inc. is not in this patent's chain of title, is not a predecessor of Cypress, and a "change of name" filed 13 days after the Cypress inventor assignment is chronologically impossible as a link in this title. Google's "Current Assignee" field nevertheless lists "THUMB Inc" alongside Longitude Flash Memory Solutions Ltd — almost certainly the same contamination. Do not treat Thumb, Inc. as an owner of this patent absent confirmation from the Assignment Center. If the Assignment Center shows no such record against 8633537, this is a Google indexing artifact.

• 2015-03-21 (indexed) — Reel/Frame: not captured

  • Conveyance: Security interest (security agreement)
  • Assignor: Cypress Semiconductor Corporation; Spansion LLC
  • Assignee: Morgan Stanley Senior Funding, Inc.
  • Correspondent: not captured
  • Context: Securitization / secured-lender lien on the Cypress–Spansion combined IP estate (merger financing). No ownership change.

• 2019-05-04 (indexed) — Reel/Frame: not captured — ⭐ the key event

  • Conveyance: Assignment of assignor's interest
  • Assignor: Cypress Semiconductor Corporation
  • Assignee: Longitude Flash Memory Solutions, Ltd. ("LFMS")
  • Correspondent: not captured (would be the recording attorney for the Cypress→IPValue/Longitude sale; this is the single most valuable field to pull, see Signal 3)
  • Context: Transfer to an asserter / monetization vehicle. LFMS is an affiliate of IPValue Management, Inc. and, since 2013, of Vector Capital (Vector acquired IPValue in 2014 and Longitude Licensing in 2013/2015). LFMS is a licensing-only entity — it holds ~500+ patents worldwide "originated from Cypress" and its only documented activity is granting licenses (Samsung, Micron, SK hynix via affiliate Longitude Licensing, and Sandisk) and suing (Western Digital, 2025). This is the classic operating-company-to-licensing-LLC transfer.

• 2019-05-07 (indexed) — Reel/Frame: not captured

  • Conveyance: Release of security interest
  • Assignor: Morgan Stanley Senior Funding, Inc.
  • Assignee: Cypress Semiconductor Corporation; Spansion LLC
  • Correspondent: not captured
  • Context: Lien release tied to the IP sale — Morgan Stanley released its security interest three days after the LFMS transfer so the portfolio could be conveyed clean. No ownership change.

• 2020-11-03 (indexed) — Reel/Frame: not captured

  • Conveyance: Corrective assignment (identified in the Google feed as a correction relating to "the 8647899 previously recorded on reel 035240 frame 0429" — note the reel 035240 / frame 0429 reference relates to a different patent, not to 8633537's own record; I could not confirm any reel/frame specific to 8633537 from this entry)
  • Assignor: Cypress Semiconductor Corporation; Spansion LLC
  • Assignee: Morgan Stanley Senior Funding, Inc.
  • Correspondent: not captured
  • Context: Corrective security-interest recordkeeping (fixing a mis-described collateral list). No ownership change. Cypress was acquired by Infineon around this same period.

• No further ownership assignment to 8633537 is indexed after 2019-05-04. LFMS remains the owner-of-record; IPValue holds enforcement rights by agreement (not by recorded assignment), per the RPX reporting on the 2025 complaints.

Litigation overlay (not assignments, but they date the enforcement campaign):

• 2025-01-22 — IPValue Management, Inc. & Longitude Flash Memory Solutions Ltd. v. Western Digital Corporation, C.D. Cal. 8:25-cv-00119 — five patents "apparently received from Cypress Semiconductor"; complaint states LFMS is the owner and IPValue "possesses substantial rights including the right to enforce." First amended complaint adds Sandisk Corporation. (https://litigation.rpxcorp.com/news/84773-ipvalue-sues-western-digital-over-former-cypress-semiconductor-patents)
• 2025-03-07 — Sandisk Corporation v. IPValue Management, Inc. et al., N.D. Cal. 5:25-cv-02389 — declaratory judgment of non-infringement filed by Sandisk against IPValue and LFMS; LFMS/IPValue filed a cross-complaint. (https://dockets.justia.com/docket/california/candce/5:2025cv02389/[446095](/patent/446095))
• 2026-01-19/21 — IPValue announces a worldwide non-exclusive license to Sandisk covering the LFMS portfolio, and states the agreements "resolved all outstanding patent disputes between the parties." (https://www.businesswire.com/news/home/20260119575213/en/)
• Unconfirmed: the five asserted patent numbers in 8:25-cv-00119 were not enumerated in the sources I reached. Google Patents' "Family has litigation" flag links this patent to the C.D. Cal. and N.D. Cal. cases, but I could not verify that US 8,633,537 specifically is one of the five asserted claims. Treat that as probable, not established.

Timeline diagram

timeline
    title Ownership of US 8633537
    2007 : Priority provisional filed
    2008 : Parent application filed
    2012 : CIP application filed
         : Inventors assign rights to Cypress
    2014 : Patent issues to Cypress
    2015 : Morgan Stanley records security interest
    2019 : Cypress assigns patent to LFMS
         : Longitude Flash Memory Solutions Ltd
    2020 : Morgan Stanley corrective filing
         : Cypress acquired by Infineon
    2025 : IPValue and LFMS sue Western Digital
         : Sandisk files declaratory judgment
    2026 : Sandisk takes worldwide license

NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT (strong). The 2019-05-04 assignment moved the patent from Cypress Semiconductor Corporation (operating merchant silicon manufacturer) to Longitude Flash Memory Solutions, Ltd., a name carrying the "Solutions"/licensing-vehicle construction with no products in commerce. LFMS's own public description — "intellectual property and technology licensing company," owner of "500+ patents worldwide" originating from Cypress — is a licensing-only profile. Corroborated by IPValue's licensing (Samsung, Micron, SK hynix, Sandisk) and suit (Western Digital) activity. I could not capture LFMS's registered address from the assignment record in this session (Verification gap: pull the LFMS address from the reel/frame to confirm a registered-agent service address).

2. Known asserter in the chain — PRESENT (strong). IPValue Management, Inc. is a long-established patent monetization firm (founded 2001; CEO John Lindgren; acquired by Vector Capital in 2014) that "owns and manages the commercialization of over 12,000 patents" and that sued a competitor in 2025 over this portfolio. IPValue/LFMS are documented NPE plaintiffs via RPX Empower (https://litigation.rpxcorp.com/news/84773-ipvalue-sues-western-digital-over-former-cypress-semiconductor-patents). Note precisely: IPValue does not appear on the canonical list in the prompt (Acacia, Marathon, IV, IPNav, Wi-LAN, Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation, Spangenberg), but it is a high-frequency licensing/assertion entity surfaced by RPX, which satisfies the "any entity surfaced by Unified Patents or RPX" clause.

3. Repeat correspondent across the chain — UNCLEAR / not assessable. This is the signal I most wanted and could not get: the correspondent-of-record fields were not retrievable in this session. There is a plausible hypothesis worth testing (the same recording firm/attorney likely handled the 2015 security interest, the 2019-05-07 release, the 2020-11-03 correction, and possibly the 2019-05-04 sale, given they are all the same collateral/lender matter), but that is a hypothesis, not a finding, and I will not assert it. Action item: pull correspondents for the four records dated 2015-03-21, 2019-05-04, 2019-05-07, and 2020-11-03. Recurrence across those four is the test. Separately note that Andrew J. Bateman (Reg. No. 45,573), Director of IP, Cypress Semiconductor, signs Cypress's 37 CFR 3.73(b) statements on sibling files — he is an in-house correspondent candidate, not an NPE-side attorney.

4. Cascading transfers — NOT PRESENT. Exactly one ownership transfer in the chain (Cypress → LFMS, 2019-05-04). No chained LLC hops. The other records are a lien, a lien release, and a corrective lien filing — securitization paperwork, not ownership cascades. The <24-month chained-LLC pattern does not exist here.

5. Pre-litigation transfer — NOT PRESENT. The controlling assignment is dated 2019-05-04; the first suits naming the LFMS portfolio were filed 2025-01-22 and 2025-03-07 — roughly 5.7 years later. That is a long-run portfolio acquisition-and-licensing campaign (2022 Samsung/Micron/SK hynix licenses preceded the litigation), not a transfer staged within six months of filing to cure standing or set venue.

6. Bankruptcy fire-sale — NOT PRESENT. Cypress was acquired by Infineon (closing April 2020) as a going concern; there is no Chapter 7/11 Cypress estate and no court-supervised patent sale here. (Contrast: Longitude Licensing itself was built in 2013 on the Elpida DRAM estate post-Elpida bankruptcy — but that is a different portfolio from the LFMS/Cypress one at issue, and it is Longitude's corporate history, not a link in this patent's title.)

7. Privateering — UNCLEAR. The economic shape is suggestive (operating company divests a patent estate to a monetization affiliate that then licenses and sues the former operating company's competitors), but true privateering requires evidence that Cypress/Infineon directs or shares in the assertion campaign. The 2022 SK hynix release attributes the portfolio to "Cypress Semiconductor, which was acquired by Infineon Technologies in 2020" but describes the licensing purely as IPValue/LFMS activity. I found no Cypress or Infineon 10-K/8-K disclosure, and no reporting, establishing retained enforcement control or a revenue share back to Infineon. Mark unclear rather than assert it.

8. Defensive aggregator (anti-NPE) — NOT PRESENT. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. It terminates at an asserting licensing vehicle. The 2026 Sandisk outcome is a commercial license that moots litigation, which is the opposite of a defensive-aggregation neutralization.

Verdict

NPE — high confidence.

Two independent strong signals are documented: (i) the shell-entity/licensing-vehicle transfer recorded 2019-05-04, moving the patent from operating manufacturer Cypress Semiconductor Corporation to Longitude Flash Memory Solutions, Ltd., a licensing-only affiliate of IPValue Management, Inc. (Vector Capital portfolio), and (ii) a known asserter in the chain, with IPValue and LFMS appearing as co-plaintiffs in C.D. Cal. 8:25-cv-00119 (filed 2025-01-22) against Western Digital and as defendants/counterclaimants in N.D. Cal. 5:25-cv-02389 (filed 2025-03-07) against Sandisk. Notably, the chain is clean and simple — one ownership transfer, no cascading LLC hops, no bankruptcy, no pre-suit tactical transfer — so the case rests on the two strong signals rather than on accumulation of weak ones. The remaining gaps (correspondent recurrence, LFMS's recorded address, and confirmation that US 8,633,537 is among the patents actually asserted) should be closed by pulling the individual reel/frame records at https://assignmentcenter.uspto.gov/ before this analysis is used in any filing.

Verification links

• Assignment Center: https://assignmentcenter.uspto.gov/ (search patent 8633537)
• Legacy assignment search: https://assignment.uspto.gov/patent/index.html
• Google Patents legal events: https://patents.google.com/patent/US8633537/en
• RPX on the 2025 assertion: https://litigation.rpxcorp.com/news/84773-ipvalue-sues-western-digital-over-former-cypress-semiconductor-patents
• C.D. Cal. docket: https://dockets.justia.com/docket/california/cacdce/8:2025cv00119/[954920](/patent/954920)
• N.D. Cal. docket: https://dockets.justia.com/docket/california/candce/5:2025cv02389/446095

Caveats on this analysis: reel/frame numbers and correspondent-of-record names were not verified in this session and no such values have been fabricated; the "OpinionAided, Inc. → Thumb, Inc." change-of-name record indexed against this patent is inconsistent with the title chain and is flagged as probable data contamination; and the specific patent numbers asserted in the 2025 complaints were not enumerated in the sources reached.

I'll search for the specific cited references on the USPTO record for US 8,633,537.

Let me target the front-page citation list more directly.

Good — I'm getting the cited-reference list. Let me pull the remainder and the Justia/Google Patents citation tables.

Prior-Art Analysis — US 8,633,537 B2

Method note and limitations (read first)

I ran the searches against the public record for US 8,633,537 B2 specifically (Google Patents, FreePatentsOnline, Justia). Two honest caveats before the substance:

1. The USPTO's own full-text citation table could not be pulled directly in this session. The patent's front page ("(56) References Cited") is reproduced by FreePatentsOnline, and I recovered it only in part — the US-patent citation list I retrieved is truncated partway through (it cuts off at US 7,312,496). The lists below are therefore incomplete, and the missing tail (plus the complete Foreign Patent Documents and "Other References" sections) should be confirmed against USPTO Patent Public Search / Patent Center or the granted front page at https://www.freepatentsonline.com/[8633537](/patent/8633537).html and https://patents.justia.com/patent/8633537.
2. I cannot state definitively which reference the examiner used as a §102 ground versus a §103 combination. The front-page listing does not, by itself, show the rejection rationale; that is in the file wrapper (Image File Wrapper / Patent Center). Accordingly, the "potential §102" tags below are my reasoned assessments, plainly marked as such.

One nuance that governs the whole analysis: the '537 is a continuation-in-part (CIP) filed 2012-07-01 with earliest priority 2007-05-25. Under §120, only subject matter present in the parent (12/152,518 → '919) gets the 2007/2008 date. Subject matter new to the CIP — the high work function gate electrode, the ONNO / anti-tunneling oxide layer, nanowire/vertical channel, and recrystallized polysilicon — carries an effective date of 2012-07-01. That matters because several cited references issue 2008–2012, i.e. they can be §102(a)/(b)/(e) art against the new-matter claims even though they post-date the 2007 provisional.

Part 1 — US patent documents cited on the face of US 8,633,537 (partial list as retrieved)

⚠️ This list is incomplete. The retrieved FPO text ends mid-entry at US 7,312,496; additional US patent citations, the entire Foreign Patent Documents column, and the Other References / NPL column were not fully retrieved. Given that the '537 issued in 2014 from a 2012 filing, one should expect roughly 30–60 cited references in total; the 23 above are a substantial but not complete subset.

Part 2 — Non-patent literature cited (partial, from the Justia record)

These were visible in the Justia citation list and are technically significant because they describe bandgap-engineered SONOS with a split (multi-layer) nitride trapping layer — the core of the '537's multi-layer charge-trapping region:

• Chen et al., "Performance Improvement of SONOS Memory by Bandgap Engineering of Charge-Trapping Layer," IEEE Electron Device Letters, Apr. 2004, vol. 25, No. 4, pp. 205–207. → Potential §102/§103 art against the oxygen-rich/oxygen-lean nitride split; a leading candidate for the examiner's rejection of multi-layer-storage claims.
• Lue et al., "BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability," IEEE, 2005. → Same; the archetypal BE-SONOS disclosure.
• Lue, Hang-Ting et al., "Reliability Model of Bandgap Engineered SONOS (bE-SONOS)," IEEE, 2006, 4 pgs. → Retention/reliability art.
• U.S. Appl. No. 61/007,566 — Polishchuk et al., "Nonvolatile Charge Trap Memory Device Having a High Dielectric Constant Blocking Region," filed Dec. 12, 2007 → provisional priority document; relevant to high-K blocking-region claims.
• U.S. Appl. No. 61/599,258 — Ramkumar et al., "New Integration of SONOS Stack," filed Feb. 15, 2012 → applicant's own; relevant to ONO-stack integration.
• International Search Reports: PCT/US07/20966 (mailed 2008-04-21), PCT/US07/20988 (mailed 2008-03-14), PCT/US12/021583 (mailed 2012-07-19). → Search documents, not themselves prior art.

⚠️ Also incomplete — the Justia NPL list ran to dozens of entries (chiefly USPTO office actions and ISRs in the same family); only the technologically meaningful ones are reproduced.

Part 3 — Assessment: which reference could anticipate which claim

Because the granted claim set was not retrieved verbatim in the earlier section (I flagged there that the granted claims were renumbered relative to publication 2013/0307053), I map the analysis to the claim subject matter disclosed in the patent, using the independent-claim structure set out earlier: claim 1 (device: memory transistor + co-integrated MOS logic transistor), the ONONO variant, the vertical-channel variant, and the dependent themes.

A. Independent claim 1 (ONNO stack + multi-layer trapping region + high-work-function gate + MOS logic transistor on the same substrate).
This is a combination limitation set. No single retrieved reference appears to disclose all of: (i) the split oxygen-rich/oxygen-lean nitride trapping region, (ii) a high work function gate electrode (spec-defined as 4.8–5.3 eV), and (iii) a MOS logic transistor with its own high-work-function gate on the same substrate. The closest single references are US 2009/0179253 (Levy) and US 8,222,688 (Jenne) for element (i), and US 7,312,496 for element (iii). My assessment: claim 1 is more likely to have been rejected under §103 as a combination, not §102. I cannot confirm a §102 ground from the retrieved data — this should be verified in the file wrapper.

B. Multi-layer charge-trapping region claims (the oxygen-rich first nitride / oxygen-lean second nitride limitation).

• US 2009/0179253 A1 (Levy, 2009-07-16) and US 8,222,688 B2 (Jenne, 2012-07-17) are the strongest §102 candidates. Both address a split/multiple-nitride SONOS storage layer. Note both are Cypress/Spansion-origin and post-date the 2007 priority but pre-date the 2012 CIP filing — so they are §102(a)/(b)/(e) art against the new-matter aspects.
• US 2008/0135946 A1 (Yan) and US 2010/0041222 A1 (Puchner) are secondary.
• The Chen 2004 and Lue BE-SONOS 2005 NPL are strong §102/§103 art for this limitation.

C. ONONO / anti-tunneling oxide layer (oxide separating the two nitride layers).

• US 7,737,488 (Lai) and the BE-SONOS NPL are the most pertinent; a mid-oxide between a trap-rich and trap-poor nitride is the essence of BE-SONOS. Potential §102 against the anti-tunneling-layer limitation.

D. High work function gate electrode (4.8–5.3 eV; boron/BF₂ implant or in-situ doping).

• No retrieved citation is specifically directed to a high-work-function polysilicon gate in a charge-trap memory. US 7,312,496 (composite vs single gate structures) is the nearest for gate-electrode architecture. Likely a §103 combination with the trapping-layer art.

E. Nanowire / vertical-channel claims.

• US 2010/0117138 A1 (Huerta, 2010-05-13) is the strongest §102 candidate for the nanowire channel dependent claim and for the vertical-channel independent claim (PCT claim 18). US 2008/0029399 (Tomita) is secondary.

F. High-K blocking dielectric claims.

• US 2009/0152621 A1 (Polishchuk, 2009-06-18), US 7,365,389 (Jeon), and the '007,566 provisional are §102 candidates.

G. Fabrication-method claims.

• US 8,318,608, US 8,283,261, US 7,670,963 (all Ramkumar/Cypress) are §102(e) process candidates.

Part 4 — What I could not verify (stated explicitly rather than guessed)

1. The complete "References Cited" list. The retrieved copy is truncated at US 7,312,496; the Foreign Patent Documents column and the tail of the US list are missing.
2. The examiner's actual §102 vs §103 designations and the specific claims rejected. These live in the Image File Wrapper / Patent Center for application 13/539,466 (which also would resolve the "13/593,466" vs "13/539,466" discrepancy flagged in the earlier section).
3. Whether any of these references was applied against the granted claims as opposed to the pre-grant claims — the claims were renumbered during prosecution (recall the "recrystallized polysilicon" limitation moved from published claim 3 to granted claim 6).
4. The full NPL list, which includes many office actions/ISRs not reproduced here.

Recommended next step for certainty: pull the full front page and the file wrapper for application 13/539,466 from USPTO Patent Center / Patent Public Search, which will give the complete (56) citation table and the examiner's rejection grounds — the only authoritative source for a true §102 anticipation determination.

Primary sources used: https://www.freepatentsonline.com/8633537.html (US Patent References), https://patents.justia.com/patent/8633537 (NPL citations), https://patents.google.com/patent/[US8633537B2](/patent/US8633537B2)/en (bibliographic/family).

Obviousness Analysis — US 8,633,537 B2 under 35 U.S.C. § 103

Task date note (flagged, not corrected): the instructions for this task state "Current Date: April 26, 2026," while the session header on this page states 2026-09-27. I proceed on the assumption that no intervening events have altered the record; both dates are after every litigation/PTAB event discussed in the earlier sections. I do not auto-reconcile the discrepancy.

Method note. Per the instruction, I build exclusively on the reference set developed in the Prior Art section of this page (the references appearing on the face of US 8,633,537 and the NPL list), and on the claim/priority framework already established in the Patent summary section. I do not introduce new prior-art references. Where the retrieved reference list is truncated (it cuts off at US 7,312,496, and the Foreign Patent Documents and much of the NPL column were not retrieved), I say so and treat the analysis as provisional on that list. Patent numbers, application numbers, and titles are reproduced literally as they appear in the source material.

1. Governing framework and why the priority/CIP question is the hinge

The '537 application (13/539,466) was filed 2012-07-01, before the AIA first-inventor-to-file effective date of 2013-03-16. The pre-AIA §§ 102/103 framework therefore governs, including pre-AIA § 103(c)(1) (commonly-owned § 102(e)/(f)/(g) art is disqualified as prior art for obviousness). That single statutory provision is the most important variable in this whole analysis, because a large fraction of the front-page art is Cypress's own — Levy, Polishchuk, Jenne, Ramkumar, Puchner.

The '537 is a continuation-in-part. Under § 120, only limitations carried over from the 2008 parent chain (12/152,518 → 13/288,919 → 60/940,160 provisional, priority 2007-05-25) get the early date. The limitations that appear to be new matter — the high work function gate electrode, the ONNO / anti-tunneling oxide layer, the nanowire and vertical channel embodiments, and recrystallized polysilicon — are entitled only to 2012-07-01.

That produces this pivot table:

Practical upshot: the patentee's best non-obviousness shield — common ownership — works best against the early claims and worst against the new-matter claims that carry the commercial weight (high work function gate + ONNO). A challenger who pleads the priority question correctly flips the § 103(c) defense off for the ONNO/high-work-function claims. (Verify each reference's filing date and the actual § 102(b) critical date for each claim; my "likely" column is an inference from the family structure, not a holding.)

2. What the obviousness case has to bridge — and where the art is strong vs. weak

Mapping the four limitations of independent claim 1 (as described in the Patent summary section; recall the granted claims were renumbered relative to publication 2013/0307053, so this is subject-matter-based, not claim-numbered) against the retrieved art:

Conclusion at the threshold: No retrieved reference anticipates claim 1 under § 102. The case is a § 103 combination case, and its strength is concentrated in limitations (a) and (b) and its weakness in (c).

3. Primary combination for claim 1

Combination A: Levy '253 (or Jenne '688) + US 7,312,496 + the high-work-function gate electrode teaching

3.1 The combination

1. Levy US 2009/0179253 A1 supplies the ONO stack with multiple oxynitride layers — i.e., the split oxygen-rich / oxygen-lean nitride charge-trapping region, and the underlying rationale (trap-rich layer for window, trap-poor layer for retention).
2. US 7,312,496 B2 supplies the co-integration of a composite-gate transistor with a single-gate transistor on one device — the embedded-memory/SOC architecture in which a memory gate stack and a logic gate stack are formed together.
3. The high work function gate electrode is supplied as a known design technique in gate-electrode engineering: selecting the gate dopant/polarity so the work function is raised into the ~4.8–5.3 eV range (in the '537's own terminology: boron or BF₂ implant), which the '537's specification itself treats as a straightforward process choice, not a discovery.

3.2 Motivation to combine (KSR factors)

• The problem was already identified in the art and admitted on the face of the '537. The '537's Background section states the exact tradeoff the combination addresses: a Si-rich trapping layer gives a large initial program/erase window but the window "collapse[s] very rapidly in retention mode," whereas a low-Si (stoichiometric) nitride reduces the collapse rate but shrinks the window (FIGS. 1A/1B). Chen 2004 and Lue BE-SONOS 2005 addressed that same tradeoff by bandgap engineering of the charge-trapping layer. Combining a bandgap-engineered split trapping layer with a work-function-engineered gate is a combination of two known solutions to the same known problem (retention vs. window), i.e., a "predictable variation" under KSR.
• The '537 also admits the second problem expressly: "Many of the current processes for forming performance of memory transistors are incompatible with those used for fabricating logic transistors," and SOC/embedded memory requires co-fabrication. US 7,312,496 is directed to exactly that — transistors of differing gate structures on one device. KSR step three: "a known technique [dual-gate-structure integration] to improve similar devices in the same way."
• Finite number of predictable solutions. For the charge-storage element, the art had converged on a small set of options (single nitride; split/bandgap-engineered nitride; nanocrystal). For the gate electrode, work-function selection by doping polarity is one of a handful of standard knobs. Where "a finite number of identified, predictable solutions" exists, KSR makes the chosen combination obvious.
• Design incentive / market pressure. Embedded NVM and SOC integration were strong, well-documented industry drivers, and Cypress's own Ramkumar process patents in the same family show the integration was being pursued contemporaneously.
• Predictable result. Raising the gate work function raises the barrier against carrier injection from the gate, which reduces gate-side leakage and mitigates erase saturation; combining that with a split trapping layer that independently reduces vertical charge loss yields an additive, expected improvement in retention. Nothing in the retrieved art teaches away.

3.3 Honest statement of the weakness

The retrieved front-page art contains no reference specifically directed to a high-work-function polysilicon gate in a charge-trap memory transistor. That is a real gap, and it is the pivot on which the patentee's non-obviousness argument will turn. Practically, the "high work function gate" element must be supported either by (i) additional art not retrieved (see the truncation caveat — the Foreign Patent Documents column and the tail of the US list are missing), or (ii) a § 103 "known technique" argument rooted in gate-work-function engineering generally plus the erase-saturation motivation above. I cannot, on this record, assert that (ii) alone is institution-proof. This is the single area where the challenger should commission a fresh prior-art search rather than rely on the '537's own citation list.

4. Alternative / secondary combinations by claim group

4.1 Claims to the ONONO variant (PCT claim 11 / "anti-tunneling layer" dependent claims)

Combination B: Lai US 7,737,488 B2 + Lue BE-SONOS 2005 (NPL) + Levy US 2009/0179253 A1.

The essence of BE-SONOS is a trap-rich nitride over a trap-poor nitride separated by a thin oxide — precisely the "oxide anti-tunneling layer separating the oxygen-lean second nitride layer from the oxygen-rich first nitride layer" recited in the '537's ONONO claims. Lai's title itself ("Blocking dielectric engineered charge trapping memory cell with high speed erase") is directed to engineering the dielectric interfaces of a charge-trap cell. A POSITA seeking to reduce back-tunneling of charge from the trap-rich layer into the lower nitride would be motivated to interpose an oxide barrier — the '537's own specification describes the function in those exact mechanical terms ("substantially reduces the probability of electron charge that accumulates at the boundaries of the oxygen-lean second nitride layer ... from tunneling into the first nitride layer"). This is a strong § 103 combination; it is close to a § 102 case for the ONONO structure standing alone.

4.2 Claims to a nanowire channel

Combination C: Huerta US 2010/0117138 A1 + any of Levy '253 / Jenne '688 / Lai '488.

Huerta supplies a non-volatile memory cell comprising a nanowire. Substituting a nanowire channel for a planar channel, and forming the same charge-trap stack around it, was a conventional application of a known structure for known benefits (better electrostatic gate control, scalability). Tomita US 2008/0029399 is a secondary reference on nanostructure fabrication. Moderate–strong.

4.3 Claims to a vertical channel / gate-first or gate-last fabrication (PCT claim 18)

Combination D: Huerta '0117138 + vertical/3D stacked-cell architecture + US 7,312,496-style integration.

Vertical-channel, gate-all-around charge-trap cells (BiCS-type) were known and are documented elsewhere on this family's record — note that the Tanaka (BiCS) reference appears in the IPR2025-01281 exhibit list (discussed in the PTAB section), though it is not front-page art on the '537. I flag it as a lead to verify, not as a sanctioned citation for a § 103 ground here. The '537 itself characterizes "gate first scheme" and "gate last scheme" as generic process architectures, which is an admission that these are conventional. Moderate.

4.4 Claims to a high-K blocking dielectric

Combination E: Polishchuk US 2009/0152621 A1 + Jeon US 7,365,389 B2 (both retrieved from the front page), plus the '007,566 provisional's subject matter. Two independent references teaching a high-K blocking region in a charge-trap cell make this limitation plainly obvious. Strong — but note the § 103(c) common-ownership caveat for the Cypress-origin Polishchuk reference.

4.5 Method/fabrication claims

Combination F: Ramkumar US 8,318,608 + US 8,283,261 + US 7,670,963 (all Cypress process patents on the front page) combined with routine CVD/HTO and ion-implantation practice recited in the '537's own specification (BTBAS/ammonia CVD for the trap-rich layer; DCS/NH₃/N₂O for the trap-poor layer; HTO for the blocking oxide; B⁺/BF₂ implant for the gate). Methods claims are the most vulnerable group, because the specification recites its process parameters as ordinary process windows without comparative data.

5. KSR motivation synthesis (why the combination as a whole is defensible)

Potential teaching-away to test (patentee's best argument): the patentee may argue the art taught that a high-work-function (P⁺-doped) gate on an NMOS charge-trap transistor would raise the transistor's threshold voltage and compress the erase window — i.e., that the art pointed away from the claimed polarity combinations (P⁺ gate → NMOS memory + PMOS logic; N⁺ gate → PMOS memory + NMOS logic). This is the argument I would expect to see and it is not rebutted by anything in the retrieved record. It requires a factual showing from the art, and the challenger should search specifically for it.

6. What the patentee will say, and the counters

1. "No reference discloses a high-work-function gate in a charge-trap memory." Possibly true on this record. Counter: (i) the retrieved list is incomplete; (ii) KSR permits the "known technique" route; (iii) the '537 does not claim the recognition of any problem with the experimental support that would make the selection non-obvious.
2. § 103(c)(1) common ownership. Real and serious for the Cypress-origin art (Levy, Polishchuk, Jenne, Ramkumar, Puchner). Counter: § 103(c) reaches only art qualifying under § 102(e)/(f)/(g). For the new-matter claims (high work function gate, ONNO, nanowire) with a 2012 effective date, publications such as US 2009/0179253 (2009-07-16) and US 2010/0117138 (2010-05-13) predate the § 102(b) critical date and are therefore § 102(b) art — outside § 103(c)'s reach. Confirm the "by another" requirement is satisfied (the inventive entities differ).
3. Unexpected results / secondary considerations. The '537's specification shows only qualitative retention schematics (FIGS. 1A/1B); the earlier sections found no comparative data isolating the high-work-function gate contribution, and no objective indicia (no license-nexus finding, no industry praise) documented in the record. The 2026 SanDisk worldwide license is commercially significant but its nexus to this patent's claims is unestablished — and per the PTAB section, the family's IPRs were settled pre-institution, so there is no § 103 holding in either direction.
4. Priority/CIP boundaries. The patentee may try to push more subject matter into the 2007/2008 parent to widen the § 103(c) shield. That is a written-description/enablement question for the parent's disclosure (12/152,518 → 13/288,919) and should be tested directly against the parent's specification.

7. Residual attack angle worth flagging

The earlier Patent summary section flagged an identifier discrepancy: the specification of related US 9,502,543 recites its parent as "application No. 13/593,466, filed on Jul. 1, 2012, now Pat. No. 8,633,537," while the '537's own record, its publication (2013/0307053), and Google Patents give 13/539,466. Per the operating rules I do not correct either number. Two consequences for a validity challenge:

• If the error is in the child's ('543) recitation only, the '537's own § 120 chain is unaffected and this is a priority-record curiosity, not a § 103 lever.
• If any application in the benefit chain misidentifies its parent, § 120 benefit for the affected claims can be challenged (failure to comply with the specific-reference requirement), which would move the effective date later and expand the available art — again flipping § 103(c) off. This is a low-cost, high-leverage item to verify in the file wrappers before committing to a § 103 theory.

8. Bottom line — ranked obviousness exposure

Blunt assessment: the '537's broad structural claims are not strongly patentable over the retrieved art on the charge-storage side — the split-nitride and mid-oxide architecture was squarely in the art (Cypress's own Levy/Jenne filings, and the third-party Chen/Lue BE-SONOS literature). The patent's genuine defensive moat is the combination of that architecture with a work-function-engineered gate in a co-integrated memory/logic flow, and that moat is only as deep as the challenger's ability to find art on the high-work-function-gate element. Because the family's IPRs were terminated pre-institution on settlement (per the PTAB section), there is no institution decision, no FWD, and no estoppel — a challenger is free to run this combination from scratch, and equally has no favorable precedent to borrow.

Items to verify before filing (in priority order):

1. Complete front-page citation table (US tail, Foreign Patent Documents, full NPL) — Patent Center for application 13/539,466.
2. File wrapper: examiner's actual § 102/§ 103 grounds and the claim renumbering.
3. Each reference's filing date + the correct § 102(b) critical date per claim group (drives the § 103(c) analysis).
4. Common-ownership status at the time of invention for every Cypress-origin reference.
5. Whether the benefit chain contains any misidentified parent application (the 13/539,466 vs. 13/593,466 discrepancy).
6. New art search specifically for work-function/polarity selection of polysilicon gate electrodes in charge-trap memory (erase-saturation and gate-injection literature) — this is the gap the retrieved list does not close.

Sources used (per instruction, the reference set from the Prior Art section): US 8,283,261; US 8,318,608; US 7,670,963; US 7,731,242(7,323,742); US 7,365,389; US 7,312,496; US 7,463,530; US 7,576,386; US 7,737,488; US 7,790,516; US 8,222,688; US 2008/0009115; US 2008/0029399; US 2008/0135946; US 2008/0150003; US 2008/0237694; US 2008/0272424; US 2008/0290399; US 2009/0152621; US 2009/0179253; US 2010/0041222; US 2010/0117138; US 2010/0295118; Chen et al., IEEE EDL Apr. 2004; Lue et al., BE-SONOS, IEEE 2005; Lue et al., Reliability Model, IEEE 2006; provisional 61/007,566; provisional 61/599,258 — all as catalogued at https://www.freepatentsonline.com/8633537.html and https://patents.justia.com/patent/8633537. Reference numbers are quoted literally as retrieved; the citation list is known to be incomplete and no finding above should be relied on without the full front page and file wrapper.