US 8516185

Summary — U.S. Patent 8,516,185 B2 ("8516185")

Search scope note: I searched for patent number 8516185 only (not similar numbers). The USPTO/Google Patents record and litigation databases were consulted. No CAFC 2026 docket specifically naming 8516185 surfaced; the February 20, 2026 Federal Circuit opinion in Micron Technology, Inc. v. Netlist, Inc. (Nos. 24-1312, 24-1313) concerns Netlist's later descendant patent 10,489,314, not 8516185 itself — I flag this to avoid conflating the two.

Bibliographic data

• Title: System and method utilizing distributed byte-wise buffers on a memory module
• Patent No.: US 8,516,185 B2
• Application No.: 12/761,179 — filed April 15, 2010 (continuation-in-part of U.S. Application 12/504,131, filed July 16, 2009, which issued as U.S. Patent 8,417,870)
• Priority date: July 16, 2009 (per family records)
• Issue (grant) date: August 20, 2013
• Inventors: Hyun Lee (Ladera Ranch, CA); Jayesh R. Bhakta (Cerritos, CA)
• Assignee: Netlist, Inc. (Irvine, CA)
• Legal status: Expired – Fee Related (Google Patents status; adjusted expiration listed as January 13, 2030)
• Classifications (CPC): G11C 5/025, G11C 5/04, G11C 5/066, G11C 8/12, G06F 12/00

Abstract (verbatim)

A memory system and method utilizing one or more memory modules is provided. The memory module includes a plurality of memory devices and a controller configured to receive control information from a system memory controller and to produce module control signals. The memory module further includes a plurality of circuits, for example byte-wise buffers, which are configured to selectively isolate the plurality of memory devices from the system memory controller. The circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller. The circuits are distributed at corresponding positions separate from one another.

Plain-language overview of the independent claims

The specification's Summary section tracks three independent claim groups. Based on the granted text and the family record, 8516185 contains three independent claims (apparatus claims 1 and the second apparatus claim, plus one method claim). I did not retrieve a machine-verified claim-numbering breakout, so treat specific claim numerals below with mild uncertainty:

1. Memory module with a control circuit plus distributed data-transmission circuits (claim 1 style). A memory module has a PCB, multiple memory devices, and a control circuit that receives control signals from a system memory controller and issues module control signals. It also has multiple data-transmission circuits distributed at separate locations on the PCB, each coupled to the memory controller and to at least two memory devices (e.g., one or more devices per rank). Each data-transmission circuit responds to the module control signals by selectively allowing or inhibiting data transfer between the memory controller and a chosen memory device — i.e., it acts as a per-byte load-reducing switch/buffer so the controller sees one load instead of many device loads.

2. Memory module with isolating/merge circuits (broader functional form). A memory module has memory devices and a controller that converts memory-controller control information into module control signals. Multiple circuits (byte-wise buffers) selectively isolate the memory devices from the system memory controller, and in response to the module control signals they drive write data from the controller to the devices and merge read data from the devices back to the controller. The circuits are physically distributed at positions separate from one another rather than centralized in a single large buffer chip.

3. Method of operating a memory module with a byte-wise buffer. A data-transmission circuit (a byte-wise buffer) is placed on a data line between a computer system memory controller and the module's memory devices. During a write, the circuit is enabled to drive a data signal from the controller along one of several paths to the devices; during a read, the circuit merges data signals coming from the memory devices and drives the merged signal back to the memory controller.

Litigation / PTAB history relevant to 8516185 (from family records)

• IPR2017-00577 (hynix/SK hynix as petitioner): reached a Final Written Decision; the Google Patents record flags it as litigated.
• IPR2014-01029 and IPR2014-01369: filed but not instituted.
• District-court cases (N.D. Cal., C.D. Cal.) and ITC Investigation 337-TA-1023 involved the family; the CAFC appeal 18-1676 is listed on the family litigation record.
• The 2026 CAFC opinion (24-1312/24-1313) affirmed PTAB decisions on obviousness for the related '314 patent — informative for the Netlist patent family but not a direct ruling on 8516185.

Uncertainty

• Exact independent-claim numbers (1 vs. 13 vs. 25, etc.) and the dependent-claim count could not be confirmed from a single authoritative source in my searches; the full claims text was truncated in the source material provided. The substance of the three independent claim groups above is well supported by the specification/abstract.
• "Expired – Fee Related" is Google Patents' label; the underlying reason (e.g., nonpayment of maintenance fees at the end of term vs. earlier lapse) was not independently verified against USPTO PAIR.

I'll search for litigation specifically involving US Patent 8,516,185.

The Stanford NPE database and PTACTS confirm several cases. Let me get more detail on each case number, filing dates, and statuses.

I have several leads. Let me verify the specific cases — the Diablo/SMART declaratory-judgment actions, the transferred infringement case, the ITC investigation, and the SK hynix case — to pin down which of them actually assert '185 and their status.

Litigation involving U.S. Patent 8,516,185 ("the '185 patent")

Based on searches of the Stanford NPE Litigation Database, the USPTO PTACTS docket, the Federal Register / USITC EDIS, CourtListener, and Justia, I identified the following proceedings that specifically name the '185 patent. District-court/ITC matters first, then PTAB petitions (administrative, not Article III litigation, but included for completeness since they name the '185 patent directly).

1. Netlist, Inc. v. Diablo Technologies, Inc., et al. — No. 4:13-cv-05962-YGR (N.D. Cal.)

• Plaintiff: Netlist, Inc.
• Defendants: Diablo Technologies, Inc.; related/associated parties included SMART Modular Technologies, Inc. / SMART Storage Systems, Inc. / Smart Worldwide Holdings (per Stanford NPE party records, SanDisk ultimately became involved via its acquisition of SMART Storage).
• Jurisdiction: U.S. District Court, Northern District of California (Judge Yvonne Gonzalez Rogers).
• Filing date: December 26, 2013 (per Stanford NPE Litigation Database).
• Role of '185: The Stanford NPE database lists the '185 patent among the patents involved in this action. Related docket materials show Netlist served infringement contentions covering the '434, '501, '185, '187, and '833 patents in the related N.D. Cal. actions.
• Status/outcome: This was the flash-DIMM dispute tried to a jury in March 2015. Netlist's appeal to the Federal Circuit (Appeal No. 16-1011) was affirmed by a nonprecedential per curiam order entered July 11, 2016 (Judges Moore, Linn, O'Malley). Caution: that Federal Circuit disposition concerned Netlist's breach-of-contract/trade-secret claims (the isolation-device Supply Agreement), so I cannot confirm from available sources the specific final disposition of the '185 infringement claims within this multi-claim case. Also related/consolidated for pretrial purposes with the cases below.

2. Diablo Technologies, Inc. v. Netlist, Inc. — No. 4:13-cv-03901-YGR (N.D. Cal.)

• Plaintiff: Diablo Technologies, Inc.
• Defendant: Netlist, Inc.
• Jurisdiction: N.D. Cal. (Judge Yvonne Gonzalez Rogers).
• Filing date: August 23, 2013 (declaratory-judgment action filed the same day as the Smart Modular DJ action; the Justia docket confirms the October 10, 2013 order denying Netlist's motion to dismiss/transfer the anticipatory DJ suit).
• Role of '185: Part of the coordinated "Five Netlist Patents" declaratory-judgment cluster (per the district court's order referencing "the actions on the Five Netlist Patents"); Google Patents' family record lists this case under the '185 family.
• Status/outcome: Scheduling order entered January 6, 2014, coordinating with 4:13-cv-03916 and the transferred infringement case; the '185 claims proceeded in the coordinated N.D. Cal. litigation. I could not confirm a separate final judgment in this specific DJ docket (as opposed to the coordinated merits case).

3. Smart Modular Technologies, Inc. v. Netlist, Inc. — No. 4:13-cv-03916-YGR (N.D. Cal.)

• Plaintiff: Smart Modular Technologies, Inc.
• Defendant: Netlist, Inc.
• Jurisdiction: N.D. Cal. (Judge Yvonne Gonzalez Rogers). (Stanford also lists a "3:13-cv-03916" variant; the Justia/Patexia record shows case 3:13-cv-03916 filed August 23, 2013.)
• Filing date: August 23, 2013 (declaratory judgment of non-infringement/invalidity, filed in response to Netlist's August 22, 2013 threat letter; per the IPR2014-01375 exhibit).
• Role of '185: Stanford NPE database lists the '185 patent in this case; Netlist's January 21, 2014 Patent L.R. 3-1 infringement contentions in this case included the '185 (claim charts filed publicly as Dkt. 193 in related Case 4:13-cv-05889).
• Status/outcome: Netlist and SMART Modular jointly stipulated to dismissal without prejudice of both this DJ case and Netlist's infringement case (4:13-cv-05889); the court entered dismissal orders on February 12, 2014.

4. Netlist, Inc. v. Smart Storage Systems, Inc. / Diablo Technologies, Inc. — No. 4:13-cv-05889-YGR (N.D. Cal.) (transferred from No. 8:13-cv-00996, C.D. Cal.)

• Plaintiff: Netlist, Inc.
• Defendants: Smart Storage Systems, Inc. (a SanDisk company) and Diablo Technologies, Inc.
• Jurisdiction: Originally filed C.D. Cal. (8:13-cv-00996, filed ~August 23, 2013); transferred to N.D. Cal. and assigned 4:13-cv-05889-YGR.
• Filing date: C.D. Cal. complaint ~August 23, 2013 (Netlist's first amended complaint accusing SMART Modular of infringing the '501 patent was filed August 23, 2013 in 8:13-cv-00996; the case later encompassed the '434, '501, '185, '187, and '833 patents).
• Role of '185: '185 infringement contentions served January 21, 2014 (filed publicly April 10, 2014, Dkt. 193); Diablo/Smart Storage invalidity contentions dated June 6, 2014 specifically addressed the '185 patent (per the '907/'9037809 family file histories).
• Status/outcome: Patent claims against SMART Modular were dismissed without prejudice on February 12, 2014 (per the IPR2014-01375 declaration). The action against Diablo proceeded in the coordinated N.D. Cal. litigation; the related Diablo matter was tried in 2015 and reached the Federal Circuit (see Case 1 above). I could not confirm a separate, final merits disposition on '185 in this specific docket from the sources retrieved.

5. Netlist, Inc. v. SK hynix Inc., et al. — No. 8:16-cv-01605 (C.D. Cal.)

• Plaintiff: Netlist, Inc.
• Defendants: SK hynix Inc., SK hynix America Inc., and SK hynix memory solutions Inc. (Stanford NPE database lists this case for the '185 patent).
• Jurisdiction: U.S. District Court, Central District of California.
• Filing date: 2016 (Stanford NPE lists the case; Google Patents family record lists 8:16-cv-01605).
• Status/outcome: Ran parallel to the ITC investigation below; I could not confirm the current status or final disposition of this district docket from the retrieved sources.

6. In the Matter of Certain Memory Modules and Components Thereof, and Products Containing Same — Inv. No. 337-TA-1023 (USITC)

• Complainant: Netlist, Inc.
• Respondents: SK hynix Inc., SK hynix America Inc., SK hynix memory solutions Inc.
• Jurisdiction: U.S. International Trade Commission (Chief ALJ Charles E. Bullock presiding; later assigned to ALJ Theodore R. Essex).
• Filing dates: Complaint filed September 1, 2016; supplements September 22–23, 2016; investigation instituted September 30, 2016 (81 FR 69853, October 7, 2016).
• Role of '185: Claims 1–3, 7, 8, and 10–12 of the '185 patent were expressly asserted in the Notice of Investigation.
• Status/outcome: Initial Determination on violation and recommended determination on remedy issued November 14, 2017 (ID section VIII addresses the '185 patent's infringement, validity, written-description/enablement, and domestic-industry issues). The family record also lists a Federal Circuit appeal, Appeal No. 18-1676, arising from this ITC matter. I could not confirm the ultimate Commission determination or the CAFC 18-1676 result from the sources retrieved — treat those specific outcomes as unverified.

PTAB inter partes review petitions naming the '185 patent (administrative, not court litigation)

• SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00577 — petitioned on the '185; instituted July 7, 2017 (Decision, Paper 8); oral hearing April 2018; a "Termination Decision Document" was filed July 7, 2018. The Google Patents family record characterizes this case as reaching a Final Written Decision. (Whether the FWD found the challenged claims unpatentable is not confirmed in my sources.)
• SanDisk Corp. v. Netlist, Inc., IPR2014-01029 — petition on the '185; institution denied December 16, 2014.
• Smart Modular Technologies, Inc. v. Netlist, Inc., IPR2014-01369 — petition on the '185; institution denied March 9, 2015.

Bottom line

There is known litigation involving the '185 patent. The core set is: (1) the coordinated 2013–2016 N.D. Cal. Netlist v. Diablo/SMART Modular litigation (Nos. 4:13-cv-05962, 4:13-cv-03901, 4:13-cv-03916, 4:13-cv-05889, and originating C.D. Cal. No. 8:13-cv-00996); (2) Netlist v. SK hynix, No. 8:16-cv-01605 (C.D. Cal.); and (3) ITC Inv. No. 337-TA-1023, with Federal Circuit appeal No. 18-1676, plus the PTAB IPRs noted above.

Confidence caveats: I could not verify from the retrieved sources (a) the precise final merits disposition of the '185 claims in the N.D. Cal. coordinated cases (as opposed to the contract claims affirmed in CAFC No. 16-1011), (b) the current status of the C.D. Cal. SK hynix case as of April 2026, or (c) the ultimate ITC Commission determination and CAFC No. 18-1676 outcome. If you need those specific dispositions, the authoritative next steps are PACER (for the district dockets), the USITC EDIS system (for 337-TA-1023), and the PTAB's PTACTS portal (for IPR2017-00577).

Important flag on the canonical proceeding list

The structured "PTAB proceedings on file" block states the USPTO Open Data Portal API returns no AIA trial proceedings for US 8,516,185 as of its most recent ingest. That is contradicted by the patent's own family/litigation record (Google Patents metadata on the '185 patent page) and by multiple independent PTAB document archives, which confirm three IPR proceedings against this patent. I am therefore reporting all three, and treating the ODP block as an indexing gap rather than as an accurate "no activity" signal.

Proceedings overview

Three inter partes review petitions have been filed against US 8,516,185: two were denied institution on the merits (IPR2014-01029, IPR2014-01369), and one was instituted and ended in a Final Written Decision holding every challenged claim unpatentable (IPR2017-00577, claims 1–3, 7, 8, and 10–12). Net result: the core asserted claims of the patent are dead — if your demand letter cites claims 1, 2, 3, 7, 8, 10, 11, or 12, Netlist has no viable infringement theory on those claims — while only the claims the 2017 petitioner did not challenge (e.g., 4–6, 9, and any claims above 12) remain textually in force and largely untested before the Board.

IPR2017-00577 — SK hynix Inc. et al. v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2017-01-05 (petition, Paper 1; NatLawReview PTO Litigation Center Report confirms filing date and parties)
• Petitioner: SK hynix Inc.; SK hynix America Inc.; SK hynix Memory Solutions Inc.
• Patent Owner: Netlist, Inc.
• Status: Final Written Decision issued 2018-07-05 — all instituted claims held unpatentable
• Judge panel: Panel members not confirmed from the sources I retrieved; do not rely on any names not verified in the decision itself.
• Petition grounds: Challenged claims 1–3, 7, 8, and 10–12 under §§ 102/103. Principal references visible in the record include Halbert (US 7,024,518, Ex. 1005), Stone, Microcomputer Interfacing (1982, Ex. 1013), US 2006/0117152 A1, JEDEC JESD79, and related DIMM/buffer art, supported by the Declaration of Harold S. Stone (Ex. 1003). (I could not fully reconstruct the ground-by-ground table from available snippets; quote the FWD's ground list directly before relying on it.)
• Institution decision: 2017-07-07 (Paper 8). The Board instituted on claims 1–3, 7, 8, and 10–12 but not on all grounds. After the Supreme Court's decision in SAS Institute, Inc. v. Iancu, 138 S. Ct. 1348 (2018), the Board modified the institution decision on 2018-05-02 (Paper 24, "SAS Order") to institute on all grounds presented in the Petition.
• Final Written Decision: Paper 26, dated 2018-07-05. Dispositive language from the decision: "we determine that Petitioner has shown by a preponderance of the evidence that claims 1–3, 7, 8, and 10–12 are unpatentable." In other words — every claim that was challenged and instituted was canceled at the Board, including independent claim 1 (quoted in the FWD) and its challenged dependents/companions. The FWD record also notes Patent Owner's motion to exclude (2018-02-28) and an oral hearing on 2018-04-06.
• Settlement / termination: No settlement identified. The 2018-07-05 paper is the Final Written Decision (some docket aggregators mislabel it "Termination Decision Document"); termination follows from the FWD as a matter of course.
• Appeal: I found no evidence that Netlist appealed this FWD to the Federal Circuit. (The family-level CAFC docket 18-1676 predates this FWD and cannot be the appeal of it.) Absent an appeal, the FWD is final and the claims fall — verify issuance of the certificate of cancellation in USPTO records before relying on this in a pleading.
• Defensive value: Very high for the claims that were in play. Claims 1, 2, 3, 7, 8, 10, 11, and 12 have a final Board holding of unpatentability on the merits. If Netlist asserts only those claims, an infringement theory built on them is dead on arrival. Primary source for the FWD: DocketAlarm copy of the 2018-07-05 Final Written Decision; docket index at Patexia — SK hynix v. Netlist, IPR2017-00577.

IPR2014-01029 — SanDisk Corp. v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2014-06-24 (petition; supplemental petition filed 2014-07-23)
• Status: Institution denied — merits (per the patent's family record); rehearing denied
• Judge panel: Not confirmed from available sources.
• Petition grounds: Challenged claims of US 8,516,185 (exact claim list not confirmed in my sources); supported by the Declaration of Charles J. Neuhauser, Ph.D. (Ex. 1008). Multiple independent citations confirm the case caption as SanDisk Corp. v. Netlist, Inc. (e.g., an exhibit title quoted in later PTAB papers: "Decision Denying Institution of Inter Partes Review of U.S. Patent No. 8,516,185, SanDisk Corp. v. Netlist, Inc., IPR2014-01029, Paper No. 11, Dec. 16, 2014").
• Institution decision: Denied — Decision Denying Institution (Paper 11), issued 2014-12-16.
• Rehearing: Petitioner's request for rehearing under 37 C.F.R. § 42.71 filed 2015-01-15; denied 2015-03-03.
• Final Written Decision: None — no trial was instituted.
• Settlement / termination: N/A (case ended on the denial).
• Appeal: No appeal identified (a denied institution is not appealable as of right).
• Defensive value: Limited directly (no estoppel attaches to a denied petition, and the claims survived this round), but the denial did not save the patent — SK hynix's later, better-developed petition succeeded on the same patent in 2018. For a defendant, this proceeding is a roadmap of art and arguments that failed at the institution stage (Neuhauser declaration), which is useful for calibrating a new petition on the surviving claims.

IPR2014-01369 — Petitioner v. Netlist, Inc. (petitioner identity not confirmed)

• Type: Inter Partes Review
• Filed: 2014-08-23 (per the exhibit label later used in IPR2017-00577: "IPR2014-01369 08-23-2014 Petition for Inter Partes Review"); Corrected Petition filed 2014-09-22
• Status: Institution denied — merits (per the patent's family record)
• Petitioner: Not confirmed from my sources. The 2014 petition wave against Netlist's memory-module patents was driven by SanDisk Corp. / Smart Storage Systems and Diablo Technologies (defendants in N.D. Cal. No. 4:13-cv-05889), and IPR2014-01029 (same patent) was SanDisk's — but I did not verify the IPR2014-01369 petitioner name and will not guess it.
• Judge panel: Not confirmed from available sources.
• Petition grounds: Corrected Petition challenged claims 1–19 of US 8,516,185; supported by the Declaration of Dr. Nader Bagherzadeh (Ex. 1008) plus dictionary exhibits (Ex. 1013, 1014).
• Institution decision: Denied — Decision Denying Institution (Paper 12). Most citations give the date as 2015-03-09; one secondary source renders it "Mar. 9, 2014," which is internally impossible for an IPR2014-01369 (petition filed Aug. 2014) and is a typographical error. I treat 2015-03-09 as the correct date.
• Final Written Decision: None.
• Settlement / termination: N/A (case ended on the denial).
• Appeal: No appeal identified.
• Defensive value: Like IPR2014-01029, this denial created no estoppel and left the claims standing at the time — but it also did not immunize the patent. The 2018 FWD in IPR2017-00577 later invalidated the claims SK hynix actually challenged. For surviving claims (not challenged in 2017), the Bagherzadeh declaration and the Board's denial reasoning are public materials worth mining before filing anything new.

Strategic summary

Canceled vs. sustained vs. untested. Through IPR, claims 1, 2, 3, 7, 8, 10, 11, and 12 have been held unpatentable in a final written decision (IPR2017-00577, 2018-07-05) — the practical equivalent of cancellation once the certificate issues. No claim of the '185 patent has ever been sustained on the merits by the Board in an instituted trial, because the two 2014 petitions never cleared the institution threshold. The claims the 2017 petitioner did not challenge — the record shows the 2014 corrected petition covered claims 1–19, so the patent contains at least claims up to 19 — remain untested by any instituted IPR (notably claims 4–6, 9, and 13 and above, exact claim numbering to be verified against the certificate). The bottom line is unusual: this is not a "hardened" patent. The main event (claim 1 and its litigation cohort) went the petitioner's way; only the non-asserted fringe claims were never reached.

Estoppel landscape. § 315(e)(2) estoppel attaches only to proceedings that reach a Final Written Decision. It therefore binds SK hynix Inc., SK hynix America Inc., SK hynix Memory Solutions Inc., and their privies as to claims 1–3, 7, 8, 10–12 on all grounds raised or reasonably available in IPR2017-00577 — largely academic because those claims are already invalidated. The two denied 2014 petitions (SanDisk's IPR2014-01029 and the unconfirmed petitioner's IPR2014-01369) generate no estoppel. A defendant who is not SK hynix or a privy is free to run any § 102/103 ground against the surviving claims — including the very art that succeeded in 2017 — and the full public record (Stone, Halbert, Neuhauser, Bagherzadeh declarations) is a ready-made starting point. Watch the § 315(b) one-year bar from service of a complaint if you are already sued.

Pattern signals. This patent has now been attacked three times: twice in 2014 during the SanDisk/Diablo-era N.D. Cal. litigation (both denied at institution), then again by SK hynix in 2017 in the shadow of ITC Inv. No. 337-TA-1023 and C.D. Cal. No. 8:16-cv-01605 — and the third attack succeeded, aided by SAS v. Iancu, which forced all-grounds institution. Netlist litigates its memory-module portfolio aggressively across district court, the ITC, and the Federal Circuit, and the family record shows heavy PTAB traffic on sibling patents (e.g., the 2014–2015 SanDisk cluster on the '150/'536/'434 patents and the 2017–2018 hynix cluster). No defensive-aggregator involvement is confirmed for these three proceedings; the "Unified Patents" attributions in the patent-page metadata are data-source credits, not petitioner names.

Recommended next steps

1. If you are a defendant facing claims 1–3, 7, 8, or 10–12: Those claims carry a final Board unpatentability holding. Pull the IPR2017-00577 Final Written Decision (Paper 26, 2018-07-05) and confirm in USPTO records that the certificate of cancellation has issued post-appeal-window. Then move to strike/dismiss or for summary judgment of no infringement/invalidity with that decision front and center — the plaintiff cannot resuscitate those claims absent a successful appeal (none identified).
2. Identify exactly which claims Netlist asserts. If the demand complaint cites only invalidated claims, say so plainly and put the burden on Netlist to identify a surviving claim. If it cites claims 4–6, 9, or 13+ (verify numbering), those are the only live targets, and none has been tested in an instituted IPR — a fresh petition on those claims is viable, with no § 315(e) estoppel from the denied 2014 petitions.
3. Run the § 315(b) clock. If you have been served with a complaint, any new IPR must be filed within one year of service. If the one-year bar has passed for you, the invalidated-claims argument and § 315(e) estoppel of prior petitioners become your primary levers, and you should check whether SK hynix or a privy (e.g., a customer or supplier in your chain) is estopped in a way you can invoke.
4. Verify threshold facts before filing: (a) Google Patents labels the '185 patent "Expired – Fee Related" with an adjusted expiration of 2030-01-13 — confirm the maintenance-fee/lapse history in USPTO records, because a lapsed patent changes the damages calculus entirely; (b) confirm the exact surviving claim list from the certificate of cancellation, since I could not verify the full claim set (1–19 or beyond) from a single authoritative source.

Primary sources: USPTO PTAB (ptabtrials.uspto.gov / PTAB Center) for Papers 8, 24, and 26 in IPR2017-00577 and the institution denials in IPR2014-01029 (Paper 11) and IPR2014-01369 (Paper 12); DocketAlarm — IPR2017-00577 Final Written Decision; Patexia docket — SK hynix v. Netlist; NatLawReview PTO Litigation Center Report, 2017-01-06 (confirming filing date and parties for IPR2017-00577).

I'll research the USPTO assignment record for US 8,516,185 to reconstruct the ownership chain.

Key lead found — SMART Modular's IPR in 2014 described the '185 patent as "assigned to DBD Credit Funding LLC." Let me dig for the actual reel/frame records.

Found the SVIC security-interest recording (reel 037150). Let me pin down the other links — the original 2010 inventor assignment, the DBD lien, and the TR Global Funding 2017 lien.

Inventors

Departure-pattern check: not present. Both inventors were Netlist personnel at filing and both remained Netlist inventors of record on later continuations. There is no "all inventors left within 12 months" fingerprint, and no recorded inventor-side assignment beyond the single 2010 recording to Netlist. Shenanigans of a different kind exist elsewhere in the family — Samsung has alleged inventorship/derivation defects on Netlist's later '506/'608 patents arising from Hyun Lee's JEDEC attendance — but no such challenge is on record against the '185, and it bears on validity, not on the ownership chain.

Contradiction flag (carried forward). The earlier "Patent summary" section reasoned that the '185 contains three independent claims (claim 1, claim 18, claim 25) from the published application's structure. The ITC expert declaration submitted in 337-TA-1023 states the granted patent "has 19 claims, two independent claims and 17 dependent claims" (Netlist 337-TA-1023 expert declaration, ¶58). Treat the two-independent-claims / 19-total figure as authoritative for the granted patent; the earlier three-independent-claim estimate should be disregarded.

Original assignee

Netlist, Inc. (Irvine, CA) — a Delaware corporation, publicly traded (NASDAQ: NLST), and the assignee named on the face of the patent (Field (73)).

• Primary line of business: design and supply of memory subsystems and modules for servers and storage — historically RDIMMs, NVvault non-volatile backup modules, and the HyperCloud line; more recently HybriDIMM and related memory-module technology. Netlist also maintains an active patent-licensing and litigation program.
• Did they ship a product embodying the claims? Substantially yes in direction, with a caveat. Netlist is a module designer/manufacturer rather than a pure licensor, and the '185's distributed byte-wise buffer architecture is the LRDIMM-style design Netlist worked on in the same JEDEC JC-40/JC-45 committees where Hyun Lee sat. Netlist also filed a JEDEC Letter of Assurance for application 12/761,179 (now the '185), committing to offer implementers a RAND license — an act only a standards-participating operating company takes. I could not verify a Netlist catalog part number that is specifically and exclusively read on claim 1; treat "ships products embodying the claims" as well supported at the portfolio level and unverified at the part-number level.
• Status: Operating, not dissolved, not in bankruptcy. Netlist filed a Form 10-K dated December 27, 2025 and, on November 7, 2025, amended its 2023 SVB credit agreement to extend maturity to November 7, 2027 (SEC EDGAR, NLST 10-K). It continues to litigate (Netlist v. Samsung/Micron appeals).

Assignment timeline

Caveat before the list: the USPTO Assignment Center record for 8516185 is indexed, but I was able to retrieve reel/frame data for only one link (the 2015 SVIC security interest). The remaining links are dated from the patent's Google Patents legal-events record and corroborated against Netlist's SEC filings, but I did not recover their reel/frame numbers in the searches available. Anything below marked "not retrieved" is a genuine gap, not a zero.

1. (executed on or before) 2010-10-19 / recorded 2010-10-19 — Reel/frame not retrieved

• Conveyance: Assignment of Assignors' Interest (see document for details)
• Assignor: Jayesh R. Bhakta; Hyun Lee
• Assignee: Netlist, Inc.
• Correspondent: not retrieved. (For scale only, and not asserted as the '185's record: a contemporaneous Netlist inventor→company recording for a different Netlist case sits at Reel 025301, Frame 0961.)
• Context: Original acquisition — the inventors assigned to their employer, the standard operating-company capture of employee inventions.

2. 2013-07-18 (executed) / recorded 2013-07-18 — Reel/frame not retrieved

• Conveyance: Security Agreement (Intellectual Property Security Agreement)
• Assignor: Netlist, Inc.
• Assignee: DBD Credit Funding LLC
• Correspondent: not retrieved
• Context: Securitization — collateral grant perfecting a lien securing a term loan under the Loan and Security Agreement dated July 18, 2013 between Netlist and DBD Credit Funding LLC (both filed as exhibits to Netlist's Form 10-Q for the quarter ended September 28, 2013, Ex. 10.1 and Ex. 10.3). A warrant was issued in the same facility (Ex. 10.4), the signature of venture/structured debt rather than patent assertion.

3. 2015-11-18 (executed) / recorded 2015-11-20 — Reel 037150 / Frame 0897 (frame reported from the recorded instrument; treat the frame digit as needing verification — the recording stamped one cover sheet across a large Netlist patent list that includes 8516185)

• Conveyance: Security Interest (Intellectual Property Security Agreement)
• Assignor: Netlist, Inc.
• Assignee: SVIC No. 28 New Technology Business Investment L.L.P. (Korean LLP; an affiliate of Samsung Venture Investment Corp.)
• Correspondent: Troy Zander, DLA Piper LLP (US), 4365 Executive Drive, Suite 1100, San Diego, CA 92121; attorney docket 350916-9; contact susan.reynholds@dlapiper.com. Recurrence flag: the same firm — DLA Piper LLP (US) — is identified in Netlist's own SEC exhibits as "satisfactory counsel" for Netlist in the contemporaneous SVIC Registration Rights Agreement and is Netlist's long-time outside IP counsel, so the correspondent here is the operating company's regular firm, not an NPE-side filer. The recorded instrument is captioned "Netlist – Project Neptune – IP Security Agreement."
• Context: Securitization — first-priority security interest in Netlist's patents securing a $15 million senior secured convertible note (2%/yr, maturing Dec. 31, 2021) plus a warrant for 2,000,000 shares; per Netlist's Form 8-K of November 12, 2015, SVIC received a first-priority patent lien and a second-priority lien on other assets, with an intercreditor agreement against SVB.

4. 2015-12-03 (executed) / recorded 2015-12-03 — Reel/frame not retrieved

• Conveyance: Termination of Intellectual Property Security Agreement
• Assignor: DBD Credit Funding LLC
• Assignee: Netlist, Inc.
• Correspondent: not retrieved
• Context: Lien release — the 2013 DBD collateral position is extinguished (indexed on Google Patents with the parties inverted, i.e., "assigned to NETLIST, INC." from DBD).

5. 2017 (executed, reported) / recording against the '185 not confirmed — no reel/frame

• Conveyance: Patent Security Agreement (junior lien)
• Assignor: Netlist, Inc.
• Assignee: TR Global Funding V, LLC (managed by TR Global Associates V, LLC)
• Correspondent: not retrieved
• Context: Securitization — the '185 is expressly named in the schedule of "Original Patents" (with 8,756,364, 8,001,434, 8,359,501, 8,689,064, 8,489,837) in the 2017 TR Global Funding patent security agreement filed as Ex. 10.3 to Netlist's Form 10-Q for the quarter ended July 1, 2017, and the May 3, 2017 Intercreditor Agreement subordinates TRGF to SVIC. However, the '185's Google Patents legal-events list shows no TR Global recordation. Either the 2017 lien was folded into a portfolio-level recording not keyed to the '185, or it was never separately recorded against this patent. Flagging rather than asserting — this is exactly the kind of gap that also produced the erroneous "no PTAB proceedings" result noted in the earlier PTAB section.

6. 2023-11-20 (executed) / recorded 2023-11-20 — Reel/frame not retrieved

• Conveyance: Release by Secured Party
• Assignor: SVIC No. 28 New Technology Business Investment L.L.P.
• Assignee: Netlist, Inc.
• Correspondent: not retrieved
• Context: Lien release — the 2015 SVIC first-priority patent lien is discharged, consistent with retirement of the SVIC secured debt. No ownership change; Netlist remains record owner.

Net effect of the chain: Title has been in Netlist, Inc. continuously since the October 2010 recording. Every post-2013 record is a collateral grant or its release. There has never been a transfer of title to a licensing vehicle.

Timeline diagram

timeline
    title Ownership of US 8516185
    2009 : Parent application filed Jul 16
    2010 : CIP filed Apr 15
         : Inventors assign to Netlist Oct 19
    2013 : Patent issued Aug 20
         : DBD security interest Jul 18
    2015 : SVIC security interest Nov 18
         : DBD lien terminated Dec 3
    2017 : TR Global Funding junior lien
    2023 : SVIC release recorded Nov 20

NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT.
No record moves the '185 to a "…IP / Licensing / Holdings / Ventures" vehicle. The only non-Netlist assignees on record are DBD Credit Funding LLC (reel/frame not retrieved; lien recorded 2013-07-18) and SVIC No. 28 New Technology Business Investment L.L.P. (reel 037150 / frame 0897, recorded 2015-11-20). Both are secured lenders, both instruments are captioned "Security Agreement" / "Intellectual Property Security Agreement," and both are neutralized by releases in Netlist's favor (2015-12-03 and 2023-11-20).

2. Known asserter in the chain — NOT PRESENT (as to assignees).
None of Acacia / Marathon / IV / IPNav / Wi-LAN / Conversant / Vringo / Pendrell / Round Rock / Spangenberg et al. appears anywhere in this chain. Netlist itself is a high-frequency plaintiff, but Stanford's NPE Litigation Database classifies Netlist in the "Product company" asserter category for the case that first asserted the '185 (Netlist v. Diablo Technologies, 4:13-cv-05962) (Stanford NPE Litigation Database – 8516185). Netlist monetizes by suing competitors over its own modules — that is operating-company assertion, not troll behavior, even though the volume and the ITC/CAFC docket are aggressive.

3. Repeat correspondent across the chain — UNCLEAR (insufficient data).
The only correspondent I recovered is Troy Zander / DLA Piper LLP (US), San Diego on the 2015 SVIC recording (reel 037150 / frame 0897). A single confirmed appearance is not a finding under the stated rule, and DLA Piper is a large general-practice firm that does both operating-company and financing work; its presence here is the debtor company's corporate counsel, not a serial NPE filer. I could not retrieve the correspondents for the 2010, 2013, 2015-release, or 2023 recordings, so recurrence cannot be tested either way.

4. Cascading transfers — NOT PRESENT.
No chained LLC-to-LLC conveyances. The 2015 links run in the wrong direction for the pattern: a security interest in (Nov. 18, 2015), then a termination out of the chain (Dec. 3, 2015). Spacing between the DBD lien (2013) and the SVIC lien (2015) is ~28 months, above the 24-month clustering threshold.

5. Pre-litigation transfer — NOT PRESENT (timing coincidence only).
The DBD security agreement was executed 2013-07-18, roughly five weeks before Netlist's first 2013 infringement complaint (C.D. Cal. 8:13-cv-00996 / N.D. Cal. 4:13-cv-05962, Aug.–Dec. 2013). That is inside the six-month window, and it is worth naming — but it fails the substance of the signal because title never moved. The instrument is a collateral grant that funded Netlist's operations during litigation; it did not set venue or create a clean standing record, and it was terminated in 2015. Netlist's standing to sue on the '185 was litigated from Netlist's own 2010 chain, not through DBD.

Data artifact worth knowing: during 2013–2015 the USPTO assignment record showed the secured party as the assignee of record. The tell is downstream: an August 2014 PTAB roundup described IPR2014-01369 as challenging "U.S. Patent No. 8,516,185 assigned to DBD Credit Funding LLC" while listing the sibling patents as "assigned to Netlist, Inc." (Harness IP AIA blog, Aug. 23, 2014). Anyone reading the Assignment Center snapshot for those months would wrongly conclude the patent had been sold to a lender-LLC.

6. Bankruptcy fire-sale — NOT PRESENT.
No Chapter 7 or Chapter 11 of Netlist, Inc. is on record, and none of the assignees acquired the patent out of an estate. Netlist's liquidity stress was managed through secured facilities (SVB credit agreements; DBD 2013; SVIC 2015; TR Global 2017) and, separately, through the $40M SK hynix settlement, not a bankruptcy sale. The 2023-11-20 Release by Secured Party is a lien discharge, which is the opposite of a fire-sale conveyance.

7. Privateering — NOT PRESENT.
The classic pattern (operating company parks patents in an NPE that sues its competitors) is absent: Netlist is both the manufacturer and the plaintiff, and it sues in its own name. Note the inversion of interest: Samsung, through its venture arm Samsung Venture Investment Corp. (SVIC No. 28), held the first-priority patent lien on the '185 from 2015 until the 2023 release — i.e., a Netlist litigation adversary was, for eight years, a secured creditor against the very patent Netlist later asserted against SK hynix and Samsung. That is a financing relationship, not privateering, but it is a genuinely unusual feature of this chain and it materially shaped Netlist's freedom to monetize during the SVIC note's life.

8. Defensive aggregator — NOT PRESENT.
The chain ends at Netlist, Inc., an asserter. It does not terminate at RPX, AST, LOT, Unified Patents, or OIN; none appears as assignee on any record. The "Unified Patents" attribution visible in the Google Patents litigation metadata is a data-source credit for the PTAB/litigation records, not an ownership interest — the earlier PTAB section flagged the same conflation.

Verdict

Operating-company assertion.

Title to U.S. 8,516,185 has been held continuously by Netlist, Inc. since the inventor assignment recorded 2010-10-19; every other record in the chain is a collateral grant by Netlist to a lender — DBD Credit Funding LLC (2013-07-18) and SVIC No. 28 New Technology Business Investment L.L.P. (recorded 2015-11-20, reel 037150 / frame 0897) — followed by the corresponding releases (DBD termination recorded 2015-12-03; SVIC release by secured party recorded 2023-11-20). Netlist is a publicly traded, still-operating memory-subsystem designer (NLST; 10-K filed December 27, 2025, SVB maturity extended to November 7, 2027) that asserts the '185 against actual competitors — SK hynix, Samsung, Micron, and Google — and Stanford's NPE database classifies it as a product company rather than a patent asserter. There is no shell-entity transfer, no asserter-LLC in the chain, no cascading conveyance, no bankruptcy sale, and no defensive-aggregator termination; the sole caveat is that the correspondent data needed to test the repeat-counsel signal is only partially recoverable, and the 2017 TR Global Funding lien is reported in SEC filings but not confirmed as separately recorded against this patent.

Verify at: https://assignment.uspto.gov/patent/index.html — search by patent number 8516185 (the same records are served by https://assignmentcenter.uspto.gov/). Pull the reel/frame for entries 1, 2, 4, 6, and 2023 to close the gaps above.

I'll research the citations listed for US 8,516,185 B2, searching the USPTO record and other authoritative sources.

The initial searches surfaced a USPTO PTACTS scan of the patent that includes part of the "References Cited" list. I need the complete cited-reference list to analyze each reference. Let me dig further.

I need the full "References Cited" list as printed on the face of US 8,516,185. Let me try to pull the FreePatentsOnline page for this patent, which reproduces that section.

I have to be candid up front about a data limitation before giving the analysis.

Search results and data-limitation note

USPTO record confirmed. The USPTO PTACTS scan of the granted patent (linked from ptacts.uspto.gov) confirms the bibliographic data: US 8,516,185 B2, "System and method utilizing distributed byte-wise buffers on a memory module," inventors Hyun Lee and Jayesh R. Bhakta, assignee Netlist, Inc., issued Aug. 20, 2013, filed Apr. 15, 2010 (Appl. 12/761,179), Primary Examiner Edward Dudek, Jr., Assistant Examiner Ralph A. Verderamo, III. The published application (US 2011/0016250 A1, per Justia) confirms three independent claims: claim 1 (apparatus — PCB, control circuit, distributed data-transmission circuits each coupled to ≥ two memory devices), claim 18 (apparatus — controller + plurality of circuits that "drive write data" and "merge read data," distributed at separate positions), and claim 25 (method — byte-wise buffer driving write data along one of plural paths and merging read data).

Limitation: I could only retrieve a partial reproduction of the "References Cited" section from the USPTO PTACTS scan (the search snippet cut off mid-list at "U.S. PATENT DOCUMENTS… (Continued)"). I could not retrieve the complete examiner citation list from the USPTO record in the searches available to me. Accordingly, the enumeration below is a partial list, and I flag every place where I am relying on a reference whose full cited set I could not verify. I am not auto-correcting any numbers; where an identifier came only from a snippet I identify it as such.

Partial confirmed list of U.S. patents cited on the face of 8,516,185 (from the USPTO scan)

These were visible in the USPTO "References Cited" section:

Foreign references visible in the same partial list: EP 1 816 570 A2 (Aug. 2007) and WO 92/02879 (Feb. 1992), with a "(Continued)" marker confirming additional cited references that I could not capture.

Honest assessment: The visible portion is dominated by 1980s–1990s U.S. patents — the kind of references examiners typically list as category "A" (background) or as secondary § 102/103 evidence. The most technically probative references for the claims' load-reducing/byte-buffer features are likely in the truncated portion (which would normally include the post-1997 art such as Netlist's own control-circuit patents, and the mid-2000s buffer/load-isolation art). I did not obtain a verified list of those, so I will not fabricate them as "cited."

Analysis of the confirmed references most relevant under 35 U.S.C. § 102

For each confirmed citation, I give the best-supported description and map to the independent claims (claim 1: distributed data-transmission circuits each coupled to ≥ 2 memory devices and selectively gating transmission; claim 18: plurality of circuits that drive write data/merge read data, distributed separately; claim 25: byte-wise-buffer method). Because I could not review the full text of each cited patent, descriptions are from title-level knowledge and secondary sources; where uncertain I say so.

Highest relevance among confirmed citations

1. US 4,368,515 A — Nielsen, "Bank switchable memory system," issued Jan. 1983

• Description: Early memory-system architecture that switches among multiple memory banks to expand the addressable memory space visible to a processor — the exact "combine chip-select with address to expand memory space" paradigm the 8516185 specification discusses in its Background as a prior approach.
• § 102 mapping: Potentially anticipatory only of very old, generic memory-expansion concepts. It does not teach distributed byte-wise data buffers, a module control circuit regenerating rank controls, or the drive/merge circuit arrangement of claims 1/18/25. Likely cited as background (category A) rather than as a § 102 rejection of any independent claim. (Note: the "Bank switchable memory system" title is corroborated by the search snippet associating Nielsen with that title; I did not open the patent text.)

2. US 5,345,412 A — Shiratsuchi, "Memory IC and memory device capable of expansion of storage capacity," issued Sep. 6, 1994

• Description: A memory IC/device arrangement enabling storage-capacity expansion, relevant to the rank/density-expansion problem addressed by 8516185. (Title corroborated by the snippet in FreePatentsOnline lists.)
• § 102 mapping: Addresses capacity expansion but not the distributed byte-wise load-reducing buffers on a module data path; does not appear to teach the "selectively allow/inhibit data transmission" per-device gating of claim 1 or the drive/merge structure of claim 18. Not likely anticipatory of the independent claims standing alone.

3. US 5,388,240 A — Olderdissen et al., "DRAM chip and decoding arrangement and method for cache fills," issued Feb. 7, 1995

• Description: DRAM decoding/select arrangements for directing data. Relevant to rank/chip-select decoding concepts the control circuit of claim 1 performs.
• § 102 mapping: No distributed byte-wise buffers; no write-drive/read-merge circuitry. Background/decoding art only.

4. US 5,426,753 A — Moon, issued Jun. 1995

• Description: Memory-system control arrangement (title not retrieved; do not rely on specifics).
• § 102 mapping: Insufficient information; at most background.

5. US 5,655,153 A — Sandorfi, issued Aug. 1997 (and the other mid-1990s entries — Matick 5,388,072; Kikuda 5,357,478; Mochizuki 5,483,497; Sugahara 5,495,435; Ludwig 5,581,498; Kolor 5,590,071; Hyatt 5,602,999; Mote 5,638,534)

• Description: I did not retrieve titles/abstracts for these; I will not characterize their disclosures beyond noting they pre-date the key load-reduced-DIMM (LRDIMM) art (post-2000) and are most plausibly category-A background or secondary references.

6. WO 92/02879 (Feb. 1992) and EP 1 816 570 A2 (Aug. 2007)

• EP 1 816 570 A2 relates to an integrated-circuit I/O / high-performance bus interface field (per the snippet in the 9037774 list where it appears as a foreign reference: "Integrated circuit I/O using a high performance bus interface"). Relevant at most to signal-buffering concepts in claim 25's "byte-wise buffer" but not to the distributed-module architecture of claims 1/18.

Bottom line on the confirmed citations

None of the confirmed (partial-list) references appears, on the information available, to teach the combination that defines the independent claims — i.e., multiple data-transmission circuits physically distributed on the module and each coupled to at least two memory devices across ranks, responding to module control signals to selectively couple only a chosen device to the memory controller (claim 1); the functionally worded drive-write/merge-read circuits distributed at separate positions (claim 18); or the byte-wise-buffer read-merge/write-drive method (claim 25). Individually, the older references are more plausibly cited as background (§ 102 does not apply to background; they would not anticipate). The technically closest anticipatory art for this Netlist LRDIMM-style invention normally comes from the truncated portion of the list and from the specification's own incorporated references.

Additional references that the specification itself treats as prior art (incorporated by reference), with § 102 caveat

The 8516185 specification explicitly incorporates U.S. Pat. Nos. 7,289,386 and 7,532,537 (both Netlist, Bhakta/Solomon et al., "Memory module decoder" and "Memory module with a circuit providing load isolation and memory domain translation") as examples of the control circuit 430/430′. These are commonly relied on in the Netlist family as § 102(e)/§ 103 references because they disclose a register/control circuit receiving chip-selects and generating module control signals for load isolation. I cannot confirm they appear in the examiner's "References Cited" list for 8516185 from the portion I retrieved, so I list them here as specification-incorporated prior art rather than as confirmed face citations. The parent application 12/504,131 (issued as US 8,417,870) is a related application (priority document for the CIP), not a § 102 reference against claims entitled to its filing date — although subject matter newly added in the CIP could in principle be attacked using the parent as prior art under § 102(e).

What I could not verify (explicitly)

1. The complete examiner "References Cited" list. The USPTO PTACTS scan is truncated in my search results ("(Continued)" appears), and Google Patents' cached text for US8516185 did not surface the citation section. The "most relevant" prior art in the classic sense — the post-2000 distributed-buffer / load-reduction art most likely to be asserted against claims 1/18/25 — is almost certainly in that un-retrieved remainder. I decline to guess which specific patents (e.g., Halbert, Tsern, Karabatsos, Klein, Holman, or Netlist's own 7,289,386/7,532,537) the examiner actually listed.
2. Full text review of each confirmed citation — several titles/abstracts above (Moon 5,426,753; Sandorfi 5,655,153; Mote 5,638,534; etc.) were not retrieved, and I have not read their disclosures.
3. A claim-by-claim § 102 chart against each cited reference requires the missing reference texts; the mapping above is therefore directional, not a formal anticipation chart.

If you want, the next step would be to pull the complete USPTO "References Cited" page (the PTACTS/PatentCenter HTML for Appl. 12/761,179) so I can give you a verified, complete anticipation analysis of every citation against claims 1, 18, and 25.

Obviousness Analysis — U.S. Patent 8,516,185 B2 ("the '185 patent") under 35 U.S.C. § 103

Preliminary note on the "Prior Art section"

The Google Patents page fetched for this analysis (the full patent text provided above) does not include a populated "Prior Art"/"Patent Citations" section — no examiner-cited U.S. patents or non-patent literature appear on that page. I therefore reconstructed the operative prior-art record from the authoritative inter partes review history for this exact patent number, which is the best available public record of art actually applied against the '185 claims:

• IPR2017-00577 (SK hynix Inc. et al. v. Netlist, Inc.), Institution Decision, Paper 8 (PTAB Jul. 7, 2017) — instituting review of claims 1–3, 7, 8, and 10–12 on anticipation and obviousness grounds;
• IPR2017-00577, Final Written Decision (PTAB Jul. 5, 2018) — holding claims 1–3, 7, 8, and 10–12 unpatentable.
• Two earlier petitions against the '185 patent were not instituted: IPR2014-01029 (SanDisk) and IPR2014-01369 (Smart Modular).

Sources: Docket Alarm FWD copy (https://www.docketalarm.com/cases/PTAB/IPR2025-01431/Samsung_Electronics_Co._Ltd/08-29-2025-Petitioner/Exhibit-1053-EX1053___2018_07_05___185_Final_Written_Decision/); Institution Decision copy (https://www.docketalarm.com/cases/PTAB/IPR2022-00639/Samsung_Electronics_Co._Ltd._v._Netlist_Inc/docs/03-02-2022-Petitioner/Exhibit-1031-2017_07_07__IPR2017_00577_Institution_on_the_185_patent.pdf); Petition (https://www.cmosedu.com/jbaker/expert_witness/2017/IPR2017_00577.pdf).

Caveat on the claims: The full granted claim text of the '185 patent is truncated in the source page, and my earlier summary's speculation about "three independent claims" should be revised in light of the IPR record: the FWD reproduces claim 1 as the illustrative independent claim and the challenged set was claims 1–3, 7, 8, and 10–12 (the earlier petitions challenged claims 1–19, indicating a 19-claim patent). Only claim 1's text is visible in the record I retrieved; dependent claims 3 and 10 are discussed below only as to the specific additional limitations identified by the PTAB grounds (Halbert + Connolly for claim 3; Halbert + JESD79 for claim 10).

1. The references (with bibliographic data, interpreted literally)

All of these references predate both the parent application (U.S. 12/504,131, filed Jul. 16, 2009) and the CIP application (U.S. 12/761,179, filed Apr. 15, 2010) that issued as the '185 patent, so they are squarely available as § 102/§ 103 art even under the earliest possible priority date.

2. Representative claim and the primary reference (Halbert)

As reproduced in the IPR2017-00577 Final Written Decision, claim 1 of the '185 patent requires, in substance:

• a plurality of memory devices;
• a controller that receives control information from a system memory controller and produces module control signals;
• a plurality of circuits receiving the module control signals, each circuit having a first bit width and coupled to at least two corresponding memory devices each having a second bit width smaller than the first bit width (e.g., a byte-wide/×8 buffer coupled to a pair of ×4 DRAMs, or the FIG. 3B/4B "n/2 data transmission circuits" embodiment);
• each circuit having at least one write buffer and at least one read buffer, configured to selectively allow data transmission to a selected memory device and selectively isolate the other coupled device(s);
• active driving of write data (write direction) and receiving/driving of read data (read direction); and
• the circuits being distributed at corresponding positions separate from one another (the "distributed byte-wise buffer" theme of the title).

Halbert's disclosure (per the IPR petition summary at cmosedu.com and the FWD table): Halbert describes buffered memory-module architectures in which a module controller 110 registers address/command signals for two ranks of devices 140/142, and Left and Right Interface Circuits 125/130 — physically separate circuits at distributed positions — sit between the system data bus 22 and the memory devices. Each interface circuit has a bidirectional buffer 122, a multiplexer/demultiplexer 124, and bidirectional registers 126/128 to two ranks, controlled by module-controller signals (e.g., DIR/SYNC). Halbert expressly contemplates configurations beyond two ranks, including a "4:1 multiplexer and four ranks of memory" (Halbert, 9:24–27, cited in the IPR record), and its data-interface circuits handle a per-circuit slice (m/2) of the system data bus — the functional equivalent of bit-sliced, distributed, load-reducing data buffers. Halbert also discloses tristate-style bidirectional buffering to interface with the memory bus.

The PTAB's FWD table of instituted grounds confirms that Halbert alone was the backbone of every ground, asserted as both § 102 anticipation and § 103 obviousness for claims 1–3, 7, 8, and 10–12, and as the base reference for each combination ground.

3. Combination grounds and motivations to combine

Ground A — Halbert alone (§ 103) — claims 1–3, 7, 8, 10–12

Where a single reference is the basis of an obviousness ground, the analysis reduces to whether the differences between the claim and the reference would have been obvious design choices. Here, the differences the Patent Owner could press — e.g., (i) per-circuit bit width larger than the coupled devices' width ("byte-wise buffer" over pairs of ×4 devices), (ii) explicit "write buffer/read buffer" recitation, and (iii) physical distribution of the circuits — are all either expressly disclosed in Halbert (distributed left/right interface circuits; per-circuit m/2 data slices; bidirectional buffer + registers) or obvious variants of it:

• Bit-width mismatch: coupling one wider buffer to two narrower devices is the standard way to assemble a module rank of fixed total width (e.g., nine ×8 devices or eighteen ×4 devices per 72-bit rank). A POSITA assembling Halbert's module from commercially available ×4 DRAMs would split each interface circuit's data slice into nibble halves — exactly the '185's FIG. 3B/4B teaching. The PTAB institution decision and the annotated Halbert exhibits (e.g., Ex. 1035 showing a 4:1 MUX/DeMUX with four ranks of memory) reflect this straightforward mapping.
• Read/write buffer structure: the claimed "drive write data/merge read data" operation is the ordinary behavior of Halbert's bidirectional buffer + MUX/DEMUX + registers under direction control.
• Distribution: Halbert's left/right interface circuits are literally at "corresponding positions separate from one another" on the module.

Because Halbert is a design patent disclosing a complete load-reducing buffered module, and because the record shows the Board found the claims unpatentable over it, Halbert alone is the strongest § 103 (indeed § 102) anchor.

Ground B — Halbert + Stone (§ 103) — claims 1–3, 7, 8, 10–12

Stone's 1982 textbook, Microcomputer Interfacing, is the classic treatment of bidirectional bus transceivers and tristate buffers — i.e., the very circuit elements the '185 claims as "write buffers," "read buffers," and the selectively enabled/disabled data paths (the '185's own FIG. 5 tristate buffers 504/506 and read buffer 509).

Motivation to combine: Implementing Halbert's bidirectional buffer 122 / registers 126/128 in practice requires tristate-capable transceivers so that the disabled path presents a high impedance and does not contend with the active path during read/write turnaround. A POSITA designing the module's data-interface circuits would consult a standard interfacing reference such as Stone to select the tristate buffer topology. Combining a textbook's conventional transceiver teaching with a system patent that requires such transceivers is precisely the "known technique applied to a known device for a predictable result" that KSR treats as obvious. The PTAB instituted this ground across all challenged claims, and the record reflects the declaration of Harold S. Stone himself (Ex. 1003 / deposition Ex. 2004) on tristate buffering.

Ground C — Halbert + Amidi (§ 103) — claims 1–3, 7, 8, 10–12

Amidi (US 2006/0117152 A1) addresses a problem the '185 patent also targets: increasing the number of ranks (memory density/capacity) on a module while remaining compatible with a system memory controller designed for fewer ranks. Amidi teaches using programmable logic (e.g., a CPLD) on the module to receive the controller's chip-select/rank signals and generate internal selects for a larger number of ranks (two → four).

Motivation to combine: The industry's constant goal of increasing memory capacity without changing the host system, combined with Halbert's own express invitation that its architecture extends to "a 4:1 multiplexer and four ranks of memory" (9:24–27), would lead a POSITA directly to Amidi's known rank-expansion technique. Applying Amidi's rank-expansion/decoding logic inside Halbert's module controller 110 yields a four-rank, load-isolated, distributed-buffer module of the kind the '185 claims (four ranks A–D in the '185's FIGS. 3A/3B; module control signals selecting one rank while buffers isolate the others). The combination is a textbook case of "combining prior art elements according to known methods to yield predictable results" (KSR, 550 U.S. at 416): Amidi contributes the rank-selection method, Halbert contributes the buffered data-path architecture, and no incompatibility exists because both concern standard JEDEC-style DIMM control signaling. This Halbert-Amidi combination is also the exact combination the PTAB and later petitions used against Netlist's descendant patents (e.g., US 9,606,907 in IPR2018-00364), confirming its coherence as an obviousness theory.

Ground D — Halbert + Connolly (§ 103) — dependent claim 3

The FWD table lists a Connolly-based ground only for claim 3, indicating that claim 3 adds a limitation (in the family of the FIG. 5 write-buffer 503/tristate write-drive structure) that the petitioner mapped to Connolly (US 6,070,217, a memory-interface patent from May 2000). Connolly supplies the specific registered/buffered write-data path detail, and the motivation is identical: Halbert identifies the need for buffered data paths between the controller and the memory devices, and Connolly provides a known, earlier implementation of such buffering that a POSITA would incorporate by routine design choice. I could not retrieve claim 3's full text or the petitioner's element-by-element mapping from the available snippets, so I flag that limitation of this ground's specificity here.

Ground E — Halbert + JESD79 (§ 103) — dependent claim 10

The JEDEC DDR SDRAM specification (JESD79, June 2000) was combined with Halbert only for claim 10. Based on the position of the ground and the '185 specification's discussion of CAS latency (the delay between column-access command and data availability, used by the control circuit 430 to time the data transmission circuits 416 — see '185, FIG. 6 and accompanying text), claim 10 most plausibly adds a latency-timing limitation on the buffer enable windows. JESD79 standardizes CAS latency timing for DDR DRAMs; a POSITA implementing Halbert's module controller to time the interface circuits' enable signals to the DRAMs' CAS latency would consult the governing JEDEC specification as a matter of course. I could not verify claim 10's exact text, and this ground's limitation-to-claim-10 suggests the added limitation was not otherwise present in Halbert; the combination is nevertheless straightforward because Halbert's module must interoperate with standard JEDEC DDR devices whose timing is defined by JESD79.

4. Graham-factor synthesis and why the combinations are obvious

• Scope and content of the prior art: Halbert discloses essentially the complete claimed architecture (module controller + distributed data-interface circuits + rank selection + bidirectional buffering); Stone, Amidi, Connolly, and JESD79 supply, respectively, conventional tristate-buffer implementation, multi-rank expansion, buffered write-data detail, and DDR timing standards.
• Differences and motivation: Any remaining differences (wider-than-device "byte-wise" buffers, two-device coupling per circuit, express write/read buffer labels, physical distribution) are (a) disclosed in or directly suggested by Halbert, or (b) conventional engineering choices driven by commercially standard ×4/×8 DRAM organizations — the very "n/2 data transmission circuits" of the '185's FIG. 3B being the natural product of pairing ×4 devices under ×8 buffers. A POSITA had express motivation from Halbert's own "4:1 multiplexer and four ranks" passage to seek Amidi's rank-expansion teaching, and from basic bus-design practice (embodied in Stone) to use tristate transceivers.
• Reasonable expectation of success: Each combination applies a known technique (rank decoding, tristate transceivers, registered buffering, JEDEC timing) to a known base design (Halbert) for a predictable result — the standard KSR formulation. No technical incompatibility or design barrier appears in the record.
• Secondary considerations: The FWD expressly notes that Patent Owner did not put forward evidence of secondary considerations of non-obviousness in IPR2017-00577, leaving the Graham factor analysis unopposed.

Outcome in the record: The PTAB instituted on all of the above grounds and, in its July 5, 2018 Final Written Decision, determined that SK hynix had shown by a preponderance of the evidence that claims 1–3, 7, 8, and 10–12 of the '185 patent are unpatentable (with the Halbert-based grounds at the core). The earlier SanDisk and Smart Modular petitions (IPR2014-01029, IPR2014-01369) were denied institution, so IPR2017-00577 is the operative merits determination for this patent.

5. Confidence and uncertainty disclosures

• High confidence: Halbert (US 7,024,518 B2), Amidi (US 2006/0117152 A1), Stone (Microcomputer Interfacing, 1982), Connolly (US 6,070,217), and JESD79 were the instituted prior art; the PTAB held the challenged claims unpatentable; Halbert was the base reference for every ground.
• Lower confidence / not verified from full text: (1) the complete text of claims 2–19 of the '185 patent (only claim 1 was reproduced in the snippets I retrieved); (2) the PTAB's ground-by-ground rationale in the FWD beyond the ground table and the overall holding; (3) the specific claim-3 and claim-10 limitations supplied by Connolly and JESD79 respectively; and (4) whether any post-FWD appeal (the family record lists CAFC matter 18-1676) altered the outcome for this patent. If precise claim-language mapping per dependent claim is needed, the FWD (Paper 26) and Petition (Paper 1) in IPR2017-00577 should be pulled in full from the PTAB's public docket.