Invalidity dossier
US 9037809
Added 9/21/2026, 10:41:41 AM
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Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
US9037809B1 — Memory Module with Circuit Providing Load Isolation and Noise Reduction
Overview: US9037809B1 (application US14/324,990, filed 2014-07-07, granted 2015-05-19) is titled "Memory module with circuit providing load isolation and noise reduction." The current and original assignee listed is Netlist Inc. The listed priority date is 2008-04-14; the application claims priority from several earlier US applications (US12/422,925, US12/504,131, US12/761,179, US13/287,042, US13/288,850, and US13/971,231). Anticipated expiration is listed as 2029-04-13.
Purpose (from the supplied text): The application relates to electrical signal integrity, specifically circuits for improving it. It notes that higher-speed processors and higher memory densities with relatively heavy fan-outs raise power dissipation and memory access time. It describes arrangements using a multiplexer/demultiplexer to isolate unused subsystems, and notes such multiplexers can create transmission-line discontinuity regions (e.g., where signal path electrical lengths exceed ¼ wavelength of the operating frequency or signal transition rate), causing signal reflections, distortion, and integrity issues. Separately, it describes isolating unused subsystems using device select (chip select) signals, which can introduce timing delays and may not address power dissipation.
Plain-language scope (from the excerpt): Certain embodiments include a memory module with a printed circuit board having at least one connector operatively coupled to a computer system's memory controller, a plurality of memory devices on the board, and a circuit. The circuit has a first set of ports (multiple bi-directional ports), each coupled to at least one memory device, a second set of ports (one or more bi-directional ports) coupled to the connector, and a switching circuit configured to selectively operate (text truncated in the excerpt).
What the excerpt does not establish: It does not include the full claims, the complete switching-circuit configuration, any prior-art references, or detailed embodiments. It also does not establish litigation, ownership transfers, validity, or prior-art conclusions; the source notes the legal status and assignee listings are assumptions, not legal conclusions. No such analysis is offered here.
Source: https://patents.google.com/patent/[US9037809](/patent/US9037809)/en
Generated 10/1/2026, 10:01:16 PM
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Litigation summary
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Proceedings on file (0)
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No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.
PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
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Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.