US 8369168

I'll run targeted searches for this specific patent number and any associated litigation.

The searches surfaced mostly unrelated documents. Let me refine with litigation- and docket-specific queries.

Let me try a couple more targeted queries to check for any litigation or family-level activity.

US Patent 8,369,168 — Analyst Summary

Search caveat up front: I ran multiple targeted queries for 8369168 / "8,369,168", including queries paired with "Micron," "litigation," "CAFC," "IPR," and "PTAB." My search tool did not return the USPTO PatentCenter record, the CAFC docket, or any PACER/docket material for this patent. One query returned a Brazilian state-registry document containing the digits "8369168" unrelated to patents (a company registration in Rio Grande do Sul), and another returned documents citing other Micron/Netlist patents (e.g., 8,301,833; 8,787,060; 9,318,160; 10,268,608). No hit pertained to US 8,369,168. I cannot confirm from live sources that this patent has been asserted, IPR-challenged, or appealed, and I do not have authoritative 2026 docket data for it. The summary below is grounded in the authoritative patent text supplied (Google Patents, fetched 2026‑09‑24).

---

Bibliographic Data

---

Abstract (as issued)

Methods, devices and systems for reducing interconnections on a memory device. A first portion of the address of the next row/page to be activated is input over the address bus and embedded in a command related to the previously activated row (e.g., PRECHARGE or REFRESH). The next row is then activated upon a concurrently received second portion of that address, also received over the address bus. Partitioning the address signals allows the address bus width — and thus the number of external interconnections (pins) — to be reduced.

Core technical insight: Conventional PRECHARGE and REFRESH commands treat the address bits as "don't care"/reserved. The patent repurposes those otherwise-unused address fields to carry the upper address bits (A9–A14) of the next page, so the activation is split into a two-phase process (ACTIVE_UPPER + ACTIVE_LOWER) with no added latency. The illustrative SDRAM uses nine address pins (A0/A9, A1/A10, A2/A11, A3/A12, A4/A13, A5/A14, A6, A7, A8) instead of fifteen, while still internally providing all of A0–A14.

---

Independent Claim Overviews (plain language)

Claim 1 — Memory device (two-page framing)

A memory device with at least first and second pages of memory cells, plus a controller and address/command buses arranged so that the device receives a first portion of the second page's address while it is still executing commands pertaining to the first page. Critically, those contemporaneous commands include a precharge command, in response to which an open page is at least partially closed.

• Practical reading: the address of the page you're about to open is folded into the command that closes the page you're currently on.

Claim 6 — Memory device (bus-width framing)

A memory device with pages addressable by a first quantity of address signals, but an address bus having only a second, smaller quantity of address lines. The device is configured to receive the "difference portion" — i.e., the address signals that the narrower bus cannot carry directly — relating to a subsequent page, while executing commands relating to the current page. At least one of those commands is a precharge command that at least partially closes an open page.

• Practical reading: this is the claim that directly ties the technique to pin-count reduction (e.g., 15 address signals carried over 9 lines).

Claim 7 — Electronic system

An electronic system comprising a controller and a memory device configured to embed a portion of the address of a subsequent page into a command pertaining to the current page, where that command includes a precharge command that at least partially closes an open page.

• Practical reading: system-level counterpart of claim 1, naming the controller explicitly as a system element.

---

Dependent Claims (brief)

• Claims 2, 8 — The contemporaneous command may include a refresh command (the FIG. 6 scenario: REFRESH serves as the first phase of activation).
• Claims 3, 9 — Add a register to store/buffer the first (upper) address portion until an activate command supplying the second (remaining) portion arrives.
• Claims 4, 10 — Specify the embedded portion is the upper address portion.
• Claims 5, 11 — Address-signal quantity exceeds address-line quantity (narrower bus).

---

Family and Related Filings

Notable forward citation family member: Samsung's US 9,082,504 B2 (from US 2014/0016421 A1).

---

Litigation / CAFC 2026 Docket — Findings

Nothing found. My searches did not identify:

• any district-court infringement action asserting US 8,369,168,
• any PTAB petition (IPR/PGR) against it,
• any Federal Circuit appeal naming it, or
• any ITC investigation involving it.

The Micron-v.-Netlist and Netlist-v.-Micron litigation activity that dominates search results involves a different patent set (e.g., 7,619,912; 8,301,833; 8,787,060; 9,318,160; 10,860,506; 10,949,339; 11,016,918; 11,232,054; 10,268,608; 11,093,417; 10,217,523; 12,675,407). None of those are US 8,369,168.

Uncertainty statement: This is a negative finding based on public web search, not a verified docket query. I did not obtain direct access to USPTO PatentCenter, PACER, or the CAFC docket system for this patent, so I cannot state with certainty that no such proceeding exists — only that my searches surfaced none.

---

Additional Notes / Uncertainties

1. Claim language quirk: Claims 1 and 6 recite "a controller" as a component of the memory device itself, while the specification describes the controller as external (e.g., memory controller 430 in FIG. 7). Read literally, the claims place the controller inside the device.
2. "At least partially closed": The claims use this hedge for the precharge command; the specification's embodiment simply says PRECHARGE "deactivates and precharges" the array.
3. Maintenance fees: Recorded payments at the 4th (2016), 8th (2020), and 12th (2024) year marks — consistent with an active patent through the 2028‑03‑05 expiration.
4. Security interests: A chain of liens (U.S. Bank 2016, Morgan Stanley 2016, JPMorgan 2018) was granted and subsequently released (2018–2019); these do not affect ownership, which remains Micron Technology, Inc.
5. I found no indication of reissue, reexamination, certificate of correction, or terminal disclaimer for this patent. I cannot rule these out without a PatentCenter query.

Primary source: https://patents.google.com/patent/US8369168/en

I'll search for litigation involving US Patent 8,369,168.

Initial searches were unhelpful. Let me try more targeted sources.

Let me try the specific patent number in quoted format and check patent-specific litigation databases.

Result: No litigation found involving U.S. Patent 8,369,168

I searched for litigation specifically naming U.S. Patent No. 8,369,168 ("Devices and system providing reduced quantity of interconnections," assigned to Micron Technology, Inc.) and found no evidence of any lawsuit, ITC investigation, or PTAB proceeding asserting or challenging this specific patent.

What I searched

• General web search for the patent number and litigation terms.
• Quoted-number searches for "8,369,168" and "8369168".
• Searches aimed at litigation aggregators (Unified Patents portal, CourtListener, PACER/CAFC references).

The only hits for the literal string "8369168" were an unrelated Brazilian state registry filing (a company registration number) and a citation string in an unrelated patent document — neither relates to this patent.

Important caveat on the noise in the results

The searches surfaced extensive Netlist v. Micron and Netlist v. Samsung litigation, but none of the asserted patents are U.S. 8,369,168. The patents in those cases include Nos. 7,619,912; 8,301,833; 8,787,060; 9,318,160; 9,858,215; 10,268,608; 10,489,314; 10,860,506; 10,949,339; 11,016,918; 11,093,417; 11,232,054 — all different patent numbers. I flag this deliberately per the instruction to interpret identifiers literally: do not conflate any of these with 8,369,168.

Context (not litigation, but relevant to why 8,369,168 is quiet)

• Owner: Micron Technology, Inc. (Idaho) — an operating semiconductor manufacturer, not a patent-assertion/NPE entity. Micron's U.S. patent enforcement activity in this period has largely been defensive (declaratory judgment actions and IPR petitions responding to Netlist) rather than affirmative infringement suits asserting its own DRAM patents like the '168.
• Family: 8,369,168 is a divisional of U.S. 8,045,416 (filed Mar. 5, 2008). The family also includes U.S. 8,730,759 and abandoned application US 2014/0254300. Priority date: Mar. 5, 2008.
• Third-party citation (not litigation): Samsung's U.S. 9,082,504 cites the '168 family, and the '168 appears in the "cited by" lists — citation is not an assertion or challenge.

Confidence and limitations

• High confidence that no reported litigation names U.S. 8,369,168. The absence is consistent across multiple query formulations.
• Caveat: I was unable to directly load and query the Unified Patents litigation caselist, PACER, or Docket Navigator APIs within this session; my conclusion rests on web-indexed sources. A definitive negative would require a direct docket search (e.g., Docket Navigator / Lex Machina) filtered on "8,369,168," which would also capture any sealed or unreported docket entries and any district-court case settled before substantial indexing.

Bottom line: Based on the available sources, there is no known litigation involving U.S. Patent 8,369,168 — neither as an asserted patent nor as a patent challenged in an IPR/PGR. If you need a court-record-grade confirmation, I'd recommend running the number directly through Docket Navigator or Lex Machina, since those sources were not fully accessible here.

I'll verify the structured "no proceedings" default against live sources before writing anything.

The first pass surfaced a lot of "’168 patent" noise — that's US 7,643,168 (E-Watch), a different patent. Let me target our number precisely.

No hits yet for our patent. Let me check the sibling/family patents and any litigation assertion, since an IPR would likely name the family.

Proceedings overview

Zero AIA trial proceedings are on file against US 8,369,168 — the USPTO Open Data Portal returns no IPR, PGR, or CBM for this patent, and my live searches surfaced none either; the breakdown is therefore 0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution denials, which leaves a defendant with no PTAB-record invalidity to lean on: all 11 claims stand exactly as they issued, and any defense has to be built from scratch in the district court or in a fresh petition.

---

No proceeding to profile

There is no {PROCEEDING_NUMBER} — {Petitioner} v. Micron Technology, Inc. entry to write for this patent. I am not going to manufacture one. Reproducing the empty canonical list is the finding here.

One trap worth naming explicitly, because it will burn you if you're briefing this fast: searches for "the '168 patent" in a PTAB context return a dense cluster of hits — IPR2015-00407, IPR2015-00414, IPR2015-00543, IPR2015-00611, and an Apple v. E-Watch petition. Those all concern US 7,643,168 (E-Watch, Inc.), an unrelated patent whose last three digits coincide with ours. None of them touch US 8,369,168, and none of the E-Watch outcomes are relevant to Micron's memory-device patent. Do not let a docket search engine conflate them.

What is actually on the record for US 8,369,168 (from the patent text and the ODP family data, not from any contested proceeding):

---

Strategic summary

Claim status. All 11 claims are UNTESTED by any tribunal. Claims 1–6 (the device claims) and 7–11 (the electronic-system claims) have never been through an AIA trial, and no claim has been canceled or amended. Note that claim 1 recites "a controller and address and command buses configured to cooperatively receive a first portion of an address of the second page … while executing commands relating to the first page … the commands including a precharge command, in response to which an open page of memory cells is at least partially closed," and claim 6 frames the invention as the difference portion between the address-signal count and the narrower address bus. Those are the two independent claims to focus on; claims 3, 4, 9, and 10 add the buffering register and the "upper address portion" limitation, which are the features that give an obviousness challenge its best purchase — embedding row-address bits in a PRECHARGE or REFRESH command is the conceptual core, and the specification itself concedes these are "reserved ('res') or 'don't care' fields of existing commands," which is a useful admission for a § 103 theory.

Estoppel landscape. Because no IPR has been instituted or decided, § 315(e)(2) estoppel has never attached to anyone. There is no petitioner, no real party in interest, and no privy carrying a bar into the district court. Every prior-art ground — patents, printed publications, and (in litigation, though not in an IPR) system art and public use — remains fully available to a current defendant. Conversely, nothing has been taken off the table and nothing has been narrowed, so there is no free ride either.

Pattern signals. None to read: no serial petitioning, no defensive aggregator (Unified Patents, RPX, etc.) in the chain, and no PTAB appeal history on either side of this patent. The only downstream citation activity is follow-on patent filings that cite it as background — US 2014/0016421 and US 9,082,504, both Samsung, directed to refresh-period storage — which is a signal of technical relevance, not of contested validity. Micron's litigation posture toward this family has been as a large-entity patent owner paying maintenance fees through the 12th year, not as a party defending it at the Board.

The timing point that matters most. The patent expires 2028-03-05. An IPR petition filed today (2026-09-30) would face a § 314(b) institution decision around 2027-03/04, and a § 316(a)(11) final written decision twelve months after institution — i.e., roughly 2028-03/04, at or past expiration. The economic case for a full IPR is therefore weak, and a defendant's better play is likely a § 315(b)-timed petition only if a litigation is actually served and a stay looks obtainable, coupled with § 102/§ 103 invalidity contentions in the district court that are unconstrained by any Board record.

---

Recommended next steps

1. Do not cite PTAB cancellation of any claim of US 8,369,168. It does not exist. Any brief, demand letter, or client memo that references an IPR on this patent is a fabrication risk — the closest-sounding real proceedings (see the 7,643,168 warning above) are a different patent and a different owner.
2. Verify independently before you rely on the null result. My check was the ODP structured block plus four targeted web searches; I did not have budget to run a complete docket-by-docket sweep of paywalled databases. Confirm at PTAB E2E / PTAB Center by searching the patent number, at USPTO Patent Center for the application's file history, and on CourtListener for any Federal Circuit appeal naming 8,369,168. Also worth a check: ex parte reexamination (a § 302 route with no § 315(b) bar and no estoppel) and any pre-AIA inter partes reexamination filed between 2011 and 2013, which would sit outside an AIA-trials query.
3. If you are defending an assertion: treat the absence of IPRs as a signal, not a shield. This patent has not been asserted widely enough to attract petitioners, which cuts both ways — it means the claims are untested and potentially vulnerable to a well-funded first petition, but also that no art has been publicly vetted, so your § 102/§ 103 search starts from the 24 references already of record rather than from a curated PTAB record. Watch your § 315(b) one-year clock from service of the complaint; if you intend to petition, that deadline drives everything else.
4. If you are the patent owner: the clean IPR record is currently an asset — 11 claims intact, no estoppel, no narrowing amendment history to explain away. Suing on claims 3–4 or 9–10 (the register/upper-address-portion dependents) keeps you on claims with more specific limitations and a harder obviousness story, and preserves the narrower claims if the independents are later challenged.

Bottom line: no PTAB activity on file — a genuinely clean slate, and the only real risk to a defendant here is research contamination from the unrelated E-Watch '168 proceedings.

I'll start by cross-checking the assignment and litigation record before writing anything.

Let me dig into the assignment records and check for any assertion activity.

US 8,369,168 B2 — Ownership & Assignment Reconstruction

Patent: Devices and system providing reduced quantity of interconnections
Application: 13/279,513 (divisional of 12/042,518, now US 8,045,416) · Priority: 2008‑03‑05 · Granted: 2013‑02‑05 · Anticipated expiration: 2028‑03‑05
Source note: The authoritative assignment data below is drawn from the Google Patents legal‑events register for this patent (which mirrors the USPTO assignment records at reel/frame level) plus corroborating USPTO/SEC material. Correspondent names are flagged where they were not exposed on the patent‑side record itself.

---

Inventors

Pattern review: No unusual inventor pattern is observable. There is a single inventor of record on a single corporate‑owned divisional, and no evidence of inventor departure within 12 months of filing. I could not independently confirm Walker's employment history or current whereabouts from the sources available; treat "Micron employee at filing" as highly probable but assignment‑derived rather than document‑confirmed.

There is no evidence of a founder‑inventor‑owned entity, no inventor‑retained rights, and therefore none of the precursor conditions (inventor‑owned shell, delayed assignment, fire‑sale after founder exit) that typically precede a portfolio sale.

---

Original assignee

Micron Technology, Inc. (Boise, Idaho; originally a Delaware corporation, address of record 8000 South Federal Way, Boise, ID 83707).

• Primary line of business: semiconductor memory — DRAM, NAND, HBM, NOR, and the SDRAM architecture that this patent addresses. This is squarely the entity's core field, not an incidental holding.
• Did they ship a product embodying the claims? The claims are directed to an SDRAM device architecture in which a portion of a next‑row address is embedded in a PRECHARGE or REFRESH command and the address bus is narrowed (claims 1–6; the specification's worked example is a 32,768‑row SDRAM with nine external address pins A0/A9 … A8 instead of fifteen, FIGS. 3A/4). Micron is one of the three global DRAM manufacturers and unquestionably ships SDRAM/DRAM parts. Caveat: I found no product documentation, mark, or claim chart tying any specific Micron part number to these claims, so "ships products embodying the claims" is inferred from field and subject matter, not proven on this record.
• Current status: Operating. Public company (NASDAQ: MU) with no bankruptcy history. Micron's own 2025 PTAB filings describe it as the only U.S.‑based memory fabricator, holder of "over 60,000 patents," with an announced $150B U.S. manufacturing program.
• Related corporate entities (important distinction): Micron Semiconductor Products, Inc. (Idaho) appears in this chain, but only as a co‑grantor under the 2018 JPMorgan security agreement — never as an assignee of this patent. Its appearance is an internal corporate‑affiliate structure, not a transfer.

---

Assignment timeline

Recorded chain, oldest to newest. All entries are security‑interest recordings and their releases — there is not a single transfer of title in this patent's post‑issuance history.

• 2013‑01‑16 (grant date) / recorded 2013‑01‑16 — no reel/frame

  • Conveyance: Original grant (not an assignment record)
  • Assignor: n/a — inventors' rights had already been assigned to Micron in the parent application 12/042,518 (filed 2008‑03‑05)
  • Assignee: Micron Technology, Inc.
  • Correspondent: n/a
  • Context: Original assignment at filing — the patent has never left its original operating‑company owner.

• 2016‑04‑26 (executed) / recorded 2016‑05‑12 — Reel 038669/0001

  • Conveyance: Security Interest (patent security agreement / collateral grant)
  • Assignor: Micron Technology, Inc.
  • Assignee: U.S. Bank National Association, as Collateral Agent (Minnesota banking association; address of record 633 West Fifth Street, 24th Floor, Los Angeles, CA 90071)
  • Correspondent: Not exposed in the Google Patents event data for the patent‑side reel. On the parallel trademark security filing for the same April 26, 2016 credit facility (reel 5792/0001, recorded the same day), the correspondent of record is "WSGR, c/o Qui Lu, Senior Paralegal, 650 Page Mill Road, FH2‑1P12, Palo Alto, CA 94304" — i.e., Wilson Sonsini Goodrich & Rosati. Treat this as a strong but unconfirmed cross‑reference, not a patent‑record citation. Either way, this is lender's counsel on a syndicated secured financing, not NPE counsel — a single appearance is not a finding and this is not an ownership correspondent.
  • Context: Securitization — collateral pledge supporting Micron's April 26, 2016 indenture and secured credit facility.

• 2016‑04‑26 (executed) / recorded 2016‑06‑02 — Reel 038954/0001

  • Conveyance: Security Interest (patent security agreement, second, pari passu or junior lien under the same 2016 financing)
  • Assignor: Micron Technology, Inc.
  • Assignee: Morgan Stanley Senior Funding, Inc., as Collateral Agent (Maryland; 1300 Thames Street, 4th Floor, Baltimore, MD 21231)
  • Correspondent: Not exposed on the patent‑side reel. The parallel trademark filing for the same facility (reel 5805/0271, recorded 2016‑06‑02) names Genevieve Dorment, Esq., Simpson Thacher & Bartlett LLP, 425 Lexington Avenue, New York, NY 10017. Again: lender's counsel, syndicated financing — no NPE significance.
  • Context: Securitization — parallel lien in the same 2016 secured financing.

• 2017‑06‑08 (recorded) — Reel 043079/0001

  • Conveyance: Correction (Corrective Assignment to the 038669/0001 U.S. Bank security interest)
  • Assignor: Micron Technology, Inc. (confirms the security interest)
  • Assignee: U.S. Bank National Association, as Collateral Agent
  • Correspondent: not exposed
  • Context: Correction of record — no change in ownership. ⚠️ Data‑quality flag: the recorded description states the correction replaces erroneously filed patent 7,358,718 with 7,358,178. Neither number is this patent. The correction record in this chain does not itself reference 8,369,168, which suggests the Google Patents event set for this patent may be carrying an over‑inclusive family/lien record. This does not create or transfer any ownership interest, but it means the patent‑side lien records should be verified visually at the USPTO before being relied on.

• 2018‑07‑03 (executed) / recorded 2018‑07‑13 — Reel 047540/0001

  • Conveyance: Security Interest (Guarantee and Collateral Agreement, closing date July 3, 2018)
  • Assignors: Micron Technology, Inc. and Micron Semiconductor Products, Inc. (both as Grantors)
  • Assignee: [JPMorgan Chase Bank, N.A., as Collateral Agent](/asserters/jpmorgan-chase-bank-n-a-as-collateral-agent) (Illinois)
  • Correspondent: not exposed in the retrieved data
  • Context: Securitization — replacement/most‑senior secured financing; executed by Micron's CFO Ernest E. Maddock and Micron Semiconductor Products' Steven L. Thorsen, Jr. Micron Technology Texas LLC is expressly carved out as an "Excluded Property Subsidiary," confirming this is a corporate treasury instrument and not a patent‑monetization vehicle.

• 2018‑06‑29 (executed) / recorded 2018‑08‑23 — Reel 047243/0001

  • Conveyance: Release by Secured Party
  • Assignor/Releasing party: U.S. Bank National Association, as Collateral Agent
  • Assignee/Beneficiary: Micron Technology, Inc.
  • Correspondent: on the parallel trademark release (reel 6403/0540) — "WSGR, c/o Qui Lu Flood, Senior Paralegal, One Market, Spear Tower, Suite 3300, San Francisco, CA 94105"
  • Context: Lien release — collateral returned; no ownership change.

• 2019‑07‑31 (executed) / recorded 2019‑10‑09 — Reel 050937/0001

  • Conveyance: Release by Secured Party
  • Releasing party: Morgan Stanley Senior Funding, Inc., as Collateral Agent
  • Beneficiary: Micron Technology, Inc.
  • Correspondent: not exposed
  • Context: Lien release — no ownership change.

• 2019‑07‑31 (executed) / recorded 2019‑11‑12 — Reel 051028/0001

  • Conveyance: Release by Secured Party
  • Releasing party: JPMorgan Chase Bank, N.A., as Collateral Agent
  • Beneficiaries: Micron Technology, Inc. and Micron Semiconductor Products, Inc.
  • Correspondent: not exposed
  • Context: Lien release — no ownership change.

Corroboration that title stayed with Micron: maintenance fees were paid as a large entity at the 8th year (2020‑08‑04) and 12th year (2024‑07‑16). An NPE‑held patent typically continues to be paid as a large entity too, so this is not dispositive on its own — but combined with the absence of any assignment of title, it is consistent with uninterrupted Micron ownership through at least July 2024. Anticipated expiration remains 2028‑03‑05.

If you are looking for an ownership assignment and not finding one: there isn't one. The Assignment Center records for this patent are collateral filings only. That is itself the finding.

---

Timeline diagram

timeline
    title Ownership of US 8369168
    2008 : Filed by Micron Technology
    2011 : Divisional filed as 13279513
    2013 : Patent issued
    2016 : Security interest to US Bank
         : Security interest to Morgan Stanley
    2018 : Security interest to JPMorgan
         : Release by US Bank
    2019 : Release by Morgan Stanley
         : Release by JPMorgan

---

NPE / troll-pattern signals

1. Shell-entity transfer — not present. No assignment of this patent to any entity with an "IP / Patents / Licensing / Holdings / Ventures" suffix, no LLC of any kind, and no transfer at all. The only non‑Micron names in the chain are three nationally chartered banks and one broker‑dealer acting as collateral agents under secured credit facilities (reels 038669/0001, 038954/0001, 047540/0001). Those are lienholders, not owners — and all three liens were released (047243/0001, 050937/0001, 051028/0001).

2. Known asserter in the chain — not present. Micron Technology, Inc. is the original and, on this record, current owner. Neither Micron nor any of the collateral agents matches the referenced NPE lists (Acacia, Marathon, Intellectual Ventures, IPNav, Wi‑LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation Corp, Spangenberg entities). Micron is in fact on the opposite side of that divide: its 2025 PTAB filings expressly frame IPR as a defense "against NPE attacks," naming Palisade and Vervain as adverse asserters. Micron is a repeat IPR petitioner against NPEs, not an asserter through one.

3. Repeat correspondent across the chain — not present, with a caveat. The lender‑side correspondents recur (WSGR c/o Qui Lu on the 2016 U.S. Bank filing and the 2018 release; Genevieve Dorment of Simpson Thacher on the Morgan Stanley filing), but (a) these names come from parallel trademark records at reels 5792/0001, 5805/0271 and 6403/0540, not from confirmed patent‑side correspondents of record, and (b) recurrence here reflects a single syndicated bank financing and its wind‑down, not a lawyer running a chain of shell LLCs. This is the precise pattern the signal is not meant to capture. Marked not present; flagged unclear/unverified as to the literal correspondent fields on the patent‑side reels, which the retrieved data did not expose.

4. Cascading transfers — not present. Zero transfers of title, let alone chained LLC hops. The 2016–2019 entries are one financing's creation, amendment and unwind, all within the same corporate family and all involving the same three institutional lenders.

5. Pre-litigation transfer — not present. I found no infringement action naming US 8,369,168 brought by Micron or anyone else. Without an assertion, there is no transfer to time against it. (Note: search results surfaced unrelated "’168" patents — E‑Watch/Sony, Casale/Topsoe, Micron/Netlist — none of which involve this patent number.)

6. Bankruptcy fire-sale — not present. Micron has no Chapter 7 or 11 history; the security interests at 038669/0001 and 038954/0001 arose from an April 26, 2016 indenture and were voluntarily released in 2018–2019, which is the opposite of a distressed liquidation. This is not a Kodak/Nortel/Polaroid scenario.

7. Privateering — not present. No transfer to a third‑party NPE, no evidence of Micron funding or directing assertion of this patent, and no Patent Progress / EFF / SEC coverage of such a scheme. Micron's known IP posture is defensive aggregation and cross‑licensing across a 60,000‑patent portfolio.

8. Defensive aggregator — not present. The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. It terminates at Micron — an operating company that is a member‑type participant in the defensive ecosystem rather than an assignee of it.

---

Verdict

Insufficient data — for NPE purposes.

The chain never leaves the original operating company: Micron Technology, Inc. is the original assignee and, as of the last recorded event (2024‑07‑16, 12th‑year maintenance fee paid as a large entity), there is no assignment of title in the record at all. Every reel/frame entry — 038669/0001 and 038954/0001 (2016 security interests), 043079/0001 (2017 correction), 047540/0001 (2018 security interest), and the three releases 047243/0001, 050937/0001, 051028/0001 (2018–2019) — is a collateral lien or its discharge, with the three secured parties being U.S. Bank, Morgan Stanley and JPMorgan as collateral agents. Zero of the eight enumerated NPE signals are present. I decline to label this "operating-company assertion" only because I found no assertion — Micron appears to hold this patent defensively and for cross‑licensing, not as a litigation asset.

Verify at: USPTO Patent Assignment Search — https://assignmentcenter.uspto.gov/ (mirror: https://assignment.uspto.gov/patent/index.html) — search 8369168, then confirm the correspondent field on reels 038669/0001, 038954/0001 and 047540/0001, which the Google Patents mirror does not expose. Also open the PEDS/ODP continuity data for application 13/279,513 to confirm no recent (2020–2026) assignment has been recorded upstream of the Google Patents mirror.

Two open items I could not close with high confidence, stated plainly: (1) the correspondent of record on the patent‑side reels for the 2016 and 2018 liens — the WSGR and Simpson Thacher names above come from parallel trademark filings and are offered as leads, not as patent‑record findings; and (2) the 2017‑06‑08 correction at reel 043079/0001, whose text references patents 7,358,718/7,358,178 rather than 8,369,168, which may indicate the Google Patents event set for this patent is over‑inclusive. Neither item affects the ownership conclusion.

I'll search for the specific patent and its cited prior art references.

Let me verify details on the key cited references.

US 8,369,168 B2 — USPTO Prior-Art / Citation Analysis

Identifier confirmed literally: I searched for the exact number 8369168. The results match the authoritative full text supplied: US 8,369,168 B2, "Devices and system providing reduced quantity of interconnections," Robert M. Walker, Micron Technology, Inc., appl. 13/279,513, filed 2011‑10‑24, granted 2013‑02‑05, priority 2008‑03‑05. I did not substitute any similar number. (Search results again surfaced unrelated strings containing "8369168" — e.g., a PubMed supplement index entry and non-patent documents — which I disregard per the literal-ID rule.)

Caveat on sources: I was not able to load USPTO PatentCenter/PAIR or a certified "References Cited" image directly in this session. The prior-art list below is taken from the face-of-patent citations reproduced in the authoritative text (24 U.S. references), cross-checked by live search on the most relevant items (US 6,931,479; US 2008/0106967; US 8,045,416). Where I could only see the bibliographic line from the patent's own citation table, I say so.

---

Important framing note on § 102

The 24 references below are the documents the examiner considered during prosecution. Being listed on the face of the patent does not mean any of them was applied under § 102. In this family the examiner appears to have used them largely as background art and for § 103 obviousness combinations — the independent claims (1, 6, 7) hinge on the specific combination of "first portion of the next page's address" + "embedded in a command relating to the current/open page" + "precharge command." Anticipation under § 102 requires a single reference disclosing every element as arranged in the claim. As analyzed below, no single cited reference appears to meet that bar for independent claims 1, 6, or 7. The entries below therefore identify the closest candidate claims each reference could bear on, with an explicit anticipation confidence.

Also critical: US 8,045,416 B2 (parent) and US 2009/0225623 A1 (its pre-grant publication) are same-family/priority documents, not prior art to the '168 divisional (filing date 2011‑10‑24, priority 2008‑03‑05). They are excluded from the anticipation analysis.

---

Tier 1 — Most relevant cited references

1. US 2008/0106967 A1 — Method and apparatus for communicating command and address signals

• Inventor/Assignee: Jong‑Hoon Oh (Micron Technology)
• Filing date: 2006‑10‑25 · Publication date: 2008‑05‑08
• Flag: marked examiner‑cited in the patent's citation table
• Description (verified via live search): Discloses a memory device with a shared interface in which a portion of the command pins and a portion of the address pins are shared to variably receive command and/or address inputs (Fig. 1–5). Referring to the bus as "command bus"/"address bus" is described as "partially arbitrary." It explicitly frames the problem as the number of input pins required to support command/address combinations and teaches multi‑cycle command/address inputs.
• Potential § 102 relevance:
  • Claims 5 and 11 (address-signal quantity > address-line quantity): the shared-pin/multi-cycle scheme is the closest thing in the art to carrying more address information than dedicated address lines permit. Anticipation confidence for the "narrower-bus" limitation: moderate/low — the reference shares command pins with address pins and reuses pins across cycles, which is a different mechanism from feeding upper row bits of the next page onto address lines during a precharge.
  • Claims 1, 6, 7: Not anticipatory. It does not disclose embedding a portion of the next page's address in a precharge command relating to the current page.

2. US 6,931,479 B2 — Method and apparatus for multi‑functional inputs of a memory device

• Assignee: Micron Technology · Filed: 2003‑03‑04 · Granted: 2005‑08‑16
• Flag: marked examiner‑cited
• Description (verified via live search): Memory device with multi‑functional input terminals. Address terminals carry a first (row) set of address signals; a second portion of the address terminals carries sub‑bank selection signals concurrently with the (column) address signals. The patent expressly addresses that "the number of inputs … has increased significantly" and reuses address terminals for a different function in the same cycle.
• Potential § 102 relevance:
  • Claims 5, 6, 11 (multi‑purpose address lines / narrower bus): this is the strongest single‑reference candidate for the "reuse address terminals to convey extra address information" concept, because it applies concurrent multi‑functional signaling on the same address terminals — structurally the same genus as the '168's A0/A9…A5/A14 sharing. Anticipation confidence: low‑to‑moderate, and only for the bus‑width claims — not for the precharge‑embedding core.
  • Claims 1, 7: Not anticipatory (no precharge/refresh embedding of a next‑page address portion).

3. US 5,627,791 A — Multiple bank memory with auto refresh to specified bank

• Assignee: Micron Technology · Filed: 1996‑02‑16 · Granted: 1997‑05‑06
• Description (from citation record): Multiple‑bank memory in which an auto‑refresh operation is directed to a specified bank — i.e., address information is conveyed in connection with a REFRESH command to select a target.
• Potential § 102 relevance:
  • Claims 2 and 8 (the contemporaneous command may be a refresh command): this is the closest cited art on "use the address field during a refresh command to point at a page/bank." There is a surface conceptual overlap (repurposing address bits active during refresh). Anticipation confidence: low — the '168 requires the referenced address portion to be the address of the next page to be activated and to be buffered for a later activate, which '791 does not show; '791 is about which bank gets refreshed, not about pre‑loading a future row address.
  • Claim 1: Not anticipatory.

4. US 2006/0039204 A1 — Method and apparatus for encoding memory control signals to reduce pin count

• Inventor: Cornelius, William P. · Filed: 2004‑08‑23 · Published: 2006‑02‑23
• Description (from citation record): Encodes memory control signals to reduce pin count.
• Potential § 102 relevance: Background art on the general goal of pin‑count reduction (all claims generally). Anticipation confidence: low — encoding control signals does not disclose embedding a next‑page address portion in a precharge.

5. US 2006/0041713 A1 — Method and system for reducing pin count in an integrated circuit when interfacing to a memory

• Inventor: Gordon, Charles · Filed: 2004‑08‑18 · Published: 2006‑02‑23
• Description (from citation record): Reducing pin count in an IC when interfacing to a memory.
• Potential § 102 relevance: Background art on pin‑count reduction generally (claims 5, 6, 11 theme). Anticipation confidence: low.

---

Tier 2 — Remaining cited references (brief)

The references below are cited primarily as background/obviousness context. Descriptions are as recorded in the patent's own citation table; claim mappings are the closest potential subjects, all with low anticipation confidence unless noted.

(Publication numbers in the table preserve the citation-table formatting; the authoritative text shows the parent‑publication numbers US20040193777A1, US20050002254A1, US20050052910A1, US20050088902A1, US20060039204A1, US20060041713A1, US20060245270A1, US20080025127A1, US20080106967A1.)

---

Bottom-line assessment

1. Closest cited reference overall: US 2008/0106967 A1 (Oh, Micron) — because it directly targets command/address pin reduction via shared pins and multi‑cycle transfers. Second-closest: US 6,931,479 B2 — because it reuses address terminals for a concurrent second function, i.e., the genus of the '168's A0/A9…A5/A14 sharing.
2. Best § 102 candidate for the bus‑width claims (5, 6, 11): US 6,931,479 B2 and/or US 2008/0106967 A1 — but each would still require the precharge/refresh‑embedded next‑page address element, which neither clearly shows. No clean § 102 anticipation.
3. Best § 102 candidate for the refresh‑related dependent claims (2, 8): US 5,627,791 A (address‑active auto‑refresh to a specified bank) — conceptually closer, but it addresses refresh target rather than pre‑loading the next row address; still not anticipatory.
4. For independent claims 1, 6, 7: I found no single cited reference that anticipates. The likely posture is that these claims were allowed over § 103 combinations of the pin‑reduction/bus‑sharing art (Oh, '479, 6363446/7, 6478231) with the precharge/refresh command‑field art ('791, 6771553, 2005/0002254).
5. Not prior art: US 8,045,416 B2 (parent) and US 2009/0225623 A1 (its publication) — same family, same priority; expressly excluded.

---

Uncertainty / limitations

• I could not pull the examiner's actual rejection record (e.g., which references were applied under § 102 vs. § 103, and the specific claim mappings). My § 102 mappings are analytical inferences from the references' disclosed subject matter, not quotations from Office Actions.
• Descriptions for the Tier‑2 references are drawn from the patent's own citation table unless a live source was verified (only items 1, 2 and the family documents were independently re‑verified here). Titles/assignees are reproduced as recorded.
• For a court‑record‑grade anticipation chart, the examiner's Notice of Allowance/Examiner's Reasons for Allowance and any applicant IDS should be pulled from USPTO PatentCenter for appl. 13/279,513 — a resource I could not query directly in this session.
• Per your standing instruction, I did not auto‑correct any identifier; all numbers and dates are as they appear in the supplied authoritative text or the cited sources.

I'll ground this analysis by pulling the actual content of the examiner-cited references and the closest family-level art before building the § 103 combinations.

Strong material on the examiner-cited art. Now let me pull the closest reference — Oh's "communicating command and address signals" — plus the pin-count-reduction references.

Let me check two more references that could supply the missing "next-row address pipelined with the prior page's command" teaching.

Obviousness Analysis — US 8,369,168 B2 under 35 U.S.C. § 103

Scope note: This is a technical/analyst assessment, not a legal opinion. It is built on (a) the authoritative patent text supplied, and (b) live-retrieved content for the key references from the "Prior Art" section of the patent page. Where I could only retrieve a reference's title/abstract and not its full disclosure, I say so rather than asserting a mapping. I flag below one issue (the § 102(e)/§ 103(c) status of the Oh reference) that materially affects the strength of the rejection.

---

1. Governing framework

Critically, because the effective date is 2008-03-05, a reference must have a qualifying date before that to be usable. Two of the cited references are post-dated publications and therefore rest on § 102(e) rather than § 102(a)/(b) — see the qualification table.

---

2. Reference qualification and probative value

New information not in the prior sections: the four references marked with an asterisk on the page — US 2005/0002254, US 6,931,479, US 2006/0245270, and US 2008/0106967 — are flagged there as cited by examiner. That is a meaningful signal: the examiner was already working with (i) the shared command/address pin concept, (ii) multi-functional address terminals, and (iii) refresh control. It is consistent with the issued claims having been narrowed to require a precharge command as the carrier of the next-page address portion — an inference, not a verified file-history fact.

§ 103(c) caveat (important). Oh's US 2008/0106967 is § 102(e) art only. Pre-AIA § 103(c) disqualifies § 102(e)/(f) art from use in a § 103 rejection if, at the time the invention was made, the reference and the application were commonly owned or subject to a common obligation of assignment. The '168 was Micron-owned. I could not verify Oh's assignee: the '168's own page lists it without assignee, while a CN counterpart of the same title/priority (CN 101169772 A) names Qimonda North America Corp. If Oh's application was Micron-owned (or under a common obligation), the § 103(c) exception would knock out the primary reference and the whole rejection built on it would collapse. This must be verified from the assignment records for the Oh application before relying on it. If Oh is disqualified, the rejection must be rebuilt on US 6,931,479 + Laberge + Gordon (see Combination 3), which is weaker but not untenable.

---

3. Claim 1 — element mapping

Claim 1's remaining gap — an express teaching that the particular address portion carried alongside the precharge is the address of the page next to be activated — is not squarely disclosed by any single reference I retrieved. That is the crux of the § 103 case and is addressed by the motivation analysis in § 5.

---

4. Claim 6 and Claim 7 — mapping

Claim 6 ("difference portion" = first quantity of address signals − second quantity of address lines):

This claim is the most exposed. US 6,931,479 does not merely suggest the concept — it recites the arithmetic:

"the plurality of address input terminals … comprises m address input terminals, the first set of input signals comprises m input signals, the second set of input signals comprises n input signals, and the selection signal comprises less than or equal to (m−n) signals." — US 6,931,479, claim 25

The '168's "difference portion" is the same quantity expressed as a bus-width deficit rather than as a pin-shared selection field. Combine with Oh's express purpose ("a lower pin count may be achieved relative to a configuration in which only dedicated command pins and dedicated address pins are provided") and claim 6 reads on the combination almost element-for-element, with the precharge limitation supplied by Laberge.

Claim 7 (electronic system: controller + memory device embedding a portion of the next page's address in a current-page command):

Oh's claim 14 is a system claim in the alternative: "An apparatus, comprising: a memory controller configured to assert a plurality of address/command combinations each comprising a plurality of address inputs and command inputs; and a memory device, comprising: a command bus interface … an address bus interface …". That is the system-level architecture the '168's claim 7 recites, minus the "precharge" hook (Laberge).

---

5. The combinations and the motivation to combine

Combination 1 (primary): Oh + Laberge + US 6,931,479

Formulation: Claim 1 is unpatentable over Oh in view of Laberge and US 6,931,479.

Rationale:

1. Same field of endeavor. All three are synchronous DRAM devices/controllers and their interfaces (Oh's illustrative device is explicitly "synchronous dynamic random access memory (SDRAM) … single data rate SDRAM, double data rate (DDR) SDRAM or any subsequent generation … DDR-III SDRAM"; US 6,931,479 is directed to DDR SDRAM and states its principles apply to SDRAMs, SLDRAMs and RDRAMs).
2. Same problem, recognized in the art. Oh: "One of the design considerations in manufacturing memory devices is the number of input pins required… The greater the number of pins required, the larger and the more costly the resulting memory device is." Gordon: "High pin count … can result in forcing designs into larger and more expensive packages." The '168's own background frames the identical conflict ("an increase in the quantity of interconnection pins … creates a conflict with design motivations of further circuit miniaturization and integration").
3. The enabling premise is admitted/known. Laberge teaches that PRECHARGE is a general command not tied to a memory location. This is corroborated by ordinary JEDEC practice and — decisively for § 103 — by the applicant's own admission in the specification: the address bits are "a 'don't care' (illustrated as reserved 'res' bits) during the PRECHARGE command" and during REFRESH. An applicant's admission about the state of the art is usable as prior art.
4. The mechanism is known. Oh supplies the mechanism of routing address information over pins during cycles in which a command is being asserted, with the route selected by the decoded command type. US 6,931,479 supplies the mechanism of a subset of address terminals carrying different information concurrently with address signals, and of an address field of width (m−n).
5. Predictable result / KSR. The combination uses the same conventional building blocks the '168 uses (command decoder, address register, upper-address register, row-address multiplexer, mode register, decoders) and changes nothing in the principle of operation of the SDRAM — it merely re-routes signals that both references already route. Where "a design need or market pressure to solve a problem" exists and "there are a finite number of identified, predictable solutions," KSR makes the combination obvious.

Combination 2: Oh + US 6,931,479 + US 2005/0002254 (for claims 2/8)

For the refresh variant, the examiner-cited Epson reference (refresh control and internal voltage generation) supplies the refresh command as the other command whose address field is unused, mirroring the '168's FIG. 6 embodiment. US 6,327,209 (multi-stage refresh control) and US 5,627,791 (auto-refresh to a specified bank) are additional Micron refresh references in the same citation list.

Combination 3 (fallback if Oh is § 103(c)-disqualified): US 6,931,479 + Laberge + Gordon

Gordon (US 2006/0041713 / US 7,689,763) supplies both the problem statement and an SDRAM-specific time-division-multiplexing solution in which "address and bank select lines … are connected to data pins" and pre-charge/activate commands are issued over a shared bus ("at time 632, pre-charge command 632 is transmitted … The location of pre-charge command is bank address 634"). Combined with US 6,931,479's (m−n) teaching and Laberge's precharge-is-location-independent teaching, all elements of claims 1, 6 and 7 are supplied, though the "next-page address embedded in the current page's precharge" sequencing is then reached purely by KSR-type reasoning rather than by an express pointer. This combination is weaker and more vulnerable to a "no reasonable expectation of success / different problem" rebuttal.

---

6. Dependent claims

Claims 3/9's "register" limitation is the easiest for the patent owner to distinguish in principle, but it is a routine buffering/staging limitation with abundant art (command buffers and buffered command-address buses, both Micron, both in the citation list) — classic obviousness territory.

---

7. Is there a § 102 anticipation case?

No clean one, on the references I could verify. No single reference retrieved teaches receiving a first portion of the next page's address while executing a precharge relating to the current page. Oh teaches shared/interchangeable pins per command, not the next-page-address pipelining. US 6,931,479 teaches concurrent non-address information on address terminals, but for sub-bank selection, not for a pending row address. Laberge teaches the opposite structural choice (a dedicated auxiliary bus for precharge). So the '168 survives § 102 on this record, and the attack must be § 103.

---

8. Weaknesses, rebuttal exposure, and what to verify

1. The sequencing gap is real. None of the references I could retrieve expressly discloses latching the upper address bits of the page to be opened next during the precharge cycle of the page being closed. A patent owner will argue that this is the "genuine inventive contribution" and that no reference recognizes the problem the '168 solves (eliminating activation latency while shrinking the bus). Counter: the specification itself concedes the goal is met "without significantly impacting the performance," i.e., no unexpected performance benefit — which undermines any secondary-considerations argument and supports the KSR "predictable use" rationale.
2. Secondary considerations are absent on the record. I found no evidence of unexpected results, industry praise, licensing, or copying tied to this patent, and no litigation (consistent with the earlier litigation section). There is therefore no objective indicia to rebut the prima facie case.
3. § 103(c) as to Oh — must be resolved. See § 2. This is the single highest-leverage verification item.
4. Unverified mappings — do not overstate. I could not confirm the disclosure of US 2006/0245270 A1 (Random cache read), US 2008/0025127 A1 (Kanda et al., Fujitsu — I confirmed the inventor name and that it concerns layer/bank/row addressing across stacked memory chips, but its abstract as quoted in later art is about a multi-chip addressing scheme, not pin reduction), US 2006/0039204 A1, or US 2004/0193777 A1 beyond their titles/abstracts. I have deliberately not used them as element disclosures in the claim charts above. A filing-grade analysis requires full-text review of each.
5. Claim-drafting quirk (carried forward from the earlier analysis). Claims 1 and 6 recite "a controller" as a component of the memory device. This does not help the patent owner: every candidate device reference (Oh, US 6,931,479) already places a command decoder/control logic and mode register on the memory die, so the internal-"controller" reading is met, while claim 7's external-controller reading is met by Oh's claim 14 system claim.
6. Reference-date caution. Oh is § 102(e)-only. Any rejection built on it must plead the § 102(e) basis and confirm the application was published (it was — 2008-05-08) and that its disclosure supports the relied-upon passages, which the examiner apparently considered satisfied by citing it.

---

9. Bottom line

Recommended primary rejection: Claims 1–11 rejected under pre-AIA § 103(a) as unpatentable over Oh (US 2008/0106967) in view of Laberge (US 2005/0088902) and US 6,931,479, with US 2005/0002254 and US 6,192,446 added against claims 2, 3, 8 and 9.

Must-verify before filing: (1) the assignee/§ 103(c) status of the Oh application; (2) full-text disclosure of US 2006/0245270, US 2008/0025127, US 2006/0039204, US 2004/0193777; (3) the '168's prosecution history to confirm what, if anything, was actually overcome by reciting "precharge command."

Sources: https://patents.google.com/patent/US8369168/en · https://patents.google.com/patent/US6931479 · https://patents.justia.com/patent/[6931479](/patent/6931479) · https://patents.google.com/patent/[US7405992](/patent/US7405992) · https://patents.justia.com/patent/20080106967 · https://patents.google.com/patent/US20060041713 · http://patentimages.storage.googleapis.com/81/8a/11/b88b6c2250646d/US7689763.pdf · https://trade.patenthub.cn/cpc/patent-[180190](/patent/180190)-JP4034268B2-3a2d97027bf9a6b4356a219730a381d7.html · https://patents.justia.com/patent/[8045416](/patent/8045416)