Patent 8169005

Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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The USPTO database shows the following as prior art cited in US Patent 8,169,005:

U.S. Patent Documents:

  • US4551905A

    • Full Citation: US Patent 4,551,905
    • Publication/Filing Date: Filed: Dec 9, 1982 / Published: Nov 12, 1985
    • Brief Description: Describes the fabrication of metal lines for semiconductor devices.
    • Potential Anticipation (35 U.S.C. § 102): This patent generally relates to metallization techniques. While US8169005B2 utilizes metal for its electrodes and field plates, US4551905A would likely not anticipate specific claims related to the multiple field plate architecture, GaN HEMT structure, or the performance metrics of US8169005B2. It might be relevant to the general manufacturing steps of forming conductive elements, which is a fundamental aspect of semiconductor fabrication, but does not teach the specific inventive features of 8169005.

  • US4947232A

    • Full Citation: US Patent 4,947,232
    • Publication/Filing Date: Filed: Mar 22, 1980 / Published: Aug 7, 1990
    • Brief Description: Discloses a high voltage MOS transistor.
    • Potential Anticipation (35 U.S.C. § 102): This patent describes a high voltage MOS transistor. While relevant to high voltage transistors, it describes MOS technology, which is distinct from the HEMT (High Electron Mobility Transistor) structure, especially GaN-based HEMTs with field plates, as claimed in US8169005B2. Therefore, it is unlikely to anticipate the specific structural or material claims (e.g., Claims 1, 7, 15, 25) of US8169005B2.

  • US5192987A

    • Full Citation: US Patent 5,192,987
    • Publication/Filing Date: Filed: May 17, 1991 / Published: Mar 9, 1993
    • Brief Description: Discloses high electron mobility transistors with GaN/AlxGa1-xN heterojunctions. This patent is explicitly mentioned in the background of US8169005B2 as describing GaN/AlGaN based HEMTs grown on a buffer and a substrate.
    • Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant as it describes GaN/AlGaN based HEMTs. It likely anticipates the basic HEMT structure with GaN/AlGaN heterojunctions (e.g., elements of Claim 7 and 15 related to semiconductor layers, buffer layer, and barrier layer) as described in US8169005B2. However, it does not appear to teach the specific multiple field plate arrangement with specific connections and performance characteristics as claimed in US8169005B2 (e.g., Claim 1, 7, 15, 25 and their dependencies on field plate configurations). The innovation of US8169005B2 lies in its particular multi-field plate design for enhanced voltage blocking and reduced on-resistance.

  • US5196359A

    • Full Citation: US Patent 5,196,359
    • Publication/Filing Date: Filed: Jun 30, 1988 / Published: Mar 23, 1993
    • Brief Description: Describes a method of forming a heterostructure field effect transistor.
    • Potential Anticipation (35 U.S.C. § 102): This patent could potentially anticipate methods of fabricating heterostructure FETs, which generally applies to HEMTs. However, similar to US5192987A, it is unlikely to disclose the specific multiple field plate structure and connections, or the performance metrics that are central to the claims of US8169005B2.

  • US5393990A

    • Full Citation: US Patent 5,393,990
    • Publication/Filing Date: Filed: Apr 4, 1989 / Published: Feb 28, 1995
    • Brief Description: Discloses a HEMT structure.
    • Potential Anticipation (35 U.S.C. § 102): This patent discloses a general HEMT structure. It likely provides background on HEMT devices but is unlikely to teach the specific multiple field plate configuration and its associated benefits in GaN technology, as detailed in the independent claims of US8169005B2.

  • US5399886A

    • Full Citation: US Patent 5,399,886
    • Publication/Filing Date: Filed: Jan 27, 1993 / Published: Mar 21, 1995
    • Brief Description: Discloses a heterojunction FET with a high potential barrier layer and gate structure.
    • Potential Anticipation (35 U.S.C. § 102): This patent describes a heterojunction FET with a high potential barrier and gate structure. While relevant to the basic components of a HEMT, it is unlikely to anticipate the unique multi-field plate arrangement and electrical connections that distinguish US8169005B2, particularly regarding the source-connected outermost field plate.

  • US5569937A

    • Full Citation: US Patent 5,569,937
    • Publication/Filing Date: Filed: Aug 28, 1995 / Published: Oct 29, 1996
    • Brief Description: Describes a high breakdown voltage silicon carbide transistor.
    • Potential Anticipation (35 U.S.C. § 102): This patent focuses on silicon carbide transistors for high breakdown voltage. While it shares the goal of high breakdown voltage, the material system (SiC vs. GaN) and the specific device structure (multiple field plates) are different from US8169005B2. Therefore, it would likely not anticipate the specific GaN HEMT claims of US8169005B2.

  • US5885860A

    • Full Citation: US Patent 5,885,860
    • Publication/Filing Date: Filed: Jun 30, 1995 / Published: Mar 23, 1999
    • Brief Description: Describes a silicon carbide transistor and method.
    • Potential Anticipation (35 U.S.C. § 102): Similar to US5569937A, this patent focuses on SiC transistors. While SiC is a wide bandgap semiconductor, the inventive features of US8169005B2 are specific to GaN HEMTs and their multiple field plate configurations, which are not directly taught in this SiC-focused patent.

  • US5929467A

    • Full Citation: US Patent 5,929,467
    • Publication/Filing Date: Filed: Dec 4, 1996 / Published: Jul 27, 1999
    • Brief Description: Discloses a field effect transistor with nitride compound.
    • Potential Anticipation (35 U.S.C. § 102): This patent is relevant due to its focus on nitride compound FETs. It could potentially anticipate aspects of using Group III nitride materials (e.g., in claims 10, 19, 20). However, the specific multiple field plate architecture with distinct connections (gate-connected field plates and a source-connected outermost field plate) as detailed in Claims 1, 7, 15, and 25 of US8169005B2 would need to be thoroughly evaluated against its disclosure. Without further details on its field plate structure, it's unlikely to fully anticipate the specific field plate arrangement.

  • US6004881A

    • Full Citation: US Patent 6,004,881
    • Publication/Filing Date: Filed: Apr 24, 1997 / Published: Dec 21, 1999
    • Brief Description: Describes digital wet etching of semiconductor materials.
    • Potential Anticipation (35 U.S.C. § 102): This patent is related to a fabrication technique (etching). While such techniques are used in manufacturing the transistors of US8169005B2, it does not disclose the device structure or its functional characteristics, and thus would not anticipate any of the claims of US8169005B2.

  • WO0004587A2

    • Full Citation: WO 2000/004587 A2
    • Publication/Filing Date: Filed: Jun 12, 1998 / Published: Jan 27, 2000
    • Brief Description: Describes nitride based transistors on semi-insulating silicon carbide substrates. This corresponds to U.S. Pat. No. 6,316,793, which is commonly assigned and explicitly incorporated by reference into US8169005B2.
    • Potential Anticipation (35 U.S.C. § 102): As the U.S. counterpart (US6316793B1) is explicitly referenced and described as commonly assigned, this publication is highly relevant. It likely anticipates the basic GaN HEMT structure on SiC substrates, including the buffer and barrier layers (elements of Claims 7, 8, 10, 16, 17, 18, 19). However, US8169005B2 states that its improvements address "limitations for high performance applications in power switching" of prior art like those demonstrating field plates. Therefore, while it provides the foundation for GaN HEMTs, it likely does not disclose the specific multiple field plate arrangement and the associated performance metrics (blocking voltage, on-resistance) that are key to US8169005B2's claims (e.g., Claims 1, 7, 15, 25).

  • US6033948A

    • Full Citation: US Patent 6,033,948
    • Publication/Filing Date: Filed: Dec 2, 1995 / Published: Mar 7, 2000
    • Brief Description: Describes a method of making high voltage metal oxide silicon field effect transistor.
    • Potential Anticipation (35 U.S.C. § 102): Similar to US4947232A, this patent focuses on high voltage MOS FETs. The technology and materials (MOS vs. GaN HEMT) are different from US8169005B2, and therefore it is unlikely to anticipate its claims.

  • US6046464A

    • Full Citation: US Patent 6,046,464
    • Publication/Filing Date: Filed: Mar 29, 1995 / Published: Apr 4, 2000
    • Brief Description: Describes integrated heterostructures of group III-V nitride semiconductor materials including epitaxial ohmic contact comprising multiple quantum well.
    • Potential Anticipation (35 U.S.C. § 102): This patent is relevant to Group III-V nitride heterostructures and ohmic contacts, which are fundamental to GaN HEMTs. It could potentially anticipate aspects of the semiconductor layers and ohmic contacts (e.g., Claim 7, 8, 15, 17). However, the emphasis of US8169005B2 is on the multiple field plate design for improved voltage and on-resistance, which would need to be explicitly present in this reference to anticipate the core claims.

  • US6064082A

    • Full Citation: US Patent 6,064,082
    • Publication/Filing Date: Filed: May 30, 1997 / Published: May 16, 2000
    • Brief Description: Discloses a heterojunction field effect transistor.
    • Potential Anticipation (35 U.S.C. § 102): This patent discloses a general heterojunction FET. Without specific details on field plate structures and their configurations as claimed in US8169005B2, it would likely not anticipate the inventive aspects related to the multiple field plate arrangement.

  • US6100571A

    • Full Citation: US Patent 6,100,571
    • Publication/Filing Date: Filed: Jun 16, 1998 / Published: Aug 8, 2000
    • Brief Description: Discloses a FET having non-overlapping field control electrode between gate and drain.
    • Potential Anticipation (35 U.S.C. § 102): This patent describes a FET with a field control electrode (which can be considered a type of field plate) between the gate and drain. This is directly relevant to the concept of field plates for electric field management. This patent could potentially anticipate elements of US8169005B2 relating to the general use of a field plate between the gate and drain (e.g., the second field plate 32 in FIG. 2). However, US8169005B2 specifies a multiple field plate arrangement including a gate-connected first field plate, a gate-connected second field plate, and a source-connected third field plate (Claims 1, 7, 15, 25). The "non-overlapping" nature and the absence of a source-connected outermost field plate in US6100571A would likely differentiate it from fully anticipating the claims of US8169005B2, especially Claim 1 and its dependencies.

Foreign Patent Documents:

  • EP0069429A2

    • Full Citation: EP 0 069 429 A2
    • Publication/Filing Date: Filed: Jul 6, 1981 / Published: Jan 12, 1983
    • Brief Description: Discloses an insulated gate field effect transistor.
    • Potential Anticipation (35 U.S.C. § 102): This patent describes an insulated gate FET. Similar to the MOS FET patents, the underlying technology (IGFET vs. GaN HEMT) and the specific multi-field plate architecture of US8169005B2 are likely not disclosed, thus limiting its ability to anticipate the claims.

  • JPH0521793A

    • Full Citation: JP H05-21793 A
    • Publication/Filing Date: Filed: Jul 9, 1991 / Published: Jan 29, 1993
    • Brief Description: Describes a semiconductor device and manufacturing method thereof.
    • Potential Anticipation (35 U.S.C. § 102): Without specific details on the device structure, especially concerning multiple field plates in a GaN HEMT, it is unlikely to anticipate the specific claims of US8169005B2.

  • JPH07283140A

    • Full Citation: JP H07-283140 A
    • Publication/Filing Date: Filed: Apr 5, 1994 / Published: Oct 27, 1995
    • Brief Description: Describes an active atom supply control method.
    • Potential Anticipation (35 U.S.C. § 102): This patent relates to a manufacturing method. It does not disclose the device structure or its functional characteristics, and thus would not anticipate any of the claims of US8169005B2.

  • EP0792028A2

    • Full Citation: EP 0 792 028 A2
    • Publication/Filing Date: Filed: Feb 21, 1996 / Published: Aug 27, 1997
    • Brief Description: Discloses a solid-state antenna switch and field-effect transistor.
    • Potential Anticipation (35 U.S.C. § 102): This patent describes a FET for an antenna switch. While it involves FETs, without a detailed field plate configuration matching US8169005B2's multi-field plate arrangement, it is unlikely to anticipate the specific claims related to voltage blocking and on-resistance.

  • JPH09307097A

    • Full Citation: JP H09-307097 A
    • Publication/Filing Date: Filed: May 16, 1996 / Published: Nov 28, 1997
    • Brief Description: Describes a semiconductor device.
    • Potential Anticipation (35 U.S.C. § 102): Without specific details on the device structure, especially concerning multiple field plates in a GaN HEMT, it is unlikely to anticipate the specific claims of US8169005B2.

  • JPH09321307A

    • Full Citation: JP H09-321307 A
    • Publication/Filing Date: Filed: May 29, 1996 / Published: Dec 12, 1997
    • Brief Description: Describes a semiconductor device.
    • Potential Anticipation (35 U.S.C. § 102): Without specific details on the device structure, especially concerning multiple field plates in a GaN HEMT, it is unlikely to anticipate the specific claims of US8169005B2.

  • JPH10223901A

    • Full Citation: JP H10-223901 A
    • Publication/Filing Date: Filed: Dec 4, 1996 / Published: Aug 21, 1998
    • Brief Description: Describes a field effect transistor and method of manufacturing the same.
    • Potential Anticipation (35 U.S.C. § 102): This patent describes a general FET and its manufacturing. Similar to other general FET references, it would need to explicitly teach the specific multiple field plate structure and its connections in a GaN HEMT to anticipate the claims of US8169005B2.

  • JPH11261052A

    • Full Citation: JP H11-261052 A
    • Publication/Filing Date: Filed: Mar 9, 1998 / Published: Sep 24, 1999
    • Brief Description: Describes a high mobility transistor.
    • Potential Anticipation (35 U.S.C. § 102): This patent describes a high mobility transistor. While HEMTs are high mobility transistors, without the specific multi-field plate configuration, material system (GaN), and performance characteristics detailed in US8169005B2, it is unlikely to anticipate the claims.

  • JP2000252458A

    • Full Citation: JP 2000-252458 A
    • Publication/Filing Date: Filed: Sep 9, 1999 / Published: Sep 14, 2000
    • Brief Description: Describes a field effect transistor.
    • Potential Anticipation (35 U.S.C. § 102): This patent describes a general FET. Similar to other general FET references, it would need to explicitly teach the specific multiple field plate structure and its connections in a GaN HEMT to anticipate the claims of US8169005B2.

Non-Patent Literature (NPL) Documents:

  • B. Gelmont, K. Kim and M. Shur, Monte Carlo Simulation of Electron Transport in Gallium Nitride, J. Appl. Phys. 74, (1993), pp. 1818-1821.

    • Brief Description: This article discusses electron transport in Gallium Nitride.
    • Potential Anticipation (35 U.S.C. § 102): This NPL discusses the fundamental physics of GaN electron transport. It provides background on the properties of GaN, which is a material used in US8169005B2. However, it does not describe a device structure, and thus would not anticipate any of the claims of US8169005B2.

  • R. Gaska, et al., Electron Transport in AlGaN—GaN Heterostructures Grown on 6H—SiC Substrates, Appl. Phys. Lett. 72, (1998), pp. 707-709.

    • Brief Description: This article discusses electron transport in AlGaN-GaN heterostructures grown on SiC substrates.
    • Potential Anticipation (35 U.S.C. § 102): This NPL is highly relevant as it describes AlGaN/GaN heterostructures on SiC, which forms the basis for the HEMT described in US8169005B2 (e.g., in Claim 7 and 15 related to semiconductor layers). It supports the understanding of 2DEG formation and electron mobility in such systems. However, similar to the patent US5192987A, it is unlikely to describe the specific multiple field plate architecture and its unique connections for high voltage/low on-resistance performance that are central to the claims of US8169005B2.

  • Y. F. Wu et al., GaN-Based FETs for Microwave Power Amplification, IEICE Trans. Electron. E-82-C, (1999). pp. 1895-1905.

    • Brief Description: This article discusses GaN-based FETs for microwave power amplification, including power density results. Y. F. Wu is also an inventor on US8169005B2.
    • Potential Anticipation (35 U.S.C. § 102): This NPL, co-authored by an inventor, describes GaN-based FETs and their power performance. While highly relevant to the general field of GaN FETs for power applications, the key question for anticipation under 35 U.S.C. § 102 is whether it discloses the specific multiple field plate arrangement (first, second, and source-connected third field plates) and the precise performance metrics (blocking voltage and on-resistance combinations) that are claimed in US8169005B2. The patent abstract explicitly refers to field plates being used to enhance performance, implying that the specific combination of field plates in US8169005B2 is an advancement over prior art. This NPL might anticipate broader aspects of GaN FETs for power, but a detailed comparison of the field plate structure is necessary to determine if it fully anticipates claims like Claim 1, 7, 15, or 25. Given the "grace period" provisions for an inventor's own publication (35 U.S.C. 102(b)(1)(A)), if this publication falls within one year of the patent's effective filing date, it might not be considered prior art against the inventor's own claims. However, its presence as a citation suggests it's considered relevant background.

  • Gaska, et al., High-Temperature Performance of AlGaN/GaN HFETs on SiC Substrates, IEEE Electron Device Letters, 18, (1997), pp. 492-494.

    • Brief Description: This article discusses the high-temperature performance of AlGaN/GaN HFETs on SiC substrates.
    • Potential Anticipation (35 U.S.C. § 102): This NPL details AlGaN/GaN HFETs on SiC, providing further background on the device platform of US8169005B2. However, it is unlikely to teach the specific multiple field plate configuration that provides the claimed high blocking voltages and low on-resistances in US8169005B2.

  • Wu, et al. “High Al-content AlGaN/GaN HEMTs With Very High Performance”, IEDM-1999 Digest, pp. 925-927, Washington D.C., December 1999.

    • Brief Description: This article discusses high Al-content AlGaN/GaN HEMTs with very high performance. Y. F. Wu is also an inventor on US8169005B2.
    • Potential Anticipation (35 U.S.C. § 102): Similar to the other NPL by Wu et al., this reference describes high-performance AlGaN/GaN HEMTs. While contributing to the general knowledge of GaN HEMT performance, it needs careful examination to see if it explicitly discloses the specific multiple field plate design and resulting performance characteristics claimed in US8169005B2 (Claims 1, 7, 15, 25). The potential applicability of the grace period (35 U.S.C. 102(b)(1)(A)) would also be a factor here.

  • Lu, et al. “AlGaN/GaN HEMTs on SiC With Over 100 GHz ft and Low Microwave Noise”, IEEE Transactions on Electron Devices, Vol. 48, No. 3, March 2001, pp. 581-585.

    • Brief Description: This article discusses AlGaN/GaN HEMTs on SiC with high gain-bandwidth product (fT) and low microwave noise.
    • Potential Anticipation (35 U.S.C. § 102): This NPL focuses on high-frequency performance (fT) and low noise. While it pertains to AlGaN/GaN HEMTs on SiC, its focus is different from the high blocking voltage and low on-resistance for power switching applications that are central to US8169005B2. Therefore, it is unlikely to anticipate the specific field plate structures designed for these power switching characteristics.

  • Wu et al., “Bias-dependent Performance of High-Power AlGaN/GaN HEMTs”, IEDM-2001, Washington D.C., Dec. 2-6, 2001.

    • Brief Description: This article discusses bias-dependent performance of high-power AlGaN/GaN HEMTs, reporting high power densities. Y. F. Wu is also an inventor on US8169005B2.
    • Potential Anticipation (35 U.S.C. § 102): This NPL, again by an inventor, discusses high-power AlGaN/GaN HEMTs. The question of anticipation would depend on whether it details the specific multiple field plate configuration and the combinations of blocking voltage and on-resistance described in the claims of US8169005B2 (Claims 1, 7, 15, 25). The grace period consideration is also applicable here.

  • Wu et al., High Al-Content AlGaN/GaN MOSFETs for Ultrahigh Performance, IEEE Electron Device Letters 19, (1998), pp. 50-53.

    • Brief Description: This article discusses high Al-content AlGaN/GaN MOSFETs for ultrahigh performance. Y. F. Wu is also an inventor on US8169005B2.
    • Potential Anticipation (35 U.S.C. § 102): This NPL, by an inventor, focuses on AlGaN/GaN MOSFETs. While using GaN, the device type (MOSFET vs. HEMT) is fundamentally different, and the claims of US8169005B2 are specific to HEMTs. Therefore, it is unlikely to anticipate the HEMT-specific claims of US8169005B2.

  • Zhang et al., IEEE Electron Device Letters, Vol. 21, pp. 421-423 (September 2000).

    • Brief Description: This article discusses overlapping gate structures, or field plates, used to modify the electric field and enhance performance of GaN-based HEMTs at microwave frequencies. This NPL is explicitly mentioned in the background of US8169005B2.
    • Potential Anticipation (35 U.S.C. § 102): This NPL is highly relevant as it describes the use of field plates in GaN-based HEMTs. It likely anticipates the general concept of using field plates to modify electric fields and enhance performance in GaN HEMTs (e.g., portions of Claims 1, 7, and 15 related to field plates over the active region). However, US8169005B2 describes a specific multiple field plate arrangement with distinct connections (some gate-connected, one source-connected outermost field plate) for achieving particular high voltage and low on-resistance figures. Whether Zhang et al. teaches this exact combination and the associated performance thresholds needs careful comparison. It likely serves as a general prior art reference for field plates but might not fully anticipate the specific inventive combination of US8169005B2.

  • Karmalkar et al., IEEE Trans. Electron Devices, Vol. 48, pp. 1515-1521 (March 2001).

    • Brief Description: This article presents simulations for field plate structures, predicting enhanced breakdown voltages. This NPL is explicitly mentioned in the background of US8169005B2.
    • Potential Anticipation (35 U.S.C. § 102): This NPL discusses the simulated benefits of field plates, specifically increased breakdown voltage. This is highly relevant to the objectives of US8169005B2. It might anticipate the concept of using field plates to improve breakdown voltage. However, similar to Zhang et al., whether it discloses the specific multiple field plate arrangement and the precise performance combinations for blocking voltage and on-resistance as claimed in US8169005B2 is crucial for anticipation of the independent claims.

  • Ando et al., IEEE Electron Device Letters, Vol. 24, pp. 289-291 (May 2003).

    • Brief Description: This article demonstrates 10.3 W output power at 2 GHz using a 1 mm wide device on a SiC substrate, utilizing a similar structure with smaller gate dimensions. This NPL is explicitly mentioned in the background of US8169005B2.
    • Potential Anticipation (35 U.S.C. § 102): This NPL demonstrates the performance of GaN HEMTs with field plates. While it uses a "similar structure" to previous field plate designs, the critical question for anticipation is whether it explicitly discloses the specific multiple field plate arrangement (including the source-connected outermost field plate) and the combination of high blocking voltage and low on-resistance recited in the independent claims of US8169005B2. Its focus on output power at 2 GHz suggests a different performance optimization than the high voltage blocking of US8169005B2.

  • Chini et al., IEEE Electron Device Letters, Vol. 25, No. 5, pp. 229-231 (May 2004).

    • Brief Description: This article implements a new variation of the field plate design with further reduced gate dimensions, achieving 12 W/mm at 4 GHz. This NPL is explicitly mentioned in the background of US8169005B2.
    • Potential Anticipation (35 U.S.C. § 102): This NPL introduces a "new variation of the field plate design" and reports power density results. Like Ando et al., the key for anticipation of US8169005B2's claims would be a direct disclosure of the specific multiple field plate arrangement and the achieved blocking voltage/on-resistance combinations. The different performance metrics and gate dimensions suggest a different design compared to the specific configuration in US8169005B2.

  • Y-F Wu et al, IEEE Electron Device Letters, Vol. 25, No. 3, pp. 117-119 (March 2004).

    • Brief Description: This article reports GaN based HEMTs with field plates boosting power density to greater than 30 W/mm at frequencies up to 8 GHz. Y-F Wu is an inventor on US8169005B2. This NPL is explicitly mentioned in the background of US8169005B2 as demonstrating boosted power density.
    • Potential Anticipation (35 U.S.C. § 102): This NPL, by an inventor, is highly relevant as it describes GaN HEMTs with field plates achieving high power density. This reference, along with the other "Wu et al." NPLs, represents the state of the art in GaN HEMTs with field plates prior to the patent's priority date. For anticipation of US8169005B2's claims (Claims 1, 7, 15, 25), this reference would need to specifically disclose the combination of the first and second gate-connected field plates and the source-connected third field plate, and the resulting high blocking voltage and low on-resistance performance as claimed. The patent itself suggests that its multiple field plate transistor provides improvements over existing field plate designs. The grace period for an inventor's own work (35 U.S.C. 102(b)(1)(A)) would also need to be considered.

Summary of Most Relevant Prior Art for Anticipation:

The most relevant prior art documents for anticipation under 35 U.S.C. § 102 would be those that detail GaN HEMT structures with field plates, especially those that discuss improving breakdown voltage or reducing on-resistance.

  • US5192987A (High electron mobility transistor with GaN/Alx Ga1-x N heterojunctions) and WO0004587A2 (Nitride based transistors on semi-insulating silicon carbide substrates / US6316793B1) are foundational for the GaN HEMT device itself and would likely anticipate the basic semiconductor layer structures (Claims 7, 8, 10, 16, 17, 18, 19).
  • US6100571A (FET having non-overlapping field control electrode between gate and drain) is relevant to the general concept of field control electrodes between the gate and drain.
  • Zhang et al. (2000), Karmalkar et al. (2001), Ando et al. (2003), Chini et al. (2004), and Y-F Wu et al. (2004) (NPLs) are highly relevant as they explicitly discuss the use of field plates in GaN-based HEMTs to modify electric fields, enhance performance, and predict/achieve increased breakdown voltages and power densities.

The core inventive step of US8169005B2 appears to be the specific arrangement of multiple field plates, including both gate-connected field plates and an outermost source-connected field plate, to achieve particular high blocking voltage and low on-resistance combinations for power switching applications. While the cited prior art introduces elements of GaN HEMTs and the general use of field plates, a detailed analysis would be required to determine if any single reference, or combination of references (for obviousness under 35 U.S.C. § 103), fully teaches or renders obvious this precise combination of structural features and the claimed performance metrics. The patent itself states that prior art approaches "have limitations for high performance applications in power switching," implying that the specific configuration of US8169005B2 addresses these limitations.

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