Obviousness — US Patent 8169005

Obviousness Analysis of US Patent 8169005 under 35 U.S.C. § 103

A patent claim is obvious if "the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art" (35 U.S.C. § 103). This analysis considers the scope and content of the prior art, the differences between the prior art and the claims, the level of ordinary skill in the pertinent art, and any secondary considerations of nonobviousness (which are not available in the provided text).

The person having ordinary skill in the art (PHOSITA) for US8169005 would be a semiconductor device engineer with expertise in GaN High Electron Mobility Transistor (HEMT) technology, particularly as applied to power electronics design and fabrication. The relevant time for assessing obviousness is before the patent's priority date of November 21, 2006.

Prior Art Landscape

The "Description" section of US8169005 identifies several pieces of prior art crucial to understanding the state of the art before the invention:

GaN HEMT Structures: Patents such as U.S. Pat. Nos. 6,316,793, 5,192,987, and 5,296,395 establish the foundational components of AlGaN/GaN HEMTs, including substrates (e.g., SiC), buffer layers (e.g., GaN), and barrier layers (e.g., AlGaN) that define the active two-dimensional electron gas (2DEG) region.
Field Plates in GaN HEMTs: The application of field plates to GaN HEMTs for performance enhancement was a known technique.
- Zhang et al., IEEE Electron Device Letters (September 2000): Taught the use of "overlapping gate structures, or field plates, ... to modify the electric field and thereby enhance the performance of GaN-based HEMTs at microwave frequencies."
- Karmalkar et al., IEEE Trans. Electron Devices (August 2001): Simulations predicted "up to five times enhancement in breakdown voltages" using field plate structures.
- Ando et al. (May 2003), Chini et al. (May 2004), and Y-F Wu et al. (March 2004): Demonstrated practical achievements in power output and power density in GaN HEMTs through the use of field plates.
- US Patent Application Publication Nos. 20050051796 and 20050051800, and International Application Publication No. WO/2005/024909: Explicitly disclose "Transistors with field plates and methods of fabricating such transistors," indicating well-established knowledge of field plate implementation in GaN HEMTs by 2005.
Recessed Gates: US Patent Application Publication No. 20060019435, titled "Methods of Fabricating Nitride-Based Transistors with a Cap Layer and a Recessed Gate," directly teaches the fabrication of recessed gates in nitride-based transistors.

The core problem addressed by US8169005 is achieving higher blocking voltages and lower on-resistances for power switching applications, building upon existing field plate technology. The patent highlights that while prior art field plates boosted power density, they had "limitations for high performance applications in power switching."

Obviousness Analysis of Independent Claims

Claim 1

Claim Language: "A transistor device, comprising: an active region; a source; a drain; a gate structure electrically connected to said active region; a plurality of field plates disposed over said active region; a plurality of insulating spacer layers, a first of said spacer layers interposed between a first of said field plates and said active region, others of said spacer layers disposed on said first field plate; wherein at least one field plate is electrically connected to said gate structure, said first of said field plates is integral to said gate and extends on said first spacer layer toward said source, and at least one field plate is connected to said source."

Differences from Prior Art: The primary distinction in Claim 1 is the specific multi-field-plate configuration: a first field plate integral to the gate extending towards the source, and importantly, "at least one field plate is connected to said source." While field plates connected to the gate were known, the deliberate incorporation of a source-connected field plate within a multiple field plate architecture is a key element.

Combination and Motivation: A PHOSITA would be motivated to combine the general knowledge of GaN HEMTs with field plates (as taught by US Patent Application Publication Nos. 20050051796, 20050051800, or WO/2005/024909) with the understanding of the performance trade-offs associated with purely gate-connected field plates. The patent itself provides explicit motivation for connecting a field plate to the source: "By having a field plate electrically connected to the source electrode, the reduced gain and instability resulting from gate connected field plates is reduced. When arranged according to the present invention, the shielding effect of a source-connected field plate can reduce capacitance between the gate and the drain (C gd ), which enhances input-output isolation." A PHOSITA seeking to mitigate issues like reduced gain, instability, or high Cgd in field-plated HEMTs would find it obvious to add or modify a field plate to be electrically connected to the source to achieve this described shielding effect and improve input-output isolation. This combination addresses a recognized problem in the field using known components with a predictable result.

Claim 7

Differences from Prior Art: The core distinctions of Claim 7 are the gate structure comprising a "contact portion and an overlay portion", where the contact portion is "recessed in said first spacer layer such that said contact portion contacts said semiconductor layers", and the overlay portion resides on the first spacer layer.

Combination and Motivation: A PHOSITA would be motivated to combine the known technology of field-plated GaN HEMTs (e.g., from US Patent Application Publication Nos. 20050051796, 20050051800, or WO/2005/024909) with the teachings of recessed gates in nitride-based transistors, as explicitly described in US Patent Application Publication No. 20060019435 ("Methods of Fabricating Nitride-Based Transistors with a Cap Layer and a Recessed Gate"). The "overlay portion" on the first spacer layer is a characteristic feature of a T-gate structure, which was a known design choice in HEMT technology to reduce gate resistance and improve high-frequency performance. Integrating a recessed gate (for threshold voltage control and reduced leakage) into a field-plated HEMT (for enhanced breakdown voltage) would be an obvious design optimization for a PHOSITA seeking to improve overall transistor characteristics. The patent itself notes that a HEMT embodiment "may include a gate that is partially recessed in the barrier layer."

Claim 15

Claim Language: "A transistor device, comprising: a plurality of semiconductor layers including an active region; a source; a drain; a gate structure electrically connected to said active region; a plurality of field plates on said active region; a plurality of insulating spacer layers, a first of said spacer layers interposed between a first of said field plates and said active region, others of said spacer layers on said first field plate; wherein said first spacer layer comprises an epitaxial material, said first of said field plates is integral to said gate and extends on said first spacer layer toward said source."

Differences from Prior Art: The central distinguishing feature of Claim 15 is that the "first spacer layer comprises an epitaxial material."

Combination and Motivation: A PHOSITA would be motivated to combine the established architecture of field-plated GaN HEMTs with insulating spacer layers (e.g., from US Patent Application Publication Nos. 20050051796, 20050051800, or WO/2005/024909) with the fundamental knowledge and common practice of epitaxial growth for Group III nitride layers in HEMT fabrication (e.g., buffer and barrier layers as detailed in U.S. Pat. Nos. 5,210,051; 5,393,993; 5,523,589; and 5,592,501). The patent explicitly provides the motivation for this combination: "When the spacer layers are formed before device metallization, the layers can be an epitaxial material... After epitaxial growth of the barrier layer 16, the spacer layers 26 and 28 can be grown using the same epitaxial growth method." This indicates a clear engineering motivation to simplify the fabrication process, leverage existing epitaxial growth capabilities for nitride materials, and ensure material compatibility and quality, particularly when the spacer layers are formed prior to metallization.

Claim 25

Claim Language: "A transistor device, comprising: a substrate; a plurality of semiconductor layers on said substrate; a source; a drain; a gate structure electrically connected to said semiconductor layers, said gate comprising a contact portion and an overlay portion; a plurality of field plates disposed over said active region; a plurality of insulating spacer layers, a first of said spacer layers interposed between said overlay portion and said semiconductor layers, others of said spacer layers disposed over said overlay portion and interspersed between others of said field plates; wherein said contact portion of said gate is recessed in said first spacer layer such that said contact portion contacts said semiconductor layers, wherein said overlay portion is on said first spacer layer opposite said plurality of semiconductor layers, wherein said gate overlay portion extends a distance on said first spacer layer toward said source on one side and extends a distance on said first spacer layer toward said drain on the opposite side, wherein an outermost of said field plates at least partially overlaps said gate and extends a distance toward said drain, and wherein said gate overlay portion extends a greater distance toward said source than toward said drain."

Differences from Prior Art: This claim combines features from Claim 7 (recessed gate, overlay portion) and Claim 1 (multi-field-plate arrangement, including a source-connected outermost field plate) with specific dimensional optimizations. The key distinguishing feature is that the "gate overlay portion extends a greater distance toward said source than toward said drain."

Combination and Motivation: This claim represents a combination of the features found in Claim 7 (recessed gate, gate overlay portion, by combining US20060019435 with general field plate HEMTs) and the multi-field-plate arrangement described in the patent's own detailed description (e.g., field plate 30 connected to the gate extending toward the source, field plate 32 connected to the gate extending toward the drain, and the outermost field plate 36 connected to the source extending toward the drain). A PHOSITA designing multi-field-plate GaN HEMTs would routinely optimize the dimensions and placement of various field plates to achieve desired performance characteristics, such as high breakdown voltage, low on-resistance, and reduced Cgd. The patent explicitly aims for "high blocking voltages... while simultaneously exhibiting on resistances of 7.0 mΩ-cm 2 or lower." Given the motivation to reduce Cgd using source-connected field plates (as identified in the analysis of Claim 1), and the general goal of optimizing electric field distribution, a PHOSITA would be motivated to experiment with the relative lengths of the gate-connected field plate extensions. Determining that a greater extension towards the source for the gate-connected field plate(s) (i.e., the "gate overlay portion") yields a better balance of performance parameters (e.g., Cgd, breakdown, and resistance) would be a matter of routine optimization and not necessarily inventive. The placement of the outermost field plate to overlap the gate and extend towards the drain is also consistent with established principles for managing the drain-side electric field to enhance breakdown voltage.