Obviousness

Obviousness Analysis under 35 U.S.C. § 103 for US Patent 8064202

As of April 26, 2026, this analysis evaluates the obviousness of US Patent 8064202 ("Sandwich structure with double-sided cooling and EMI shielding") under 35 U.S.C. § 103, considering combinations of prior art references cited within the patent.

Legal Standard for Obviousness (35 U.S.C. § 103)

Under 35 U.S.C. § 103, a patent may not be obtained "if the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains." The Supreme Court, in KSR International Co. v. Teleflex Inc. (2007), articulated several rationales for finding an invention obvious, including:

1. Combining prior art elements according to known methods to yield predictable results.
2. Simple substitution of one known element for another to obtain predictable results.
3. Use of a known technique to improve similar devices (methods, or products) in the same way.
4. Obvious to try choices when there are a finite number of identified, predictable solutions.
5. Known problems with known solutions in one field leading to obvious adaptations in another.
6. Design choice or market demand driving a predictable variation.

For an obviousness challenge, it must be shown that a person having ordinary skill in the art (POSITA) would have had a motivation or reason to combine the prior art references to achieve the claimed invention, and that the combination would have yielded a predictable result.

Most Relevant Prior Art References

Based on the "Prior Art" section, the most relevant references for an obviousness analysis are:

• US7880282B2 ("Semiconductor package with integrated heatsink and electromagnetic shield"): This patent explicitly discloses a semiconductor package that integrates both a heatsink for thermal management and an electromagnetic shield, directly addressing the core functions of the top lead frame in US8064202.
• US20080054439A1 ("Power electronic package having two substrates with multiple semiconductor chips and electronic components"): This patent application describes a power electronic package incorporating two substrates, multiple semiconductor chips, and other electronic components, often arranged for optimized performance and heat dissipation. This aligns with the "sandwich structure" concept of US8064202.
• US7646093B2 ("Thermal management of dies on a secondary side of a package"): This patent focuses on thermal management techniques for dies located on a secondary side of a semiconductor package, directly supporting the concept of "double-sided cooling."

Obviousness Combination and Rationale

A person of ordinary skill in the art (POSITA) in the field of electronic packaging, particularly for power modules and mini-modules, confronted with the limitations of existing wire bonding technology (e.g., high power loss, limited heat dissipation, parasitic inductance causing EMI noise) as described in US8064202's background, would have been motivated to combine elements from the identified prior art.

The objective would be to develop a compact module with enhanced thermal dissipation from multiple sides and effective EMI shielding, while also providing robust current paths.

Combination: US7880282B2 in view of US20080054439A1 and US7646093B2.

Motivation for Combination:

1. Need for combined thermal and EMI solution: US8064202 explicitly states the problem of both limited heat dissipation and EMI noise in mini-modules. A POSITA would logically look for solutions that address both issues simultaneously. US7880282B2 directly provides a "semiconductor package with integrated heatsink and electromagnetic shield," offering a known solution for both thermal management and EMI shielding.
2. Desire for enhanced, double-sided cooling: The prior art recognized the importance of thermal management (e.g., US6442026B2, US6724631B2, US7129577B2, US20050224955A1, US7345885B2). Specifically, US7646093B2 teaches "thermal management of dies on a secondary side of a package," directly suggesting the benefit and techniques for dissipating heat from multiple surfaces of a component or package. This would motivate a POSITA to incorporate a heatsink/shield on one side (from US7880282B2) and utilize the substrate on the other side for cooling, leading to a "double-sided cooling" approach.
3. Use of multi-substrate/sandwich structure for component integration: US20080054439A1 describes a "power electronic package having two substrates with multiple semiconductor chips and electronic components." This provides the structural framework for a "sandwich structure" where components can be mounted on one substrate, and another substrate or heat-dissipating element can form the opposing side. It would be an obvious design choice to arrange the integrated heatsink/EMI shield (from US7880282B2) as the "top lead frame" and one of the substrates (from US20080054439A1) as the "bottom structure" in such a stacked configuration.
4. Known methods for electrical and thermal connections: Once the stacked structure is conceived, connecting the internal components to both the top heatsink/shield and the bottom substrate, and connecting the top heatsink/shield to the bottom substrate for current paths (e.g., ground), would involve conventional means like solder, metal pins, or conductive epoxies, which are well-known in the art and even described in US8064202 itself. These are predictable solutions for establishing electrical and thermal communication in semiconductor packages.

Obviousness of Independent Claims

Claim 1 (Apparatus Claim)

Claim 1 recites a sandwich structure for mini-modules. The combination of US7880282B2, US20080054439A1, and US7646093B2 would render Claim 1 obvious:

• "a top lead frame for thermal cooling, EMI shielding and current carrying, wherein said top lead frame has a top surface and a bottom surface;": US7880282B2 explicitly teaches a "semiconductor package with integrated heatsink and electromagnetic shield." A POSITA would adopt this heatsink and shield to serve as the "top lead frame" for thermal cooling and EMI shielding. As metal structures, such heatsinks/shields are inherently conductive and commonly used for current carrying, especially as ground planes, making the current-carrying aspect obvious.
• "a bottom structure for thermal cooling, current carrying and circuit controlling, wherein said bottom structure has a top surface and a bottom surface;": US20080054439A1 discloses a "power electronic package having two substrates," one of which would serve as the "bottom structure." Substrates, like PCBs, are well-known for thermal cooling, current carrying, and circuit control.
• "internal components, wherein said internal components comprise at least a first set of one or more components, further wherein a first side of each of said first set of one or more components is mounted on said top surface of said bottom structure;": US20080054439A1 explicitly mentions "multiple semiconductor chips and electronic components" within the package and on substrates, covering the mounting of internal components on the bottom structure. This is a standard practice in semiconductor packaging.
• "a first set of one or more connecting structures, each of said first set of one or more connecting structures for connecting each of said first set of one or more components with said bottom surface of said top lead frame;": With the motivation for double-sided cooling (from US7646093B2), a POSITA would find it obvious to connect components on the bottom substrate to the top heatsink/shield (lead frame) for enhanced thermal and electrical performance. Such connections (e.g., metal pins, solder bumps, conductive paste) are conventional means for establishing thermal and electrical paths in stacked packages.
• "a second set of one or more connecting structures connected between said bottom surface of said top lead frame and said top surface of said bottom structure for providing one or more current paths for said internal components.": In a multi-substrate package (US20080054439A1) where the top layer also functions as a conductive lead frame/shield (US7880282B2), it would be an obvious engineering choice to implement connecting structures (e.g., metal pins, solder columns, conductive vias) between the top lead frame and the bottom structure to provide necessary current paths, such as ground, for the internal components. This connection provides predictable electrical functionality.

Therefore, the combination of US7880282B2, US20080054439A1, and US7646093B2 would render the apparatus of Claim 1 obvious to a POSITA.

Claim 11 (Method Claim)

Claim 11 outlines a method for cooling mini-modules, shielding EMI, and carrying currents. The steps of this method are the logical manufacturing steps to construct the apparatus described in Claim 1, which has been shown to be obvious.

• "mounting a first set of one or more components on a top surface of a bottom structure, wherein said bottom structure is configured for thermal cooling, current carrying and circuit controlling;": This is a conventional step for assembling electronic packages, taught by US20080054439A1 and widely known in the art.
• "connecting a first side of each of a first set of one or more connecting structures with a top lead frame, wherein said top lead frame is configured for thermal cooling, EMI shielding and current carrying;": Given the goal of double-sided cooling (US7646093B2) and using a top lead frame for thermal and EMI functions (US7880282B2), it would be an obvious step to connect components to this top lead frame.
• "connecting a first side of each of a second set of one or more connecting structures with a bottom surface of said top lead frame, wherein said second set of one or more connecting structures are configured to provide one or more current paths for said mini-modules;": Establishing current paths between the top lead frame (US7880282B2) and other parts of the module, especially in a multi-substrate context (US20080054439A1), is a predictable engineering step using known connecting structures.
• "connecting a second side of each of a first set of one or more connecting structures with each of said first set of one or more components; and": This completes the connection from the components to the top lead frame for thermal and electrical purposes, a conventional and predictable step.
• "connecting a second side of each of said second set of one or more connecting structures with said top surface of said bottom structure.": This completes the current path connection between the top lead frame and the bottom structure, also a conventional and predictable step in constructing such a module.

The method steps are the predictable result of combining the structural elements from the prior art to achieve the desired improvements in cooling and EMI shielding in a compact module. The techniques for performing these connections are standard in the art.

Therefore, the combination of US7880282B2, US20080054439A1, and US7646093B2 would render the method of Claim 11 obvious to a POSITA.