US 7760733

A detailed analysis of U.S. Patent 7,760,733 reveals a technology focused on enhancing network efficiency by offloading packet filtering tasks to the network interface card (NIC), a hardware component. This approach is designed to reduce the processing load on a host computer's main processor.

Patent Number: US 7,760,733 B1

Title: Filtering ingress packets in network interface circuitry

Assignee: Chelsio Communications, Inc.

Inventors: Asgeir Thor Eiriksson, Chris Yuhong Mao

Filing Date: October 13, 2005

Issue Date: July 20, 2010

Abstract: The patent describes a method for managing data transfer between a peer application and a host computer through network interface circuitry. This circuitry, often a NIC, can offload data processing from the host for specific protocols. The core of the invention lies in applying filtering rules to incoming data based on its characteristics before it is passed to the host. When multiple filtering rules could apply, the system is designed to automatically determine the appropriate rule to use.

Plain-Language Overview of Independent Claims:

The independent claims of a patent define the core of the invention in the broadest terms. Here is a simplified explanation of each independent claim in US 7,760,733:

• Independent Claim 1: This claim outlines a method for network interface hardware to prioritize how it handles incoming data. The hardware can either "filter" the data (e.g., block or modify it) or perform "protocol processing" for connections that have been offloaded from the main computer to the network card for faster handling. The system uses a predefined order to decide which action takes precedence, with the offloaded protocol processing being the higher priority.

• Independent Claim 9: This claim focuses on a method for network interface hardware that is already handling offloaded connections. When new data arrives, the hardware first checks if it belongs to one of these offloaded connections. If so, it processes it accordingly. If the data does not belong to an offloaded connection, the hardware then looks for a matching filtering rule and applies the one with the highest priority based on a predetermined order.

• Independent Claim 12: This claim describes the physical network interface circuitry itself. It specifies that the hardware is built with the capability to receive data and determine the highest priority action to take—either protocol processing for an offloaded connection or filtering for all other data. A key aspect of the circuitry is its ability to selectively prevent data from ever reaching the host computer if a filtering rule dictates it should be blocked.

• Independent Claim 18: This claim is largely similar to claim 1, detailing a method for network interface hardware to process incoming data by choosing a "highest priority" action from a list that includes filtering and offloaded protocol processing. The decision is made by lookup circuitry that automatically gives preference to protocol processing for offloaded connections over the application of filtering rules.

CAFC Litigation:

A thorough search of the U.S. Court of Appeals for the Federal Circuit (CAFC) dockets for the year 2026 reveals no pending or decided cases specifically involving US Patent 7,760,733. Further investigation into litigation involving the assignee, Chelsio Communications, Inc., in the same timeframe also did not yield any results pertinent to this patent. Therefore, as of the current date, there is no indication of recent appellate-level litigation concerning this patent.

A search for litigation involving US Patent 7,760,733 was conducted using several resources, including Unified Patents, PACER, and CAFC dockets. As of April 26, 2026, no known litigation cases specifically naming US Patent 7,760,733 as the patent in question were found. The previously generated section regarding CAFC litigation, which states there is no indication of recent appellate-level litigation concerning this patent, remains consistent with these findings.

Proceedings overview

There are no AIA trial proceedings on file for US Patent 7,760,733 in the USPTO Open Data Portal. A comprehensive web search also did not reveal any active or concluded PTAB proceedings. Therefore, the patent currently has no PTAB activity on file, which means all claims remain untested by an AIA trial.

Strategic summary

As of the current date, all claims of US 7,760,733 are UNTESTED by any AIA trial proceeding. There are no canceled or sustained claims through PTAB review. This means there is no estoppel landscape from prior PTAB decisions that would bar a potential petitioner from raising any ground of unpatentability under 35 U.S.C. §§ 102, 103, or 112. The absence of PTAB activity could indicate that the patent has not been heavily asserted in litigation or that prior challenges have not materialized into formal AIA trials. Chelsio Communications, Inc. is an active technology company in high-performance networking and storage solutions, and holds several patents.

Recommended next steps

If facing an assertion of US 7,760,733, a potential defendant has a clear path to pursue an AIA trial (Inter Partes Review, Post-Grant Review, or Covered Business Method review, depending on eligibility) without being constrained by prior PTAB decisions. The absence of previous challenges means all prior art grounds under 35 U.S.C. §§ 102 and 103, and invalidity grounds under 35 U.S.C. § 112, are potentially available. There are no active proceedings or upcoming trial-stage milestones to monitor.

Inventors

• Asgeir Thor Eiriksson: Chelsio Communications Inc.
• Chris Yuhong Mao: Chelsio Communications Inc.

Both inventors were employed by Chelsio Communications Inc. at the time of filing. There is no unusual pattern of departure within 12 months of filing discernible from the provided information.

Original assignee

Chelsio Communications, Inc.
Chelsio Communications, Inc. is the entity named on the issued patent. They primarily develop and market high-performance Ethernet adapters for servers, storage, and embedded applications, embodying the claims in their products. As of the current date, Chelsio Communications, Inc. appears to be an operating company, as indicated by their continuous ownership of the patent and its use as collateral for ongoing financing.

Assignment timeline

• 2005-10-13 (executed) / recorded 2005-10-13 — Reel 017257/0090
  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: ERIKISSON, ASGEIR THOR; MAO, CHRIS YUHONG
  • Assignee: CHELSIO COMMUNICATIONS, INC.
  • Correspondent: BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN, LLP
  • Context: Original assignment of inventorship rights to the company.
• 2013-05-09 (executed) / recorded 2013-05-13 — Reel 030232/0330
  • Conveyance: SECURITY AGREEMENT
  • Assignor: CHELSIO COMMUNICATIONS, INC.
  • Assignee: EAST WEST BANK
  • Correspondent: SHEPPARD MULLIN RICHTER & HAMPTON LLP, 333 SOUTH HOPE STREET 43RD FLOOR, LOS ANGELES, CA 90071. This correspondent firm recurs in this chain.
  • Context: Patent used as collateral for a loan.
• 2014-10-21 (executed) / recorded 2014-10-24 — Reel 032549/0256
  • Conveyance: RELEASE
  • Assignor: EAST WEST BANK
  • Assignee: CHELSIO COMMUNICATIONS, INC.
  • Correspondent: SHEPPARD MULLIN RICHTER & HAMPTON LLP, 333 SOUTH HOPE STREET, 43RD FLOOR LOS ANGELES, CA 90071. This correspondent firm recurs in this chain.
  • Context: Release of security interest by East West Bank.
• 2014-10-21 (executed) / recorded 2014-10-24 — Reel 032549/0259
  • Conveyance: SECURITY AGREEMENT
  • Assignor: CHELSIO COMMUNICATIONS, INC.
  • Assignee: SILICON VALLEY BANK
  • Correspondent: COOLEY LLP, 3175 HANOVER STREET PALO ALTO, CA 94304-1130. This correspondent firm recurs in this chain.
  • Context: New security interest granted to Silicon Valley Bank.
• 2016-07-15 (executed) / recorded 2016-07-21 — Reel 036325/0747
  • Conveyance: RELEASE
  • Assignor: EAST WEST BANK
  • Assignee: CHELSIO COMMUNICATIONS, INC.
  • Correspondent: SHEPPARD MULLIN RICHTER & HAMPTON LLP, 333 SOUTH HOPE STREET 43RD FLOOR, LOS ANGELES, CA 90071. This correspondent firm recurs in this chain.
  • Context: Second release of security interest by East West Bank.
• 2016-07-29 (executed) / recorded 2016-08-01 — Reel 036398/0048
  • Conveyance: SECURITY AGREEMENT
  • Assignor: CHELSIO COMMUNICATIONS, INC.
  • Assignee: NOVIRIAN CAPITAL, LLC
  • Correspondent: O'MELVENY & MYERS LLP, 400 SOUTH HOPE STREET, 18TH FLOOR LOS ANGELES, CA 90071. This correspondent firm recurs in this chain.
  • Context: New security interest granted to Novirian Capital, LLC.
• 2017-04-25 (executed) / recorded 2017-04-26 — Reel 038030/0620
  • Conveyance: RELEASE
  • Assignor: NOVIRIAN CAPITAL, LLC
  • Assignee: CHELSIO COMMUNICATIONS, INC.
  • Correspondent: O'MELVENY & MYERS LLP, 400 SOUTH HOPE STREET, 18TH FLOOR LOS ANGELES, CA 90071. This correspondent firm recurs in this chain.
  • Context: Release of security interest by Novirian Capital, LLC.
• 2019-08-14 (executed) / recorded 2019-08-16 — Reel 047814/0396
  • Conveyance: SECURITY AGREEMENT
  • Assignor: CHELSIO COMMUNICATIONS, INC.
  • Assignee: WESTERN ALLIANCE BANK, AN ARIZONA CORPORATION
  • Correspondent: COOLEY LLP, 3175 HANOVER STREET PALO ALTO, CA 94304-1130. This correspondent firm recurs in this chain.
  • Context: New security interest granted to Western Alliance Bank.
• 2019-08-15 (executed) / recorded 2019-08-19 — Reel 050050/0396
  • Conveyance: CORRECTIVE ASSIGNMENT
  • Assignor: CHELSIO COMMUNICATIONS, INC.
  • Assignee: WESTERN ALLIANCE BANK, AN ARIZONA CORPORATION
  • Correspondent: COOLEY LLP, 3175 HANOVER STREET PALO ALTO, CA 94304-1130. This correspondent firm recurs in this chain.
  • Context: Corrective assignment to a prior security agreement.
• 2025-12-18 (executed) / recorded 2025-12-19 — Reel 061483/0321
  • Conveyance: RELEASE
  • Assignor: WESTERN ALLIANCE BANK, AN ARIZONA CORPORATION
  • Assignee: CHELSIO COMMUNICATIONS, INC.
  • Correspondent: COOLEY LLP, 3175 HANOVER STREET PALO ALTO, CA 94304-1130. This correspondent firm recurs in this chain.
  • Context: Release of security interest by Western Alliance Bank.

Timeline diagram

timeline
    title Ownership of US 7760733
    2005 : Inventors assign to Chelsio
    2010 : Patent issued
    2013 : Sec Agmt to East West Bank
    2014 : East West Bank releases
         : Sec Agmt to Silicon Valley Bank
    2016 : East West Bank releases
         : Sec Agmt to Novirian Capital
    2017 : Novirian Capital releases
    2019 : Sec Agmt to Western Alliance Bank
         : Corrective Assignment
    2025 : Western Alliance Bank releases

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The patent has consistently been held by Chelsio Communications, Inc., an operating company. All recorded transfers are security interests to financial institutions, not transfers of ownership to licensing-only entities.
2. Known asserter in the chain — Not present. None of the listed assignees (Chelsio Communications, Inc., East West Bank, Silicon Valley Bank, Novirian Capital, LLC, Western Alliance Bank, an Arizona Corporation) are known patent asserters or NPEs.
3. Repeat correspondent across the chain — Present.
   • SHEPPARD MULLIN RICHTER & HAMPTON LLP appears on Reel 030232/0330, 032549/0256, and 036325/0747.
   • COOLEY LLP appears on Reel 032549/0259, 047814/0396, 050050/0396, and 061483/0321.
   • O'MELVENY & MYERS LLP appears on Reel 036398/0048 and 038030/0620.
     While multiple correspondent firms recur, they are associated with the financial institutions in security interest transactions, which is typical for such financing arrangements and does not indicate an NPE pattern in this context.
4. Cascading transfers — Not present. Although there are multiple transactions, they are all security interests and releases, not transfers of ownership between chained LLCs. Chelsio Communications, Inc. has retained ownership throughout the recorded history.
5. Pre-litigation transfer — Not present. The previous litigation summary indicates no known litigation cases involving this patent.
6. Bankruptcy fire-sale — Not present. There is no indication that Chelsio Communications, Inc. has filed for bankruptcy, and the transfers are for securing financing.
7. Privateering — Unclear. There is no evidence in the assignment records or provided context to suggest privateering.
8. Defensive aggregator (anti-NPE) — Not present. The patent is held by an operating company, not a defensive aggregator.

Verdict

Insufficient data
There are no recorded transfers of ownership for US 7760733 to any entity other than the original assignee, Chelsio Communications, Inc. The extensive assignment history consists entirely of security agreements and their subsequent releases with various financial institutions, indicating the patent has been used as collateral for corporate financing rather than being transferred for assertion. Therefore, there are no signals to categorize it as an NPE asset.

USPTO Assignment Center Search for US7760733

To identify the most relevant prior art for US Patent 7,760,733, I will analyze the patent citations listed within the patent itself, as this directly indicates what the examiners and inventors considered relevant during prosecution.

Prior Art Analysis for US Patent 7,760,733

The following are the most relevant prior art references cited in US Patent 7,760,733. For each reference, a brief description and potential anticipation of claims under 35 U.S.C. § 102 are provided. Anticipation under 35 U.S.C. § 102 requires that all elements of a claimed invention are disclosed in a single prior art reference.

Patent Citations:

• US 6,226,680 B1

  • Full Citation: US 6,226,680 B1, "Intelligent network interface system method for protocol processing," issued May 1, 2001.
  • Publication/Filing Date: October 14, 1997 (Filing Date).
  • Brief Description: This patent describes an intelligent network interface system and method for offloading protocol processing from a host computer. It focuses on accelerating communication by handling protocols like TCP/IP on the network interface device itself, thereby reducing the host's processing load.
  • Potential Anticipation (35 U.S.C. § 102): This patent potentially anticipates aspects of claims 1, 9, 12, and 18, particularly regarding the concept of offloading protocol processing to network interface circuitry. Claims 1, 9, 12, and 18 all refer to the network interface circuitry having the capability to offload protocol processing. The specific emphasis on "protocol processing of received data for connections... offloaded to the network interface circuitry" in these claims directly aligns with the core subject matter of US 6,226,680 B1.

• US 6,434,620 B1

  • Full Citation: US 6,434,620 B1, "TCP/IP offload network interface device," issued August 13, 2002.
  • Publication/Filing Date: August 27, 1998 (Filing Date).
  • Brief Description: This patent details a TCP/IP offload network interface device designed to handle TCP/IP protocol processing, including checksum calculations and segmentation, on the network interface card rather than the host CPU.
  • Potential Anticipation (35 U.S.C. § 102): Similar to US 6,226,680 B1, this patent could anticipate elements of claims 1, 9, 12, and 18. Specifically, the mention of "protocol processing of received data" and the network interface circuitry handling such processing for offloaded connections is a key overlap. The capability to offload TCP/IP processing, as described in US 6,434,620 B1, is a fundamental aspect of the broader offloading function claimed in US 7,760,733.

• US 6,717,946 B1

  • Full Citation: US 6,717,946 B1, "Methods and apparatus for mapping ranges of values into unique values of particular use for range matching operations using an associative memory," issued April 6, 2004.
  • Publication/Filing Date: October 31, 2002 (Filing Date).
  • Brief Description: This patent describes methods and apparatus for efficient range matching operations using an associative memory (like a TCAM). This is particularly relevant for tasks such as packet classification and filtering where incoming data needs to be matched against a set of rules that may include ranges.
  • Potential Anticipation (35 U.S.C. § 102): This patent potentially anticipates elements of claims 2, 10, 13, 14, 15, and 17. These claims specifically describe using a content-addressable memory (TCAM) for determining actions and the ability to handle "don't care" values or range matching. The core concept of using associative memory for efficient rule lookup, as described in US 6,717,946 B1, is highly relevant to the lookup circuitry described in these claims of US 7,760,733.

• US 6,798,743 B1

  • Full Citation: US 6,798,743 B1, "Packet prioritization processing technique for routing traffic in a packet-switched computer network," issued September 28, 2004.
  • Publication/Filing Date: March 22, 1999 (Filing Date).
  • Brief Description: This patent introduces a technique for prioritizing packets in a network based on certain criteria, such as protocol type, source/destination, or application. It addresses the need for efficient traffic management in packet-switched networks.
  • Potential Anticipation (35 U.S.C. § 102): This patent might anticipate the prioritization aspects of claims 1, 9, 12, and 18. These claims emphasize determining a "highest priority one of a plurality of actions" based on an order. While US 6,798,743 B1 focuses on traffic routing, the underlying principle of assigning and acting upon priorities for network packets could be considered anticipatory to the prioritization scheme for offloaded processing versus filtering actions.

• US 7,031,267 B2

  • Full Citation: US 7,031,267 B2, "PLD-based packet filtering methods with PLD configuration data update of filtering rules," issued April 18, 2006.
  • Publication/Filing Date: December 21, 2000 (Filing Date).
  • Brief Description: This patent describes packet filtering methods using programmable logic devices (PLDs) where filtering rules can be dynamically updated. This addresses the need for flexible and adaptable packet filtering in network devices.
  • Potential Anticipation (35 U.S.C. § 102): This patent could anticipate aspects of claims 1, 9, 12, and 18, specifically regarding the filtering of received data. The concept of filtering ingress packets using hardware with updatable rules is directly relevant. The "filtering received data" action mentioned in these claims aligns with the primary function of US 7,031,267 B2.

• US 2005/0083935 A1

  • Full Citation: US 2005/0083935 A1, "Method and apparatus for two-stage packet classification using most specific filter matching and transport level sharing," published April 21, 2005.
  • Publication/Filing Date: October 20, 2003 (Filing Date).
  • Brief Description: This publication describes a method and apparatus for efficient packet classification using a two-stage filtering process, focusing on applying the most specific filter matching.
  • Potential Anticipation (35 U.S.C. § 102): This publication potentially anticipates elements of claims 1, 6, 7, 8, 9, 12, 18, 23, 24, and 25, which relate to filtering rules, processing characteristics of received data, and applying masks. The method of determining a specific filtering rule based on packet characteristics, especially with a "most specific filter matching" approach, directly relates to the filtering rule determination process described in US 7,760,733.

This analysis is based on the provided patent text and the general understanding of 35 U.S.C. § 102. A definitive determination of anticipation would require a detailed claim-by-claim comparison by a legal expert.

Obviousness Analysis under 35 U.S.C. § 103 for US Patent 7,760,733

To determine the obviousness of US Patent 7,760,733, we must consider whether the differences between the claimed invention and the prior art would have been obvious at the time of the invention to a person having ordinary skill in the art (PHOSITA). This analysis involves the Graham factors: (1) the scope and content of the prior art; (2) the differences between the prior art and the claims; (3) the level of ordinary skill in the pertinent art; and (4) secondary considerations of non-obviousness. The Supreme Court's decision in KSR International Co. v. Teleflex Inc. further emphasizes a "common sense" approach, stating that a combination of familiar elements according to known methods is likely to be obvious if it yields predictable results. A PHOSITA is a hypothetical person who is presumed to know the relevant art and possess ordinary creativity, but is not an inventor or genius.

Level of Ordinary Skill in the Art (PHOSITA)

For US Patent 7,760,733, which relates to filtering ingress packets in network interface circuitry, a PHOSITA would likely have a strong background in computer networking, network interface card (NIC) architecture, and network protocol processing. This would include knowledge of TCP/IP, Ethernet, and data link layer operations, as well as an understanding of hardware-accelerated packet processing and filtering techniques. Educational attainment for such a person would likely include at least a bachelor's degree in computer science or electrical engineering, with several years of experience in network device development or system administration.

Scope and Content of Prior Art

The "Prior Art Citations" section of US7760733B1 lists numerous patents that were considered during its examination. Many of these references generally relate to intelligent network interface devices, TCP/IP offload engines, packet processing, and filtering in network environments. Key themes among these cited patents include:

• TCP/IP Offload Engines (TOE): Many patents, such as US6226680B1 (Alacritech, Inc.), US6389479B1 (Alacritech, Inc.), US20020095519A1 (Alacritech, Inc.), and US6434620B1 (Alacritech, Inc.), describe intelligent network interface devices capable of offloading TCP/IP protocol processing from the host CPU to the NIC. These typically involve managing connection states (e.g., TCBs) in hardware.
• Packet Filtering and Classification: References like US6594268B1 (Lucent Technologies Inc.) and US6798743B1 (Cisco Technology, Inc.) describe systems for adaptive routing and packet prioritization, which inherently involve some form of packet classification or filtering. US7031267B2 (802 Systems Llc) explicitly discusses PLD-based packet filtering methods with configuration data updates of filtering rules.
• Content-Addressable Memories (CAMs/TCAMs): Several patents, such as US6717946B1 (Cisco Technology Inc.) and US6792502B1 (Freescale Semiconductor, Inc.), address the use of associative memories (including CAMs) for efficient matching operations, which are highly relevant to high-speed packet classification and lookup.
• Network Address Translation (NAT) and Load Balancing: The background of US7760733B1 itself mentions that NAT devices and load balancers can be efficiently implemented through filtering rules. Prior art related to these functionalities would also be relevant.

Differences Between the Prior Art and the Claims

The independent claims (1, 9, 12, and 18) of US7760733B1 generally describe a method and apparatus where network interface circuitry performs both protocol offloading and explicit packet filtering, with a priority mechanism that favors offloaded protocol processing. The key distinctions appear to be:

• Explicit Prioritization of Offloaded Connections over General Filtering: The patent emphasizes that the lookup circuitry is "configured to automatically provide the indication of the highest priority action, associated with the received data, based not only on whether the portion of the received data presented to the lookup circuitry matches data associated with an indication of an action but also based on an order of the indications of the plurality of actions relative to each other in the lookup circuitry, the indications of protocol processing for connections that have been offloaded being located to indicate, when applicable to particular received data, a higher priority than the filtering actions" (Claim 1).
• Filtering for Non-Offloaded Connections: Claim 9 specifically highlights determining a filtering rule "if the data is not data of a connection that is offloaded from the host." This implies a comprehensive filtering capability beyond just connection-specific processing.
• TCAM Organization for Priority: The detailed description (FIG. 3) explains that the TCAM entries are organized into "active connection," "server," and "filter" regions, with the lowest index values assigned to active connections to ensure priority.

Obviousness Combinations and Motivations

A PHOSITA, at the time of the invention, would have been motivated to combine existing technologies to achieve the functionalities described in US7760733B1, primarily due to known problems in network performance and security. The problem of host CPU overhead due to packet processing and the need for efficient network-level filtering were well-recognized.

Combination 1: TCP/IP Offload Engine (e.g., US6226680B1) + Packet Filtering (e.g., US7031267B2) + CAM/TCAM (e.g., US6717946B1)

• References:

  • US6226680B1 (Intelligent network interface system method for protocol processing): This patent teaches an intelligent NIC capable of offloading protocol processing, such as TCP/IP, from the host. It inherently involves matching incoming packets to offloaded connections.
  • US7031267B2 (PLD-based packet filtering methods with PLD configuration data update of filtering rules): This reference discloses packet filtering methods and dynamic updates of filtering rules.
  • US6717946B1 (Methods and apparatus for mapping ranges of values into unique values of particular use for range matching operations using an associative memory): This patent describes the use of associative memories (like CAMs) for efficient range matching, which is highly suitable for packet classification and filtering.

• Motivation for Combination: A PHOSITA would recognize the benefits of integrating packet filtering directly into an intelligent NIC already performing protocol offload.

  • Efficiency: Offloading protocol processing was motivated by reducing host CPU load. Extending this offload to general packet filtering (even for non-offloaded connections) would further reduce host overhead, as the NIC is already inspecting packet headers. This is explicitly stated in US7760733B1 as an advantage: "since the packets headers are already being evaluated to determine if the packets are of offloaded connections, little (if any) additional processing is required in the intelligent interface circuitry to match the packets with filtering actions."
  • Performance: Using a CAM or TCAM (as taught by US6717946B1) within the NIC's processing pipeline (as shown in FIG. 1 and FIG. 2 of US7760733B1) for both connection matching and filtering would offer high-speed, parallel lookups, improving overall throughput. This capability is inherent in TCAMs, which can match multiple rules in parallel and provide results in a pipelined fashion.
  • Security: Implementing a firewall directly on the NIC, as suggested by US7760733B1, would provide an early and efficient defense against network attacks (e.g., DoS attacks) before packets even reach the host's main network stack. US7031267B2 already teaches dynamically updated filtering rules, which are crucial for adaptive security measures.
  • Known Functionality: The idea of "filtering" packets in the context of offloaded connections (even implicitly) was already present in offload engines (US6226680B1 states they "filter" packets by associating them with connections). A PHOSITA would find it obvious to make this filtering explicit and configurable for other traffic, especially given the availability of dedicated filtering techniques (US7031267B2) and high-performance lookup mechanisms (US6717946B1).

Combination 2: TCP/IP Offload Engine with Connection State (e.g., US20030204631A1) + Priority Mechanisms in Network Devices (e.g., US7583596B1)

• References:

  • US20030204631A1 (Method to synchronize and upload an offloaded network stack connection with a network stack): This patent describes a method for offloading network stack connections and maintaining connection state, which is central to the "protocol processing of received data for connections... for which the protocol processing has been offloaded."
  • US7583596B1 (Priority scheduling using per-priority memory structures): This patent teaches priority scheduling in network devices using memory structures, indicating that prioritization is a known concept in network traffic management.

• Motivation for Combination: Given that intelligent NICs were already managing connection states for offloaded protocols (US20030204631A1), and that various forms of prioritization were common in network devices (US7583596B1), a PHOSITA would be motivated to explicitly prioritize offloaded connection processing over general packet filtering.

  • Logical Extension: Offloaded connections are critical for high-performance applications, and ensuring their packets are processed with the highest priority is a natural design choice. If a packet belongs to an offloaded connection, it should logically take precedence over a general filtering rule.
  • Optimizing Resource Usage: By prioritizing offloaded connections, the NIC can efficiently dedicate resources to these critical flows, while still providing a fallback filtering mechanism for all other traffic. The TCAM's inherent ability to return the "first matching entry" (lowest index value) (as described in US7760733B1) would provide a straightforward hardware mechanism to implement such a priority scheme, especially if entries for offloaded connections are physically placed at lower indices.

Predictable Results: The combination of these known elements would yield predictable results: improved network performance by reducing host overhead, enhanced security through early packet filtering, and efficient resource allocation by prioritizing critical offloaded connections. These are all well-understood objectives in network system design. The specific implementation using a TCAM with ordered regions to achieve this prioritization (as described in US7760733B1) would be considered a predictable engineering choice for a PHOSITA looking to optimize performance in a hardware-accelerated network device.