US 7685393

A concise summary of US patent 7685393 is provided below, followed by a plain-language overview of its independent claims and a note on litigation status.

US Patent 7685393 Summary

• Title: Synchronous memory read data capture
• Assignee: MOSAID TECHNOLOGIES INCORPORATED
• Inventors: Peter Gillingham, Robert McKenzie
• Filing Date: June 30, 2006
• Issue Date: March 23, 2010
• Abstract: The patent describes a method for "snap-shot data training" to determine the optimal timing for a DQS (Data Strobe) enable signal in a single read operation. This is achieved by first writing a Gray code sequence into the memory and then reading it back in a single burst. The memory controller samples the read data at a fixed time after issuing the command to determine the "loop-around delay." A lookup table then helps determine the ideal DQS enable timing for subsequent normal reads. An advantageous aspect during normal read operations is using the first positive edge of the enabled DQS signal to sample a counter. If this counter sample changes, it indicates a timing drift, allowing the DQS enable signal to be adjusted to maintain its centered position within the DQS preamble. This technique can also be applied to systems using an iterative approach for DQS enable timing at power-up. Additionally, an embodiment includes a low-latency clock domain crossing circuit based on the DQS-latched counter sample.

Plain-Language Overview of Independent Claims

US Patent 7685393 contains five independent claims (Claims 1, 17, 18, 21, and 22).

• Claim 1: Method for Determining Read Delay
  This claim describes a method for determining the delay in the path of read data between a memory and its controller. The process involves the memory controller writing a specific initialization sequence to certain memory locations. Then, the controller issues a read command for those locations and receives the data. At a specific time after the read command is sent, the controller takes a single snapshot (sample) of the returned data. This sample is then used to figure out the exact read data path delay.

• Claim 17: Memory Controller for Implementing Read Delay Determination
  This claim covers a memory controller that includes a circuit specifically designed to determine read delays. This controller is used with memories that have a two-way (bidirectional) read/write data bus, where data is synchronized with a clock signal (source synchronous clocking), and there's a two-way data strobe. The method performed by this controller is the same as in Claim 1: writing an initialization sequence, sending a read command, sampling the returned data at a set time, and using that sample to calculate the read data path delay.

• Claim 18: Memory Controller with Read Delay Determination and Data Strobe Gating
  This claim defines a memory controller for a synchronous memory with a two-way data bus and data strobe. This controller comprises two key components: a read delay determination circuit and a data strobe enable circuit. During the initial setup, the read delay determination circuit figures out the data path delay by sampling data at a specific moment to produce an initialization sample. This circuit also includes a lookup table that stores a known read delay for every possible initialization sample. The data strobe enable circuit then uses this determined read delay to control (gate) the incoming DQS (data strobe) signal.

• Claim 21: Specific Data Strobe Enable Circuit Design
  This claim details a specific circuit for enabling a data strobe in a memory system with a two-way data bus and data strobe. The circuit has an input for the data strobe signal and an output for a controlled (gated) data strobe signal. A multiplexer is used to gate the data strobe based on a "select input." A "select input generator circuit" manages this select input, turning the data strobe on when an enable signal is active and turning it off after the next strobe edge when a disable signal is active. The generator circuit is specifically composed of two D flip-flops, an AND gate, and an SR flip-flop, ensuring immediate enabling and precise disabling after a data strobe edge.

• Claim 22: Data Strobe Enable Circuit with Inverse Strobe Production
  Similar to Claim 21, this claim describes a data strobe enable circuit for memories with a two-way data bus and data strobe. It receives a data strobe signal and produces a gated data strobe signal using a multiplexer and a select input generator circuit that responds to enable and disable signals. The key additional feature of this claim is that the circuit is also configured to produce a gated inverse data strobe signal using the same select input.

CAFC 2026 Dockets Search

A search of CAFC 2026 dockets for US patent 7685393 did not return specific results indicating active litigation in the Federal Circuit for 2026. However, Google Patents indicates that the patent family has litigation, with a US case filed in the Texas Western District Court (case 1:25-cv-00436). This suggests litigation may be ongoing at the district court level, but no specific CAFC 2026 dockets were identified in the provided information or a direct search.### US Patent 7685393 Summary

• Title: Synchronous memory read data capture
• Assignee: MOSAID TECHNOLOGIES INCORPORATED
• Inventors: Peter Gillingham, Robert McKenzie
• Filing Date: June 30, 2006
• Issue Date: March 23, 2010
• Abstract: The patent describes a method for "snap-shot data training" to determine the optimal timing for a DQS (Data Strobe) enable signal in a single read operation. This is achieved by first writing a Gray code sequence into the memory and then reading it back in a single burst. The memory controller samples the read data at a fixed time after issuing the command to determine the "loop-around delay." A lookup table then helps determine the ideal DQS enable timing for subsequent normal reads. An advantageous aspect during normal read operations is using the first positive edge of the enabled DQS signal to sample a counter. If this counter sample changes, it indicates a timing drift, allowing the DQS enable signal to be adjusted to compensate for the drift and maintain its centered position within the DQS preamble. This technique can also be applied to systems using an iterative approach for DQS enable timing at power-up. Additionally, an embodiment includes a low-latency clock domain crossing circuit based on the DQS-latched counter sample.

Plain-Language Overview of Independent Claims

US Patent 7685393 contains five independent claims: Claims 1, 17, 18, 21, and 22.

• Claim 1: Method for Determining Read Delay
  This claim describes a method for figuring out the delay in the data path when reading information between a memory and its controlling unit (memory controller). The process involves the memory controller first storing a unique sequence (initialization sequence) in specific memory spots. Then, the controller requests to read that data back. At a precise moment after sending the read request, the controller captures a single sample of the incoming data. This captured sample is then used to determine the exact read data path delay.

• Claim 17: Memory Controller for Implementing Read Delay Determination
  This claim defines a memory controller that includes a specialized circuit for determining read delays. This controller is designed to work with memories that use a two-way (bidirectional) data bus, where data transmission is synchronized with a clock signal (source synchronous clocking), and there's also a two-way data strobe. The method carried out by this controller is the same as described in Claim 1: writing an initialization sequence, sending a read command, sampling the returned data at a predetermined time, and using that sample to calculate the read data path delay.

• Claim 18: Memory Controller with Read Delay Determination and Data Strobe Gating
  This claim describes a memory controller for a synchronous memory that features a two-way data bus and a data strobe. The controller includes two main parts: a read delay determination circuit and a data strobe enable circuit. During the initial setup, the read delay determination circuit calculates the read data path delay by taking a single sample of the incoming data at a specific time (creating an initialization sample). This circuit also uses a lookup table that matches each possible initialization sample to a corresponding read delay value. The data strobe enable circuit then utilizes this determined read delay to control (gate) a received DQS (data strobe) signal.

• Claim 21: Specific Data Strobe Enable Circuit Design
  This claim outlines a particular data strobe enable circuit for use with memory that has a two-way read/write bus, source synchronous clocking, and a two-way data strobe. The circuit has an input for the data strobe signal (which has rising and falling edges) and an output for a controlled (gated) data strobe signal. A multiplexer within the circuit gates the data strobe signal based on a "select input." A "select input generator circuit" is connected to receive "data strobe enable" and "data strobe disable" signals. This generator circuit sets the select input to allow the data strobe signal through when the enable signal is activated, and to block the data strobe signal after the next edge of the data strobe signal when the disable signal is activated. Specifically, the select input generator circuit is composed of a first D flip-flop for the enable signal, a second D flip-flop for the disable signal, an AND gate that combines their outputs, and an SR flip-flop clocked by the gated data strobe signal, which produces the select input for the multiplexer. This arrangement ensures the data strobe is quickly enabled upon activation and disabled precisely after the subsequent strobe edge.

• Claim 22: Data Strobe Enable Circuit with Inverse Strobe Production
  This claim describes another data strobe enable circuit for use with memories that have a bidirectional read/write bus, source synchronous clocking, and a bidirectional data strobe. Similar to Claim 21, it takes a data strobe signal as input and produces a gated data strobe signal via a multiplexer and a select input generator circuit that responds to enable and disable signals. The unique feature of this circuit, as specified in this claim, is that it is also configured to produce a gated inverse data strobe signal using the same select input.

CAFC 2026 Dockets

As of April 26, 2026, a search for CAFC 2026 dockets specifically mentioning US patent 7685393 did not return any direct results. While Mosaid Technologies Inc., the current assignee, is engaged in ongoing litigation against Intel (Case No. 3:26-cv-246 in the District of Oregon, transferred from Western District of Texas 1:25-cv-00677 in February 2026), this case involves different patent numbers, such as US8809940B2, and does not explicitly list US7685393 as being asserted. Therefore, there is no authoritative information to indicate active litigation concerning US7685393 in the CAFC dockets for 2026.