US 7685393

A concise summary of US patent 7685393 is provided below, followed by a plain-language overview of its independent claims and a note on litigation status.

US Patent 7685393 Summary

• Title: Synchronous memory read data capture
• Assignee: MOSAID TECHNOLOGIES INCORPORATED
• Inventors: Peter Gillingham, Robert McKenzie
• Filing Date: June 30, 2006
• Issue Date: March 23, 2010
• Abstract: The patent describes a method for "snap-shot data training" to determine the optimal timing for a DQS (Data Strobe) enable signal in a single read operation. This is achieved by first writing a Gray code sequence into the memory and then reading it back in a single burst. The memory controller samples the read data at a fixed time after issuing the command to determine the "loop-around delay." A lookup table then helps determine the ideal DQS enable timing for subsequent normal reads. An advantageous aspect during normal read operations is using the first positive edge of the enabled DQS signal to sample a counter. If this counter sample changes, it indicates a timing drift, allowing the DQS enable signal to be adjusted to maintain its centered position within the DQS preamble. This technique can also be applied to systems using an iterative approach for DQS enable timing at power-up. Additionally, an embodiment includes a low-latency clock domain crossing circuit based on the DQS-latched counter sample.

Plain-Language Overview of Independent Claims

US Patent 7685393 contains five independent claims (Claims 1, 17, 18, 21, and 22).

• Claim 1: Method for Determining Read Delay
  This claim describes a method for determining the delay in the path of read data between a memory and its controller. The process involves the memory controller writing a specific initialization sequence to certain memory locations. Then, the controller issues a read command for those locations and receives the data. At a specific time after the read command is sent, the controller takes a single snapshot (sample) of the returned data. This sample is then used to figure out the exact read data path delay.

• Claim 17: Memory Controller for Implementing Read Delay Determination
  This claim covers a memory controller that includes a circuit specifically designed to determine read delays. This controller is used with memories that have a two-way (bidirectional) read/write data bus, where data is synchronized with a clock signal (source synchronous clocking), and there's a two-way data strobe. The method performed by this controller is the same as in Claim 1: writing an initialization sequence, sending a read command, sampling the returned data at a set time, and using that sample to calculate the read data path delay.

• Claim 18: Memory Controller with Read Delay Determination and Data Strobe Gating
  This claim defines a memory controller for a synchronous memory with a two-way data bus and data strobe. This controller comprises two key components: a read delay determination circuit and a data strobe enable circuit. During the initial setup, the read delay determination circuit figures out the data path delay by sampling data at a specific moment to produce an initialization sample. This circuit also includes a lookup table that stores a known read delay for every possible initialization sample. The data strobe enable circuit then uses this determined read delay to control (gate) the incoming DQS (data strobe) signal.

• Claim 21: Specific Data Strobe Enable Circuit Design
  This claim details a specific circuit for enabling a data strobe in a memory system with a two-way data bus and data strobe. The circuit has an input for the data strobe signal and an output for a controlled (gated) data strobe signal. A multiplexer is used to gate the data strobe based on a "select input." A "select input generator circuit" manages this select input, turning the data strobe on when an enable signal is active and turning it off after the next strobe edge when a disable signal is active. The generator circuit is specifically composed of two D flip-flops, an AND gate, and an SR flip-flop, ensuring immediate enabling and precise disabling after a data strobe edge.

• Claim 22: Data Strobe Enable Circuit with Inverse Strobe Production
  Similar to Claim 21, this claim describes a data strobe enable circuit for memories with a two-way data bus and data strobe. It receives a data strobe signal and produces a gated data strobe signal using a multiplexer and a select input generator circuit that responds to enable and disable signals. The key additional feature of this claim is that the circuit is also configured to produce a gated inverse data strobe signal using the same select input.

CAFC 2026 Dockets Search

A search of CAFC 2026 dockets for US patent 7685393 did not return specific results indicating active litigation in the Federal Circuit for 2026. However, Google Patents indicates that the patent family has litigation, with a US case filed in the Texas Western District Court (case 1:25-cv-00436). This suggests litigation may be ongoing at the district court level, but no specific CAFC 2026 dockets were identified in the provided information or a direct search.### US Patent 7685393 Summary

• Title: Synchronous memory read data capture
• Assignee: MOSAID TECHNOLOGIES INCORPORATED
• Inventors: Peter Gillingham, Robert McKenzie
• Filing Date: June 30, 2006
• Issue Date: March 23, 2010
• Abstract: The patent describes a method for "snap-shot data training" to determine the optimal timing for a DQS (Data Strobe) enable signal in a single read operation. This is achieved by first writing a Gray code sequence into the memory and then reading it back in a single burst. The memory controller samples the read data at a fixed time after issuing the command to determine the "loop-around delay." A lookup table then helps determine the ideal DQS enable timing for subsequent normal reads. An advantageous aspect during normal read operations is using the first positive edge of the enabled DQS signal to sample a counter. If this counter sample changes, it indicates a timing drift, allowing the DQS enable signal to be adjusted to compensate for the drift and maintain its centered position within the DQS preamble. This technique can also be applied to systems using an iterative approach for DQS enable timing at power-up. Additionally, an embodiment includes a low-latency clock domain crossing circuit based on the DQS-latched counter sample.

Plain-Language Overview of Independent Claims

US Patent 7685393 contains five independent claims: Claims 1, 17, 18, 21, and 22.

• Claim 1: Method for Determining Read Delay
  This claim describes a method for figuring out the delay in the data path when reading information between a memory and its controlling unit (memory controller). The process involves the memory controller first storing a unique sequence (initialization sequence) in specific memory spots. Then, the controller requests to read that data back. At a precise moment after sending the read request, the controller captures a single sample of the incoming data. This captured sample is then used to determine the exact read data path delay.

• Claim 17: Memory Controller for Implementing Read Delay Determination
  This claim defines a memory controller that includes a specialized circuit for determining read delays. This controller is designed to work with memories that use a two-way (bidirectional) data bus, where data transmission is synchronized with a clock signal (source synchronous clocking), and there's also a two-way data strobe. The method carried out by this controller is the same as described in Claim 1: writing an initialization sequence, sending a read command, sampling the returned data at a predetermined time, and using that sample to calculate the read data path delay.

• Claim 18: Memory Controller with Read Delay Determination and Data Strobe Gating
  This claim describes a memory controller for a synchronous memory that features a two-way data bus and a data strobe. The controller includes two main parts: a read delay determination circuit and a data strobe enable circuit. During the initial setup, the read delay determination circuit calculates the read data path delay by taking a single sample of the incoming data at a specific time (creating an initialization sample). This circuit also uses a lookup table that matches each possible initialization sample to a corresponding read delay value. The data strobe enable circuit then utilizes this determined read delay to control (gate) a received DQS (data strobe) signal.

• Claim 21: Specific Data Strobe Enable Circuit Design
  This claim outlines a particular data strobe enable circuit for use with memory that has a two-way read/write bus, source synchronous clocking, and a two-way data strobe. The circuit has an input for the data strobe signal (which has rising and falling edges) and an output for a controlled (gated) data strobe signal. A multiplexer within the circuit gates the data strobe signal based on a "select input." A "select input generator circuit" is connected to receive "data strobe enable" and "data strobe disable" signals. This generator circuit sets the select input to allow the data strobe signal through when the enable signal is activated, and to block the data strobe signal after the next edge of the data strobe signal when the disable signal is activated. Specifically, the select input generator circuit is composed of a first D flip-flop for the enable signal, a second D flip-flop for the disable signal, an AND gate that combines their outputs, and an SR flip-flop clocked by the gated data strobe signal, which produces the select input for the multiplexer. This arrangement ensures the data strobe is quickly enabled upon activation and disabled precisely after the subsequent strobe edge.

• Claim 22: Data Strobe Enable Circuit with Inverse Strobe Production
  This claim describes another data strobe enable circuit for use with memories that have a bidirectional read/write bus, source synchronous clocking, and a bidirectional data strobe. Similar to Claim 21, it takes a data strobe signal as input and produces a gated data strobe signal via a multiplexer and a select input generator circuit that responds to enable and disable signals. The unique feature of this circuit, as specified in this claim, is that it is also configured to produce a gated inverse data strobe signal using the same select input.

CAFC 2026 Dockets

As of April 26, 2026, a search for CAFC 2026 dockets specifically mentioning US patent 7685393 did not return any direct results. While Mosaid Technologies Inc., the current assignee, is engaged in ongoing litigation against Intel (Case No. 3:26-cv-246 in the District of Oregon, transferred from Western District of Texas 1:25-cv-00677 in February 2026), this case involves different patent numbers, such as US8809940B2, and does not explicitly list US7685393 as being asserted. Therefore, there is no authoritative information to indicate active litigation concerning US7685393 in the CAFC dockets for 2026.

As of April 26, 2026, a search for litigation involving US Patent 7,685,393 revealed one case:

• Case Name: MOSAID TECHNOLOGIES INCORPORATED vs. ALL Defendants
• Plaintiff(s): Mosaid Technologies Incorporated
• Defendant(s): ALL Defendants (specific defendants are not detailed in the available search snippet)
• Jurisdiction: Texas Western District Court
• Case Number: 1:25-cv-00436
• Filing Date: The filing date is not explicitly mentioned in the provided information, but the case is listed as "US case filed in Texas Western District Court" with a link to Unified Patents (https://portal.unifiedpatents.com/litigation/Texas%20Western%20District%20Court/case/1%3A25-cv-00436).
• Outcome/Current Status: The status is listed as "litigation". More specific details regarding the outcome or current status are not provided in the search results.

Proceedings overview

There are no AIA trial proceedings on file for US patent 7685393 as of the most recent ingest of USPTO Open Data Portal data, and no such proceedings were surfaced through web searches. This means the patent's claims have not been challenged or adjudicated through Inter Partes Review (IPR), Post-Grant Review (PGR), or Covered Business Method (CBM) reviews at the Patent Trial and Appeal Board (PTAB). For a defendant, this indicates that the patent's claims remain untested by these specific administrative review processes.

Strategic summary

As there are no PTAB proceedings associated with US7685393, all claims of the patent (claims 1-23) remain untested by IPR, PGR, or CBM challenges. This means there are no claims that have been canceled or sustained through PTAB Final Written Decisions. Consequently, there is no estoppel landscape established by PTAB proceedings under 35 U.S.C. § 315(e)(2) for potential petitioners or their privies regarding prior-art grounds. The absence of PTAB activity could imply that either the patent has not yet been aggressively asserted in a manner that would provoke such challenges, or that potential challengers have not identified strong enough grounds for an AIA trial.

Recommended next steps

Since no PTAB activity exists for US7685393, a potential defendant facing assertion of this patent would have all prior-art grounds available for a potential IPR petition, assuming they meet the statutory requirements (e.g., timing, standing, grounds). The absence of PTAB activity is a notable signal; well-asserted patents often eventually attract IPRs. Therefore, a thorough prior art search and validity analysis would be a prudent first step to assess the potential for filing an IPR if faced with an infringement accusation.

Inventors

The named inventors for US patent 7685393 are Peter Gillingham and Robert McKenzie. At the time of filing, both inventors were associated with Mosaid Technologies Inc., the original assignee, as indicated by the initial assignment record.

Original assignee

The original assignee named on the issued patent is Mosaid Technologies Inc. Mosaid Technologies Inc. primarily operated as a semiconductor intellectual property (IP) licensing company, specializing in DRAM memory design and patent monetization. They were not typically a product-shipping entity for technologies like those described in this patent, but rather asserted and licensed their IP portfolio. The company later rebranded as Conversant Intellectual Property Management Inc. and subsequently reverted to Mosaid Technologies Incorporated. As of today's date, the patent is listed as "Active" and the current assignee is Mosaid Technologies Inc., indicating it is an operating entity for IP licensing and assertion.

Assignment timeline

The following is a chronological list of recorded assignments and related events for US patent 7685393, derived from the patent's legal events history:

• 2006-09-07 (executed) / recorded 2006-09-07 - Reel N/A

  • Conveyance: Assignment
  • Assignor: MCKENZIE, ROBERT, GILLINGHAM, PETER
  • Assignee: MOSAID TECHNOLOGIES INCORPORATED
  • Correspondent: N/A (not provided in source)
  • Context: Original assignment from inventors to the company.

• 2008-07-17 (executed) / recorded 2008-07-17 - Reel N/A

  • Conveyance: Assignment
  • Assignor: GILLINGHAM, PETER, MR.
  • Assignee: MOSAID TECHNOLOGIES INCORPORATED
  • Correspondent: N/A (not provided in source)
  • Context: Subsequent assignment from one inventor, potentially clarifying or completing prior rights.

• 2012-01-10 (executed) / recorded 2012-01-10 - Reel N/A

  • Conveyance: U.S. INTELLECTUAL PROPERTY SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) - SHORT FORM
  • Assignor: 658276 N.B. LTD., 658868 N.B. INC., MOSAID TECHNOLOGIES INCORPORATED
  • Assignee: ROYAL BANK OF CANADA
  • Correspondent: N/A (not provided in source)
  • Context: Grant of a security interest for financing.

• 2014-03-13 (executed) / recorded 2014-03-13 - Reel N/A

  • Conveyance: Change of Name
  • Assignor: MOSAID TECHNOLOGIES INCORPORATED
  • Assignee: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Correspondent: N/A (not provided in source)
  • Context: Corporate rebranding and name change of the patent owner.

• 2014-08-07 (executed) / recorded 2014-08-07 - Reel N/A

  • Conveyance: RELEASE OF SECURITY INTEREST
  • Assignor: ROYAL BANK OF CANADA
  • Assignee: CONVERSANT IP N.B. 868 INC., CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CONVERSANT IP N.B. 276 INC.
  • Correspondent: N/A (not provided in source)
  • Context: Release of previously granted security interest by the bank.

• 2014-09-03 (executed) / recorded 2014-09-03 - Reel N/A

  • Conveyance: CHANGE OF ADDRESS
  • Assignor: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Assignee: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Correspondent: N/A (not provided in source)
  • Context: Administrative change of address for the patent owner.

• 2014-09-09 (executed) / recorded 2014-09-09 - Reel N/A

  • Conveyance: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS)
  • Assignor: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Assignee: ROYAL BANK OF CANADA, AS LENDER, CPPIB CREDIT INVESTMENTS INC., AS LENDER
  • Correspondent: N/A (not provided in source)
  • Context: Grant of new security interests to lenders for financing.

• 2018-08-22 (executed) / recorded 2018-08-22 - Reel N/A

  • Conveyance: AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS)
  • Assignor: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Assignee: CPPIB CREDIT INVESTMENTS, INC.
  • Correspondent: N/A (not provided in source)
  • Context: Update to existing security agreement.

• 2018-10-12 (executed) / recorded 2018-10-12 - Reel N/A

  • Conveyance: RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS)
  • Assignor: ROYAL BANK OF CANADA, AS LENDER
  • Assignee: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Correspondent: N/A (not provided in source)
  • Context: Release of security interest by one of the lenders.

• 2020-11-03 (executed) / recorded 2020-11-03 - Reel N/A

  • Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS)
  • Assignor: CPPIB CREDIT INVESTMENTS INC.
  • Assignee: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Correspondent: N/A (not provided in source)
  • Context: Release of security interest by the secured party.

• 2021-10-19 (executed) / recorded 2021-10-19 - Reel N/A

  • Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS)
  • Assignor: CONVERSANT INTELLECTUAL PROPERTY INC.
  • Assignee: MOSAID TECHNOLOGIES INCORPORATED
  • Correspondent: N/A (not provided in source)
  • Context: Corporate rebranding and name change back to Mosaid.

• 2023-08-28 (executed) / recorded 2023-08-28 - Reel 057857/0193

  • Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY'S NAME PREVIOUSLY RECORDED AT REEL: 057857 FRAME: 0193. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME.
  • Assignor: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Assignee: MOSAID TECHNOLOGIES INCORPORATED
  • Correspondent: N/A (not provided in source)
  • Context: Corrective assignment to rectify a previous name change record.

Timeline diagram

timeline
    title Ownership of US 7685393
    2006 : Inventors assign to Mosaid
    2008 : Inventor assigns to Mosaid
    2010 : Patent Issued
    2012 : Security Agreement to RBC
    2014 : Mosaid changes name to Conversant
         : RBC releases security interest
         : Conversant changes address
         : New Security Agreement to RBC CPPIB
    2018 : Amended Security Agreement to CPPIB
         : RBC releases security interest
    2020 : CPPIB releases security interest
    2021 : Conversant changes name to Mosaid
    2023 : Corrective assignment
    2025 : First infringement suit filed

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The original assignee, Mosaid Technologies Inc., is a known patent licensing and assertion entity. The patent also transferred through a name change to Conversant Intellectual Property Management Inc., which is also a known patent assertion entity. These entities are primarily engaged in patent monetization rather than product development and sales related to the claims.
2. Known asserter in the chain — Present. Mosaid Technologies Inc. and Conversant Intellectual Property Management Inc. are explicitly recognized as known patent assertion entities (NPEs) or frequently-identified plaintiffs in patent litigation. They appear as assignees throughout the patent's ownership history (e.g., Mosaid 2006-09-07, Conversant 2014-03-13, Mosaid 2021-10-19).
3. Repeat correspondent across the chain — Unclear. The provided source data from Google Patents does not include correspondent attorney names or firms for most of the assignment records, making it impossible to determine if the same correspondent recurs. One entry (2023-08-28, Reel 057857/0193) provides a reel/frame but no correspondent details.
4. Cascading transfers — Present. There are several rapid successions of events, particularly between 2012 and 2014, including security agreements, releases, and name/address changes (e.g., 2012-01-10, 2014-03-13, 2014-08-07, 2014-09-03, 2014-09-09). This indicates active financial management and restructuring common in patent monetization strategies.
5. Pre-litigation transfer — Not present. The patent was issued in March 2010, and the earliest recorded litigation (Texas Western District Court case 1:25-cv-00436) was filed in 2025. There were no transfers of ownership to a new asserting entity within six months prior to the 2025 litigation; the entity (Mosaid/Conversant) had owned the patent since its inception.
6. Bankruptcy fire-sale — Not present. There is no indication in the provided records that Mosaid Technologies Inc. or Conversant Intellectual Property Management Inc. underwent bankruptcy proceedings that led to the sale of this patent.
7. Privateering — Unclear. While Mosaid/Conversant's general business model often involves acquiring patents from operating companies for assertion, the initial assignment for this patent is directly from the inventors. Therefore, this specific chain does not provide direct evidence of a privateering arrangement for this patent.
8. Defensive aggregator (anti-NPE) — Not present. The ownership chain ends with Mosaid Technologies Incorporated, which is a known NPE, not a defensive aggregator.

Verdict

NPE — high confidence

The patent exhibits strong signals of NPE ownership and assertion patterns. Mosaid Technologies Inc. and its rebranded entity, Conversant Intellectual Property Management Inc., are well-known patent assertion entities. The series of name changes and multiple security agreements/releases for financing (e.g., from 2012-01-10 to 2014-09-09) are typical activities for organizations focused on patent monetization. The ongoing litigation (1:25-cv-00436) further supports the assertion pattern.

Verification link to USPTO Assignment Center search page for US7685393: https://assignmentcenter.uspto.gov/patents/7685393

The USPTO database confirms the existence of US patent 7685393, titled "Synchronous memory read data capture," with a publication date of March 23, 2010.

The provided full patent text for US7685393 explicitly identifies one prior art patent: U.S. Pat. No. 6,889,336.

Due to the nature of the search tool, direct access to the full text, abstract, or detailed claims of US Patent 6,889,336 from the search snippets was not possible. Therefore, a comprehensive analysis of its content for potential anticipation of claims in US7685393 under 35 U.S.C. § 102 cannot be performed with high confidence and direct grounding in the search results at this time.

However, based on the information available within the text of US7685393, the following details for U.S. Pat. No. 6,889,336 are provided:

Prior Art Reference: US 6,889,336 B2

• Full Citation: U.S. Pat. No. 6,889,336, granted to A. M. Schoenfeld et al., titled (as inferred from the context of US7685393) "Method and apparatus for enabling a data strobe in a memory controller" or a similar title relating to DDR SDRAM and bidirectional data strobes.
• Publication Date: May 3, 2005.
• Filing Date: The filing date was not directly obtainable from the search results, but it would precede the publication date of May 3, 2005.
• Brief Description (as referenced by US7685393): US 6,889,336 discloses "An application of a bidirectional data strobe signal to DDR SDRAM." It describes the use of a bidirectional data strobe signal for DDR SDRAM memory systems.
• Potential Anticipation under 35 U.S.C. § 102: Without direct access to the claims and full description of US 6,889,336 from current search results, a definitive determination of which specific claims of US7685393 it potentially anticipates cannot be made. However, given that US7685393 itself cites this patent in its background for disclosing the "application of a bidirectional data strobe signal to DDR SDRAM," it likely anticipates fundamental aspects related to the concept of using bidirectional data strobes in DDR SDRAM.
  • For example, claims in US7685393 that broadly relate to "a method for controlling a synchronous memory comprising... receiving a data strobe signal synchronously with the data signal" (Claim 2, last part) or "a memory that has a bidirectional read/write bus with source synchronous clocking and a bidirectional data strobe" (Claim 18, preamble) could potentially be generally related to the subject matter of US 6,889,336. However, the inventive steps of US7685393 primarily revolve around measuring a read delay using a single initialization sample derived from a Gray code sequence and dynamically adjusting DQS enable timing, which are specific methods and circuits that would need to be compared directly against the claims of US 6,889,336 for a precise anticipation analysis.

Obviousness Analysis of US Patent 7,685,393 under 35 U.S.C. § 103

This analysis identifies combinations of prior art references that would render the claims of US patent 7,685,393 obvious to a person having ordinary skill in the art (PHOSITA), along with the motivation for such combinations. The analysis relies on the prior art explicitly described within the '393 patent itself, particularly U.S. Pat. No. 6,889,336 to Schoenfeld et al. and the LSI Logic 0.11 µm DDR2 PHY document cw000733—1—0 dated February 2005.

The '393 patent addresses several challenges in synchronous memory read data capture, specifically for Double Data Rate (DDR) Synchronous DRAM (SDRAM) systems using bidirectional data strobes (DQS). These challenges include determining the optimal timing for the DQS enable signal during system initialization, adjusting for timing drift during operation, and transferring data from the DQS clock domain to the system clock domain.

Core Problem Addressed by the Patent

The '393 patent highlights that for DDR400 and higher data rates, the read data timing can vary significantly, exceeding the DQS preamble interval, thus rendering fixed timing solutions for DQS enablement unreliable. It notes that existing DQS gating approaches, such as those described in the LSI Logic DDR2 PHY document, have limitations:

• "Programmable GATEON": Requires iterative read data training, significant initialization time, higher-level controller intelligence, and cannot accommodate timing drift.
• "Feedback GATEON": Requires additional pins, PCB traces, and consumes power, while not perfectly matching the actual command-to-read data loop-around delay.
• "External GATEON": Also requires additional pins and interconnects.

The invention proposes a "snap-shot data training" method using a Gray code initialization sequence and a lookup table for efficient initial DQS enable timing determination, a drift detection mechanism, and a clock domain crossing circuit.

Obviousness Arguments Based on Prior Art Combinations

1. Snap-Shot Read Delay Determination (Claims 1, 3-9, 17, 18, 20)

Claim 1 describes a method for establishing a read data path delay by writing an initialization sequence, sending a read command, sampling the returned data signals at a predetermined time to produce a single initialization sample, and using this sample to determine the read data path delay. Claims 3-8 specify the use of a Gray code sequence and sampling its bits with four clock phases. Claim 9 adds storing expected initialization samples for lookup.

• Prior Art Teachings:

  • Schoenfeld '336 (and general DDR SDRAM knowledge): Discloses the context of DDR SDRAM with bidirectional data strobe signals. A PHOSITA would be familiar with the architecture and operation of such memory systems.
  • LSI Logic "Programmable GATEON": Explicitly teaches the necessity of "read data training" to determine the optimal DQS enable timing. This involves performing read operations and analyzing the received data to set a programmable delay register. This method implicitly requires writing a known initialization sequence and reading it back to determine the proper timing.
  • General Knowledge of Gray Codes: Gray codes are well-known in digital electronics for their property that only a single bit changes between successive codewords. This makes them inherently robust for timing measurements where small skews might otherwise lead to erroneous readings, a property recognized by the '393 patent itself. A PHOSITA would understand the utility of Gray codes for reliable state encoding, especially in asynchronous or delay-sensitive contexts.
  • General Knowledge of Lookup Tables: Lookup tables are standard mechanisms in digital design for mapping a set of input values (e.g., a sampled pattern) to corresponding output values (e.g., a delay setting or control parameter).

• Motivation to Combine:
  A PHOSITA, facing the "significant amount of time during system initialization" required by the iterative "Programmable GATEON" approach for read data training, would be strongly motivated to devise a faster and more efficient method. Combining the concept of read data training (from LSI Logic) with the robust properties of Gray codes (general knowledge) would naturally lead to using a Gray code as the initialization sequence to reliably capture the system's state relative to the read command in a single attempt. Sampling this known sequence at a predetermined time to get a "snapshot" and then using a lookup table to directly determine the optimal DQS enable timing (instead of iterative searching) would be an obvious improvement to reduce initialization time and complexity. The idea of characterizing a system's delay by transmitting a known pattern, capturing a snapshot of the received pattern relative to a reference, and mapping this snapshot to a delay value is a fundamental diagnostic technique.

2. Drift Detection and Compensation (Claim 13, and related aspects)

Claim 13 teaches on an ongoing basis determining if there is clock drift, and if so, updating the read delay. The patent describes a specific drift detector circuit in FIG. 9A, using D flip-flops clocked by DQS and sampling 0° and 90° phases of a master clock.

• Prior Art Teachings:

  • LSI Logic "Programmable GATEON": Explicitly identifies a major disadvantage as its inability to "accommodate timing drift during operation." This highlights the recognized problem of drift.
  • General Knowledge of Phase Detection: The concept of detecting phase differences or drift between two clock signals using multiple phases of a reference clock is a fundamental technique in digital circuit design, commonly implemented in Phase-Locked Loops (PLLs) and Delay-Locked Loops (DLLs) for clock synchronization. Using 0° and 90° phases to detect a quarter-cycle (90°) phase shift is a basic and well-known method of phase detection.

• Motivation to Combine:
  Given that "Programmable GATEON" cannot accommodate timing drift, a PHOSITA would be motivated to add a mechanism for drift detection and compensation. The problem of timing drift due to environmental factors (temperature, voltage) is well-understood. Applying known phase detection techniques, such as latching multiple phases (e.g., 0° and 90°) of a stable master clock with the potentially drifting DQS signal (as the input clock) to identify phase changes, would be an obvious solution to the identified problem. Once drift is detected, the logical next step is to update the previously determined DQS enable timing to compensate, thereby maintaining robust data capture.

3. Specific DQS Enable Gating Circuit (Claims 21-23)

Claim 21 details a DQS enable circuit comprising an input for DQS, an output for a gated DQS, a multiplexer, and a select input generator circuit (including D flip-flops, an AND gate, and an SR flip-flop clocked by the gated DQS) that sets the select input to enable DQS upon activation of a DQS enable signal and deselects it upon activation of a DQS disable signal and following a next edge of the data strobe signal. Claim 22 adds producing a gated inverse DQS. Claim 23 describes a circuit for selecting between DDR1 and DDR2 modes.

• Prior Art Teachings:

  • Schoenfeld '336 (and general DDR SDRAM knowledge): Discloses the use of a bidirectional data strobe signal in DDR SDRAM. The background of the '393 patent emphasizes the necessity to gate the DQS clock input to prevent "spurious clock edges created by a tri-stated clock input level from triggering internal data capture."
  • LSI Logic (GATEON): Reinforces the concept of enabling the DQS read strobe using a control signal (GATEON).
  • General Digital Circuit Design Principles: Glitch-free clock gating is a fundamental concern in synchronous digital design. Common techniques involve synchronizing control signals to the clock being gated and using logic (such as SR flip-flops or other combinational logic with edge synchronization) to ensure that the clock is enabled/disabled cleanly without introducing partial pulses or metastability. The use of multiplexers for signal selection and for providing backward compatibility (e.g., between DDR1 and DDR2 modes, as described for circuit 180 in FIG. 8A) is also a standard engineering practice.

• Motivation to Combine:
  A PHOSITA tasked with designing a DQS enable circuit for a DDR memory controller would be motivated to ensure robust and glitch-free operation, as required for reliable data capture. Combining the functional requirement of DQS gating (from the DDR standard and LSI Logic's GATEON concept) with standard digital circuit design principles for clock gating would lead to the design of a circuit similar to that described in Claim 21. The specific arrangement of D flip-flops, an AND gate, and an SR flip-flop clocked by the gated DQS is a well-known and conventional approach to synchronize enable/disable signals and produce a glitch-free gated clock output. Extending this to gate an inverse DQS (Claim 22) when both are present (e.g., in DDR2) or to generate an inverse DQS for backward compatibility (Claim 23) using multiplexers would be obvious design choices for a PHOSITA implementing a flexible DDR controller.

4. Clock Domain Crossing for Data Re-timing (Claim 16, 19)

Claim 16 describes re-timing read data signals to an RTL clock. Claim 19 includes a circuit for re-timing data signals to a main clock.

• Prior Art Teachings:

  • General DDR Memory System Knowledge: The '393 patent explicitly identifies "how to transfer data clocked in with DQS to the system clock domain when the phase between the DQS clock and master system clock CLK can be completely arbitrary" as a "third problem." This describes a classic clock domain crossing (CDC) scenario.
  • General Knowledge of Clock Domain Crossing (CDC) Techniques: Solutions for CDC are widely known and documented in digital design. These include using asynchronous FIFOs, multi-flop synchronizers, or sampling data with multiple phases of the destination clock to determine the best sampling point. The patent describes circuit 85 (FIG. 4) that samples DQ0 and DQ1 with 0° and 180° clock phases and selects between them with a multiplexer to "produce outputs... that are re-timed to be synchronous with the 0° clock."

• Motivation to Combine:
  A PHOSITA designing a memory controller would be motivated to reliably transfer data from the memory's DQS clock domain to the controller's internal system clock (RTL clock) domain, especially when their phases are arbitrary. This is a recognized problem (the "third problem" identified by the '393 patent). Applying known CDC techniques, such as capturing data with multiple phases of the destination clock (e.g., 0° and 180° from the master DLL, which are explicitly stated to be available) and selecting the appropriately timed sample, would be an obvious engineering solution to achieve robust clock domain crossing.

In conclusion, the innovations claimed in US7685393, while providing specific implementations, represent combinations of known techniques and solutions to identified problems within the context of DDR memory controllers. A PHOSITA, aiming to overcome the limitations of existing read data training and DQS gating methods (as described in prior art like the LSI Logic document) and to address common challenges in high-speed synchronous memory interfaces (like timing drift and clock domain crossing), would have been motivated to combine these known elements in the manner claimed.