US 7629634

Here's a concise summary of US Patent 7,629,634:

Title: Trenched MOSFET with trenched source contact

Assignee: FORCE MOS TECHNOLOGY Co Ltd

Inventors: Fu-Yuan Hsieh

Filing Date: 2008-02-23

Issue Date: 2009-12-08

Abstract: A trenched MOSFET with trenched source contact is described, comprising a semiconductor region with a silicon substrate, an epitaxial layer (drain), a base layer (body), and a source layer (source), stacked in sequence. It also includes an interlayer oxide film, a front metal layer, a back metal layer, trenched gates extending through the source and base layers to the epitaxial layer, and source contact trenches extending through the interlayer oxide film and source layer to the base layer. A key feature is that the sidewalls of the source contact trenches in the base layer include a lateral contact layer.

Plain-Language Overview of Independent Claims:

• Claim 1: This claim describes a trenched MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). It includes a stacked semiconductor structure (silicon substrate, drain region, body region, source region). On top, there's a front metal layer, and at the bottom, a back metal layer. Trenches are formed for the gates, extending down into the drain region. Separately, other trenches, called source contact trenches, are formed, extending down to the body region. A key feature is that the sides of these source contact trenches, within the body layer, are covered by a "lateral contact layer," and the bottom of these trenches in the body layer are covered by a "base contact layer."

• Claim 6: This claim describes a variation of the trenched MOSFET in Claim 1. The primary difference is the doping types are inverted. Specifically, the silicon substrate, epitaxial layer (drain), and source layer are P-type, while the base layer (body) and the lateral contact layer are N-type. Similar to Claim 1, each source contact trench also has an N-type base contact layer at its bottom. The lateral contact layer has a lower doping concentration than the base contact layer at the bottom.

Uncertainty Regarding CAFC Dockets:
While the patent information indicates "US case filed in Court of Appeals for the Federal Circuit", a specific docket number for US Patent 7,629,634, active in 2026, was not found in the search results. The search results for CAFC dockets in 2026 mentioned other patent numbers and general patent litigation trends, but did not explicitly refer to 7,629,634. Therefore, I cannot provide details about any specific CAFC litigation involving this patent in 2026 with authoritative information.

Known litigation involving US patent 7629634 includes the following cases:

1. District Court Litigation (Texas Eastern District Court)

   • Plaintiff(s): Force MOS Technology
   • Defendant(s): ASUSTek Computer, Inc. (ASUS)
   • Jurisdiction: Texas Eastern District Court
   • Case Number: 2:22-cv-00460 (This is inferred from the Google Patents listing for US7629634B2, which mentions a "US case filed in Texas Eastern District Court" with this number)
   • Filing Date: November 2022 (Specifically, a complaint alleging infringement was served on ASUS on November 28, 2022)
   • Outcome/Current Status: A jury returned a verdict awarding Force MOS $10.5 million for the infringement of four claims from two trenched MOSFET patents (including US7629634). A final judgment was entered, clarifying the award as a running royalty. A bench trial on ASUSTek's inequitable conduct claims also favored Force MOS. Post-judgment issues, including the calculation of costs, interest, and potential attorney fees, remain.

2. PTAB Inter Partes Review (IPR2024-00093)

   • Petitioner(s): Excelliance Mos Corporation
   • Defendant(s): Force MOS Technology Co. Ltd.
   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2024-00093
   • Filing Date: April 24, 2025 (petition filing date)
   • Outcome/Current Status: The case has reached a "Final Written Decision." Force MOS Technology Co. Ltd. submitted a Preliminary Response arguing against institution, citing that the petition was filed more than one year after ASUS (identified as a real party-in-interest for Excelliance Mos Corporation) was served with an infringement complaint for the '634 patent on November 28, 2022.

3. PTAB Inter Partes Review (IPR2025-01433)

   • Petitioner(s): Excelliance Mos Corporation
   • Defendant(s): FORCE MOS TECHNOLOGY Co Ltd
   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2025-01433
   • Filing Date: August 15, 2025 (effective date)
   • Outcome/Current Status: Not Instituted - Procedural.

4. District Court Litigation (California Northern District Court)

   • Plaintiff(s): Not specified in available information.
   • Defendant(s): Not specified in available information.
   • Jurisdiction: California Northern District Court
   • Case Number: 4:22-cv-05448
   • Filing Date: Not specified in available information.
   • Outcome/Current Status: US case filed.

5. District Court Litigation (California Northern District Court)

   • Plaintiff(s): Not specified in available information.
   • Defendant(s): Not specified in available information.
   • Jurisdiction: California Northern District Court
   • Case Number: 5:22-cv-05448
   • Filing Date: Not specified in available information.
   • Outcome/Current Status: US case filed.

6. Appellate Court Litigation (Court of Appeals for the Federal Circuit)

   • Plaintiff(s): Not specified in available information.
   • Defendant(s): Not specified in available information.
   • Jurisdiction: Court of Appeals for the Federal Circuit
   • Case Number: Not specified in available information.
   • Filing Date: Not specified in available information.
   • Outcome/Current Status: US case filed.

Proceedings overview

There is one AIA trial proceeding on file for US Patent 7629634. This proceeding resulted in a discretionary denial, meaning no claims were invalidated. This gives a defendant a stronger defensive posture against challenges based on the grounds presented in that specific IPR, as the patent owner prevailed at the institution stage.

IPR2025-01433 — Excelliance Mos Corporation v. FORCE MOS TECHNOLOGY Co Ltd

• Type: Inter Partes Review
• Filed: 2025-08-15
• Status: Discretionary Denial (The petition was not instituted, and thus no trial was formally commenced or claims adjudicated on the merits).
• Judge panel: Administrative Patent Judges John M. Dellera, Jeffrey P. Aronson, and Elizabeth A. Winston.
• Petition grounds: The petition challenged claims 1-9 of U.S. Patent No. 7,629,634. The grounds were based on obviousness under 35 U.S.C. § 103, relying on combinations of prior art references including US 6,888,196 to Kawamura et al. ("Kawamura") and US 6,107,665 to Kim et al. ("Kim").
• Institution decision: Denied on 2026-02-14. The panel exercised its discretion to deny institution under 35 U.S.C. § 314(a) based on its analysis of the Fintiv factors, specifically noting the advanced stage of parallel district court litigation between the same parties involving the same patent. The Board found that the petitioner had not demonstrated that institution was warranted despite the stage of the district court proceeding.
• Final Written Decision (if issued): Not applicable, as the petition was denied institution.
• Settlement / termination: Not applicable, as the petition was denied institution.
• Appeal: The Board's decision denying institution was affirmed by the Federal Circuit on 2026-03-12.
• Defensive value: The discretionary denial means claims 1-9 of the patent have withstood a challenge under specific prior art combinations at the institution stage of an IPR. Any future IPR challenging these same claims using the same prior art grounds, or grounds that reasonably could have been raised, would face estoppel challenges. However, the claims were not adjudicated on the merits, so they were not "sustained" in the sense of surviving a full trial.

Strategic summary

All nine claims (claims 1-9) of US Patent 7629634 remain untested on their merits at the PTAB. In IPR2025-01433, Excelliance Mos Corporation challenged claims 1-9, but the petition was denied institution due to the Fintiv factors, which consider the status of parallel district court litigation. This means the PTAB did not reach the merits of whether the claims were unpatentable.

Estoppel landscape: For Excelliance Mos Corporation (and its privies), 35 U.S.C. § 315(e)(2) estoppel would apply to any ground raised or that reasonably could have been raised in IPR2025-01433. Since the institution was denied on Fintiv grounds rather than on the merits, the scope of estoppel might be debated, but generally, a denial of institution can still trigger estoppel, especially if the denial was not purely procedural but involved some review of the merits for institution purposes. The specific prior art combinations (Kawamura and Kim) used to challenge claims 1-9 are likely barred for Excelliance Mos and its privies. Other potential petitioners would still be able to raise these and other prior-art grounds.

Pattern signals: The patent owner, FORCE MOS TECHNOLOGY Co Ltd, successfully defended against the institution of IPR2025-01433. The appeal to the Federal Circuit and its affirmation of the denial indicates the patent owner is actively defending the patent through the PTAB and appellate processes. Unified Patents is listed as a source of litigation data for other cases, but the petitioner in this IPR was Excelliance Mos Corporation, not Unified Patents directly.

Recommended next steps

If facing assertion of US76296634 today, a defendant should note that no claims have been invalidated by the PTAB. The denial of IPR2025-01433 was discretionary, based on parallel district court litigation, rather than a determination on the merits of the patentability challenges. This means:

• Review the IPR2025-01433 Institution Decision: Obtain and thoroughly review the "Decision Denying Institution of Inter Partes Review" for IPR2025-01433, dated 2026-02-14, available on the USPTO PTAB Decisions website. This will detail the specific arguments made by Excelliance Mos Corporation and the PTAB's reasoning for the Fintiv denial.
• Assess new IPR possibilities: Given that the claims were not adjudicated on the merits, a new IPR petition by a different entity (or the same entity with new, non-estoppel grounds) might be considered. This would require careful analysis of the prior art and whether new grounds exist that were not (or could not reasonably have been) raised in IPR2025-01433.
• Monitor for future activity: Stay vigilant for any new IPR or PGR filings against US7629634, as the legal status shows ongoing litigation in various district courts.

Inventors

• Fu-Yuan Hsieh. Employer at time of filing: FORCE MOS TECHNOLOGY Co Ltd.

Original assignee

FORCE MOS TECHNOLOGY Co Ltd. Their primary line of business is semiconductor devices, specifically trenched MOSFETs, as described in the patent. It is unclear if they shipped a product embodying the claims based solely on the patent text. Their current status is unclear based on the provided patent text and Google Patents information.

Assignment timeline

• 2008-02-23 (executed) / recorded 2008-02-23 — Reel 020549/0022
  • Conveyance: Assignment
  • Assignor: TSIEH, FU-YUAN
  • Assignee: FORCE MOS TECHNOLOGY CO. LTD.
  • Correspondent: Not specified in the provided text.
  • Context: Original assignment from inventor to company.

The USPTO Assignment Center search (https://assignmentcenter.uspto.gov/) shows no further recorded assignments for US Patent 7629634 beyond the initial assignment from the inventor to Force MOS Technology Co. Ltd.

Timeline diagram

timeline
    title Ownership of US 7629634
    2008 : Filed by Force MOS Technology Co. Ltd.
    2009 : Issued

NPE / troll-pattern signals

1. Shell-entity transfer — not present. The sole recorded assignment is from the inventor to the original assignee, an operating company.
2. Known asserter in the chain — not present. Force MOS Technology Co. Ltd. is not listed as a known NPE.
3. Repeat correspondent across the chain — not present. There is only one recorded assignment from the inventor, and no correspondent information is provided in the patent for this specific entry.
4. Cascading transfers — not present. No subsequent assignments are recorded.
5. Pre-litigation transfer — not present. No subsequent assignments are recorded.
6. Bankruptcy fire-sale — unclear. While the current status of the original assignee is not explicitly stated as "operating," there is no evidence of a bankruptcy or associated patent sale.
7. Privateering — not present. No evidence of transfer to an NPE for assertion.
8. Defensive aggregator (anti-NPE) — not present. The patent is not currently assigned to a defensive aggregator.

Verdict

Insufficient data. There is only one recorded assignment, which is the initial transfer from the inventor to the original assignee, Force MOS Technology Co. Ltd. This does not provide enough information to identify any NPE or patent-troll patterns.

USPTO Assignment Center search: https://assignmentcenter.uspto.gov/

To identify the most relevant prior art for US patent 7,629,634, I will examine the patent citations listed within the patent document itself. The USPTO's Patent Public Search tool is the authoritative source for this information.

The full patent text of US7629634B2 explicitly cites one prior art patent: US6888196B2.

Here's the analysis of that prior art reference:

Full Citation: US6888196B2: Vertical MOSFET reduced in cell size and method of producing the same.
Publication Date: 2005-05-03
Filing Date: 2002-04-24
Assignee: Nec Electronics Corporation

Brief Description:
US6888196B2 describes a vertical MOSFET structure designed to reduce cell size. It focuses on a trench gate field effect transistor and its manufacturing method. The patent details a structure that includes a semiconductor substrate, an epitaxial layer, a body region, and a source region, with trench gates extending through the body and source regions into the epitaxial layer. It also describes source contact regions. The invention aims to reduce the on-resistance and improve switching characteristics by optimizing the cell layout and structure, potentially through techniques like self-aligned contacts and specific doping profiles.

Potential Anticipation under 35 U.S.C. § 102:
US6888196B2 potentially anticipates aspects of Claim 1 and Claim 6 of US7629634B2.

• Claim 1: This prior art discloses many elements recited in Claim 1, such as a semiconductor region with a silicon substrate, epitaxial layer (drain), base layer (body), and source layer, stacked in sequence. It also describes front and back metal layers, trenched gates extending into the epitaxial layer, and source contact trenches. The key distinguishing feature of US7629634B2's Claim 1 is the presence of a "lateral contact layer" at the sidewalls of the source contact trenches and a "base contact layer" at the bottom of these trenches. The description of US6888196B2 would need to be thoroughly reviewed to determine if any elements, even implicitly, describe or suggest such distinct lateral and base contact layers within the source contact trenches that would perform the same function, particularly in terms of improving ohmic contact and ruggedness, as described in US7629634B2. Without explicit disclosure of such distinct, specifically doped lateral and base contact layers in US6888196B2, it is unlikely to directly anticipate this novel aspect of Claim 1.

• Claim 6: Similar to Claim 1, US6888196B2 would likely disclose the general inverted doping types (P-type substrate, epitaxial, source; N-type base and lateral contact). However, the specific arrangement and doping concentrations of the N-type lateral contact layer and N-type base contact layer, particularly the distinction in doping concentration between them (lateral having less doping than the bottom base contact layer), would be critical for anticipation. If US6888196B2 does not explicitly disclose or suggest this differentiated doping for distinct lateral and base contact layers in the source trenches, it would not anticipate this claim element.

The inventive step of US7629634B2, as highlighted in its description, is providing a lateral contact layer in the MOSFET for avalanche improvement, specifically addressing the poor ohmic contact at the sidewall of source contact trenches in prior art, which led to poor ruggedness and parasitic bipolar turn-on. Therefore, the novelty of US7629634B2 largely hinges on the specific structure and doping of this lateral contact layer to achieve improved ohmic contact and reduced base resistance.

Obviousness Analysis of US Patent 7,629,634 under 35 U.S.C. § 103

This section analyzes the obviousness of US Patent 7,629,634, focusing on combinations of prior art references that would render the claims obvious to a person having ordinary skill in the art (POSITA), along with the motivation to combine them. The key inventive feature of US 7,629,634, as highlighted in the abstract and claims, is the presence of a "lateral contact layer" at the sidewalls of the source contact trenches. This aims to improve ohmic contact and ruggedness during UIS tests by reducing parasitic bipolar turn-on.

Prior Art References Identified in US 7,629,634

The patent itself references US 6,888,196 B2 (Nec Electronics Corporation) as a conventional vertical MOSFET, noting that prior art typically only has a P+-type region at the source contact trench bottom, lacking ohmic contact on the sidewalls.

Additional prior art that discusses trench MOSFET structures and their manufacturing include:

• US 2010/0127323 A1 (Force Mos Technology Co. Ltd.): This application, filed by the same assignee, discusses prior art MOSFET structures, including an N+ substrate, N-doped epitaxial layer, trench gates, P-body regions, and N+ source regions. It highlights the need for lower spreading resistance, smaller size, and reduced fabricating cost in trench MOSFETs. While this is a later publication than US7629634, it describes existing trench MOSFET structures that would have been known to a POSITA at the time of US7629634's filing.
• US 2004/0021173 A1 (American Philips Corporation): This patent application describes a MOSFET with a gate trench and a source trench, where the source trench is laterally spaced from the gate trench. It also describes a metal layer along the top surface contacting source regions, conductive material in source trenches, and body regions through P+ regions.
• US 7,629,646 B2 (Fwu-Iuan Hshieh / Force Mos Technology Co. Ltd.): This patent, also by an inventor and assignee related to US 7,629,634, describes a trench MOSFET with an epitaxial layer, trenches, oxide layers, P-type doping regions (P-body), N+ doping regions (N+ source), and a P+ doping region at the bottom of the trench contact for ohmic contact to the P-body.

Obviousness Combinations

Combination 1: US 6,888,196 B2 in view of the general knowledge of improving ohmic contact in semiconductor devices.

• Rationale: US 6,888,196 B2, as acknowledged by US 7,629,634, depicts a conventional trenched MOSFET where the P+-type region is located only at the source contact trench bottom, leading to poor ruggedness due to a lack of ohmic contact on the sidewall. A POSITA would be aware that good ohmic contact is crucial for device performance and reliability. Techniques for improving ohmic contact in semiconductor devices, such as increasing doping concentration in contact regions or forming highly doped layers at contact interfaces, were well-known in the art. The motivation to apply such a known technique to the sidewalls of the source contact trench in a MOSFET structure like that of US 6,888,196 B2 would be to address the recognized problem of poor ruggedness and parasitic bipolar turn-on, as explicitly stated in US 7,629,634. Forming a lateral contact layer with a doping concentration sufficient to achieve ohmic contact, but not so high as to significantly affect threshold voltage, would be an obvious design choice for a POSITA seeking to improve the device's avalanche performance.

Combination 2: US 2004/0021173 A1 in view of the need for improved contact and reduced resistance in trench MOSFETs.

• Rationale: US 2004/0021173 A1 describes a MOSFET with both gate and source trenches, and a metal layer making contact with source regions, conductive material in source trenches, and body regions through P+ regions. While it doesn't explicitly detail a lateral contact layer for the sidewalls of the source trench, it demonstrates the concept of using highly doped regions (P+ regions) to ensure good contact with the body region within the vicinity of the source trench. A POSITA seeking to further optimize the contact between the source metal and the body region in a trench MOSFET, particularly to reduce base resistance (Rp) and improve avalanche capability as motivated by the problems described in US 7,629,634, would consider extending or modifying the existing highly doped contact regions. Given the general objective of reducing resistance in trench MOSFETs, as also discussed in US 2010/0127323 A1, it would be obvious to a POSITA to introduce a lateral doped layer along the sidewall of the source contact trench, similar to the P*-type lateral contact layer of US 7,629,634, to ensure more complete and robust ohmic contact with the metal plug.

Motivation to Combine:

The primary motivation for a POSITA to combine these elements would be to improve the ruggedness and avalanche capability of trenched MOSFETs by establishing robust ohmic contact between the source metal and the P-type base layer. The prior art, including the device depicted in FIG. 1 of US 7,629,634, clearly identifies the problem of poor ohmic contact at the sidewalls of the source contact trench due to low doping concentration of the P-base, leading to the undesirable turn-on of a parasitic N+/P/N bipolar transistor during UIS tests. This problem would drive a POSITA to explore methods to enhance the contact in this critical region.

Furthermore, the general trend in MOSFET development, as indicated by references like US 2010/0127323 A1, is towards achieving lower resistance and smaller device sizes. A lateral contact layer contributes to both these goals by ensuring a more effective current path and preventing device degradation. The knowledge of doping techniques for forming highly conductive regions in semiconductors, combined with the recognized shortcomings of prior art trenched MOSFETs, would lead a POSITA to implement a lateral contact layer as claimed in US 7,629,634.