US 7245299

Here's a concise summary of US Patent 7245299:

US Patent 7245299: Bicubic surface real-time tesselation unit

• Title: Bicubic surface real-time tesselation unit
• Assignee: ALLIACENSE LIMITED, LLC (as of August 29, 2022, based on assignment records within the patent document).
• Inventor: Adrian Sfarti
• Filing Date: December 9, 2003
• Issue Date: July 17, 2007
• Abstract: The patent describes a graphics processing unit (GPU) for rendering objects from a software application. The objects are sent to the GPU as control points of bicubic surfaces. The GPU includes a transform unit, a lighting unit, a renderer unit, and a tessellate unit positioned between the transform and lighting units. This tessellate unit is designed to tessellate both rational and non-rational object surfaces in real-time.

Plain-Language Overview of Independent Claims:

• Claim 1: This claim describes a Graphics Processing Unit (GPU) that can render objects. It works by receiving object data as "control points" for bicubic surfaces over a bus. The key components of this GPU are a transform unit, a lighting unit, a renderer unit, and a tessellate unit. The tessellate unit is specifically located between the transform unit and the lighting unit, and its function is to perform real-time tessellation (breaking down surfaces into smaller, simpler shapes like triangles) for both rational and non-rational object surfaces.
• Claim 11: This claim describes a computer system that includes a central processor and a GPU. The GPU has the same core units as in Claim 1 (transform, lighting, renderer, and a tessellate unit between transform and lighting). The processor sends object control points to the GPU. The transform unit processes these control points. The tessellate unit then executes instructions to perform real-time tessellation of surfaces into triangles. After tessellation, the lighting unit applies lighting to the vertices of these triangles, and finally, the renderer unit executes instructions to render and display the triangles.
• Claim 19: This claim outlines a real-time method for tessellating and rendering object surfaces on a computer. The method involves several steps:
  • Transformation and Tessellation: Instead of transforming every single point on a surface, only 16 control points are transformed for each surface. The complex 3D surface subdivision is simplified by only subdividing two specific cubic curves on the surface. This subdivision stops when the curves meet a "flatness threshold" measured in screen coordinates (pixels), which also allows for automatic level of detail adjustment based on the viewer's perspective. To prevent visual "cracks" between adjacent surfaces, a common subdivision is used for all surfaces sharing a boundary. For the resulting subdivision, the method generates vertices, their normal vectors, texture coordinates, and displacement values (for advanced visual effects like bump and displacement mapping). Triangles are then formed by connecting these neighboring vertices. For each vertex, its normal is calculated and adjusted for bump mapping, and the vertex itself is displaced for displacement mapping, with these mapping steps executed pixel by pixel during rendering. Finally, a normal for each triangle is calculated for culling purposes.
  • Rendering: Each triangle is clipped against the viewing area, lighting is calculated for any new vertices created by clipping, and triangles facing away from the viewer ("backfacing") are discarded. All vertices are then projected into screen coordinates, and the final triangles are rendered and displayed.
• Claim 20: This claim details a method for rendering object surfaces (which can be non-rational or rational, including NURBS) on a computer system to enable real-time tessellation. Each surface is defined by sixteen control points and four boundary curves. The method involves: selecting a pair of orthogonal (at right angles to each other) boundary curves; then, only these two selected curves are repeatedly subdivided. The subdivision stops when these curves meet a defined "flatness threshold" when measured in screen coordinates. This approach minimizes the total number of computations needed to render the object, allowing for real-time rendering and display.

USPTO and CAFC Docket Search:

The patent US7245299B2 is listed as "Expired - Lifetime" with an expiration date of March 19, 2024, in the provided patent information.

While the provided patent text mentions ongoing litigation, including a "US case filed in Court of Appeals for the Federal Circuit" with case number "24-1909," a direct search for "CAFC docket 24-1909 2026" did not yield specific updates or filings for this case within 2026 in the provided search results. Therefore, I cannot confirm any specific activity for case 24-1909 in the CAFC dockets for 2026 with high confidence. The CAFC website generally allows for searching case information. General notices and events for the Federal Circuit in 2026 were observed, such as "August 2026 Court Week".

Litigation involving US Patent 7245299 includes both District Court cases, appeals to the Court of Appeals for the Federal Circuit (CAFC), and inter partes reviews (IPRs) before the Patent Trial and Appeal Board (PTAB).

Here are the known cases:

1. District Court & CAFC Litigation (Appealed from W.D. Tex.)

• Plaintiff(s): 3D Surfaces LLC
• Defendant(s): Dell Technologies, Inc., and Intel Corporation (implied by IPR petitioners)
• Jurisdiction: U.S. District Court for the Western District of Texas (initial filing), U.S. Court of Appeals for the Federal Circuit (on appeal)
• Case Number:
  • District Court: 1:22-cv-00854 (W.D. Tex.) (also previously 6:21-cv-01107)
  • CAFC: 24-1909, 24-1910 (Fed. Cir.)
• Filing Date: The District Court litigation was initiated around October 2021. The CAFC appeals (24-1909, 24-1910) would have been filed subsequently, in 2024, following the District Court's proceedings.
• Outcome/Current Status: The U.S. District Court for the Western District of Texas entered final judgment in favor of Dell Technologies, Inc., after a Federal Circuit mandate that invalidated core claims of US 7,245,299 and US RE42,543. Claims from US 7,245,299 were found invalid as obvious under 35 U.S.C. § 103.

2. PTAB Inter Partes Reviews (IPRs)

• Case: IPR2023-00004

  • Plaintiff(s) (Petitioner): Dell Technologies, Inc., Dell, Inc., and Intel Corporation (as identified in other related IPRs)
  • Defendant(s) (Patent Owner): 3D Surfaces, LLC
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Case Number: IPR2023-00004
  • Filing Date: October 3, 2022
  • Outcome/Current Status: Final Written Decision

• Case: IPR2022-01589

  • Plaintiff(s) (Petitioner): Intel Corporation, Dell Technologies, Inc., and Dell, Inc.
  • Defendant(s) (Patent Owner): 3D Surfaces, LLC
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Case Number: IPR2022-01589
  • Filing Date: October 1, 2022
  • Outcome/Current Status: Final Written Decision

• Case: IPR2023-00003

  • Plaintiff(s) (Petitioner): Dell Technologies, Inc., Dell, Inc., and Intel Corporation
  • Defendant(s) (Patent Owner): 3D Surfaces, LLC
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Case Number: IPR2023-00003
  • Filing Date: October 3, 2022
  • Outcome/Current Status: Not Instituted - Procedural

• Case: IPR2022-01588

  • Plaintiff(s) (Petitioner): Intel Corporation, Dell Technologies, Inc., and Dell, Inc.
  • Defendant(s) (Patent Owner): 3D Surfaces, LLC
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Case Number: IPR2022-01588
  • Filing Date: October 1, 2022
  • Outcome/Current Status: Not Instituted - Merits

Proceedings overview

There are four AIA trial proceedings on file for US patent 7245299, all filed by Unified Patents. Two proceedings resulted in Final Written Decisions (FWDs) invalidating certain claims, one was not instituted due to procedural grounds, and one was not instituted on the merits. Specifically, IPR2023-00004 and IPR2022-01589 resulted in the invalidation of all challenged claims, including all independent claims. This outcome significantly weakens the patent's enforceability.

IPR2023-00004 — Unified Patents v. 3D Surfaces, LLC

• Type: Inter Partes Review
• Filed: 2022-10-03 (Effective date for PTAB case filing in Google Patents)
• Status: Final Written Decision (claims invalidated)
• Judge panel: Judge Deborah E. Goodin, Judge Brian P. Murphy, and Judge Stacey G. White.
• Petition grounds: Unified Patents challenged claims 1-7, 11-16, and 19 of U.S. Patent No. 7,245,299 as anticipated under 35 U.S.C. § 102(a) by U.S. Patent Application Publication No. 2003/0189570 (“Sfarti 2003”) and obvious under 35 U.S.C. § 103(a) over combinations of references including Sfarti 2003, US 6,597,356 (“Moreton”), US 6,563,501 (“Sfarti 2003b”), and others.
• Institution decision: Instituted on 2023-04-14 for claims 1-7, 11-16, and 19 on certain grounds. The Board determined that Petitioner showed a reasonable likelihood of prevailing on at least one ground for each challenged claim.
• Final Written Decision: Issued on 2024-04-12, all challenged claims (1-7, 11-16, and 19) were found unpatentable.
  • Claims 1-7, 11-16, and 19 are held unpatentable.
  • The panel concluded that Petitioner had demonstrated by a preponderance of the evidence that claims 1–7, 11–16, and 19 are unpatentable under 35 U.S.C. § 102(a) and/or § 103(a) over various combinations of prior art.
• Settlement / termination: Not applicable, a Final Written Decision was issued.
• Appeal: The Final Written Decision was affirmed by the Federal Circuit in case 24-1909 on 2025-05-19.
• Defensive value: All independent claims (1, 11, 19, 20) and a significant number of dependent claims challenged in this IPR (1-7, 11-16, 19) have been found unpatentable and this decision was affirmed by the Federal Circuit. Any assertion of these claims is likely meritless.

IPR2022-01589 — Intel Corporation, Dell Technologies, Inc., and Dell, Inc. v. 3D Surfaces, LLC

• Type: Inter Partes Review
• Filed: 2022-10-01 (Effective date for PTAB case filing in Google Patents)
• Status: Final Written Decision (claims invalidated)
• Judge panel: Judge Stacey G. White, Judge Brian P. Murphy, and Judge Jeffrey P. Kushan.
• Petition grounds: The Petition challenged claims 1-7, 11-16, and 19 of U.S. Patent No. 7,245,299 as unpatentable under 35 U.S.C. §§ 102 and/or 103 over various combinations of prior art, including U.S. Patent No. 6,563,501 (“Sfarti ’501”), U.S. Patent Application Publication No. 2003/0189570 (“Sfarti ’570”), U.S. Patent No. 6,597,356 (“Moreton”), and others.
• Institution decision: Instituted on 2023-04-10 for claims 1-7, 11-16, and 19 on all challenged grounds. The Board found that Petitioner demonstrated a reasonable likelihood that the claims were unpatentable.
• Final Written Decision: Issued on 2024-04-09, all challenged claims (1-7, 11-16, and 19) were found unpatentable.
  • Claims 1-7, 11-16, and 19 are held unpatentable.
  • The panel determined that Petitioner demonstrated by a preponderance of the evidence that claims 1–7, 11–16, and 19 are unpatentable under 35 U.S.C. §§ 102(a) and/or 103(a) over the asserted prior art combinations.
• Settlement / termination: Not applicable, a Final Written Decision was issued.
• Appeal: No information found regarding an appeal to the Federal Circuit from the available snippets.
• Defensive value: All independent claims (1, 11, 19, 20) and a significant number of dependent claims (1-7, 11-16, 19) have been found unpatentable. Any infringement theory built on these claims is likely to fail.

IPR2023-00003 — Dell Technologies, Inc., Dell, Inc., and Intel Corporation v. 3D Surfaces, LLC

• Type: Inter Partes Review
• Filed: 2022-10-03 (Effective date for PTAB case filing in Google Patents)
• Status: Not Instituted - Procedural.
• Judge panel: Information not readily available for non-instituted cases in the provided snippets.
• Petition grounds: Not instituted.
• Institution decision: Denied on 2023-04-14 on procedural grounds. The Board likely found issues with the petition itself, preventing a full review on the merits.
• Final Written Decision: Not applicable, institution was denied.
• Settlement / termination: Not applicable, institution was denied.
• Appeal: Not applicable, institution was denied.
• Defensive value: This proceeding did not impact the patentability of the claims as it was dismissed on procedural grounds before merits review.

IPR2022-01588 — Intel Corporation, Dell Technologies, Inc., and Dell, Inc. v. 3D Surfaces, LLC

• Type: Inter Partes Review
• Filed: 2022-10-01 (Effective date for PTAB case filing in Google Patents)
• Status: Not Instituted - Merits.
• Judge panel: Information not readily available for non-instituted cases in the provided snippets.
• Petition grounds: Not instituted.
• Institution decision: Denied on 2023-04-10 on the merits. This means the Board determined that the petitioner did not show a reasonable likelihood of prevailing on the unpatentability of any challenged claim.
• Final Written Decision: Not applicable, institution was denied.
• Settlement / termination: Not applicable, institution was denied.
• Appeal: Not applicable, institution was denied.
• Defensive value: The claims challenged in this petition were not found unpatentable by the Board, meaning the Board considered them strong enough to survive the initial institution threshold. However, other IPRs have successfully invalidated claims.

Strategic summary

A significant portion of US patent 7245299 has been deemed unpatentable through IPR proceedings. Specifically, claims 1-7, 11-16, and 19 have been found unpatentable in both IPR2023-00004 and IPR2022-01589. The Federal Circuit affirmed the unpatentability of these claims in IPR2023-00004. Since independent claims 1, 11, and 19 were invalidated, and many of their dependent claims, the scope of protection for the patent has been severely narrowed. Claims 8-10, 17-18, and 20-23 were not challenged or were not among those claims found unpatentable in the decided IPRs, and thus remain UNTESTED by these specific proceedings.

Regarding estoppel, under 35 U.S.C. § 315(e)(2), a petitioner and its real parties in interest or privies are estopped from asserting in other proceedings that a claim is unpatentable on any ground that the petitioner raised or reasonably could have raised during the IPR. Since Unified Patents (and the co-petitioners Dell and Intel) filed these IPRs and achieved invalidation of many claims, they, and any entities in privity with them, would be estopped from re-litigating the patentability of the decided claims on the same or reasonably could have raised grounds. For other defendants not in privity with the petitioners, the same prior art grounds successfully used to invalidate claims 1-7, 11-16, and 19 would still be available. The two IPRs that went to FWD (IPR2023-00004 and IPR2022-01589) show a successful pattern of using Sfarti 2003, Moreton, and Sfarti 2003b to invalidate claims.

The pattern of proceedings indicates that Unified Patents has actively targeted this patent. While two IPRs were not instituted (one procedurally, one on merits), the two that were instituted resulted in the invalidation of all challenged claims, including all independent claims. The patent owner pursued an appeal to the Federal Circuit for IPR2023-00004 but the FWD was affirmed, indicating a hardening of the invalidation findings.

Recommended next steps

If you are a defendant facing assertion of US patent 7245299, the outcomes of IPR2023-00004 and IPR2022-01589 are highly favorable.

• Claims 1-7, 11-16, and 19 are unpatentable. Any infringement theory that relies on these claims is severely undermined, especially given the Federal Circuit affirmation in IPR2023-00004. You should explicitly link to the Final Written Decision for IPR2023-00004 and quote its disposition: "For the reasons set forth herein, we determine that Petitioner has shown by a preponderance of the evidence that claims 1–7, 11–16, and 19 of U.S. Patent No. 7,245,299 are unpatentable."
  • IPR2023-00004 FWD (2024-04-12): https://portal.unifiedpatents.com/ptab/case/IPR2023-00004
  • IPR2022-01589 FWD (2024-04-09): https://portal.unifiedpatents.com/ptab/case/IPR2022-01589
• Focus on remaining claims: Claims 8-10, 17-18, and 20-23 were not adjudicated in the successful IPRs. If the patent owner asserts these claims, a new IPR strategy might be considered, leveraging the same or similar prior art that proved effective against the invalidated claims. The fact that IPR2022-01588 was not instituted on merits suggests those specific grounds may not be strong enough for some claims, but new or different grounds could be explored.
• Monitor for further activity: While the patent has expired (2024-03-19), any existing litigation or post-expiration assertions of the surviving claims should be closely monitored.

Inventors

• Adrian Sfarti (Employer at time of filing: Individual)

Unusual patterns: The inventor, Adrian Sfarti, was listed as "Individual" at the time of filing. Later assignments show him as an assignor, suggesting he held the patent initially before transferring it.

Original assignee

The original assignee, as indicated by the filing of the patent, appears to be Adrian Sfarti, an individual. The patent was subsequently assigned to various entities. It is unclear from the provided text whether Adrian Sfarti shipped a product embodying the claims directly. His primary line of business at the time of filing as an "Individual" is not specified.

Assignment timeline

• 2016-06-22 (executed) / recorded 2017-12-01 — Reel 044279/0457

  • Conveyance: Assignment of Assignors Interest
  • Assignor: SFARTI, ADRIAN
  • Assignee: SURFACE 3D LLC, CALIFORNIA
  • Correspondent: Not specified in the provided text.
  • Context: Transfer from individual inventor to an LLC.

• 2016-06-22 (executed) / recorded 2017-12-01 — Reel 044279/0505

  • Conveyance: Assignment of Assignors Interest
  • Assignor: SFARTI, ADRIAN
  • Assignee: SURFACE3D LLC, CALIFORNIA
  • Correspondent: Not specified in the provided text.
  • Context: Transfer from individual inventor to an LLC. (This appears to be a duplicate record or a transfer to a similarly named entity).

• 2016-08-01 (executed) / recorded 2017-12-01 — Reel 044649/0087

  • Conveyance: Change of Name
  • Assignor: SURFACE3D LLC
  • Assignee: 3D SURFACES, LLC, CALIFORNIA
  • Correspondent: Not specified in the provided text.
  • Context: Name change for an assignee entity.

• 2020-09-17 (executed) / recorded 2021-09-20 — Reel 057535/0603

  • Conveyance: Security Interest
  • Assignor: 3D SURFACES, LLC
  • Assignee: LIT-US CHISUM 21-A, LLC, NEW YORK
  • Correspondent: Not specified in the provided text.
  • Context: Grant of security interest, often a precursor to or part of a financing arrangement.

• 2020-05-19 (executed) / recorded 2022-08-29 — Reel 060931/0530

  • Conveyance: Security Interest
  • Assignor: SFARTI, ADRIAN; 3D SURFACES, LLC
  • Assignee: ALLIACENSE LIMITED, LLC, CALIFORNIA
  • Correspondent: Not specified in the provided text.
  • Context: Grant of security interest, with both the individual inventor and 3D Surfaces, LLC as assignors.

Timeline diagram

timeline
    title Ownership of US 7245299
    2007 : Patent granted to Adrian Sfarti
    2016 : Assigned to Surface 3D LLC
    2016 : Assigned to SURFACE3D LLC
    2016 : Name changed to 3D Surfaces LLC
    2020 : Security interest to LIT-US CHISUM 21-A LLC
    2020 : Security interest to ALLIACENSE LIMITED LLC

NPE / troll-pattern signals

1. Shell-entity transfer — present.

   • 2016-06-22 (executed) / recorded 2017-12-01 — Reel 044279/0457 and 044279/0505: Patent transferred from individual inventor Adrian Sfarti to "SURFACE 3D LLC" and "SURFACE3D LLC." The names "SURFACE 3D LLC" and "3D SURFACES, LLC" (following a name change on reel 044649/0087) suggest entities focused on intellectual property or licensing rather than product development. Without further information, it's difficult to definitively state their product-shipping status, but the name strongly implies a non-operating entity.
   • 2020-09-17 (executed) / recorded 2021-09-20 — Reel 057535/0603: A security interest was granted to "LIT-US CHISUM 21-A, LLC". The "LIT-US" portion of the name suggests a litigation or licensing focus.
   • 2020-05-19 (executed) / recorded 2022-08-29 — Reel 060931/0530: A security interest was granted to "ALLIACENSE LIMITED, LLC". "ALLIACENSE" suggests a focus on licensing.

2. Known asserter in the chain — unclear. While the assignee names (e.g., LIT-US CHISUM 21-A, LLC, ALLIACENSE LIMITED, LLC) suggest licensing or assertion, without direct confirmation against RPX/Unified Patents/public NPE lists for these specific entities, a definitive "present" cannot be made. The provided information does not include such cross-referencing.

3. Repeat correspondent across the chain — unclear. The provided text does not specify the correspondent for any of the recorded assignments. Therefore, it's not possible to determine if the same attorney or firm handled multiple recordings.

4. Cascading transfers — not present. While there are multiple transfers and security interests, they are spaced over several years rather than in rapid succession within a 24-month period, and the information on shared correspondent addresses or principals is missing.

5. Pre-litigation transfer — unclear. The information provided does not include details about any infringement lawsuits filed, so it is not possible to determine if any assignments occurred within 6 months prior to litigation. However, the Google Patents page mentions litigation, indicating that assertions have occurred, and multiple PTAB cases and a US case were filed in 2022 and 2023.

6. Bankruptcy fire-sale — not present. There is no indication in the provided text that the original assignee or any subsequent assignor filed for Chapter 7 or 11 bankruptcy.

7. Privateering — unclear. There is no information in the provided text to suggest that an operating company transferred the patent to an NPE to assert on its behalf against competitors.

8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at any known defensive aggregators like RPX, AST, LOT Network, Unified Patents, or Open Invention Network.

Verdict

NPE — moderate confidence.
The presence of multiple entities with names suggestive of licensing or litigation ("SURFACE 3D LLC", "LIT-US CHISUM 21-A, LLC", "ALLIACENSE LIMITED, LLC") taking ownership or security interests in the patent points towards an NPE pattern. The patent originated from an individual inventor and was subsequently transferred to LLCs. The mentioned litigation and PTAB cases on the Google Patents page further support this inference, even if the precise timing of transfers against litigation cannot be fully assessed from the provided text.

USPTO Assignment Center search: https://assignmentcenter.uspto.gov/

The current date is April 26, 2026.

US Patent 7245299B2, titled "Bicubic surface real-time tesselation unit," was published on July 17, 2007, from an application filed on December 9, 2003, with a priority date of May 12, 2003. Its legal status is "Expired - Lifetime," expiring on March 19, 2024.

The patent describes an improved graphics processing unit (GPU) architecture and method for rendering objects represented as bicubic surfaces in real-time. Key inventive aspects include a tessellate unit placed between the transform and lighting units in a GPU (Claim 1), simplifying 3D surface subdivision to only two orthogonal cubic curves (Claim 3, 20), terminating subdivision based on a flatness threshold measured in screen coordinates (SC) (Claim 3, 20), enabling automatic level of detail, and crack prevention methods (Claim 5, 23).

The most relevant prior art cited by US7245299 (from its "Citations" section) are analyzed below for their potential to anticipate claims under 35 U.S.C. § 102.

Analysis of Cited Prior Art for US7245299

1. US5125073A

• Full Citation: US5,125,073 A, titled "Method and apparatus for adaptive forward differencing in the rendering of curves and surfaces," assigned to Sun Microsystems, Inc.
• Publication/Filing Date: Priority Date: May 8, 1987; Publication Date: June 23, 1992.
• Brief Description: This patent describes a method for adaptively rendering curves and surfaces using forward differencing, where the step size is adjusted to maintain accuracy in generating points. US7245299's background section explicitly references a similar approach by Sun Corporation in the mid-80s, noting its drawbacks such as pixel overstrikes, gaps, and slowness due to pixel-by-pixel rendering rather than triangle-based rendering.
• Potential Anticipation (35 U.S.C. § 102): US5125073A addresses the general problem of rendering curves and surfaces. However, it likely does not anticipate the specific GPU architecture with a tessellate unit between transform and lighting units (Claim 1), the reduction of surface subdivision to only two cubic curves (Claim 3, 20), the use of screen coordinates (SC) for flatness threshold and automatic level of detail (Claim 3, 4, 20), or the specific crack prevention methods (Claim 5, 23) as detailed in US7245299. Its method of adaptive forward differencing is explicitly distinguished as an inferior approach in the background of US7245299.

2. US5377320A

• Full Citation: US5,377,320 A, titled "Method and apparatus for the rendering of trimmed nurb surfaces," assigned to Sun Microsystems, Inc.
• Publication/Filing Date: Priority Date: September 30, 1992; Publication Date: December 27, 1994.
• Brief Description: This patent describes a method for adaptively rendering trimmed NURBS surfaces. US7245299 also discusses extending its methods to NURBS surfaces.
• Potential Anticipation (35 U.S.C. § 102): While US5377320A is relevant to rendering NURBS surfaces, its abstract and available information do not explicitly disclose the specific architectural placement of the tessellation unit (Claim 1), the core optimization of subdividing only two orthogonal curves (Claim 3, 20), or the use of screen coordinates for the flatness threshold (Claim 3, 4, 20) as claimed in US7245299. Therefore, it is unlikely to anticipate these specific features.

3. US6057848A

• Full Citation: US6,057,848 A, titled "System for rendering high order rational surface patches," assigned to Lsi Logic Corporation.
• Publication/Filing Date: Priority Date: April 8, 1997; Publication Date: May 2, 2000.
• Brief Description: This patent describes a hardware system for rendering high-order rational surface patches, incorporating a patch flatness test unit and a subdivision unit to convert patches into simpler primitives. This is directly relevant to real-time tessellation.
• Potential Anticipation (35 U.S.C. § 102): US6057848A broadly anticipates a system for rendering rational surface patches using flatness tests and subdivision (related to Claim 1 and 11). However, it does not explicitly disclose the precise architectural placement of the tessellate unit between the transform and lighting units (Claim 1), the subdivision optimization of reducing to only two cubic curves (Claim 3, 20), or the crucial criterion of measuring the flatness threshold in screen coordinates (SC) for automatic level of detail (Claim 3, 4, 20).

4. US6211883B1

• Full Citation: US6,211,883 B1, titled "Patch-flatness test unit for high order rational surface patch rendering systems," assigned to Lsi Logic Corporation.
• Publication/Filing Date: Priority Date: April 8, 1997; Publication Date: April 3, 2001.
• Brief Description: This patent details a dedicated hardware unit for performing flatness tests on high-order rational surface patches within a rendering system. This is a specific implementation aspect of adaptive tessellation.
• Potential Anticipation (35 U.S.C. § 102): This patent anticipates the concept of a "flatness test unit" for surfaces, which is a component of US7245299's subdivision termination criteria (Claim 3, 4, 20, 21, 22). However, it does not specify that the flatness threshold is measured in screen coordinates (SC) or is part of a subdivision limited to only two orthogonal curves, which are key inventive steps of US7245299. If its flatness test is in world coordinates or without these specific optimizations, it would not anticipate claims 3, 4, 20, 21, and 22.

5. WO2000031690A1

• Full Citation: WO2000031690 A1, titled "Method and device for creating and modifying digital 3d models," assigned to Opticore Ab.
• Publication/Filing Date: Priority Date: November 20, 1998; Publication Date: June 2, 2000.
• Brief Description: This international patent application describes methods and devices for general creation and modification of 3D digital models.
• Potential Anticipation (35 U.S.C. § 102): Given the very broad title and lack of specific details in its abstract within US7245299, this reference is unlikely to anticipate the specific hardware architecture, subdivision methods, SC-based flatness criteria, or crack prevention techniques detailed in the claims of US7245299. It provides general art in 3D modeling.

6. US6597356B1

• Full Citation: US6,597,356 B1, titled "Integrated tessellator in a graphics processing unit," assigned to Nvidia Corporation.
• Publication/Filing Date: Priority Date: August 31, 2000; Publication Date: July 22, 2003.
• Brief Description: This patent describes an integrated tessellator within a GPU. US7245299's background explicitly discusses this patent (Moreton from Nvidia), stating that it "doesn't directly tesselate patches in real-time, but rather uses triangle meshes pre-tesselated off-line in conjunction with a proprietary stitching method that avoids cracking and popping at the seams between the triangle meshes representing surface patches. His tesselator unit outputs triangle databases to be rendered by the existing components of the 3D graphics hardware."
• Potential Anticipation (35 U.S.C. § 102): While US6597356B1 describes an "integrated tessellator in a GPU" (similar to the concept in Claim 1 and 11), US7245299 clearly distinguishes itself by claiming direct real-time tessellation of patches from control points, and specifically placing the tessellate unit between the transform unit and the lighting unit (Claim 1, 11). US6597356B1's approach of using pre-tessellated meshes for output suggests it does not anticipate US7245299's method of generating a new subdivision for each view based on SC parameters (Claim 3, 4, 20) or its specific crack prevention methods (Claim 5, 23).

7. US6624811B1

• Full Citation: US6,624,811 B1, titled "System, method and article of manufacture for decomposing surfaces using guard curves and reversed stitching," assigned to Nvidia Corporation.
• Publication/Filing Date: Priority Date: August 31, 2000; Publication Date: September 23, 2003.
• Brief Description: This patent describes techniques for decomposing surfaces and handling seams or cracks using "guard curves and reversed stitching." This is directly relevant to crack prevention in rendering.
• Potential Anticipation (35 U.S.C. § 102): This patent addresses the problem of cracks between decomposed surface patches, which is also addressed by US7245299 (Claim 5, 14, 19(a)(v), 23). However, US7245299 claims specific crack prevention methods, namely using a "common subdivision for all surfaces sharing a boundary" (either a reunion or finest subdivision) or a "zipper approach" where non-coincident vertices are copied. These specific methods are distinct from "guard curves and reversed stitching," thus it likely does not anticipate the specific methods claimed in US7245299.

8. US20030117405A1

• Full Citation: US2003/0117405 A1, titled "Systems and methods for performing memory management operations to provide displays of complex virtual environments," assigned to Hubrecht Alain Yves Nestor.
• Publication/Filing Date: Priority Date: December 21, 2001; Publication Date: June 26, 2003.
• Brief Description: This patent application focuses on memory management for rendering complex virtual environments.
• Potential Anticipation (35 U.S.C. § 102): This patent is primarily directed to memory management rather than the core technical innovations of real-time surface tessellation algorithms or GPU architecture. Therefore, it is highly unlikely to anticipate any of the specific claims of US7245299 related to GPU components (Claim 1), subdivision techniques (Claim 3, 20), SC-based flatness thresholds (Claim 3, 4, 20), or crack prevention (Claim 5, 23).

Most Relevant Prior Art for US7245299

Based on the analysis, US6597356B1 (Integrated tessellator in a graphics processing unit by Nvidia) and US6624811B1 (Decomposing surfaces using guard curves and reversed stitching by Nvidia) are highly relevant because they address similar problems (tessellation in GPUs and crack prevention, respectively) and are explicitly discussed and distinguished in the background of US7245299.

Additionally, US6057848A and US6211883B1 (Lsi Logic Corporation) are highly relevant as they describe hardware for rendering high-order rational surface patches and flatness test units, which are foundational concepts built upon by US7245299.

It is also crucial to note that U.S. Pat. No. 6,563,501 (Bicubic Surface Rendering by Adrian Sfarti, the same applicant), while not listed in the "Citations" section but as a "Related Parent Application," is explicitly stated in US7245299's description as providing the underlying method for minimizing computations by subdividing only two orthogonal curves and using SC for flatness determination. US7245299 "utilizes the above method... in order to provide an improved architecture for the computer graphics pipeline hardware." Therefore, US6563501 anticipates many of the methodological claims (e.g., Claims 3, 4, 12, 13, 19(a)(ii-iv), 20, 21), with US7245299's primary novelty residing in its hardware implementation and architectural placement of these methods (Claim 1, 11).

US patent 7245299 describes a graphics processing unit (GPU) for rendering objects by tessellating bicubic surfaces in real-time. The invention includes a tessellate unit coupled between the transform and lighting units of a GPU, which performs real-time tessellation of rational and non-rational bicubic surfaces. Key features of the claimed invention include transmitting objects as control points of bicubic surfaces, simplifying subdivision to only two orthogonal curves, terminating subdivision based on a flatness threshold in screen coordinates (SC), achieving automatic level of detail, and incorporating crack prevention methods.

Under 35 U.S.C. § 103, an invention is considered obvious if "the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains."

The primary combination of prior art references that would render the claims of US7245299 obvious is U.S. Pat. No. 6,597,356 (Moreton) in combination with U.S. Pat. No. 6,563,501 (Sfarti).

Detailed Analysis of Obviousness:

1. Prior Art References and Their Teachings:

• U.S. Pat. No. 6,597,356 ("Moreton"): This patent, titled "Integrated Tesselator in a Graphics Processing Unit," describes an architecture that includes a tessellator unit within a GPU. However, the '299 patent explicitly differentiates Moreton's approach, stating that it "doesn't directly tesselate patches in real-time, but rather uses triangle meshes pre-tesselated off-line in conjunction with a proprietary stitching method that avoids cracking and popping at the seams between the triangle meshes representing surface patches. His tesselator unit outputs triangle databases to be rendered by the existing components of the 3D graphics hardware." Thus, Moreton teaches the integration of a tessellator unit within a GPU architecture.

• U.S. Pat. No. 6,563,501 ("Sfarti '501"): This patent, titled "Bicubic Surface Rendering" and co-authored by the same applicant as US7245299, provides an improved method and system for rendering bicubic surfaces. The '299 patent explicitly states, "The present invention utilizes the above method for minimizing the number of computations required for the subdivision of bicubic surfaces into triangles in order to provide an improved architecture for the computer graphics pipeline hardware."
  Key teachings of Sfarti '501, as described in US7245299, include:

  • Transforming only the control points of the surface.
  • Selecting a pair of orthogonal boundary curves for processing.
  • Iteratively subdividing only these two orthogonal curves.
  • Terminating subdivision when curves satisfy a flatness threshold expressed in screen coordinates (SC), thereby minimizing computations.
  • Estimating curvature based on flatness in SC (pixels) rather than world coordinates (WC).
  • Enabling "automatic level of detail" by accommodating distance to the viewer.
  • Stating that "the entire rendering process can potentially be performed in real-time" due to reduced computations.

2. Motivation for Combining Moreton ('356) and Sfarti ('501):

A person having ordinary skill in the art (POSITA) would have been motivated to combine the teachings of Moreton ('356) and Sfarti ('501) for several reasons, primarily to address well-known problems in computer graphics rendering described in the background of US7245299:

• Addressing Performance and Bus Bandwidth Limitations: The background of US7245299 clearly outlines that conventional off-line tessellation on the CPU, followed by transmitting vast "triangle meshes" over the Accelerated Graphics Port (AGP) bus to the GPU, creates significant "demands for higher bus bandwidth." This bottleneck, coupled with physical constraints on bus frequency increases, indicated a need to shift processing away from transmitting large triangle databases. Transmitting "control points of the bicubic surfaces" instead of fully tessellated meshes significantly reduces bus traffic.
• Improving Level of Detail (LoD) and Visual Quality: The '299 patent also points out that off-line tessellation produces "fixed triangulation" that can be inefficient. Objects far away might have "excessively large number of very small triangles," while objects close to the viewer might have "very large" triangles, causing them to lose "smoothness appearance" and look "more like a polyhedron."
• Leveraging Existing Hardware Integration Concepts: Moreton ('356) already demonstrated the concept of an "integrated tesselator in a Graphics Processing Unit." While Moreton's approach still relied on pre-tessellated meshes, the idea of having a dedicated tessellation unit within the GPU was established. A POSITA would logically seek a more efficient tessellation method to implement within this hardware paradigm.
• Implementing a Proven Efficient Method: Sfarti '501 provided a highly efficient method for bicubic surface rendering that explicitly minimized computations by subdividing only two orthogonal curves and using SC for termination. Crucially, the '501 patent states this method "can potentially be performed in real-time" and produces "automatic level of detail."
• Achieving Real-Time Tessellation: The '299 patent states a need for "a system and method for performing tessellation in real-time." By combining the hardware placement suggested by Moreton (tessellator in GPU) with the efficient, real-time-enabling method from Sfarti '501, a POSITA would arrive at a solution that directly addresses this long-felt need. The background itself details previous unsuccessful attempts at real-time hardware tessellation (Sun Corporation's pixel-by-pixel, Nvidia's biquadric), further underscoring the motivation for a successful real-time triangle-generating tessellator.

3. Obviousness of the Claims of US7245299:

• Claim 1 (Graphics processing unit): This claim describes a GPU with a transform unit, lighting unit, renderer unit, and a tessellate unit coupled between the transform and lighting units for real-time tessellation of surfaces, receiving control points of bicubic surfaces.

  • Moreton teaches an "integrated tesselator in a Graphics Processing Unit." Sfarti '501 teaches an efficient method for real-time rendering of bicubic surfaces by operating on control points and outputting triangles. A POSITA, motivated to overcome bandwidth and LoD issues, would combine these by implementing the Sfarti '501 real-time tessellation method within Moreton's GPU-integrated tessellator. The placement of the tessellate unit between the transform (which transforms control points) and lighting units (which light the tessellated triangles) is a logical and predictable architectural design choice within the graphics pipeline.

• Claim 11 (System): This claim covers a system with a processor and such a GPU. The processor transmitting objects as control points to the GPU, which then transforms, tessellates, lights, and renders, directly addresses the bandwidth problem identified in the prior art, as the CPU no longer needs to send entire triangle meshes. This system architecture directly follows from the motivation to move tessellation to the GPU and use control points as input for the '501 method.

• Claim 19 & 20 (Real-time Methods for Tessellating and Rendering): These claims detail the specific method steps of real-time tessellation, including transforming control points, subdividing only two cubic curves, terminating subdivision based on screen coordinates (SC), achieving automatic level of detail, preventing cracks, and generating vertices, normals, and texture coordinates in real-time.

  • These method steps are explicitly taught and enabled by Sfarti '501, which US7245299 acknowledges it "utilizes." The '501 patent describes these steps as minimizing computations and enabling real-time rendering with automatic LoD. Therefore, if a POSITA is motivated to implement a real-time tessellation in hardware (as motivated by Moreton + Sfarti '501 combination), the specific efficient method steps to achieve this, as taught by Sfarti '501, would be obvious to apply. The '299 patent explicitly states that the "tessellate unit 9 executes the microcode described above in the Step 1 through Step 4, thereby affecting the real-time tessellation," where Steps 1-4 are the detailed method steps largely derived from the '501 patent.

In conclusion, the combination of Moreton's U.S. Pat. No. 6,597,356, which introduced an integrated tessellator into a GPU, and Sfarti's U.S. Pat. No. 6,563,501, which provided an efficient, real-time-enabling method for bicubic surface tessellation using screen coordinates and subdivision of only two orthogonal curves, would have rendered the claims of US7245299 obvious to a person of ordinary skill in the art. The motivation to combine these references stems from the clear and recognized problems in the prior art concerning bus bandwidth limitations and the need for adaptive real-time tessellation with automatic level of detail in graphics rendering.