Invalidity dossier

US 6597356

Integrated tessellator in a graphics processing unit

Current assignee: Nvidia Corp

Added 9/23/2026, 1:57:28 PM

At a glanceNo PTAB challengesNo litigation on file

Active provider: DeepSeek · deepseek-flash

Patent summary

Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.

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Patent Overview: US6597356B1

Title: Integrated tessellator in a graphics processing unit

Patent number: US6597356B1
Application number: US09/718,890
Inventors: Henry P. Moreton, Justin Legakis, Douglas H. Rogers
Original/current assignee: Nvidia Corp (per the listing)
Priority date: 2000-08-31
Filing date: 2000-11-21
Publication/grant date: 2003-07-22
Legal status listed: Expired – Lifetime; anticipated expiration 2020-08-31

Purpose / plain-language scope (based only on the supplied text):
The patent concerns an integrated tessellator within a graphics processing unit. The excerpt labels its subject matter with prior-art keywords including "module," "tessellation," "vertex," "data," and "recited," indicating the disclosed subject matter involves a tessellation module handling vertex data in a GPU context. The claimed subject matter appears directed to a tessellation module that operates on vertex data as part of the graphics pipeline.

Note: The supplied excerpt consists almost entirely of bibliographic and procedural data from the Google Patents page. It does not contain the abstract, specification, or claim text, so the precise scope of the claims cannot be summarized from this source. The summary above is limited to what the title and keyword listings literally state.

Related filings referenced (per the listing): priority claims from US09/652,866, US09/655,103, and US09/655,105 (2000); later PCT/US2001/045562 (WO2002043011A1), EP1350225B1, JP4113776B2, AU2002228718A1, and a continuation US10/418,364 (US6906716B2, 2003).

What this excerpt does not establish: It does not provide the abstract, claims, specification, or drawings, so the exact claimed invention cannot be stated with confidence. It does not establish inventorship disputes, validity, enforceability, litigation history, ownership transfers beyond the listed assignments, or the content of any cited prior art. The legal status shown is expressly labeled an assumption, not a legal conclusion. No independent research beyond the supplied text was performed.

Source: https://patents.google.com/patent/[US6597356](/patent/US6597356)/en

Generated 10/1/2026, 9:52:41 PM

Cases on file (0)

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Litigation summary

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Proceedings on file (0)

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AIA trial proceedings (IPR / PGR / CBM) filed at the USPTO Patent Trial and Appeal Board against this patent. Sourced from the USPTO Open Data Portal and refreshed every six hours; each proceeding number deep-links to the PTAB E2E docket.

No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.

PTAB challenges

AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.

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Assignment history

Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.

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Prior art

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Obviousness

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Extensions

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Derivative works

Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.

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