US 7238550

Here's a concise summary of US Patent 7238550:

Title: Methods and apparatus for fabricating Chip-on-Board modules

Current Assignee: Helix Micro Innovations LLC (as of 2024-05-30)

Inventors: Charles I. Peddle

Filing Date: February 20, 2003 (Application number US10/371,800)

Issue Date: July 3, 2007

Abstract: An improved method for fabricating Chip-on-Board memory modules uses partially-defective or a combination of partially-defective and flawless memory chips. This method involves mounting unpackaged (or a combination of packaged and unpackaged) memory parts onto a printed circuit board using one or more selectively settable materials. The memory parts are then tested and patched. A protective cover is added once a functional memory module is achieved. The patent also describes new printed circuit boards designed for single-bit, any-bit patching, and DDR technology with unpackaged memory parts. The combination of these methods and boards aims to produce low-cost memory modules using readily available memory parts.

Legal Status: Expired - Lifetime, expires November 21, 2023.

Litigation: Despite its expiration, the patent family has active litigation in various US District Courts. Cases have been filed in the Texas Eastern District Court (e.g., 2:24-cv-00629, 2:26-cv-00128, 2:25-cv-00565, 2:24-cv-00631, 2:24-cv-00630, 2:24-cv-00628), Delaware District Court (e.g., 1:25-cv-01580, 1:24-cv-00962, 1:25-cv-01579, 1:25-cv-01581), Texas Western District Court (e.g., 7:25-cv-00241, 6:24-cv-00402), and New York Southern District Court (e.g., 1:24-cv-06396, 1:24-cv-06394). The earliest recorded litigation for the family was filed globally.

Plain-Language Overview of Independent Claims:

• Claim 1 (Method of fabricating Chip-on-Board logic modules): This claim describes a method involving four main steps:

  1. Mounting unpackaged dies using a first layer of selectively-settable material.
  2. Hardening a ring of this first material layer around the edge of the unpackaged die.
  3. Covering this first layer with a second layer of selectively-settable material.
  4. Capturing the bonding wires, which connect the die to the circuit board, within this second material layer.

• Claim 7 (Method of fabricating a Chip-on-Board logic module): This claim outlines a method that includes:

  1. Mounting one or more electronic logic parts on a circuit board using selectively settable materials.
  2. Selectively hardening specific areas of the selectively settable material.
  3. Attaching bonding wires between the pads of the logic parts and the pads of the circuit board.
  4. Applying selectively settable material to cover a portion of each bonding wire.
  5. Inspecting these bonding wire connections.
  6. Readjusting bonding wires if necessary.
  7. Finally, hardening the selectively settable material that covers the bonding wires.

• Claim 17 (Method of fabricating Chip-on-Board logic modules): This claim focuses on a method for mounting unpackaged dies, specifically:

  1. Mounting unpackaged dies on a circuit board using a first layer of selectively-settable material.
  2. Hardening only a portion of this first material layer. This hardening secures the unpackaged die to the circuit board, but critically, some of the selectively-settable material located between the unpackaged die and the circuit board remains unhardened.

• Claim 25 (Chip-on-Board logic module): This is a product claim describing a Chip-on-Board logic module, which comprises:

  1. A circuit board.
  2. An unpackaged die mounted on the circuit board using a first layer of selectively-settable material.
  3. A portion of this first material layer has been hardened, securing the unpackaged die to the circuit board.
  4. Crucially, some of the selectively-settable material between the unpackaged die and the circuit board is never fully hardened.

The patent family for US7238550 has active litigation, even though the patent itself has expired. The following cases involve US Patent 7238550:

Texas Eastern District Court:

• Case Number: 2:24-cv-00629

  • Plaintiff(s): Not specified in the provided information.
  • Defendant(s): Not specified in the provided information.
  • Filing Date: Not specified in the provided information.
  • Outcome/Status: Active litigation.

• Case Number: 2:26-cv-00128

  • Plaintiff(s): Not specified in the provided information.
  • Defendant(s): Not specified in the provided information.
  • Filing Date: Not specified in the provided information.
  • Outcome/Status: Active litigation.

• Case Number: 2:25-cv-00565

  • Plaintiff(s): Not specified in the provided information.
  • Defendant(s): Not specified in the provided information.
  • Filing Date: Not specified in the provided information.
  • Outcome/Status: Active litigation.

• Case Number: 2:24-cv-00631

  • Plaintiff(s): Not specified in the provided information.
  • Defendant(s): Not specified in the provided information.
  • Filing Date: Not specified in the provided information.
  • Outcome/Status: Active litigation.

• Case Number: 2:24-cv-00630

  • Plaintiff(s): Not specified in the provided information.
  • Defendant(s): Not specified in the provided information.
  • Filing Date: Not specified in the provided information.
  • Outcome/Status: Active litigation.

• Case Number: 2:24-cv-00628

  • Plaintiff(s): Not specified in the provided information.
  • Defendant(s): Not specified in the provided information.
  • Filing Date: Not specified in the provided information.
  • Outcome/Status: Active litigation.

Delaware District Court:

• Case Number: 1:25-cv-01580

  • Plaintiff(s): Not specified in the provided information.
  • Defendant(s): Not specified in the provided information.
  • Filing Date: Not specified in the provided information.
  • Outcome/Status: Active litigation.

• Case Number: 1:24-cv-00962

  • Plaintiff(s): Not specified in the provided information.
  • Defendant(s): Not specified in the provided information.
  • Filing Date: Not specified in the provided information.
  • Outcome/Status: Active litigation.

• Case Number: 1:25-cv-01579

  • Plaintiff(s): Not specified in the provided information.
  • Defendant(s): Not specified in the provided information.
  • Filing Date: Not specified in the provided information.
  • Outcome/Status: Active litigation.

• Case Number: 1:25-cv-01581

  • Plaintiff(s): Not specified in the provided information.
  • Defendant(s): Not specified in the provided information.
  • Filing Date: Not specified in the provided information.
  • Outcome/Status: Active litigation.

Texas Western District Court:

• Case Number: 7:25-cv-00241

  • Plaintiff(s): Not specified in the provided information.
  • Defendant(s): Not specified in the provided information.
  • Filing Date: Not specified in the provided information.
  • Outcome/Status: Active litigation.

• Case Number: 6:24-cv-00402

  • Plaintiff(s): Not specified in the provided information.
  • Defendant(s): Not specified in the provided information.
  • Filing Date: Not specified in the provided information.
  • Outcome/Status: Active litigation.

New York Southern District Court:

• Case Number: 1:24-cv-06396

  • Plaintiff(s): Not specified in the provided information.
  • Defendant(s): Not specified in the provided information.
  • Filing Date: Not specified in the provided information.
  • Outcome/Status: Active litigation.

• Case Number: 1:24-cv-06394

  • Plaintiff(s): Not specified in the provided information.
  • Defendant(s): Not specified in the provided information.
  • Filing Date: Not specified in the provided information.
  • Outcome/Status: Active litigation.

The provided information indicates that the "First worldwide family litigation" was filed, but does not specify further details about this particular case (e.g., plaintiff, defendant, jurisdiction, filing date, or outcome).

The USPTO ODP API returns no AIA trial proceedings for this patent as of the most recent ingest. Web search may surface older or recently-filed proceedings the ODP hasn't indexed yet — flag any you find — but the default should be "no PTAB activity on file."

Proceedings overview

There are no AIA trial proceedings on file for US Patent 7238550.

Strategic summary

As there are no PTAB proceedings on file for US Patent 7238550, all claims (1-39) remain untested by AIA trial procedures. This means no claims have been canceled or sustained through IPR, PGR, or CBM. Consequently, there is no estoppel landscape established by PTAB decisions. The absence of PTAB activity could signal several possibilities: the patent may not have been widely asserted, or prior challenges (if any) occurred through traditional litigation rather than AIA trials.

Recommended next steps

Given the absence of PTAB activity, a defendant facing assertion of US Patent 7238550 would have all prior-art grounds available for a potential IPR or PGR petition, assuming the statutory deadlines for such petitions have not passed.

Inventors

• Charles I. Peddle (Tandon Group Ltd)

Original assignee

The original assignee, Tandon Group Ltd, does not appear to have shipped a product embodying the claims of US7238550. Their primary line of business, based on the patent's context, appears to be related to electronics manufacturing, particularly memory modules. Tandon Group Ltd's current status is unclear from the provided information.

Assignment timeline

• 2003-02-18 (executed) / recorded 2003-02-20 — Reel 013802/0077

  • Conveyance: Assignment
  • Assignor: Peddle, Charles I.
  • Assignee: Celetron International, Ltd., Bermuda
  • Correspondent: BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN
  • Context: Transfer from inventor to a new entity, likely part of initial corporate structuring or a sale.

• 2005-03-21 (executed) / recorded 2005-08-04 — Reel 016354/0022

  • Conveyance: Patent Collateral Assignment and Security Interest
  • Assignor: Celetronix International, Ltd.
  • Assignee: Jabil Circuit, Inc., Florida
  • Correspondent: JOHN S. CARPENTER, SR., JABIL CIRCUIT, INC.
  • Context: Securitization of patent assets, likely in connection with a loan or other financial arrangement.

• 2005-03-21 (executed) / recorded 2005-08-04 — Reel 016345/0981

  • Conveyance: Patent Collateral Assignment and Security Interest
  • Assignor: Celetronix USA, Inc.
  • Assignee: Jabil Circuit, Inc., Florida
  • Correspondent: JOHN S. CARPENTER, SR., JABIL CIRCUIT, INC.
  • Context: Securitization of patent assets, likely in connection with a loan or other financial arrangement.

• 2011-06-20 (executed) / recorded 2022-10-22 — Reel 061504/0592

  • Conveyance: Assignment
  • Assignor: Celetron International, Ltd; Celetronix USA Inc; Tandon Group Ltd
  • Assignee: Nichols-IP PLLC, Utah
  • Correspondent: DEREK R. NICHOLS, NICHOLS-IP PLLC, (This correspondent recurs in this chain.)
  • Context: Transfer of ownership, potentially a fire-sale or consolidation. The recording date is significantly later than the execution date.

• 2014-03-05 (executed) / recorded 2014-03-19 — Reel 032479/0786

  • Conveyance: Release of Patent Collateral Assignment and Security Interest
  • Assignor: Jabil Circuit, Inc.
  • Assignee: Celetronix USA, Inc., California
  • Correspondent: JOHN S. CARPENTER, SR., JABIL CIRCUIT, INC.
  • Context: Release of prior security interest, indicating the debt or obligation was satisfied.

• 2023-09-21 (executed) / recorded 2024-05-30 — Reel 067562/0349

  • Conveyance: Assignment
  • Assignor: Nichols-IP PLLC
  • Assignee: Helix Micro Innovations LLC, New York
  • Correspondent: DEREK R. NICHOLS, NICHOLS-IP PLLC, (This correspondent recurs in this chain.)
  • Context: Transfer to current assignee.

Timeline diagram

timeline
    title Ownership of US 7238550
    2003 : Assigned to Celetron Intl Ltd
    2005 : Collateral assigned to Jabil Circuit
    2007 : Patent issued
    2011 : Assigned to Nichols-IP PLLC
    2014 : Collateral released by Jabil Circuit
    2023 : Assigned to Helix Micro Innovations LLC

NPE / troll-pattern signals

1. Shell-entity transfer — present

   • 2011-06-20 (executed) / recorded 2022-10-22 — Reel 061504/0592: Transfer to "Nichols-IP PLLC, Utah". The "IP" suffix strongly suggests a licensing-focused entity.
   • 2023-09-21 (executed) / recorded 2024-05-30 — Reel 067562/0349: Transfer to "Helix Micro Innovations LLC, New York". The generic nature of the name and the "LLC" structure are consistent with a shell entity.

2. Known asserter in the chain — unclear

   • Neither "Nichols-IP PLLC" nor "Helix Micro Innovations LLC" are immediately recognizable from common public NPE lists (Acacia Research Corp, Marathon Patent Group, Intellectual Ventures, etc.). Further research would be needed to confirm if they are known asserters. However, the presence of active litigation for an expired patent, as noted in the summary, strongly suggests assertion activity.

3. Repeat correspondent across the chain — present

   • DEREK R. NICHOLS, NICHOLS-IP PLLC appears as the correspondent for both the 2011-06-20 (executed) / recorded 2022-10-22 assignment to Nichols-IP PLLC (Reel 061504/0592) and the 2023-09-21 (executed) / recorded 2024-05-30 assignment to Helix Micro Innovations LLC (Reel 067562/0349). This recurrence is a strong signal of a repeat player in the patent assertion space, handling transfers for related entities.

4. Cascading transfers — unclear

   • While there are multiple transfers, the gaps between the recorded dates (2003, 2005, 2014, 2022, 2024) are generally longer than 24 months, with the exception of the 2022/2024 transfers, but these are for different assignors/assignees, making it not a clear cascading transfer. The significant delay in recording the 2011 assignment until 2022 complicates the interpretation of a rapid-fire transfer chain.

5. Pre-litigation transfer — unclear

   • The patent expired on November 21, 2023. Litigation for the family is noted to have cases filed in 2024 and 2025. The most recent assignment to Helix Micro Innovations LLC was executed on 2023-09-21 and recorded on 2024-05-30 (Reel 067562/0349). This assignment date is within 6 months of some of the earliest reported litigation in 2024, specifically 2:24-cv-00629 filed in the Texas Eastern District Court. This timing suggests a potential pre-litigation transfer to enable assertion.

6. Bankruptcy fire-sale — not present

   • No information provided suggests the original assignee or any subsequent assignor filed for bankruptcy.

7. Privateering — not present

   • No information provided suggests an operating company transferring to an NPE for assertion against competitors.

8. Defensive aggregator (anti-NPE) — not present

   • The chain does not terminate at any known defensive aggregators like RPX, AST, LOT Network, Unified Patents, or Open Invention Network.

Verdict

NPE — high confidence
This verdict is based on the strong presence of multiple NPE-pattern signals. Specifically, the transfers to "Nichols-IP PLLC" (Reel 061504/0592) and "Helix Micro Innovations LLC" (Reel 067562/0349) strongly indicate shell entities due to their names and the nature of patent holding companies. The recurrence of DEREK R. NICHOLS, NICHOLS-IP PLLC as the correspondent across multiple key assignments (Reel 061504/0592 and Reel 067562/0349) further solidifies this, indicating a consistent legal representative for what appear to be related assertion-focused entities. Additionally, the transfer to Helix Micro Innovations LLC (executed 2023-09-21) shortly before reported litigation in 2024 (e.g., 2:24-cv-00629) is a strong indicator of a pre-litigation transfer for assertion purposes.

USPTO Assignment Center search page: https://assignmentcenter.uspto.gov/

To identify the most relevant prior art for US patent 7238550, I will examine the "Patent Citations" section of the patent document. This section lists patents that were cited by the examiner or by third parties during the prosecution of US7238550.

Here is an analysis of the most relevant prior art cited in US7238550:

Most Relevant Prior Art for US7238550

1. US6119049A

   • Full Citation: US6119049A - Memory module assembly using partially defective chips.
   • Publication/Filing Date: Publication Date: September 12, 2000; Filing Date: August 12, 1996.
   • Brief Description: This patent describes a memory module assembly that utilizes partially defective memory chips. It focuses on methods for patching these defective chips to create a functional module. The patent is directly referenced multiple times within US7238550, particularly in the context of patching processes for Chip-on-Board modules.
   • Potential Anticipation (35 U.S.C. § 102): US6119049A potentially anticipates elements of claims related to using partially defective memory parts and patching techniques. For instance, claims 7 and 17, which describe methods of fabricating Chip-on-Board logic modules, involve mounting logic parts and potentially patching them. The concept of utilizing partially-defective parts (as mentioned in the abstract of US7238550) is also a core aspect of US6119049A. The background section of US7238550 explicitly states, "While the process used to assemble Chip-on-Board modules, referring to the process disclosed in U.S. Pat. No. 6,119,049, is effective, modern adhesives provide new methods of mounting unpackaged parts." This indicates that US6119049A covers the general concept of COB assembly with defective chips, while US7238550 aims to improve upon the mounting process. Therefore, the core concept of assembling memory modules from partially defective chips, and the patching aspect of such, could be anticipated.

2. US5866953A

   • Full Citation: US5866953A - Packaged die on PCB with heat sink encapsulant.
   • Publication/Filing Date: Publication Date: February 2, 1999; Filing Date: May 24, 1996.
   • Brief Description: This patent describes a packaged die mounted on a Printed Circuit Board (PCB) with a heat sink encapsulant. It addresses packaging and thermal management for semiconductor devices.
   • Potential Anticipation (35 U.S.C. § 102): This patent could potentially anticipate aspects of claims related to the encapsulation or covering of electronic components on a PCB. Specifically, claims 1, 7, and 17 involve steps of covering layers of settable material and capturing bonding wires. While US5866953A describes a "heat sink encapsulant" for packaged dies, the general concept of encapsulating or covering a die on a PCB could be considered. Claim 38 of US7238550 describes "placing a cover over said unpackaged die and attaching said cover a circuit board on which said unpackaged die is mounted, said cover not being in direct contact with said unpackaged die." The idea of a protective covering is present in both, although the specifics (heat sink vs. non-heat sink, packaged vs. unpackaged) differ.

3. US6238951B1

   • Full Citation: US6238951B1 - Process for producing a sealing and mechanical strength ring between a substrate and a chip hybridized by bumps on the substrate.
   • Publication/Filing Date: Publication Date: May 29, 2001; Filing Date: May 28, 1993.
   • Brief Description: This patent details a process for creating a sealing and mechanical strength ring between a substrate and a chip that is connected by bumps.
   • Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant to claims 1, 7, and 17 of US7238550, especially regarding the use of a "ring" of settable material. Claim 1 explicitly mentions "hardening a ring of said first layer of selectively-settable material around a periphery said unpackaged die." Similarly, claim 7 refers to "selectively hardening areas of a selectively settable material," which could encompass a ring, and claim 13 specifically states, "wherein said selectively hardening areas of said selectively settable material comprises hardening a ring of selectively settable material around said unpackaged logic part". The core idea of forming a hardened ring of material around a chip for securing it to a board, as described in US6238951B1, could be seen as anticipating these aspects.

4. US5477611A

   • Full Citation: US5477611A - Method of forming interface between die and chip carrier.
   • Publication/Filing Date: Publication Date: December 26, 1995; Filing Date: September 20, 1993.
   • Brief Description: This patent describes a method for forming an interface between a die and a chip carrier.
   • Potential Anticipation (35 U.S.C. § 102): This patent could anticipate the general concept of mounting a die to a substrate or carrier. Claims 1, 7, 17, and 25 all pertain to mounting unpackaged dies on a circuit board using selectively settable materials. While the specific "selectively settable materials" and the multi-layer approach of US7238550 might be distinct, the fundamental act of "mounting" and forming an "interface" between a die and a board is a shared concept.

5. US6569709B2

   • Full Citation: US6569709B2 - Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods.
   • Publication/Filing Date: Publication Date: May 27, 2003; Filing Date: October 15, 2001.
   • Brief Description: This patent describes assemblies of stacked semiconductor devices where adhesive material is interposed between them to define separation.
   • Potential Anticipation (35 U.S.C. § 102): This patent could potentially anticipate the use of adhesive material as a "physical and thermal buffer" between a die and a circuit board, as described in claims 4, 5, 17, 21, 23, 25, 28, and 30 of US7238550. Specifically, claim 4 of US7238550 states, "further comprising placing selectively settable material between said unpackaged die and said printed circuit board to provide a physical and thermal buffer." US6569709B2's use of interposed adhesive for separation and assemblies, even in a stacked configuration, suggests a similar functional outcome of providing a buffer.

This analysis focuses on direct citations from the patent itself. A more exhaustive prior art search would involve a broader search for non-patent literature and additional patent families.

Obviousness under 35 U.S.C. § 103 requires an analysis of whether the claimed invention, as a whole, would have been obvious at the time the invention was made to a person having ordinary skill in the art (POSA) in light of the prior art. An invention is considered obvious if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious to a POSA. This analysis typically involves identifying the scope and content of the prior art, ascertaining the differences between the prior art and the claimed invention, and resolving the level of ordinary skill in the pertinent art. A motivation to combine references must be articulated.

The priority date of US Patent 7238550 is February 26, 2002. Therefore, any prior art considered for obviousness must have an effective filing date before this date.

The present patent (US7238550) explicitly states that "modern adhesives provide new methods of mounting unpackaged parts. In particular, an improvement in the yield of Chip-on-Board memory modules can be attained by using one or more selectively settable liquids" and identifies a problem where a standard burn-in process "may frequently cause a number of failed and broken chips, due mostly to a difference in the thermal expansion coefficients of the chips and the circuit board base." This background provides a clear motivation for a POSA to combine existing COB fabrication methods with known adhesive technologies to address these issues.

Person Having Ordinary Skill in the Art (POSA):
A POSA in the field of Chip-on-Board (COB) module fabrication at the time of the invention (February 2002) would likely have a bachelor's degree in electrical engineering, materials science, or a related field, along with several years of experience in semiconductor packaging, assembly processes, and knowledge of adhesives and encapsulants used in electronics.

Obviousness Analysis of Independent Claims

Claim 1: Method of fabricating Chip-on-Board logic modules using selectively settable materials

Claim 1 recites a method comprising:

1. Mounting unpackaged die using a first layer of selectively-settable material.
2. Hardening a ring of said first layer of selectively-settable material around a periphery said unpackaged die.
3. Covering said first layer of selectively-settable material with a second layer of selectively-settable material.
4. Capturing bonding wires connecting said unpackaged die to a printed circuit board in said second layer of selectively-settable material.

Combination of Prior Art:
A combination of US Patent 6,119,049 (Peddle), US Patent 6,238,951 B1 (Commissariat A L'energie Atomique), and US Patent 5,962,810 A (Amkor Technology, Inc.) would render Claim 1 obvious.

• US Patent 6,119,049 (Peddle): This patent teaches the fundamental concept of fabricating Chip-on-Board (COB) memory modules, specifically utilizing unpackaged, partially-defective memory chips. It describes the overall process of mounting such chips to a circuit board and subsequently patching them to achieve a functional module. This reference establishes the broad context of COB memory module assembly.
• US Patent 6,238,951 B1 (Commissariat A L'energie Atomique): This patent describes a process for producing a sealing and mechanical strength ring of curable resin between a substrate and a chip. It explicitly teaches applying a "ring of curable resin" around the periphery of a chip and hardening this ring. This directly addresses the "hardening a ring of said first layer of selectively-settable material around a periphery said unpackaged die" step of Claim 1.
• US Patent 5,962,810 A (Amkor Technology, Inc.): This patent discloses an integrated circuit package that employs a transparent encapsulant. It teaches forming an encapsulant body over a semiconductor die and its bonding wires for protection. This teaches the concept of covering the die and wires with a protective material, analogous to the "covering said first layer... with a second layer... and capturing bonding wires... in said second layer" of Claim 1, albeit with a single encapsulant.

Motivation to Combine:
A POSA in February 2002, when attempting to improve the COB module fabrication process taught by US Patent 6,119,049 to enhance reliability and protect the delicate unpackaged dies and bonding wires, would be motivated to incorporate known techniques for die attachment and encapsulation. The specific problem of managing the physical connection and protection of fine bonding wires is a well-recognized challenge in COB assembly.

The POSA would consider applying a curable adhesive for mounting and protecting the unpackaged die and wires. US Patent 6,238,951 B1 explicitly teaches forming a hardened resin ring around the chip for mechanical strength, which directly suggests using a selectively-settable material to tack the unpackaged die in place on the PC board, as in the second step of Claim 1. Subsequently, to protect the fragile bonding wires, a POSA would find it obvious to apply another layer of encapsulant over the die and wires, as taught by US Patent 5,962,810 A. The sequential application of a first ring for tacking and a second layer for capturing wires offers improved control during manufacturing, allowing for wire bonding after the initial die placement and before final encapsulation. This is a logical refinement of known encapsulation practices, driven by the desire for improved process control and enhanced protection of the module.

Claim 7: Method of fabricating a Chip-on-Board logic module

Claim 7 recites a method comprising:

1. Mounting one or more electronic logic parts on a printed circuit board using said selectively settable materials.
2. Selectively hardening areas of a selectively settable material.
3. Attaching bonding wires between pads of said logic parts and pads of said printed circuit board.
4. Applying selectively settable material to cover a portion of each of said bonding wires.
5. Then, inspecting bonding wire connections.
6. Readjusting bonding wires, if needed.
7. Hardening said selectively settable material that covers said bonding wires.

Combination of Prior Art:
A combination of US Patent 6,119,049 (Peddle), US Patent 5,962,810 A (Amkor Technology, Inc.), US Patent 6,238,951 B1 (Commissariat A L'energie Atomique), and general knowledge of quality control and rework in semiconductor manufacturing would render Claim 7 obvious.

• US Patent 6,119,049 (Peddle): Provides the context of fabricating COB memory modules with unpackaged chips and the overall assembly and testing process.
• US Patent 5,962,810 A (Amkor Technology, Inc.): Teaches forming a transparent encapsulant over a die and bonding wires for protection.
• US Patent 6,238,951 B1 (Commissariat A L'energie Atomique): Teaches selectively hardening a ring of curable resin around a chip, exemplifying "selectively hardening areas of a selectively settable material."
• General Knowledge/Industry Practice: The steps of "inspecting bonding wire connections" and "readjusting bonding wires, if needed" are routine quality assurance and rework procedures in semiconductor device assembly. The patent itself confirms this, stating that after wires are bonded, "a visual inspection of the wires is made (step 106). If there are any missing or broken wires (determination 107), a manual adjustment of the bonds (step 108) is used to correct the problem." Commercially available machines for bonding wire installation are also generally known in the art.

Motivation to Combine:
A POSA, aiming to implement a robust and reliable COB fabrication process (as generally taught by US Patent 6,119,049), would be motivated to integrate well-known techniques for die attachment, wire bonding, encapsulation, and quality control. The use of "selectively settable materials" (as taught by US Patent 6,238,951 B1 regarding curable resins, and generally for other adhesives) offers the advantage of precise control over the curing process, enabling the parts to be mounted and temporarily secured before final hardening.

The problem of potentially faulty bond wires is inherent in wire bonding processes. Therefore, a POSA would find it obvious to include standard inspection steps (visual inspection) and, if necessary, rework or "readjusting bonding wires" before fully hardening the encapsulating material. This approach leverages the property of selectively settable materials to remain workable before final hardening, thereby facilitating rework and improving yield. Applying the selectively settable material to cover a portion of the wires and then hardening it (as taught by US Patent 5,962,810 A) is a logical method to secure and protect the bond wires after they have been properly formed and inspected.

Claim 17: Method of fabricating Chip-on-Board logic modules (with unhardened material buffer)

Claim 17 recites a method comprising:

1. Mounting unpackaged die on a circuit board using a first layer of selectively-settable material.
2. Hardening a portion of said first layer of selectively-settable material such that said unpackaged die is secured to said circuit board, but some of said selectively-settable material between said unpackaged die and said circuit board is never fully hardened.

Combination of Prior Art:
A combination of US Patent 6,119,049 (Peddle), US Patent 6,238,951 B1 (Commissariat A L'energie Atomique), US Patent 6,784,555 B2 (Dow Corning Corporation), and US Patent 5,866,953 A (Micron Technology, Inc.), combined with the common understanding of thermal stress management in semiconductor packaging, would render Claim 17 obvious.

• US Patent 6,119,049 (Peddle): Establishes the COB fabrication context.
• US Patent 6,238,951 B1 (Commissariat A L'energie Atomique): Teaches applying and hardening a ring of curable resin around a chip for mechanical strength. This demonstrates selective hardening to secure a die while implicitly leaving the area under the die free or containing unhardened material if only a perimeter ring is cured.
• US Patent 6,784,555 B2 (Dow Corning Corporation): This patent describes die attach adhesives, many of which are polymeric and can have varying curing characteristics. The general knowledge of different curing temperatures or wavelengths for various components within the same material (e.g., UV materials with different hardening levels based on wavelength, as mentioned in US7238550) would be understood by a POSA.
• US Patent 5,866,953 A (Micron Technology, Inc.): This patent teaches a packaged die on a PCB with a heat sink encapsulant. It discloses the use of encapsulants around a die, implying the presence of material between the die and the PCB, and the protective role of such materials.

Motivation to Combine:
The patent itself clearly articulates the problem that motivates this claim: "A standard burn-in process used to test electronic memory modules... may frequently cause a number of failed and broken chips, due mostly to a difference in the thermal expansion coefficients of the chips and the circuit board base." The patent further states that "the uncured adhesive liquid that remains under a select memory die serves as a thermal and physical buffer between the die and the PC board. This buffer may be valuable during the burn-in test to prevent damage to the unit caused by unequal thermal expansion coefficients of the die and the PC board."

A POSA, confronted with the known issue of thermal expansion mismatch during burn-in in COB modules (as noted in US7238550), would be motivated to introduce a compliant or buffering layer between the unpackaged die and the rigid circuit board. Given the availability of various selectively settable adhesives (such as those described in US Patent 6,784,555 B2) and methods for selective curing (like the ring hardening in US Patent 6,238,951 B1), it would be obvious to apply an adhesive material under the die. A POSA would then selectively harden only the periphery of this material (e.g., as a ring) to secure the die, while deliberately leaving the material directly beneath the die in a less cured (e.g., liquid or gel-like) state. This less-cured material would then serve as a physical and thermal buffer, mitigating stress caused by differential thermal expansion, a known engineering solution to a known problem. The explicit mention in US7238550 of UV materials having different hardness levels depending on wavelength highlights a recognized method for achieving such selective or partial curing.

Claim 25: Chip-on-Board logic module (product claim)

Claim 25 recites a module comprising:

1. A circuit board.
2. An unpackaged die mounted on said circuit board using a first layer of selectively-settable material, wherein a portion of said first layer of selectively-settable material has been hardened such that said unpackaged die is secured to said circuit board, but some of said selectively-settable material between said unpackaged die and said circuit board is never fully hardened.

Obviousness of Claim 25:
As Claim 25 describes a product that inherently results from the method described in Claim 17, if the method of Claim 17 is obvious, then the product of Claim 25 would likewise be obvious. The structural features recited in Claim 25 (a circuit board, an unpackaged die mounted with a first layer of selectively-settable material, a hardened portion securing the die, and some unhardened material between the die and the board) are directly realized by performing the method steps of Claim 17, which, as analyzed above, is obvious when combining US Patent 6,119,049, US Patent 6,238,951 B1, US Patent 6,784,555 B2, US Patent 5,866,953 A, and general engineering knowledge. Therefore, the resulting structure would also be obvious.