US 7238550

Here's a concise summary of US Patent 7238550:

Title: Methods and apparatus for fabricating Chip-on-Board modules

Current Assignee: Helix Micro Innovations LLC (as of 2024-05-30)

Inventors: Charles I. Peddle

Filing Date: February 20, 2003 (Application number US10/371,800)

Issue Date: July 3, 2007

Abstract: An improved method for fabricating Chip-on-Board memory modules uses partially-defective or a combination of partially-defective and flawless memory chips. This method involves mounting unpackaged (or a combination of packaged and unpackaged) memory parts onto a printed circuit board using one or more selectively settable materials. The memory parts are then tested and patched. A protective cover is added once a functional memory module is achieved. The patent also describes new printed circuit boards designed for single-bit, any-bit patching, and DDR technology with unpackaged memory parts. The combination of these methods and boards aims to produce low-cost memory modules using readily available memory parts.

Legal Status: Expired - Lifetime, expires November 21, 2023.

Litigation: Despite its expiration, the patent family has active litigation in various US District Courts. Cases have been filed in the Texas Eastern District Court (e.g., 2:24-cv-00629, 2:26-cv-00128, 2:25-cv-00565, 2:24-cv-00631, 2:24-cv-00630, 2:24-cv-00628), Delaware District Court (e.g., 1:25-cv-01580, 1:24-cv-00962, 1:25-cv-01579, 1:25-cv-01581), Texas Western District Court (e.g., 7:25-cv-00241, 6:24-cv-00402), and New York Southern District Court (e.g., 1:24-cv-06396, 1:24-cv-06394). The earliest recorded litigation for the family was filed globally.

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Plain-Language Overview of Independent Claims:

• Claim 1 (Method of fabricating Chip-on-Board logic modules): This claim describes a method involving four main steps:

  1. Mounting unpackaged dies using a first layer of selectively-settable material.
  2. Hardening a ring of this first material layer around the edge of the unpackaged die.
  3. Covering this first layer with a second layer of selectively-settable material.
  4. Capturing the bonding wires, which connect the die to the circuit board, within this second material layer.

• Claim 7 (Method of fabricating a Chip-on-Board logic module): This claim outlines a method that includes:

  1. Mounting one or more electronic logic parts on a circuit board using selectively settable materials.
  2. Selectively hardening specific areas of the selectively settable material.
  3. Attaching bonding wires between the pads of the logic parts and the pads of the circuit board.
  4. Applying selectively settable material to cover a portion of each bonding wire.
  5. Inspecting these bonding wire connections.
  6. Readjusting bonding wires if necessary.
  7. Finally, hardening the selectively settable material that covers the bonding wires.

• Claim 17 (Method of fabricating Chip-on-Board logic modules): This claim focuses on a method for mounting unpackaged dies, specifically:

  1. Mounting unpackaged dies on a circuit board using a first layer of selectively-settable material.
  2. Hardening only a portion of this first material layer. This hardening secures the unpackaged die to the circuit board, but critically, some of the selectively-settable material located between the unpackaged die and the circuit board remains unhardened.

• Claim 25 (Chip-on-Board logic module): This is a product claim describing a Chip-on-Board logic module, which comprises:

  1. A circuit board.
  2. An unpackaged die mounted on the circuit board using a first layer of selectively-settable material.
  3. A portion of this first material layer has been hardened, securing the unpackaged die to the circuit board.
  4. Crucially, some of the selectively-settable material between the unpackaged die and the circuit board is never fully hardened.