US 7007259

Here's a concise summary of US Patent 7007259:

US Patent Number: US7007259B2

Title: Method for providing clock-net aware dummy metal using dummy regions

Inventors: Vikram Shrowty; Santhanakrishnan Raman

Current Assignee: Bell Semiconductor LLC (as of December 17, 2017)

Original Assignee: LSI Logic Corp

Filing Date: July 31, 2003

Issue Date: February 28, 2006

Abstract:
A method and system for inserting dummy metal into a circuit design is disclosed, specifically for designs including a plurality of objects and clock nets. The invention involves identifying free spaces on each layer of the chip as "dummy regions" suitable for dummy metal insertion. These dummy regions are then prioritized so that those located adjacent to clock nets are filled with dummy metal last, aiming to minimize timing impact on the clock nets. In a preferred embodiment, further prioritization ensures that dummy regions adjacent to wider clock nets are filled after those adjacent to narrower clock nets.

Plain-Language Overview of Independent Claims:

• Claim 1 (Method for Inserting Dummy Metal): This claim describes a method for placing inactive metal (dummy metal) into an integrated circuit design. The method involves two primary steps:

  1. Finding empty areas on each layer of the chip, which are designated as "dummy regions."
  2. Deciding the order in which these dummy regions will be filled. Crucially, the dummy regions that are next to "clock nets" (wires that carry timing signals) are filled last. This strategy is used to reduce any negative effects the dummy metal might have on the timing of the clock signals.

• Claim 18 (Computer-Readable Medium): This claim covers a computer program (stored on a computer-readable medium) that, when executed, performs the same two main steps described in Claim 1. That is, it identifies dummy regions and then prioritizes them so that dummy metal is inserted into clock-net adjacent regions last, thereby minimizing timing impact.

• Claim 35 (Method for Inserting Dummy Metal with Timing Factors): This claim outlines a more detailed method for inserting dummy metal:

  1. Identifying free spaces on each layer as dummy regions.
  2. Determining which of these dummy regions are located next to clock nets.
  3. Assigning a "timing factor" to each dummy region. This factor is based on the width of the clock net wire it is adjacent to (wider wires are generally more critical for timing).
  4. Sorting all the dummy regions according to these timing factors.
  5. Inserting dummy metal into the sorted regions. The insertion is done in an order where regions next to progressively wider clock nets are filled last, again to minimize any negative timing impact on the clock nets.

Litigation Information:
The patent "Family has litigation," with a "US case filed in Court of Appeals for the Federal Circuit" identified by case number 24-1057. While this patent has been noted as "Expired - Lifetime" as of April 16, 2024, the listed CAFC case indicates that litigation involving this patent family existed. A search for "CAFC 2026 dockets" provided a schedule of cases for May 2026, but case number 24-1057 was not explicitly listed among those scheduled for that month, so its specific status within 2026 dockets beyond its initial filing is not definitively confirmed by the provided search results.

Based on the provided patent text and the current search capabilities, a significant number of litigation cases involving US patent 7007259 have been identified. While the specific plaintiff(s), defendant(s), filing date, and detailed outcome/current status for each individual case could not be retrieved directly from the search results, the patent document itself lists the jurisdiction and case number for these litigations, with links to Unified Patents for further details. The current assignee of US7007259 is Bell Semiconductor LLC.

Please note that US7007259 expired on April 16, 2024.

Known litigation involving US patent 7007259:

• Jurisdiction: Michigan Eastern District Court

  • Case Number: 2:22-cv-10906
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: California Eastern District Court

  • Case Number: 3:22-cv-01178
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Texas Western District Court

  • Case Number: 1:22-cv-01096
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Texas Eastern District Court

  • Case Number: 4:23-cv-00128
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Texas Eastern District Court

  • Case Number: 4:23-cv-00070
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Delaware District Court

  • Case Number: 1:22-cv-01569
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Oregon District Court

  • Case Number: 3:22-cv-01437
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Oregon District Court

  • Case Number: 3:22-cv-01435
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Ohio Southern District Court

  • Case Number: 3:22-cv-00273
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Idaho District Court

  • Case Number: 1:22-cv-00192
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Ohio Northern District Court

  • Case Number: 3:22-cv-00273 (Note: This case number is identical to the Ohio Southern District Court listing. It may indicate a transfer or an error in the source data).
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: New York Southern District Court

  • Case Number: 1:22-cv-08166
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Minnesota District Court

  • Case Number: 0:22-cv-02344
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Michigan Eastern District Court

  • Case Number: 3:22-cv-11857
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Delaware District Court

  • Case Number: 1:22-cv-01512
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: California Central District Court

  • Case Number: 8:22-cv-01127
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: California Central District Court

  • Case Number: 8:22-cv-01512
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: California Eastern District Court

  • Case Number: 2:22-cv-00726
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Massachusetts District Court

  • Case Number: 4:22-cv-10635
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: California Northern District Court

  • Case Number: 4:23-cv-03116
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: California Southern District Court

  • Case Number: 3:22-cv-00594
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: California Southern District Court

  • Case Number: 3:22-cv-00595
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: California Southern District Court

  • Case Number: 3:22-cv-01178 (Note: This case number is identical to the California Eastern District Court listing. It may indicate a transfer or an error in the source data).
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Colorado District Court

  • Case Number: 1:22-cv-02485
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Court of Appeals for the Federal Circuit

  • Case Number: 24-1057
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee, or related parties).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results (Indicated as 2024 by case number).
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Michigan Eastern District Court

  • Case Number: 2:22-cv-11857 (Note: This case number for Michigan Eastern is listed twice).
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Texas Eastern District Court

  • Case Number: 4:22-cv-00819
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Massachusetts District Court

  • Case Number: 4:22-cv-10636
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Massachusetts District Court

  • Case Number: 1:22-cv-10632
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Massachusetts District Court

  • Case Number: 1:22-cv-10633
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Massachusetts District Court

  • Case Number: 1:22-cv-10634
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Massachusetts District Court

  • Case Number: 1:22-cv-10635 (Note: A case 4:22-cv-10635 for Massachusetts District is also listed).
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Massachusetts District Court

  • Case Number: 1:22-cv-10636 (Note: A case 4:22-cv-10636 for Massachusetts District is also listed).
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Massachusetts District Court

  • Case Number: 1:22-cv-11290
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Massachusetts District Court

  • Case Number: 1:22-cv-11291
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

• Jurisdiction: Massachusetts District Court

  • Case Number: 1:22-cv-11292
  • Plaintiff(s): Not explicitly retrieved from search results (Likely Bell Semiconductor LLC as the current assignee).
  • Defendant(s): Not explicitly retrieved from search results.
  • Filing Date: Not explicitly retrieved from search results.
  • Outcome/Current Status: Not explicitly retrieved from search results.

Proceedings overview

There is no PTAB activity on file for US patent 7007259. This means the patent has not been challenged through AIA trial proceedings at the USPTO.

Strategic summary

As of the current date, all claims of US patent 7007259 are UNTESTED by AIA trial proceedings. There have been no IPR, PGR, or CBM filings against this patent. This implies that the patent has not yet faced validity challenges before the PTAB.

Since there are no AIA trial proceedings, the estoppel provisions of § 315(e)(2) are not applicable. Therefore, all prior-art grounds remain available for potential challengers. The absence of PTAB activity could suggest that the patent has not been extensively asserted, or that previous assertions have not prompted third-party challenges to its validity at the PTAB.

Recommended next steps

Since there is no PTAB activity on file for US patent 7007259, a potential defendant facing assertion of this patent would not benefit from any claims having been invalidated or narrowed through AIA trials. The absence of PTAB activity is a signal that the patent's validity has not been tested in this forum.

Inventors

• Vikram Shrowty: LSI Logic Corp
• Santhanakrishnan Raman: LSI Logic Corp

No unusual patterns, such as all inventors departing within 12 months of filing, are immediately determinable from the provided information.

Original assignee

LSI Logic Corp. was the original assignee. LSI Logic Corp. was a prominent designer and manufacturer of semiconductors and integrated circuits, indicating they shipped products embodying the claims. LSI Logic Corp. was acquired by Avago Technologies in 2014, which subsequently became Broadcom Limited.

Assignment timeline

• 2003-07-28 (executed) / recorded 2003-07-31 — Reel 014374/0425

  • Conveyance: Assignment
  • Assignor: SHROWTY, VIKRAM; RAMAN, SANTHANAKRISHNAN
  • Assignee: LSI LOGIC CORPORATION
  • Correspondent: Not recorded.
  • Context: Original assignment from inventors to employer.

• 2014-05-06 (executed) / recorded 2014-05-08 — Reel 032856/0031

  • Conveyance: Patent Security Agreement
  • Assignor: LSI CORPORATION; AGERE SYSTEMS LLC
  • Assignee: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
  • Correspondent: Not recorded.
  • Context: Securitization of patent assets.

• 2007-04-06 (executed) / recorded 2014-06-06 — Reel 033102/0270

  • Conveyance: Change of Name
  • Assignor: LSI LOGIC CORPORATION
  • Assignee: LSI CORPORATION
  • Correspondent: Not recorded.
  • Context: Change of name for the entity.

• 2014-08-04 (executed) / recorded 2015-02-20 — Reel 035058/0248

  • Conveyance: Assignment
  • Assignor: LSI CORPORATION
  • Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
  • Correspondent: Not recorded.
  • Context: Acquisition of LSI Corporation by Avago Technologies.

• 2016-02-01 (executed) / recorded 2016-02-02 — Reel 037684/0039

  • Conveyance: Termination and Release of Security Interest in Patent Rights
  • Assignor: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
  • Assignee: LSI CORPORATION; AGERE SYSTEMS LLC
  • Correspondent: Not recorded.
  • Context: Release of prior securitization.

• 2016-02-01 (executed) / recorded 2016-02-11 — Reel 037808/0001

  • Conveyance: Patent Security Agreement
  • Assignor: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
  • Assignee: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
  • Correspondent: Not recorded.
  • Context: Securitization of patent assets.

• 2017-01-19 (executed) / recorded 2017-02-03 — Reel 041710/0001

  • Conveyance: Termination and Release of Security Interest in Patents
  • Assignor: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
  • Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
  • Correspondent: Not recorded.
  • Context: Release of prior securitization.

• 2017-12-08 (executed) / recorded 2017-12-17 — Reel 044887/0109

  • Conveyance: Assignment
  • Assignor: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
  • Assignee: BELL SEMICONDUCTOR, LLC
  • Correspondent: Not recorded.
  • Context: Transfer to Bell Semiconductor, LLC.

• 2018-01-24 (executed) / recorded 2018-02-01 — Reel 045216/0020

  • Conveyance: Security Interest
  • Assignor: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
  • Assignee: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
  • Correspondent: Not recorded.
  • Context: Securitization of patent assets.

• 2022-04-01 (executed) / recorded 2022-04-15 — Reel 059720/0223

  • Conveyance: Release by Secured Party
  • Assignor: CORTLAND CAPITAL MARKET SERVICES LLC
  • Assignee: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
  • Correspondent: Not recorded.
  • Context: Release of prior securitization.

Timeline diagram

timeline
    title Ownership of US 7007259
    2003 : Assigned to LSI Logic Corp
    2006 : Patent Granted
    2014 : Security Agreement Deutsche Bank
         : LSI Logic changes name to LSI Corp
    2015 : Assigned to Avago Tech IP (Singapore)
    2016 : Release of Security Interest
         : Security Agreement Bank of America
    2017 : Release of Security Interest
         : Assigned to Bell Semiconductor LLC
    2018 : Security Interest Cortland Capital
    2022 : Release of Security Interest
    2024 : Patent Expired

NPE / troll-pattern signals

1. Shell-entity transfer — present. The transfer from Avago Technologies General IP (Singapore) Pte. Ltd. to BELL SEMICONDUCTOR, LLC (Reel 044887/0109, recorded 2017-12-17) suggests a shell entity. Bell Semiconductor, LLC is the current assignee according to Google Patents and is frequently associated with patent assertion.

2. Known asserter in the chain — present. Bell Semiconductor LLC is a known patent asserter (often referred to as an NPE).

3. Repeat correspondent across the chain — unclear. The provided data does not consistently list correspondent information, so it's not possible to definitively identify recurring correspondents or link them to known NPE activities.

4. Cascading transfers — not present. While there are multiple transfers, they are typically separated by more than 24 months or involve security agreements and releases, rather than a rapid succession of assignments through chained LLCs.

5. Pre-litigation transfer — unclear. The assignment to Bell Semiconductor, LLC occurred in late 2017. A quick search of the Google Patents litigation section shows many cases filed in 2022-2024 by Bell Semiconductor, LLC (e.g., 2:22-cv-10906, 3:22-cv-01178, 1:22-cv-01096), but without precise filing dates for the first suit naming this specific patent, it is hard to say with high confidence if the transfer was within 6 months of litigation. However, the timing is somewhat suggestive, with litigation appearing several years after the transfer.

6. Bankruptcy fire-sale — not present. LSI Logic Corp. was acquired by Avago Technologies, not involved in a bankruptcy fire sale for this patent.

7. Privateering — unclear. While Avago/Broadcom transferred the patent to Bell Semiconductor, LLC, there's no explicit evidence within the provided records to confirm a privateering arrangement where Bell Semiconductor is asserting on Broadcom's behalf against competitors.

8. Defensive aggregator (anti-NPE) — not present. The chain ends with Bell Semiconductor, LLC, which is a known asserter, not a defensive aggregator.

Verdict

NPE — high confidence

The presence of Bell Semiconductor, LLC, a known patent asserter, as the current assignee (Reel 044887/0109, recorded 2017-12-17) is a strong signal. This transfer from an operating company (Avago Technologies) to an entity with a name indicative of a licensing focus, combined with Bell Semiconductor's documented history of patent litigation, strongly points to an NPE pattern.

For verification, you can search the USPTO Assignment Center: https://assignmentcenter.uspto.gov/ (search for patent number 7007259).

To identify the most relevant prior art for US patent 7007259, I will examine the patent citations listed within the patent itself.

Here are the patent citations for US7007259B2 and their potential relevance:

1. US6093214A

• Full Citation: US6093214A, "Standard cell integrated circuit layout definition having functionally uncommitted base cells"
• Publication/Filing Date: Publication Date: July 25, 2000; Priority Date: February 26, 1998
• Brief Description: This patent generally relates to integrated circuit layout definition using standard cells with functionally uncommitted base cells. While it addresses aspects of integrated circuit layout, its primary focus is on standard cell methodology rather than dummy metal filling and its impact on clock nets.
• Potential Anticipated Claim(s) under 35 U.S.C. § 102: It is unlikely to anticipate the core claims of US7007259B2 (Claims 1, 18, 35) directly, as US7007259B2 specifically deals with "clock-net aware dummy metal using dummy regions" and prioritization based on clock nets, especially their widths and criticality. US6093214A does not appear to disclose the prioritization of dummy regions based on proximity or characteristics of clock nets.

2. US6446248B1

• Full Citation: US6446248B1, "Spare cells placement methodology"
• Publication/Filing Date: Publication Date: September 3, 2002; Priority Date: January 28, 2000
• Brief Description: This patent describes a methodology for placing spare cells in an integrated circuit. It concerns the placement of functional units, not the insertion of non-functional dummy metal for manufacturing planarity.
• Potential Anticipated Claim(s) under 35 U.S.C. § 102: Similar to US6093214A, this patent is unlikely to anticipate the specific dummy metal filling and clock-net aware prioritization aspects of US7007259B2's claims (Claims 1, 18, 35).

3. US6815811B2

• Full Citation: US6815811B2, "Semiconductor integrated circuit with dummy patterns"
• Publication/Filing Date: Publication Date: November 9, 2004; Priority Date: November 30, 2000
• Brief Description: This patent broadly discusses semiconductor integrated circuits with dummy patterns. It acknowledges the need for dummy patterns in manufacturing but does not explicitly detail the clock-net aware prioritization method of US7007259B2. While it addresses dummy patterns, its description of the placement method would need to specifically include the prioritization based on clock net adjacency, width, and criticality to directly anticipate the claims of US7007259B2.
• Potential Anticipated Claim(s) under 35 U.S.C. § 102: This patent could be a general reference for the concept of dummy patterns. However, without explicit disclosure of prioritizing dummy regions based on their adjacency to clock nets (and further based on clock net width/criticality) for the purpose of minimizing timing impact, it is unlikely to fully anticipate the specific method claims (Claims 1, 18, 35) of US7007259B2. It might address the broader concept of inserting dummy metal but not the specific "clock-net aware" aspect with prioritization.

4. US6751785B1

• Full Citation: US6751785B1, "System and method for limiting increase in capacitance due to dummy metal fills utilized for improving planar profile uniformity"
• Publication/Filing Date: Publication Date: June 15, 2004; Priority Date: March 12, 2002
• Brief Description: This patent addresses the issue of increased capacitance caused by dummy metal fills and aims to limit this increase to improve planar profile uniformity. This is highly relevant as it deals directly with the negative impact of dummy metal on circuit performance, which is a core problem US7007259B2 seeks to mitigate. The abstract mentions a method for limiting capacitance increase but does not explicitly detail the prioritization scheme of US7007259B2 involving clock nets.
• Potential Anticipated Claim(s) under 35 U.S.C. § 102: This patent is highly relevant as it addresses the core problem of parasitic capacitance due to dummy metal fill. Depending on the full description of its "limiting increase in capacitance" method, it could potentially anticipate aspects of claims related to minimizing timing impact (e.g., the preamble of Claim 1 or 18) if its method inherently or explicitly includes a similar prioritization or consideration of signal nets, especially critical ones like clock nets. However, without a detailed disclosure of prioritizing dummy regions adjacent to clock nets last and further by width/criticality, it might not fully anticipate the specific steps of US7007259B2's claims.

5. US20030177464A1

• Full Citation: US20030177464A1, "Integrated circuit layout method and program thereof permitting wire delay adjustment"
• Publication/Filing Date: Publication Date: September 18, 2003; Priority Date: March 15, 2002
• Brief Description: This patent application describes an integrated circuit layout method and program that allows for wire delay adjustment. This relates to timing, a critical aspect also addressed by US7007259B2. While it focuses on adjusting wire delay, it does not explicitly mention dummy metal filling or its clock-net aware prioritization.
• Potential Anticipated Claim(s) under 35 U.S.C. § 102: This document is relevant to timing optimization in integrated circuits. If its wire delay adjustment method implicitly or explicitly considers the placement of non-functional metal and prioritizes certain nets (like clock nets) in a way that aligns with US7007259B2, it could potentially anticipate certain claims. However, the abstract and general description do not immediately suggest the specific dummy fill prioritization scheme of US7007259B2.

6. US20030204832A1

• Full Citation: US20030204832A1, "Automatic generation method of dummy patterns"
• Publication/Filing Date: Publication Date: October 30, 2003; Priority Date: April 26, 2002
• Brief Description: This patent application describes an automatic generation method of dummy patterns. This is highly relevant as it directly concerns the process of creating dummy patterns. To anticipate US7007259B2, it would need to disclose the specific prioritization of dummy regions adjacent to clock nets, considering their width and criticality.
• Potential Anticipated Claim(s) under 35 U.S.C. § 102: This is a strong candidate for prior art as it describes an "automatic generation method of dummy patterns." If its detailed method for generating dummy patterns includes the steps of identifying dummy regions, determining adjacency to clock nets, assigning timing factors based on clock net characteristics (width, criticality), and prioritizing insertion accordingly to minimize timing impact (as in Claims 1, 18, and 35), then it could potentially anticipate these claims.

7. US20030229479A1

• Full Citation: US20030229479A1, "Dummy fill for integrated circuits"
• Publication/Filing Date: Publication Date: December 11, 2003; Priority Date: June 7, 2002
• Brief Description: This patent application pertains to "dummy fill for integrated circuits." This is another highly relevant piece of prior art. To anticipate US7007259B2, it would need to detail a method that specifically prioritizes dummy metal insertion based on clock net adjacency, width, and criticality to minimize timing impact.
• Potential Anticipated Claim(s) under 35 U.S.C. § 102: Similar to US20030204832A1, this document explicitly addresses "dummy fill for integrated circuits." If its method for dummy filling encompasses the specific prioritization steps related to clock nets as claimed in US7007259B2 (Claims 1, 18, 35), it would be a strong anticipatory reference.

Most Relevant Prior Art Summary:

Based on the titles and brief descriptions, US6751785B1, US20030204832A1, and US20030229479A1 appear to be the most relevant prior art. They directly address dummy metal filling and/or its impact on circuit performance. To determine actual anticipation, a full review of their specifications would be necessary to see if they disclose all the elements of US7007259B2's independent claims, particularly the specific clock-net aware prioritization scheme.

Specifically, US20030204832A1 ("Automatic generation method of dummy patterns") and US20030229479A1 ("Dummy fill for integrated circuits") are highly relevant because they directly concern the generation and insertion of dummy patterns, which is the core subject of US7007259B2. US6751785B1 ("System and method for limiting increase in capacitance due to dummy metal fills utilized for improving planar profile uniformity") is also very relevant as it aims to mitigate the negative electrical effects of dummy metal, which is a key objective of US7007259B2. The novelty of US7007259B2 largely resides in its specific prioritization strategy for dummy metal placement, especially concerning clock nets and their characteristics (width, criticality). Therefore, any prior art that discloses a similar clock-net aware prioritization method for dummy metal insertion would be highly anticipatory.

Obviousness Analysis of US Patent 7007259 Under 35 U.S.C. § 103

This analysis assesses the obviousness of claims in US Patent 7007259 (hereinafter '259 patent) by identifying combinations of prior art references that would render the claimed invention obvious to a person having ordinary skill in the art (PHOSITA) at the time of the invention (priority date July 31, 2003).

The '259 patent addresses the problem of inserting dummy metal for chemical-mechanical planarization (CMP) while minimizing negative timing impact, particularly on critical clock nets. The invention proposes prioritizing dummy regions so that those adjacent to clock nets are filled last, and further prioritizing those adjacent to wider clock nets to be filled even later.

The background of the '259 patent explicitly states that minimizing timing impact from dummy metal, especially on clock nets, was a known problem, and that "the dummy fill tool is programmed to maintain a larger distance between wires of clock nets and the inserted dummy metal." The patent describes this traditional approach as "simplistic" and highlights its disadvantages, such as requiring multiple runs to meet density requirements. This establishes that the problem of timing impact from dummy fill, and the particular importance of clock nets, was well-recognized in the prior art.

Claim 1: Method for Inserting Dummy Metal

Claim 1: A method for inserting dummy metal into a circuit design, the circuit design including a plurality of objects and clock nets, the method comprising:
(a) identifying free spaces on each layer of the circuit design suitable for dummy metal insertion as dummy regions; and
(b) prioritizing the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last, thereby minimizing any timing impact on the clock nets.

Combination of Prior Art References: US20030204832A1 (Nec) in view of US6751785B1 (Ubitech) and general knowledge of a PHOSITA regarding clock net criticality.

• US20030204832A1 (Nec): This reference discloses an "Automatic generation method of dummy patterns." It teaches "calculating the area ratio of actual patterns in each unit area," "detecting dummy pattern regions," and "generating dummy patterns in the dummy pattern regions." These disclosures collectively satisfy element (a) of Claim 1, which involves identifying free spaces suitable for dummy metal insertion as dummy regions. Nec's stated objective to "prevent degradation of circuit characteristics by the generated dummy patterns" also broadly aligns with minimizing negative impact.

• US6751785B1 (Ubitech): This patent directly addresses "limiting increase in capacitance due to dummy metal fills utilized for improving planar profile uniformity." It describes "defining a region of interest around the active circuit components" and "inserting dummy metal fills only if an increase in parasitic capacitance of the active circuit components is within a predetermined limit." Ubitech explicitly teaches minimizing parasitic capacitance from dummy metal to active circuits, which directly relates to minimizing timing impact (element (b) of Claim 1).

• Motivation for Combination: A PHOSITA, seeking to improve dummy fill methods to effectively minimize timing impact (as described in Ubitech for active components generally), would be motivated to adapt a general dummy pattern generation method (like Nec's) to be "clock-net aware." It was well-known in the art (and acknowledged in the '259 patent's background) that clock nets are of critical importance and require care to minimize negative timing impact. Given Ubitech's teaching of limiting capacitance increase around active circuit components, and the common general knowledge that clock nets are particularly critical active components, it would have been obvious to a PHOSITA to treat dummy regions adjacent to clock nets differently. Specifically, to implement Ubitech's principle of limiting capacitance increase for clock nets, a PHOSITA would be motivated to prioritize these clock-adjacent dummy regions to be filled last, thereby maximizing the distance between dummy metal and clock nets and minimizing timing impact, as required by element (b). This combination addresses the known problem of timing degradation due to dummy metal near critical signals, particularly clock nets, using established dummy fill techniques and known methods for managing parasitic effects.

Claim 18: Computer-Readable Medium

Claim 18: A computer-readable medium containing program instructions for inserting dummy metal into a circuit design, the circuit design including a plurality of objects and clock nets, the program instructions for:
(a) identifying free spaces on each layer of the circuit design suitable for dummy metal insertion as dummy regions; and
(b) prioritizing the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last, thereby minimizing any timing impact on the clock nets.

Obviousness: Claim 18 is a method claim directed to a computer-readable medium with program instructions for performing the same steps as Claim 1. If the method of Claim 1 is obvious, then implementing that method as computer program instructions on a computer-readable medium would also be obvious to a PHOSITA skilled in software development for electronic design automation (EDA) tools. The conversion of a known process into computer-executable instructions is a routine engineering task.

Claim 35: Method for Inserting Dummy Metal with Timing Factors

Claim 35: A method for inserting dummy metal into a circuit design, the circuit design including a plurality of objects and clock nets, the method comprising:
(a) identifying free spaces on each layer of the circuit design suitable for dummy metal insertion as dummy regions;
(b) determining which of the dummy regions are located adjacent to clock nets;
(c) assigning a timing factor to each dummy region based on an width of an adjacent clock net wire;
(d) sorting the dummy regions based on the timing factors; and
(e) inserting dummy metal into the sorted dummy regions such that the dummy regions located adjacent to increasingly wider clock nets are filled last, thereby minimizing any timing impact on the clock nets.

Combination of Prior Art References: US20030204832A1 (Nec) in view of US6751785B1 (Ubitech), US20030177464A1 (Fujitsu '177), and general knowledge of a PHOSITA regarding clock net hierarchy and criticality.

• US20030204832A1 (Nec): As discussed for Claim 1, Nec discloses identifying dummy regions (element (a)).

• US6751785B1 (Ubitech): As discussed for Claim 1, Ubitech provides the motivation and teaching for minimizing capacitance/timing impact near critical active circuits (element (e) – minimizing timing impact, and motivation for prioritization).

• US20030177464A1 (Fujitsu '177): This patent describes an "Integrated circuit layout method and program thereof permitting wire delay adjustment." While not explicitly about dummy metal, it highlights the importance of fine-tuning timing characteristics of wires in IC layout. This reinforces the PHOSITA's motivation to consider wire characteristics when dealing with timing-sensitive aspects.

• PHOSITA Knowledge: The '259 patent's own detailed description explicitly states, "In a clock tree, the width of a wire is indicative of its order in a hierarchy. A wide wire is likely to be supplying current to more branches than a thinner wire, and is therefore more timing critical." This statement reflects common general knowledge in the field of IC design. Therefore, determining criticality based on wire width for clock nets, and consequently assigning a "timing factor" based on the width of an adjacent clock net wire (element (c)), would have been obvious to a PHOSITA. Once such factors are assigned, sorting the dummy regions based on these factors (element (d)) is a straightforward and conventional data processing step to enable filling them in a desired order (element (e)).

• Motivation for Combination: Starting from Nec's general dummy fill method and Ubitech's teaching to limit capacitance around active components to minimize timing impact, a PHOSITA would naturally seek to apply this with greater specificity to the highly timing-critical clock nets. Given the universally understood principle that wider clock net wires are generally more timing critical, a PHOSITA would be motivated to differentiate between dummy regions adjacent to clock nets of varying widths (elements (b) and (c)). To effectively implement a refined "limiting increase in capacitance" strategy (Ubitech) or "wire delay adjustment" (Fujitsu '177) that accounts for varying clock net criticality, assigning a quantitative "timing factor" based on wire width is a logical and obvious step. Subsequently, sorting the dummy regions based on these timing factors (element (d)) to ensure that regions adjacent to increasingly wider (and thus more critical) clock nets are filled last (element (e)) would be a straightforward engineering decision to optimize timing predictability and minimize iterative design cycles, as the '259 patent itself identifies as a problem with traditional methods.