US 6456557

I'll search for this specific patent number across USPTO and CAFC sources.

Let me run a couple more targeted searches for litigation/CAFC activity and assignment history.

US 6,456,557 B1 — Identification and Bibliographic Data

All bibliographic data below is taken verbatim from the authoritative full-text record at https://patents.google.com/patent/US6456557/en, cross-checked against Espacenet (https://worldwide.espacenet.com/publicationDetails/biblio?CC=US&NR=[6456557B1](/patent/6456557B1)&KC=B1&FT=D).

Assignment chain (per the Google Patents reassignment record):

• 2001-08-28 — Assigned to Tower Semiconductor Ltd. (assignment of inventors Dadashev/Jacob)
• 2010-11-24 — Assigned to RPX Corporation
• 2018-06-29 — Security interest to Jefferies Finance LLC
• 2019-10-21 — Release of lien (RPX)
• 2020-02-07 — Assigned to Taiwan Semiconductor Manufacturing Co., Ltd. (from RPX)
• 2020-10-26 — Release of security interest
• 2021-08-28 — Anticipated expiration

Caveat: the Google Patents page lists the "Current Assignee" as TSMC while also noting that listed assignees "may be inaccurate." The recorded chain is Tower → RPX → TSMC. I have no independent confirmation of current ownership beyond that record.

Abstract (verbatim)

"A memory device includes a voltage regulator that compensates for resistance variations in the bit line control (multiplexing) circuit used to access the memory cells by including in its feedback path an emulated multiplexing circuit having an identical resistance to that of the multiplexing circuit. The voltage regulator also includes a differential amplifier, a pull-up transistor for generating a reference voltage, and a first clamp transistor controlled by the reference voltage to pass a desired voltage level to the multiplexing circuit. The feedback path incorporates the emulator circuit between a second clamp transistor and a voltage divider. Because the emulation and multiplexing circuits have the same resistance, the voltage passed to the voltage divider is essentially identical to the voltage passed by the multiplexing circuit to a selected memory cell, thereby allowing the voltage regulator to produce an optimal voltage level at the selected memory cell."

Independent Claims — Plain-Language Overview

The patent has three independent claims: 1, 12, and 20 (claims 2–11 depend from 1; 13–19 depend from 12).

Claim 1 — Emulated multiplexing circuit with equal resistance

An IC device comprising:

• a memory cell;
• a first clamp transistor;
• a multiplexing circuit coupled between the first clamp transistor and the memory cell that selectively couples them in response to control signal(s). When coupled, the multiplexing circuit exhibits a "first resistance";
• a voltage regulator including:
  • a differential amplifier whose first input is tied to a reference voltage;
  • a pull-up transistor whose gate is driven by the amplifier output, whose first terminal ties to a first voltage source, and whose second terminal couples to the gate of the first clamp transistor; and
  • a feedback path running from the clamp-transistor gate to the second amplifier input, where that feedback path contains an "emulated multiplexing circuit" whose "second resistance" is equal to the multiplexing circuit's first resistance.

Drafting notes (literal reading): the claim opens with the grammatically off "A integrated circuit device"; the memory cell is first introduced as "a memory cell" but later referred to as "the first memory cell"; and the two independent inputs of the differential amplifier are both described as "the second input terminal," which is imprecise but readable as the non-inverting input.

Claim 12 — Scaled (×M) emulated multiplexing circuit

Same general architecture as claim 1, but the multiplexing circuit is expressly a first transistor and a second transistor in series (turned on by corresponding first and second control signals), exhibiting a first resistance and a second resistance respectively. The feedback path's emulated multiplexing circuit contains a third and fourth transistor in series, where:

• the third transistor's resistance = the first transistor's resistance multiplied by an integer M; and
• the fourth transistor's resistance = the second transistor's resistance multiplied by the integer M.

This claim captures the specification's "multiply by M" teaching used to raise feedback current for loop stability (component-resistance scaling in the emulated path).

Claim 20 — Voltage regulator per se (apparatus-claim framing)

A voltage regulator for generating an actual voltage at a node, where the regulator transmits an intermediate voltage that passes through a multiplexing circuit formed by first pass transistors whose resistances are set by "variable conditions" — and where "the first pass transistors include a first clamp transistor." The regulator comprises:

• a differential amplifier with a first input connected to a reference voltage;
• a pull-up transistor (gate from amplifier output; first terminal to a first voltage source; second terminal to the gate of the first clamp transistor); and
• a feedback path including an emulated multiplexing circuit connected to a voltage divider, where the emulated multiplexing circuit's second pass transistors have resistances equal to the first pass transistors' resistances, so that the emulated voltage equals the actual voltage at the node, and the voltage divider samples that emulated voltage back to the second amplifier input.

Drafting note: claim 20's statement that the multiplexing circuit's "first pass transistors include a first clamp transistor" is loose — the clamp transistor is functionally separate in the specification.

Representative dependent-claim themes: second clamp transistor matched in size to the first and tied to the same second voltage source (claims 2, 13); voltage-divider relation Vdemul = Vbgref × (1 + R4/R3) (claims 3, 14); divider current matched to read cell current (claims 4, 15); a leaker circuit to keep the pull-up transistor in saturation and suppress overshoot (claims 5–7, 16–18); matched series pass-transistor counts between real and emulated muxes and shared gate bias (claims 8–10); and a 2-bit non-volatile memory cell having a nitride layer sandwiched between two oxide layers (claims 11, 19).

Prior Art Cited on the Face of the Patent

U.S. references: US 5,296,801 (Toshiba, bias voltage generating circuit); US 5,768,192 (Saifun, asymmetrical charge trapping cell); US 5,995,412 (Sharp, nonvolatile storage and writing method); US 6,081,456 (Tower Semiconductor, bit line control circuit for 2-bit cells); US 6,195,297 B1 (NEC, pull-down for non-selected bit lines). Non-patent citation: commonly owned application Ser. No. 09/244,316 (Aloni et al., "Methods for Fabricating a Semiconductor Chip Having CMOS Devices and a Fieldless Array").

USPTO / CAFC Docket Check for 6,456,557 (2026)

I ran targeted searches for "6456557" / "6,456,557" combined with CAFC, Federal Circuit, and 2026 docket terms. I found no CAFC 2026 docket, appeal, IPR, or district-court litigation activity involving US 6,456,557. On the record available to me:

• The patent's anticipated expiration was 2021-08-28 and its status is "Expired – Lifetime." A 2026 appellate docket on this patent would therefore be unusual, though not impossible (e.g., a long-tail damages appeal).
• I cannot rule out activity on a docket that is not surfaced by public web search. Treat "no CAFC activity found" as a negative search result, not an affirmative confirmation.

⚠ Near-Number / Unrelated Matches — Do Not Confuse

Two same/similar-digit items surfaced and are not the patent at issue:

1. JP 6456557 B1 — Japanese Patent No. 6456557, Mitsubishi Electric, titled (translated) "Grasping position/posture teaching device…" (B25J 9/22, robot gripping). Same digits, different jurisdiction, different invention.
2. US 6,456,556 B1 — "Voltage regulator and data path for a memory device" — an adjacent but distinct US patent, not US 6,456,557.

Uncertainty Statement

The bibliographic data, abstract, claim text, and cited references above are drawn from the authoritative full-text record and are stated with high confidence. The following carry residual uncertainty: (a) the current owner (the record shows Tower → RPX → TSMC, but Google's "current assignee" field is expressly disclaimed as possibly inaccurate); and (b) the absence of any CAFC 2026 docket — this reflects a negative web-search result, and I have not queried a paid docket service (e.g., Docket Navigator, Lex Machina, or the CAFC's own PACER/CM-ECF) that would be required for a definitive litigation-clearance check.

I'll search litigation-focused sources for US patent 6456557.

Let me try additional targeted searches.

Let me try more targeted searches on litigation databases and possible asserting parties.

Summary: No litigation found

I searched litigation-oriented sources (Unified Patents portal, CourtListener, Docket Alarm, general web) for US 6,456,557 ("Voltage regulator for memory device," Tower Semiconductor Ltd., filed 2001-08-28, issued 2002-09-24, expired 2021-08-28). I found no district court litigation, ITC Section 337 investigation, or PTAB proceeding involving this patent.

What the searches did return

No case caption, docket number, court, or party identifying US 6,456,557 as a patent-in-suit appeared in any result.

Ownership / assignment history (relevant to assertion risk)

From the patent's public record:

• 2001-08-28 — Filed by/applied for Tower Semiconductor Ltd. (inventors Oleg Dadashev, Kyra Jacob)
• 2010-11-24 — Assigned to RPX Corporation
• 2018-06-29 — Security interest to Jefferies Finance LLC; 2019-10-21 release of lien
• 2020-02-07 — Assigned to Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC)
• 2021-08-28 — Anticipated expiration (term expired; status "Expired – Lifetime")

Caveats

• PACER is not directly searchable via the tools available to me, and the Unified Patents litigation caselist / Docket Alarm pages for this specific patent did not surface. Those databases are the most authoritative for a negative confirmation, and my inability to retrieve them directly is a genuine limitation.
• A patent that expired on 2021-08-28 can no longer be asserted for infringement occurring after expiration (infringement requires an unexpired patent), so active litigation is unlikely. However, lawsuits filed before expiration could theoretically have continued (e.g., for past damages/appeals), and I found no record of any such case.
• I cannot rule out a sealed case, a state-court action, or an arbitration/ITC matter that would not appear in the sources searched.

Recommendation if you need a definitive negative: run a party/patent search in PACER's Case Locator, Lex Machina, Docket Navigator, and the RPX/Unified litigation portals restricted to patent number 6,456,557, and confirm via the USPTO Patent Assignment Search that no assertion-related license or transfer is on record.

If you'd like, I can search again with a different source strategy (e.g., focusing on TSMC or RPX as plaintiffs).

Proceedings overview

Total AIA trial proceedings on US 6,456,557: zero. The structured "PTAB proceedings on file" block (USPTO Open Data Portal, most recent ingest) lists no IPR, PGR, or CBM for US 6,456,557, and my independent searches (Google Patents litigation/proceeding tabs, PTAB E2E/PTAB Center document indexes, general web) surfaced no petition, institution decision, FWD, or Federal Circuit appeal naming this patent. There is therefore no "claims invalidated" bucket, no "claims sustained" bucket, no settlement, and no institution denial — the patent's 20 claims (1–20, with independent claims 1, 12, and 20) are all untested at the Board. The bottom-line defensive posture is not "hardened by surviving IPRs" and not "claims canceled" — it is "never challenged, and now expired": the patent's anticipated expiration date was 2021-08-28, which matters far more to a defendant today than the (empty) PTAB docket.

Proceedings on file

None — no AIA trial proceeding has been filed against US 6,456,557

• Type: N/A (no IPR / PGR / CBM docket exists)
• Filed: N/A
• Status: Verbatim from the structured data: no AIA trial proceedings returned for this patent. Google Patents' corresponding status field for the patent as a whole is "Expired - Lifetime" (anticipated expiration 2021-08-28).
• Judge panel: None — no panel has ever been assigned.
• Petition grounds: None. For completeness on vehicle availability: the application was filed 2001-08-28, i.e., pre-AIA, so PGR was never available (35 U.S.C. § 321 applies only to first-inventor-to-file patents); CBM was never available (the patent claims a memory voltage regulator, not a "financial product or service" under § 18 of the AIA); the only viable AIA vehicle was IPR, and none was filed.
• Institution decision: None.
• Final Written Decision: None. No claim of this patent has ever been canceled or confirmed by the Board.
• Settlement / termination: None to report.
• Appeal: None. No CAFC appeal exists because there is no Board decision to appeal. (Note: the CAFC decisions my searches surfaced involving a "'645 patent" — e.g., LG Electronics v. ASUSTeK-related claim construction and the LGE page-mode-memory line of cases — are about different patents numbered '645, not US 6,456,557; do not cite them against this patent.)
• Defensive value: A defendant receiving a demand letter citing US 6,456,557 has no IPR estoppel problem to litigate and no adverse Board precedent to distinguish, and equally no free win from a canceled claim. The decisive defenses lie elsewhere: (1) expiration on 2021-08-28 caps any damages to pre-expiration conduct, and (2) 35 U.S.C. § 286 caps recovery to six years before suit — meaning as of today (2026-09-30) a complaint could reach back only to 2020-09-30, i.e., under one year of pre-expiration damages remain recoverable, shrinking every day. A suit filed after 2027-08-28 recovers nothing.

Context a defendant should have (ownership, assertion history, prior art)

Ownership chain (from the ODP reassignment record, verbatim dates):

The defensive-aggregator signal is strong and answers the "is Unified Patents in the chain?" question in the negative — RPX is. RPX Corporation acquired the patent in 2010 and held it for roughly nine years before transferring it into TSMC's portfolio in 2020. RPX's own Patent Portfolios Report (October 2018) lists US 6,456,557 within the Tower portfolio ("Portfolio developed by Tower Semiconductor relating to CMOS and NVRAM design, manufacturing, reliability, and operation"), a 15-patent set. A patent that sat in an aggregator's defensive portfolio for a decade, was never asserted in any reported district court action I could locate, and then expired, is not the profile of a litigation-tested monetization asset. There is also no serial-petitioner pattern to analyze — no petitioner has ever filed against this patent, once or otherwise.

Prior art already of record (a ready-made invalidity starting kit, if it were ever needed): the examiner cited and considered US 5,296,801 (Toshiba, "Bias voltage generating circuit"), US 5,768,192 (Saifun, asymmetrical charge-trapping memory cell — also referenced in the specification), US 5,995,412 (Sharp), US 6,195,297 (NEC, pull-down for non-selected bit lines), and US 6,081,456 (Tower, "Bit line control circuit for a memory array using 2-bit non-volatile memory cells" — the co-owned companion patent), plus non-patent literature: Aloni et al., application Ser. No. 09/244,316, "Methods for Fabricating a Semiconductor Chip Having CMOS Devices and a Fieldless Array." The '557 patent has 68 citing documents ("Cited By"), including several memory drain-voltage-regulator patents (e.g., US 7,460,415, "Drain voltage regulator," Spansion), which is a useful map of how the art evolved around the claimed emulated-multiplexing feedback path.

What the claims actually cover (for infringement-theory triage): independent claim 1 recites a memory cell, a first clamp transistor, a multiplexing circuit between them, and a voltage regulator whose feedback path includes "an emulated multiplexing circuit having a second resistance that is equal to the first resistance of the multiplexing circuit." Claim 3/14 add the divider equation Vdemul = Vbgref*(1 + R4/R3); claim 5/16 add a leaker circuit; claim 8 adds the same-number-of-series-pass-transistors limitation; claim 11/19 tie to a 2-bit nitride-trapping cell. These are structural, mirror-circuit limitations — narrow, and the kind of claim that is hard to prove infringed without die-level analysis of a feedback replica path.

Strategic summary

Canceled vs. sustained vs. untested. Because no IPR/PGR/CBM was ever filed, no claim of US 6,456,557 is canceled and no claim has been adjudicated sustained — not by the Board, and (on the record I could find) not by any district court. All 20 claims stand as issued, but their validity is entirely untested and now largely irrelevant: the patent expired 2021-08-28. If a demand letter asserts claims 1–20 today, the assertion is not vulnerable to a "claim 1 is dead" argument; it is vulnerable to a timing argument. Enforceable recovery is confined to infringing acts before expiration and, under 35 U.S.C. § 286, to acts within six years of the complaint. Pre-expiration conduct earlier than 2020-09-30 is already time-barred as of 2026-09-30, and the residual window closes against any complaint filed after 2027-08-28.

Estoppel landscape. There is no § 315(e)(2) estoppel against anyone, because there is no petitioner and no final written decision. Conversely, there is no SAS/joinder or Fintiv baggage either. If a defendant somehow faces a live, timely suit today, every § 102/§ 103/§ 112 ground remains fully available in district court and § 282 is unencumbered. Note also that an IPR on an expired patent is legally permissible (the Board applies Phillips-style construction to expired claims), but it is economically irrational where the damages tail is under a year — the correct move is a § 286 / expiration defense, not a PTAB petition.

Pattern signals. No repeat petitioner (none at all); no PTAB appeals by any patent owner (nothing to appeal); the chain runs Tower Semiconductor → RPX Corporation (defensive aggregator, 2010–2020) → TSMC (2020). The RPX intermediate step, the absence of any reported assertion campaign, and expiration less than two years after the TSMC transfer together indicate this patent functioned as portfolio/defensive inventory rather than a litigation weapon. Treat any demand letter invoking it as a low-precision licensing play, not a well-litigated campaign.

Recommended next steps

1. Do not build a PTAB strategy. There is nothing to petition against that would matter, and no estoppel to defeat. Filing an IPR on a patent that expired 2021-08-28, with a § 286 damages reach-back to 2020-09-30, spends six figures to shorten a five-figure exposure. Say so in writing if a plaintiff's counsel raises the IPR threat in negotiation.
2. Lead with expiration and § 286. Demand the plaintiff identify (a) accused products sold on or before 2021-08-28, and (b) the filing date it intends to anchor the § 286 lookback to. Absent both, the damages case is limited to at most the window from 2020-09-30 to 2021-08-28. Confirm whether any terminal disclaimer, § 154(b) patent term adjustment, or intervening PTA/PTE extends the expiration beyond 2021-08-28 — the Google Patents "anticipated expiration" field gives 2021-08-28, and I did not independently verify the face of the patent for a printed PTA figure. That is the one factual point I would verify against the USPTO Patent Center file wrapper before relying on it in a demand response.
3. If a complaint has actually been filed, pull the docket on CourtListener and the district court's CM/ECF to see whether the asserted claims were amended by reissue or reexamination — neither a reissue nor a reexam appears in the record I have, and an expired patent cannot be reissued for prospective effect. Also check for any terminal disclaimer / assignment covenant running from the RPX-era portfolio that could exhaust or license the patent against certain products (RPX member licenses are typically confidential, but if you or your supply chain were an RPX member during 2010–2020, that is a priority inquiry).
4. For the record-keeping point you asked me to be explicit about: sources to monitor for late-indexed proceedings are the USPTO PTAB E2E / PTAB Center docket (https://ptacts.uspto.gov/ptacts/) and the USPTO Patent Center file wrapper for application 09/941,451, plus the Federal Circuit docket and CourtListener for any appeal. My searches produced no hits, so the correct representation to a client remains: no PTAB activity on file, zero AIA trials, zero claims canceled, zero claims sustained — and expiration as the controlling fact. I did not find any PTAB decision, FWD, or CAFC opinion to link for this patent, and I will not manufacture a citation for one.

I'll research the assignment record and the entities in this chain before writing.

Let me dig into the RPX/TSMC transactions and the RPX correspondent patterns.

Let me check for the Tower→RPX 2010 sale and any litigation involving this patent.

I hit the tool-call limit mid-research, and — importantly — I was unable to retrieve reel/frame numbers or correspondent-of-record data for this patent. I will not fabricate them. Below is what the record does support, with explicit gaps flagged.

Assignment Record Reconstruction — US 6,456,557 B1

⚠ Source limitation up front. The USPTO Assignment Center (assignmentcenter.uspto.gov / assignment.uspto.gov) exposes reel/frame, execution vs. recording dates, and correspondent-of-record. I could not pull those fields for this patent — the assignment-center index was not returned by the tooling available to me. The Google Patents legal events view (https://patents.google.com/patent/US6456557/en#legalEvents) does supply the entity names and event dates, and it is the basis for everything below. Reel/frame numbers and correspondent names below are marked "NOT RETRIEVED" rather than estimated. Any downstream "repeat correspondent" analysis is therefore incomplete and must be re-run against the Assignment Center directly.

Inventors

Pattern notes:

• Both inventors are Israel-based and both assigned to the Israeli parent, not to a US subsidiary — consistent with Tower's R&D being centered at Fab 1/Fab 2 in Migdal Haemek.
• No inventor-departure fire-sale pattern is observable. The original assignee (Tower) retained the patent for ~9 years after filing, then divested in 2010. I found no evidence of either inventor leaving Tower within 12 months of filing — and I did not find departure data at all. This signal is untested, not cleared.

Original assignee

Tower Semiconductor Ltd. (Israel, incorporated 1993; at the time of filing and issuance a NASDAQ/TASE-listed specialty semiconductor foundry; later branded TowerJazz after the September 2008 merger with Jazz Technologies).

• Primary line of business: pure-play specialty wafer foundry — CMOS image sensors, RF/mixed-signal, power management, and embedded non-volatile memory. Fabrication, not a chip-product company in the consumer sense.
• Did they ship a product embodying the claims? Partially / indirect. This patent is process-technology IP covering the voltage regulator and bit-line multiplexing scheme used to read 2-bit (NROM-style, ONO charge-trapping) cells — the same cell family described in the patent's own cited art (US 5,768,192, Saifon; US 6,081,456, Tower). Tower's own SEC filings describe Fab 2 supporting embedded flash / NVM technology and NVM as one of its differentiated process platforms. So the invention is enabled into Tower's foundry process offering to customers rather than being sold as a standalone Tower-branded memory device. I have not found a specific Tower part number that maps to this patent.
• Current status: Operating. Tower Semiconductor Ltd. remains a public, independent specialty foundry (fabs in Israel, Newport Beach CA, San Antonio TX, and TPSCo in Japan). It was not in bankruptcy. Note for context: Intel announced an acquisition of Tower in Feb 2022 that was terminated in Aug 2023, with Intel instead agreeing to provide foundry services and make an investment; Tower continues operating. (Moderate confidence on the current corporate status; the patent-relevant point — Tower never filed Chapter 7/11 — is high confidence.)

Assignment timeline

All entries below are from the Google Patents reassignment record for US 6,456,557. Reel/frame and correspondent fields: NOT RETRIEVED.

1. 2001-08-28 (executed) / recorded on or about 2001-08-28 — Reel NOT RETRIEVED

   • Conveyance: Assignment (of inventors' rights)
   • Assignor: Oleg Dadashev; Kyra Jacob (individually)
   • Assignee: Tower Semiconductor Ltd. (Israel)
   • Correspondent: NOT RETRIEVED
   • Context: Standard employment/original assignment filed contemporaneously with the application.

2. 2010-11-24 — Reel NOT RETRIEVED

   • Conveyance: Assignment of interest
   • Assignor: Tower Semiconductor Ltd.
   • Assignee: RPX Corporation
   • Correspondent: NOT RETRIEVED
   • Context: Portfolio divestiture by the operating company to a defensive aggregator — i.e., a cash-generating asset sale to RPX's catch-and-hold fund, ~9 years post-issuance, with no assertion by Tower in the interim.

3. 2018-06-29 — Reel NOT RETRIEVED

   • Conveyance: Security interest / Security Agreement
   • Assignor: RPX Corporation
   • Assignee: Jefferies Finance LLC (collateral agent)
   • Correspondent: NOT RETRIEVED
   • Context: Securitization — RPX pledged patent collateral to its lender. This is a financing event, not a change of ownership.

4. 2019-10-21 — Reel NOT RETRIEVED

   • Conveyance: Release of lien on patents
   • Assignor: Jefferies Finance LLC (as collateral agent)
   • Assignee: RPX Corporation (lien released back to RPX)
   • Correspondent: NOT RETRIEVED
   • Context: Release of securitization — the 2018 pledge was discharged, restoring RPX's unencumbered title.

5. 2020-02-07 — Reel NOT RETRIEVED

   • Conveyance: Assignment of interest
   • Assignor: RPX Corporation
   • Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC)
   • Correspondent: NOT RETRIEVED
   • Context: Aggregator-to-operating-company divestiture. Corroborated independently: IAM Media reported on 2020-02-25 that "Taiwan Semiconductor bolsters portfolio in AMD, RPX deals — The chipmaker picked up over 100 US patents in transactions executed last year, assignments show" (https://www.iam-media.com/index.php/industry/technology?page=339). That matches the RPX→TSMC recording date and confirms this was part of a bulk, multi-patent transfer, not a patent-specific deal.

6. 2020-10-26 — Reel NOT RETRIEVED

   • Conveyance: Release of security interest
   • Assignor: Jefferies Finance LLC
   • Assignee: RPX Corporation
   • Correspondent: NOT RETRIEVED
   • Context: Residual securitization cleanup. Note the sequencing oddity: this release was recorded after the 2020-02-07 assignment to TSMC, meaning it appears to relate to a pledge the record does not otherwise show, or to a blanket release covering assets (including this patent) that had already moved. Worth an Assignment Center pull to confirm whether a second, unlisted security agreement exists.

7. 2021-08-28 — Anticipated expiration (no conveyance). Patent is listed Expired – Lifetime; term ran 20 years from the 2001-08-28 filing with no recorded term extension or PTA visible in the record.

If the Assignment Center shows additional entries (e.g., a change-of-name for Tower→TowerJazz, an internal Jazz/Tower US Holdings conveyance, or a second security agreement), those would slot between 2001 and 2010 and around 2019–2020 respectively. The Google record does not show them.

Timeline diagram

timeline
    title Ownership of US 6456557
    2001 : Filed and assigned to Tower Semiconductor
    2002 : Patent issued
    2010 : Assigned to RPX Corporation
    2018 : Security interest to Jefferies Finance
    2019 : Lien released back to RPX
    2020 : Assigned to TSMC
         : Further security interest released
    2021 : Anticipated expiration

NPE / troll-pattern signals

Verdict

Defensive / non-asserting (with an explicit caveat on the rubric's "terminus" wording)

Justification: the ownership chain is Tower Semiconductor Ltd. (2001-08-28) → RPX Corporation (2010-11-24) → TSMC (2020-02-07), and at no point in that ~20-year life was this patent asserted. The nine-year RPX appearance on the 2010-11-24 record placed the asset squarely in the defensive-aggregation stream that exists precisely to suppress NPE assertions, and the patent exited to a non-asserting operating foundry rather than to any listed asserter — then expired 2021-08-28. NPE — high confidence is ruled out (zero of the strong signals — shell entity, known asserter, pre-litigation transfer, <24-month cascade — are present), and Operating-company assertion is ruled out (no suit by TSMC or anyone else against a competitor was found). The strict-rubric mismatch is that "Defensive / non-asserting" is defined as the chain terminating at the aggregator; here it terminated at TSMC. On the available record, defensive/non-asserting is the nearest fit and the alternative ("Insufficient data") is not warranted because six recorded events are documented.

Confidence: moderate. It is capped by two gaps — (a) no reel/frame or correspondent data retrieved, and (b) no litigation-clearance search performed against a paid docket service.

Verify at: https://assignment.uspto.gov/patent/index.html (search 6456557) and https://patents.google.com/patent/US6456557/en#legalEvents

Explicit non-findings / things I did not establish

• Reel/frame numbers for any of the seven events — NOT RETRIEVED. Not estimated.
• Correspondent of record for any event — NOT RETRIEVED. Signal 3 is therefore unresolved.
• Executive dates vs. recording dates — I have only the Google legal-events dates, which are recording-side. The Assignment Center pull is required to distinguish "executed" from "recorded."
• No CAFC / district-court / IPR activity found on this patent (negative search result only — consistent with the prior section's finding of no 2026 CAFC docket).
• Consider a mismatched near-number: the JP 6456557 B1 hit (Mitsubishi Electric, robot gripping, B25J 9/22) surfaced again during this search — same digits, unrelated patent, different jurisdiction. Do not merge into this chain.

I'll verify each cited reference and search USPTO records for US 6,456,557. Running targeted searches.

Prior-Art Analysis for US 6,456,557 B1 ("Voltage regulator for memory device")

Scope note / search method. I queried Google Patents, Espacenet, FreePatentsOnline, and patentimages for the literal number 6456557 and for each of the five U.S. references printed on the face of the patent. The bibliographic record returned matches the front page of the patent at issue (Dadashev/Jacob, Tower Semiconductor, app. 09/941,451, filed 2001‑08‑28, granted 2002‑09‑24). I did not substitute results for adjacent numbers (e.g., US 6,456,556) or for same‑digit foreign documents (e.g., JP 6456557 B1) — those are excluded as required.

Critical framing for the §102 analysis: The five references below are the art cited by the examiner. Four of them (US 5,296,801; US 5,768,192; US 5,995,412; US 6,195,297) predate the 2001‑08‑28 priority date and are true prior art. US 6,081,456 is the applicant's own earlier Tower Semiconductor patent (filed 1999‑02‑04, granted 2000‑06‑27) and is also prior art. The single novel limitation of every independent claim — a feedback path containing an "emulated multiplexing circuit" whose resistance equals that of the real multiplexing circuit — is absent from every one of these references, so none of them anticipates claims 1, 12, or 20 individually under §102. They are relevant as §103 combination art and as §102 art against specific sub-features claimed in dependencies. I state this explicitly rather than manufacturing anticipation that the references do not support.

1. US 5,296,801 A — Kabushiki Kaisha Toshiba

Description. A bias-voltage-generating circuit that supplies a controlled bias to a memory's bit lines. A differential/sense arrangement clamps the bit‑line potential to approximately Vbias − Vthn during read so that the cell drain does not rise high enough to cause "soft write" (inadvertent programming). The circuit includes a load transistor pair (N1/N2/N3) and reset devices driven by a chip‑enable signal, and the output node feeds the gates of pass/clamp transistors (Q1, Q4) that sit between the cell and the sense lines.

Anticipation analysis.

• Claim 20 (voltage regulator per se, "the first pass transistors include a first clamp transistor") is the closest fit, because US 5,296,801 expressly discloses a transistor that clamps the bit‑line voltage of a memory cell to prevent disturb. However, claim 20 also requires (a) a differential amplifier with a reference voltage input, (b) a pull‑up transistor with gate driven by that amplifier's output and first terminal tied to a first voltage source, and (c) a feedback path including an emulated multiplexing circuit connected to a voltage divider with matched resistances. None of (a)–(c) is disclosed, so claim 20 is not anticipated — this reference is at most §103 art for the "clamp transistor" element.
• Claim 1 — discloses a clamp transistor and a bit‑line node, but not a multiplexing circuit between the clamp and the cell, nor the feedback/emulated‑mux structure. No anticipation.
• Claim 12 — no series first/second pass transistors, no ×M emulated transistors. No anticipation.

Potential §102/§103 relevance: Best mapped to the generic "clamp transistor" and "prevent soft‑write by limiting cell drain voltage" concepts recited in claims 1, 12, 20; useful only in combination.

2. US 5,768,192 A — Saifun Semiconductors, Ltd.

Description. The foundational ONO (oxide–nitride–oxide) charge‑trapping, 2‑bits‑per‑cell memory cell. Trapping dielectric (silicon nitride) is sandwiched between two silicon‑dioxide layers; the cell is programmed in the forward direction and read in the reverse/backward direction, which localizes the trapped charge near one junction and permits two independently stored bits. Claim 4 recites the two SiO₂ layers with the nitride between them; claim 5 recites "said charge trapping layer comprises silicon nitride"; claims 12/14–15 recite nitride/SiO₂/P‑type/N+ combinations.

Anticipation analysis.

• Claims 11 and 19 ("a 2‑bit non‑volatile memory cell including a nitride layer sandwiched between two oxide layers") — the memory‑cell sub‑feature is fully disclosed by US 5,768,192 (see its claim 4/5 and Fig. 2). But claims 11 and 19 are dependent on claims 1 and 12 respectively and therefore also require the entire voltage‑regulator architecture. Since US 5,768,192 discloses no voltage regulator, it cannot anticipate claims 11/19 as a whole, only the cell structure they borrow.
• Claims 1, 12, 20 — no voltage regulator, no differential amplifier, no emulated multiplexing circuit. No anticipation.

Potential §102/§103 relevance: The strongest §102 reference for the "2‑bit cell / nitride‑between‑oxide" limitation recited in dependent claims 11 and 19, and background/motivation art explaining why a precise drain voltage (1.5–2 V) is required.

3. US 5,995,412 A — Sharp Kabushiki Kaisha

Description. A non‑volatile (multi‑value) storage device that concurrently performs write and verify. It includes a latch circuit, a multi‑value sense amplifier, and importantly a bit‑line voltage generating circuit that applies a specified voltage to the bit line connected to a selected memory cell based on latched input data and read‑back data. The word‑line read/write voltage is held constant to reduce gate disturbance.

Anticipation analysis.

• The reference discloses a "bit line voltage generating circuit" — superficially a cousin of the patent's voltage regulator 420 — but its control is data/verify driven, not a closed‑loop differential amplifier feeding a clamp transistor through an emulated multiplexing circuit.
• Claim 20 — includes a "voltage regulator … transmitting an intermediate voltage that is passed through a multiplexing circuit," but US 5,995,412 has no differential amplifier + pull‑up transistor + clamp transistor + emulated‑mux feedback path. No anticipation.
• Claims 1 and 12 — no multiplexing circuit between a clamp transistor and the cell, no matched‑resistance feedback. No anticipation.

Potential §102/§103 relevance: Background art showing that bit‑line voltage generation/pass‑transistor routing for non‑volatile cells was known; supports a §103 obviousness rationale only when combined with a regulator reference. No standalone §102 hit against any claim.

4. US 6,081,456 A — Tower Semiconductor Ltd. (same assignee)

Description. Discloses the bit‑line control / multiplexing architecture later reproduced in the patent at issue: first‑level and second‑level column selectors built from pass transistors, OBL/EBL odd/even lines, and second‑level pass transistors (n‑channel and p‑channel) that can reverse the bit‑line pair order so a 2‑bit cell can be read in either direction (reverse read). Claims recite "controlling the first‑level pass transistors to selectively couple a subset of the first set of bit lines to a second set," and "coupling each bit line … to a parallel‑connected pair of second‑level pass transistors," with reversal of order for the two charge‑trapping regions.

Anticipation analysis.

• Claims 8, 9, 10 (multiple series‑connected pass transistors; equal gate voltage on real and emulated pass transistors; two NMOS transistors with gates connected together) — the real multiplexing‑circuit structure (series first/second‑level pass transistors, NMOS second‑level devices) is disclosed in US 6,081,456. But claims 8–10 depend from claim 1 and thus also require the emulated multiplexing circuit with equal resistance. US 6,081,456 has no emulated mux and no regulator feedback, so it cannot anticipate them as whole claims.
• Claim 12 — the "first transistor and second transistor connected in series" multiplexing circuit matches US 6,081,456's two‑level pass‑transistor YMUX. But claim 12 also requires the emulated third/fourth transistors scaled ×M in the feedback path — absent. No anticipation.
• Claims 1, 20 — multiplexing circuit present in US 6,081,456; differential amplifier, pull‑up, clamp transistor, and emulated‑mux feedback path absent. No anticipation.

Potential §102/§103 relevance: The most pertinent reference on the "multiplexing circuit / pass‑transistor" element of claims 1, 8–10, 12, and 20. Because it is the applicant's own prior art describing the exact YMUX the patent's regulator is designed to compensate for, it is the natural §103 primary reference for the YMUX half of the invention. Still does not meet the feedback‑path limitation.

5. US 6,195,297 B1 — NEC Corporation

Description. A semiconductor memory device in which non‑selected bit lines are pulled down (biased to a low reference rather than left floating) to improve read margin and reduce coupling. Concerns bit‑line biasing/leakage management adjacent to selected columns.

Anticipation analysis.

• Claim 5 / 16 (leaker circuit) — The patent's "leaker circuit" (claims 5–7, 16–18) draws a constant current to keep the pull‑up PMOS in saturation and suppress overshoot; it is not the same function as pull‑down of non‑selected bit lines. US 6,195,297's pull‑down is for non‑selected bit lines, a different node and purpose. No anticipation of the leaker‑circuit claims.
• Claims 1, 12, 20 — no differential amplifier/feedback/emulated mux. No anticipation.

Search caveat: my lookup for US 6,195,297 returned a step‑limited result, so the description above relies on the title/date data from the face of the patent at issue rather than a fresh full‑text read. Treat the characterization as medium confidence and verify against the reference's own specification before relying on it.

Potential §102/§103 relevance: Peripheral art on bit‑line biasing; possible §103 support for bit‑line‑node‑biasing concepts, but not a §102 reference against any claim of the patent at issue.

6. Non‑Patent Citation — Ser. No. 09/244,316 (Aloni et al.)

Description. Fabrication‑process disclosure for a chip integrating CMOS periphery with a fieldless (virtual‑ground) array. It is cited because the patent at issue relies on the process‑matching premise — that the pass transistors of the multiplexing circuit and the emulated transistors are "fabricated during the same process steps," giving matched resistances over process variation.

Anticipation analysis. A fabrication‑method reference discloses no voltage‑regulator circuitry; it cannot anticipate any of claims 1–20. Its role is evidentiary support for the enablement / matching rationale, not §102 art.

Consolidated §102 summary table

Bottom line. The patent's point of novelty — the emulated multiplexing circuit inside the regulator feedback path, resistance‑matched to the real YMUX — is not disclosed by any cited reference, and accordingly no cited reference invalidates claims 1, 12, or 20 under §102. The references divide cleanly into (a) the YMUX/multiplexing art (US 6,081,456, most relevant), (b) the bit‑line clamp/bias art (US 5,296,801, US 5,995,412, US 6,195,297), and (c) the 2‑bit cell art (US 5,768,192). Their realistic use is as §103 combination art (e.g., US 6,081,456 + US 5,296,801 as primary/secondary references), and as §102 art against the sub‑features of dependent claims (claims 8–10 pass‑transistor structure via US 6,081,456; claims 11/19 cell structure via US 5,768,192).

Uncertainty. (1) The US 6,195,297 lookup was truncated; its functional description is from the patent's own title/date, not an independent full‑text read. (2) I did not read the full claim sets of US 5,296,801 or US 5,995,412 line‑by‑line; the anticipation conclusions rest on their abstracts, claim excerpts, and the reasons the examiner cited them. (3) My §102 conclusion that no reference anticipates the independent claims is a negative finding from the available text, not a guarantee that no uncited art reads on them.

I'll ground this §103 analysis in the actual content of the five references and the NPL item cited on the face of US 6,456,557. Let me pull details on each.

Now the two Tower/Sharp references and the Saifun cell patent:

Obviousness Analysis — US 6,456,557 B1 under 35 U.S.C. § 103

Building on the prior sections (bibliographic record, claim map, and the five-reference citation list), this section treats the art cited on the face of the patent as the universe of prior art, plus the applicant-admitted prior art disclosed in the patent's own Background (FIG. 1 regulator) and specification. The five references are: US 5,296,801; US 5,768,192; US 5,995,412; US 6,081,456; US 6,195,297 B1, and the NPL item (Ser. No. 09/244,316, Aloni et al.).

1. Governing framework and the level of ordinary skill

Effective filing/priority date: 2001-08-28. All five references predate that date (1994, 1998, 1999, 2000, 2001), so each qualifies as prior art under § 102(b)/(e).

PHOSITA (proposed): a BS-level electrical engineer with ~3–5 years in non-volatile memory IC design, conversant with (i) bit-line clamp/biasing circuits, (ii) column-decoder and Y-multiplexer architecture built from series pass transistors, (iii) op-amp feedback regulators and resistor dividers, and (iv) charge-trapping (ONO / NROM-type) cells and their read-voltage sensitivities. This is a mature, crowded, highly predictable art — the KSR prerequisite of a "finite number of identified, predictable solutions" is easily satisfied here.

Graham factors: (1) scope/content of prior art; (2) differences between prior art and claims; (3) level of ordinary skill; (4) secondary considerations (none of record).

2. The art of record — what each reference actually teaches

Critical observation: No reference of record discloses or suggests placing a replica ("emulated") multiplexing circuit in the feedback path of the regulator so that the regulator's feedback loop closes around a copy of the access resistance. That is the sole point of novelty in independent claims 1, 12, and 20. Any § 103 rejection must therefore be built as a combination in which the emulation feature is supplied either by an additional reference (not of record here) or by Official Notice / judicial notice of the well-known "replica" / "dummy tracking" technique, and the remaining elements are supplied by the art of record plus the patent's own admitted prior art.

3. Element mapping for claim 1 (the pivot claim)

Claim 1 breaks into a preamble set plus a "voltage regulator" set. The regulator's non-emulation portions are admitted prior art: the patent's own FIG. 1 (and its Background text) describes a conventional regulator comprising a differential (operational) amplifier 132, a PMOS pull-up 134, a clamp transistor 136, and a resistor divider 138 feeding back to the op-amp input. Under MPEP 2129, an applicant's own characterization of prior art in the specification is admissible as prior art.

The combination and its motivation

Combination A (primary rejection theory): Admitted FIG. 1 regulator + US 6,081,456 + US 5,296,801, optionally + knowledge of replica-path biasing.

Reasoning a PHOSITA would follow, articulated without hindsight:

1. The problem was known and expressly recognized. US 5,296,801 states the object of clamping the bit-line during read so that cell drain voltage does not rise to the soft-write region, and further that the bias must be constant independent of Vcc. US 6,081,456 fixes the read level at ~2 V for the very same 2-bit ONO cell. The patent's own Background states that variations in Vdrain cause Vt margin loss.
2. The cause was known. It is elementary that series pass transistors in a column multiplexer contribute an IR drop that varies with process, temperature, and supply. A PHOSITA reading US 6,081,456's two-level pass-transistor mux would recognize its series impedance as part of the read path.
3. The solution was a known, finite, predictable technique in this art. Closing a regulator/current-mirror loop around a scaled replica (dummy) of the signal path — replica bit lines, dummy cells, matched "tracking" transistor stacks — was standard in analog/memory design (e.g., matched tracking devices to cancel process/temperature drift). A PHOSITA who has already been taught (FIG. 1) to sample the regulated node through a divider has a plain design incentive to move the sampling point downstream of the multiplexer, and doing so through a matched replica gives the predictable result of cancellation of common-mode resistance variation.
4. Reasonably expected to succeed. Device matching is routine; fabricating the emulation transistors "at the same time and at the same size" as the mux transistors is exactly how designers ensure tracking. No unpredictable mechanism is invoked.

Result: claim 1 obvious under § 103 as a matter of the combination, provided the fact-finder accepts Official Notice (or an added reference) for the replica-path technique. Without that, a prima facie case on the art of record alone is not made out for the equal-resistance emulation limitation.

Dependencies of claim 1

4. Claim 12 — the ×M scaled emulation

Claim 12 restates claim 1 but recites the mux as two series transistors (met by US 6,081,456's first- and second-level pass transistors) and requires the emulated transistors' resistances to be the real transistors' resistances multiplied by an integer M.

• The two-series-transistor limitation is squarely met by US 6,081,456.
• The ×M scaling is the patent's own stated means of raising feedback current for loop stability (specification: "the current can be increased by any multiple M by increasing the resistance of each element in emulated path 914 by the multiple M"). Choosing M is routine optimization of a design parameter with a known, predictable effect (set feedback-loop current/pole). Under KSR, "a patent composed of several elements is not proved obvious merely by demonstrating that each element was independently known," but here the variation is a mere scaling of an already-suggested parameter with a predictable result — a textbook obvious-to-try/design-choice scenario.
• Claims 13–19 track claims 2–11 and carry the same analysis (13 ↔ 2, 14 ↔ 3, 15 ↔ 4, 16–18 ↔ 5–7, 19 ↔ 11).

Net: claim 12 rises or falls with the same replica-limitation gap as claim 1; the "M" integer does not add meaningful patentable weight.

5. Claim 20 — the broadest and most vulnerable claim

Claim 20 is drafted as a voltage regulator per se and is strikingly loose. It recites:

• a multiplexing circuit "formed by first pass transistors having first resistances determined by variable conditions," and — critically — that "the first pass transistors include a first clamp transistor."

That last phrase conflicts with the specification, where the clamp (906) is a distinct device and the YMUX (930) is composed of pass transistors 702/812. As drafted, claim 20 (a) covers a regulator whose "multiplexing circuit" merely contains the clamp and pass devices, and (b) requires only that the emulated pass transistors have resistances equal to the first pass transistors'.

Under the broadest reasonable interpretation:

• US 5,296,801 + US 6,081,456 together disclose a bit-line clamp fed by a generated bias, driving a pass-transistor multiplexer to a 2-bit cell, with the clamp/pass devices' impedances set by "variable conditions" (the patent's own definition).
• The only remaining element is the emulated mux in the feedback path with equal resistance.

Because claim 20 is not tied to the specific pull-up/diff-amp topology as tightly as claims 1/12 and its "include a first clamp transistor" bridge is ambiguous, claim 20 is the easiest independent claim to invalidate — a single well-placed secondary reference or Official Notice establishes the replica path, and the claim's own looseness supplies the rest.

6. Where the § 103 case is weak (and why the patent issued)

1. The dispositive limitation is absent from the art of record. None of US 5,296,801 / 5,768,192 / 5,995,412 / 6,081,456 / 6,195,297 discloses a feedback path containing a replica of the multiplexing circuit. US 5,296,801's feedback/bias network loops around its own devices, not around the downstream bit-line selection path. The examiner allowed the case over exactly this gap.
2. Hindsight risk. The problem statement ("compensate for resistance variations in the multiplexing circuit") and the solution ("emulate the multiplexing circuit in the feedback path") are stated in the same breath in the specification. A rejection that merely takes the patent's recitation of the problem and maps it onto the art risks impermissible hindsight. The proper rebuttal to hindsight is the combination's independent motivation in the references: US 5,296,801's own stated object (constant, supply-independent clamp bias), plus US 6,081,456's two-level pass-transistor mux for 2-bit cells with a 2 V read level. Those two provide the problem and the structures; the replica technique must come from the general knowledge of the art.
3. No secondary-considerations record. I found no evidence of unexpected results, industry praise, licensing-for-merit, or long-felt-but-unsolved need in the record reviewed. Conversely, there is no evidence of copying either. So nexus-based rebuttal is unavailable on this record — which helps an obviousness challenge.
4. Prior-art status of US 6,081,456 and the Aloni NPL. Both are commonly owned, same-inventor-lineage Tower materials. Their use as art is permitted (they are § 102(b)/(e) art and not disqualified), and US 6,081,456 is especially strong because it is the actual multiplexer the patent's regulator is designed around — but a challenger should expect an argument that these are merely "the inventor's own earlier work," which does not defeat their prior-art status but may affect weight.

7. Comparative vulnerability ranking

8. Explicit uncertainty and caveats

• Factual basis: I reviewed the contents of the five references through public full-text sources (Google Patents and mirrors) and the patent's own face record. I have not verified every figure/paragraph citation line-by-line against the PDFs. Two points I cannot assert with high confidence: (a) whether US 5,296,801 contains any differential-amplifier topology (the retrieved abstract/claims describe a load-and-diode-stack bias generator, not an op-amp — so I have not relied on it for the "differential amplifier" element, which I instead attribute to the patent's own admitted FIG. 1 prior art); and (b) the exact correspondence between NPL Ser. No. 09/244,316 and issued US 6,346,442 (Aloni), which I infer from the fieldless-array subject matter and inventor name.
• No additional art considered: This analysis is confined to the art of record per the task instruction. A real-world § 103 rejection of the independent claims would most likely require at least one secondary reference disclosing replica/dummy-path feedback compensation, or a documented Official Notice supported by technical literature — neither of which is in the five-reference set. If such art does not exist as of 2001-08-28, the independent claims may well withstand a § 103 attack on this record, while claims 11/19 and 20 remain the most exposed.
• No legal conclusion: This is a technical-obviousness assessment, not a validity opinion. A formal invalidity analysis should run the full Graham/KSR record, including any yet-unlocated secondary references and any evidence of unexpected results.
• Consistency check with prior sections: Nothing here contradicts the earlier sections; this analysis depends on the claim map (three independents 1/12/20) and the citation list already generated. The one flagged tension is internal to the patent itself — claim 20's "first pass transistors include a first clamp transistor" versus the specification's separation of clamp 906 from YMUX 930 — which I treat as broadening rather than correcting, per the literal-reading rule.