US 5138619

I'll verify this patent's details through searches, including checking for any CAFC 2026 litigation activity.

Let me run a couple more targeted searches to check for any litigation, PTAB, or CAFC docket activity involving this specific patent number.

US Patent 5,138,619 — Verification Summary

Searches performed: Google Patents (via the authoritative full text supplied, plus live fetch), FreePatentsOnline, Justia, Unified Patents portal, and general web queries for litigation/PTAB/CAFC activity. No results were found for any Federal Circuit (CAFC) 2026 docket, PTAB proceeding, or district-court litigation specifically involving patent 5,138,619. I could not confirm any CAFC 2026 activity; treat "none found" as a negative search result, not an affirmative certification.

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Bibliographic Data

Literal-record notes (per the "do not auto-correct" rule):

• The assignment record on the Google Patents page names the assignee as "NATURAL SEMICONDUCTOR CORPORATION" (Assignors: Bridgewater, Walter F.; Fasang, Patrick P.). This is the record as printed, and it appears to be a transcription artifact for National Semiconductor Corporation — I am flagging it rather than silently correcting it, per your rule.
• Date discrepancy: The Unified Patents portal lists priority/app date 1990-02-14 and grant date 1992-08-10, whereas Google Patents (authoritative in your instructions) lists 1990-02-15 / 1992-08-11. I am treating the Google Patents dates as controlling; the one-day variance is unexplained.
• Examiner is listed by the secondary source (Unified Patents) as Smith, Jerry / Hua, Ly V. — not corroborated by Google Patents, so treat as low-confidence.
• Claim 1 typography artifact: As printed, the PSA PRPG element is introduced with "…said data PRPG comprising:" where the intended antecedent is said PSA PRPG. Also a malformed "having and clocked by" appears in claim 9. These are text/OCR defects in the published claim text; I have not altered them.

Classifications: G11C29/00, 29/04, 29/08, 29/12, 29/14, 29/18, 29/20 (BIST / built-in arrangements; address generation using counters or LFSRs).

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Abstract (as issued)

A built-in self-test ("BIST") circuit for on-chip testing of an IC memory. A control logic circuit responds to an external signal on a test select pin to control the BIST operations of the major circuit groups: an address PRPG (pseudo-random pattern generator) supplying test or mission addresses; a data PRPG supplying test or mission data; a PSA (parallel signature analyzer) PRPG that passes mission data through in normal mode and computes a signature in test mode; and a decoder that compares the PSA signature against a known-correct signature and sets a pass/fail flag. The design is modular/extendable to any N-word × M-bit memory: the control-logic counter, address PRPG, data PRPG, and PSA PRPG are each built by replicating a "slice", so only certain feedback paths and certain control-logic combinatorial circuits need customization.

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Plain-Language Overview of the Independent Claims

(1) Apparatus claim (independent). An integrated-circuit memory that tests itself, having three external pins/interfaces: a clock input, a BIST-select input, and a BIST error-flag output. It comprises:

• a RAM;
• an address PRPG connected to the RAM by a parallel address bus, built from a chain of substantially identical, successively arranged address slices — each slice (after the first) takes its test-address input from the immediately preceding slice's output — plus an address PRPG feedback circuit whose output feeds the first slice and whose inputs tap selected slices;
• a data PRPG, similarly built from identical cascaded data slices with its own data PRPG feedback circuit feeding the first slice;
• a PSA PRPG ("parallel signature analyzer") connected to the RAM by a parallel data output bus,built from identical cascaded PSA slices that take their data inputs from respective RAM bits, plus a PSA PRPG feedback circuit; and a parallel signature output bus made of the PSA slice outputs;
• a decoder holding a predetermined known-correct signature; it compares the determined signature on the signature bus against the known signature and sets the BIST error flag to indicate pass/fail; and
• control logic wired to the BIST-select input and clock input, with output control lines to the address PRPG, data PRPG, PSA PRPG, and decoder — including provision of a seed number to the data PRPG.

In short: the independent apparatus claim is directed to a slice-replicated, LFSR-based BIST architecture that wraps a RAM with address/data pattern generation and on-chip signature comparison, with a single test-select pin.

(14) Method claim (independent) — "method for designing" the BIST circuit. For a memory with an address bus of preselected width and a data bus of preselected width, the steps are:

1. Replicate an address slice a selected number of times per the address-bus width; serially interconnect them to form an address PRPG (the slices being its stages), providing test address bits to the memory; provide a feedback signal to the first stage derived from selected stage outputs;
2. Replicate a data slice per the data-bus width; serially interconnect to form a data PRPG with its own derived feedback signal to the first stage;
3. Replicate a PSA slice per the data-bus width; serially interconnect to form a PSA PRPG that receives respective memory data bits on its inputs and provides signature bits on its outputs; provide a feedback signal to its first stage from selected stage outputs; and
4. Provide a known-correct signature for comparison against the signature bits to determine memory pass/fail.

Notably, this is drafted as a design/construction method (slice replication and feedback derivation), not merely an operating method. Claim 15 depends from claim 14 and sets the replication counts for an N×M memory: address slice replicated A+1 times (where 2**A = N), data slice replicated M times, PSA slice replicated M times.

Dependent claims (2–13, non-independent) add: a sliced counter in the control logic with ripple register-carry between slices (2–3); a pattern control bit PCB that selects the seed vs. its complement on reset/initialize (4); a read/write signal RW sequencing first/second write and read cycles, with PCB switching at the second write (5); data-slice and address-slice and PSA-slice internal structures (6, 8, 9, 10); mission/test mode multiplexing per slice type (7); and stage-count relationships — data/PSA stages = M (11), address stages = A+1 (12, 13).

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Supporting Technical Detail from the Specification

• Worked example is a 256×8 single-port RAM; full test runs 2,049 clock pairs, with the general formula (8 × 2**M) + 1 clock cycles.
• Seeds: 0 on the first fill and its complement (255) on the second fill, to obtain stuck-at-fault coverage by writing each word with a pattern and its complement.
• Address PRPG is deliberately sized A+1 bits (9 bits for 256 words) because an 8-bit LFSR yields only 255 unique values, so one address would otherwise be skipped.
• Feedback taps are tabulated for 2–30 LFSR stages (e.g., 8 stages → taps 3, 5, 7, 8; 9 stages → taps 5 and 9).
• Prior art cited in the background: U.S. Pat. No. 4,433,413 (Fasang, 1984); non-patent literature includes Abadir & Reghbati (1983), Scholz et al. (1989), and Nadeau-Dostie et al. (1989 CICC).

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Confidence / Uncertainty Statement

• High confidence in the title, inventors, application number, assignee, claim count, abstract, and claim substance — these are drawn from the authoritative full text you supplied and corroborated by multiple independent patent databases.
• Moderate confidence in the exact issue/filing day and examiner name, given the 1-day and attribution discrepancies noted above; I have not resolved them.
• Negative finding, not a certification: I found no evidence of any CAFC 2026 docket, PTAB IPR, or infringement litigation naming 5,138,619. This is consistent with the patent having expired in 2010. If you need a definitive litigation check, a paid docket service (e.g., Darts-IP, Lex Machina, or the CAFC/PACER dockets directly) would be required; open web search is not a reliable negative for that question.

I'll search for litigation involving US patent 5138619 across patent litigation sources.

Let me search more targeted litigation databases.

Search Results: Litigation Involving U.S. Patent No. 5,138,619

Bottom line: I found no litigation — past or pending — involving U.S. Patent No. 5,138,619 ("Built-in self test for integrated circuit memory," Fasang & Bridgewater, National Semiconductor Corp., issued Aug. 11, 1992).

What I searched and what I found

I searched patent-litigation aggregators and court sources (Unified Patents portal, RPX Insight, Justia Dockets, CourtListener, Docket Alarm, and general litigation reporting) for the exact identifier 5138619 / 5,138,619.

Caution about false positives

My searches returned several decisions referencing a "'619 patent," but none of them involve U.S. 5,138,619 — they concern other patents that happen to share the last three digits:

• Tuna Processors, Inc. v. Hawaii International SeaFood, Inc., 327 F. App'x 204 (Fed. Cir. 2009) — a "619 patent" on cooling smoke before contacting tuna (unrelated art).
• Speedfit LLC v. Woodway USA, Inc. — the '619 patent there is a treadmill/exercise patent.
• Upjohn Co. v. Medtron Laboratories, Inc., 800 F. Supp. 1181 — the '619 patent there is a pharmaceutical patent.
• Hailo Technologies' U.S. Patent No. 5,973,619 (taxi-dispatch, asserted against Uber/Lyft) — a different number entirely.

None of these is U.S. 5,138,619, and I have excluded them.

Contextual notes (from the patent record itself)

• Original assignee: National Semiconductor Corp. (assignment recorded Feb. 15, 1990 to "NATURAL SEMICONDUCTOR CORPORATION" — a typographical variant in the assignment record; the patent lists National Semiconductor Corp.).
• Current assignee of record: Natural/National Semiconductor Corp. (subsequently acquired by Texas Instruments in 2011).
• Legal status: "Expired – Lifetime"; anticipated expiration Feb. 15, 2010 (20 years from the Feb. 15, 1990 filing date). The patent has now been expired for over 16 years as of the April 26, 2026 current date.
• The patent is heavily cited by later patents (162 citing-document entries in the Google Patents "Cited By" list; 269 "Referenced By" items on Unified Patents), so it appears as prior art/metadata in other documents — which is a common source of misleading hits — but that is not litigation.

Caveat on completeness

Because I was unable to complete exhaustive queries against every paid docket system (PACER full-text, Lex Machina, Docket Navigator, or RPX's full case database), I cannot certify that zero suits exist in every venue. However, based on the public litigation-focused sources searched, no assertion of U.S. 5,138,619 surfaced. If you need a definitive negative, the appropriate confirmation steps would be a Lex Machina / Docket Navigator patent-case search on the patent number, plus a PACER full-text search across all district courts and the Federal Circuit.

Conclusion: No known litigation involves U.S. Patent No. 5,138,619. It appears to be a National Semiconductor portfolio patent that was never asserted and has been expired since February 15, 2010.

Proceedings overview

Zero AIA trial proceedings are on file for US 5,138,619 — the USPTO Open Data Portal returns no IPR, PGR, or CBM for this patent, and my independent web checks surfaced no petition, institution decision, Final Written Decision, or Federal Circuit appeal naming it (the ODP result is the default "no PTAB activity on file," and nothing in the public record contradicts it).

Because there is no proceeding list, there are no per-proceeding entries to populate — I will not manufacture case numbers. What follows instead documents the verification trail and the far more consequential fact for a defendant: the patent's term has already expired, so there is no live PTAB posture to litigate at all.

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Verification trail (what was checked, and what it returned)

• Structured source (canonical): "PTAB proceedings on file" block supplied with this task — returns no AIA trial proceedings as of the most recent ODP ingest.
• Google Patents family/prosecution record (https://patents.google.com/patent/US5138619/en): the only prosecution-history entries are the 1990-02-15 application filing, the 1990-02-15 assignment to National Semiconductor Corporation, the 1992-08-11 grant, and the 2010-02-15 anticipated expiration. No PTAB trial-history entries appear on the patent page — Google Patents does surface IPR/PGR links when they exist, and there are none here.
• Web searches for the patent number paired with "IPR," "PTAB," "inter partes review," "petition," "challenged," and "docketalarm" returned only: (a) prior-art citation listings from later patents (e.g., U.S. 5,701,308; U.S. 6,000,048) that cite the '619 patent as background art on BIST; (b) foreign search reports citing it; and (c) unrelated hits (an Italian municipal procurement ID and an FCC document ID that happen to share the number).
• Unified Patents portal (https://portal.unifiedpatents.com/patents/patent/US-[5138619](/patent/5138619)-A): the page exists, and I flag it so the next searcher is not misled — but it is a crowdsourced prior-art page, not evidence of a proceeding. Its listed art (U.S. 4,433,413 to Fasang; Abadir & Reghbati; Nadeau-Dostie et al.; Scholz et al.; National Semiconductor ASIC Design Manual) is essentially the same material cited on the face of the '619 patent itself. Treat it as a search aid, not as an IPR docket entry. No Unified Patents IPR is on record for this patent.

Bottom line for a defendant: there is no IPR or PGR estoppel to work with, and no cancelled claims — but there is also no patent left to assert. The defensive posture is not "hardened by PTAB" or "claims canceled"; it is "the right has run its course."

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Patent status facts that actually drive the defense

These are grounded in the Google Patents record, not in any PTAB filing:

Two claims-drafting details worth noting if anyone ever does challenge it (both are § 112 footholds, not § 102/103 ones): claim 1 recites "said data PRPG comprising:" when introducing the PSA PRPG elements, and dependent claim 8 refers to "an AND gate for applying a seed number to a second input of said multiplexed flipflop" in the address slice where the specification describes a complemented NAND gate — antecedent-basis / typographical-mismatch territory under § 112(b). That is an observation about the text, not a ruling by anyone.

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Strategic summary

Claim status: all 15 claims are UNTESTED, not SUSTAINED. This is the critical distinction. No claim of the '619 patent has ever been canceled, and none has ever been adjudicated patentable by the Board. Do not tell a client that claims 1–15 "survived" anything — they were simply never challenged at the PTAB. The reason is structural rather than tactical. The patent was filed 1990-02-15 and granted 1992-08-11, making it a pre-AIA patent. PGR was never available (post-grant review reaches only first-inventor-to-file patents filed on or after 2013-03-16), and CBM was inapplicable — the claims are directed to on-chip RAM self-test circuitry, not to a "financial product or service," so § 18 of the AIA never supplied a hook. IPR, created 2012-09-16, was theoretically available for the roughly eighteen months of post-AIA life remaining before the 2010-02-15... namely none: the patent expired 2010-02-15, more than two and a half years before the first IPR was ever filed in the United States. The AIA trial regime simply post-dates this patent's enforceable life. The absence of PTAB activity is therefore not a signal that the patent is a hardened survivor that scared off challengers — it is a signal that the window in which an AIA petition could have mattered had already closed.

Estoppel landscape: there is none, and it does not matter. 35 U.S.C. § 315(e)(2) estoppel attaches only to petitioners (and their privies) in an instituted IPR that reaches a final written decision. With no institution, no petitioner is estopped, and any party accused of infringement would be free to raise § 102/§ 103 grounds in district court. But the practical vehicle for those grounds is gone too: an IPR petition must be filed within one year of service of a complaint alleging infringement (§ 315(b)), and IPRs can be instituted against expired patents (the Board has done so, and applies Phillips claim construction to expired claims per Wasica Fin. GmbH v. Cont'l Auto. Sys., 853 F.3d 1272 (Fed. Cir. 2017)). Filing an IPR against an expired patent would be an exercise in fee-paying, not defense — for reasons in the next paragraph, there is nothing to defend against.

Pattern signals: none. No petitioner has filed anything (first, second, or serial petitions) against this patent; the patent owner (National Semiconductor, now subsumed into Texas Instruments' lineage) has never appeared as a patent owner before the Board on this patent and therefore has no PTAB appeal history here; and there is no defensive aggregator — Unified Patents is not in this chain, notwithstanding that its portal hosts a prior-art page for the patent. The only "pattern" visible is bibliographic: the '619 patent is heavily cited as background art by later BIST patents (U.S. 5,701,308; U.S. 6,000,048, among others cited above), which is a recognition signal, not an enforcement signal.

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Recommended next steps

1. If you are a defendant and received a demand letter citing US 5,138,619, the threshold response is the expiration date, not the PTAB. The patent's legal status is "Expired - Lifetime" with an anticipated expiration of 2010-02-15 (https://patents.google.com/patent/US5138619/en). No claim can be infringed by post-2010-02-15 activity. There is no Final Written Decision to quote, because no proceeding exists — so the demand cannot be grounded in any PTAB disposition, favorable or unfavorable.
2. Run the damages math before anything else. Under 35 U.S.C. § 286, damages are recoverable only for infringement occurring within six years before the complaint is filed. From today (2026-09-21) the § 286 lookback reaches to 2020-09-21 — a period entirely after the patent expired on 2010-02-15. Absent an unusual and unsupportable theory of pre-2010 conduct, the recoverable-damages figure is zero, and any suit should be answered with a Rule 12 motion or an early summary judgment motion rather than an IPR petition.
3. Do not file an IPR. It would burn six figures in fees and a year of statutory clock (institution decision within six months of filing under § 314(b); final written decision within twelve months of institution under § 318(a)) to invalidate an already-expired patent. It also risks nothing positive — with no live claims, there is no infringement exposure to estop away.
4. If someone tells you this patent "was never invalidated at the PTAB," treat that as a red herring, not a strength. The correct framing is that AIA trials (2012+) post-date the patent's expiration (2010-02-15). Untested ≠ validated. The patent's entire claim set is UNTESTED and, of equal importance, unassertable going forward.
5. Keep the record honest for the client briefing. Cite the Google Patents record for status and expiry; describe the Unified Patents page (https://portal.unifiedpatents.com/patents/patent/US-5138619-A) as a prior-art collection only; and state plainly that no PTAB E2E or CourtListener docket exists for this patent because no AIA trial was ever filed.

Confidence note: the ODP "no proceedings" result plus the absence of any PTAB or CAFC docket trace in search gives me high confidence in the zero-count conclusion. I could not view a raw PTAB E2E docket query in this session, so if the matter is high-stakes, a one-click confirmation at https://ptacts.uspto.gov/ptacts/ and a Federal Circuit docket check on the patent number is cheap insurance before you represent the absence as fact in a filing.

I'll reconstruct the assignment record. Let me search the USPTO assignment sources and cross-reference.

Let me dig into the assignment record details and inventor backgrounds.

I have enough to reconstruct the chain. One important limitation up front: I was not able to retrieve the individual USPTO Assignment Center detail page (reel/frame + correspondent) for US 5138619 in this session — the Assignment Center is a JavaScript application that does not expose its record detail to the search tools available here, and the mirror indexes (Google Patents legal events, Unified Patents, FreePatentsOnline, uspto.report) surface only the event summary, not the reel/frame or the corresponding attorney. I flag that explicitly rather than invent a reel/frame. Everything below is built from the event record that is verifiable, plus the patent front matter and corporate history.

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Inventors

Unusual patterns: A departure pattern exists but is benign, not fire-sale-linked. Fasang's published career path is National Semiconductor → Hitachi Semiconductor (manager, ASIC product engineering) → Altera Corporation (senior member of technical staff, marketing), a normal semiconductor-industry career arc. Crucially, no inventor retained or later acquired an interest in US 5138619 — both inventors assigned 100% to National at filing, and no inventor appears as an assignor or assignee in any later record. This is the opposite of the "inventors keep the patent and later sell it" pattern. No conclusion of "all inventors departed within 12 months → portfolio fire-sale" is supported here.

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Original assignee

• Entity on the issued patent: National Semiconductor Corporation, Santa Clara, California (patent front matter, [73]).
• Recorded assignment spellings: the USPTO assignment record spells the assignee "NATURAL SEMICONDUCTOR CORPORATION" — a well-known typographical variant of "National Semiconductor" appearing in National's own recording paperwork; the patent document and all later bibliographic records read "National Semiconductor Corporation." (This same quirk was flagged in the earlier litigation section; I confirm it is a record-spelling artifact, not a distinct entity.)
• Primary line of business: National Semiconductor was a U.S. analog/mixed-signal and ASIC semiconductor manufacturer. It is a true operating company, not a holding vehicle.
• Did it ship a product embodying the claims? Yes — indirectly but demonstrably. The patent is directed at on-chip BIST for RAM embedded in ASICs, and the specification expressly builds on National's own 256×8 single-port RAM macrocell and macrocell library (NSC ASIC Design Manual No. 400010, Rev. 1, 1987), citing NSC macrocell part numbers (C056/X056, C001/X001, X930, X970, X973, C830/X830, etc.) throughout. The claimed "slice" architecture was implemented in NSC's ASIC/RAM-compiler macrocell library, so National shipped the enabling macrocell family.
• Current status: Acquired/dissolved as an independent entity. Texas Instruments completed its acquisition of National Semiconductor in September 2011, making TI the successor-in-interest to National's patent estate. No assignment or merger record transferring US 5138619 to Texas Instruments was surfaced as a recorded event (TI's acquisition was effected as a merger, so chain of title passes by operation of law and did not require a per-patent assignment filing). The patent itself expired for lack of maintenance/term on 2010-02-15 — before the TI deal closed.

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Assignment timeline

Only one assignment is of record. The Google Patents legal-events record for US 5138619 shows a single reassignment event, dated the filing date, with the assignor pair Bridgewater/Fasang and assignee National Semiconductor; there are no subsequent post-issuance transfers, security interests, mergers, or changes of name on the record.

• 1990-02-15 (executed) / recorded 1990-02-15 — Reel/frame: not retrievable in this session (USPTO Assignment Center detail page did not expose reel/frame through the tools available; see caveat at top)
  • Conveyance: Assignment ("ASSIGNMENT OF ASSIGNORS INTEREST" — original filing assignment, i.e., inventor-to-employer)
  • Assignor: Walter F. Bridgewater and Patrick P. Fasang
  • Assignee: "NATURAL SEMICONDUCTOR CORPORATION" (record spelling) = National Semiconductor Corporation, Santa Clara, CA
  • Correspondent: not retrievable in this session — cannot assess repeat-player status without the recorded attorney/agent of record
  • Context: Original inventor-to-employer assignment executed contemporaneously with filing — not an acquisition, fire-sale, securitization, or transfer-to-asserter. Standard operating-company practice: employees assign their inventions to the employer as a condition of employment.

No later link exists. There is no second link to analyze for cascading transfers, shell-entity transfer, or pre-litigation transfer, because the chain never moved again.

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Timeline diagram

timeline
    title Ownership of US 5138619
    1990 : Inventors assign to National Semiconductor
         : Application filed same day
    1992 : Patent issued Aug 11
    2010 : Patent expires Feb 15
    2011 : National Semiconductor acquired by Texas Instruments

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NPE / troll-pattern signals

1. Shell-entity transfer — not present. The only assignee in the chain is National Semiconductor Corporation, a public operating semiconductor manufacturer. No "IP / Patents / Licensing / Holdings / Ventures" suffixed entity ever appears. No single-purpose LLC, no registered-agent service address, no Delaware/Texas shell. (Reel/frame detail unavailable, but the assignee name on the single recorded event is unambiguous and is corroborated by the patent's [73] field.)

2. Known asserter in the chain — not present. Neither National Semiconductor Corporation nor Texas Instruments (successor-in-interest) appears on any public NPE list (Acacia, Marathon, IV, IPNav, Wi-LAN, Conversant/Mosaid, Vringo, Pendrell, Round Rock, etc.). No asserter entity appears anywhere in the chain.

3. Repeat correspondent across the chain — not assessable / no chain to recur on. With a single recorded assignment, there is no second link against which to test recurrence. The 1990 correspondent of record could not be retrieved, so I cannot confirm or deny repeat-player status — I flag this as a genuine data gap rather than calling it negative.

4. Cascading transfers — not present. Zero consecutive post-issuance transfers, let alone multiple LLC-to-LLC hops within 24 months.

5. Pre-litigation transfer — not present. No infringement suit naming US 5138619 was found (per the earlier litigation section), and no assignment postdates issuance at all, so no "clean standing" transfer exists.

6. Bankruptcy fire-sale — not present. National Semiconductor was acquired by Texas Instruments in a solvent, ~$6.5B strategic acquisition (2011); it did not file Chapter 7/11 and no patent sale in bankruptcy proceedings touched this patent. The patent had already expired nine months before the TI deal closed (expiry 2010-02-15), so it could not have been an asset in that transaction.

7. Privateering — not present. No transfer to any third-party NPE, and no evidence of National/TI using an NPE proxy to assert this patent. The patent was never in suit.

8. Defensive aggregator — not present (and not needed). The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. Neutralization here came from term expiry (2010-02-15), not from defensive aggregation.

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Verdict

Insufficient data (only the original assignment).

Justification: the documented record contains exactly one assignment — the 1990-02-15 inventor-to-employer assignment of Fasang and Bridgewater to "NATURAL SEMICONDUCTOR CORPORATION," executed the same day the application was filed — with no post-issuance transfers, no LLCs, no NPE, and no litigation over the patent's entire life. That single-record chain falls squarely within the "only the original assignment" prong of the insufficient-data category: there is simply no transfer activity from which an NPE pattern could arise, and the original assignee is a genuine operating semiconductor company whose macrocell library embodies the claimed slice architecture, later succeeded by Texas Instruments (2011). This should be read as a clean, non-NPE chain rather than an ambiguous one — the patent sat with its operating-company owner and expired on 2010-02-15.

Two documented gaps to close for a certifiable negative: (a) retrieve the reel/frame and correspondent of record for the 1990-02-15 assignment from the USPTO Assignment Center, and (b) confirm no post-2011 TI merger-side assignment exists.

Verify at the USPTO Assignment Center: https://assignmentcenter.uspto.gov/ and https://assignment.uspto.gov/patent/index.html (search patent number 5138619). Patent record: https://patents.google.com/patent/US5138619/en

I'll research the prior art cited in and against US 5,138,619, starting with USPTO and patent-database lookups.

I found the USPTO/PTO-side citation records. Let me now pull details on the individual cited references to assess § 102 relevance.

Let me pull the remaining cited references' details.

I've completed the searches. Note: I hit the tool-call limit before I could pull independent abstracts for a few of the lower-relevance references (US 4,369,511; 4,370,746; 4,608,683; 4,785,785; 4,835,774; 4,876,685; 4,888,772; 4,788,684), so for those I rely on the PTO/Unified Patents citation record for title/date/assignee and on the art field for the description — flagged below as lower confidence. Everything else is grounded in the fetched records.

Date discrepancy flagged (carrying forward): your task header says "Current Date: April 26, 2026," while my session date is 2026-09-21. The earlier summary sections used April 26, 2026. I flag rather than silently reconcile; it does not affect the analysis.

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Prior Art for US 5,138,619 — Examiner-Cited References

A. The authoritative citation record

Per the USPTO-side citation record (Unified Patents "Patent Art (12)" / "Non-Patent Literature (14)" lists for US-5138619-A, corroborated by Google Patents' citation table), the reference set considered during prosecution consists of 12 US patents and 8 unique non-patent items (listed 14 times, several duplicated). These are the references that were before the examiner. Note this list differs from the references cited in the patent's own background section — the background mentions only US 4,433,413 and three NPL items, while the PTO record contains the full 12-patent search.

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B. US Patent References — § 102 analysis

1. US 4,903,266 — "Memory Self-test" ⭐ most relevant

Description. On-chip memory self-test using a random pattern generator ("RPG") built on a primitive polynomial, connected to both the address lines and the input (data) lines of the memory array, and a multiple-input signature register ("MISR") connected to the memory output lines. Critically, the RPG has "at least one stage in addition to the number of address lines" — the extra stage(s) are not connected to addressing — specifically so that the all-zero address is generated and every memory address is exercised (see '266 claims 8 and 10, which recite "exactly one stage in addition to the number of address lines"). Data is written to every address, then read back and compressed into the MISR; seeding is done by scanning known data in.

Claims potentially anticipated:

• Claim 1 (partial/strong). '266 discloses the RAM, an address-side PRPG (LFSR) plus a data-side shift register, a MISR (i.e., a parallel signature analyzer) fed from the memory data outputs, and on-chip control — mapping to elements (b), (c), (d), (e). It does not expressly disclose the "substantially identical slices" architecture, a single BIST-select pin, or an on-chip decoder holding a predetermined known-correct signature.
• Claims 11, 12, 13 (strong). The stage-count relationships are the closest match in the entire set: claim 12/13 (address PRPG stages = A+1 where 2**A = N) is essentially the express teaching of '266 (m = address lines; at least m+1 RPG stages; claim 10: exactly one extra stage).
• Claim 2 (partial). '266 discloses control clocks/mode-select for sequencing, but not a ripple-carry sliced counter as recited.

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2. US 4,782,487 — "Memory Test Method and Apparatus" ⭐ most relevant on claims 4–5

Description. A memory test in which a first pattern of pseudo-random data is written into the memory in a pseudo-random address sequence determined by an address LFSR, read back and checked; then a second pattern that is the complement of the first is written in the same pseudo-random address sequence and checked; then a third pattern with complementary check bits. Claim 16 of '487 expressly recites the data generator as a linear feedback shift register; claim 17 recites the address generator is an LFSR that can address memory address zero as part of the pseudo-random sequence.

Claims potentially anticipated:

• Claim 4 (strong). '487's "write pattern, then write the complement of that pattern" directly reads on the PCB limitation (seed vs. its complement on reset/initialize).
• Claim 5 (strong). '487's ordered first-pattern / complement-pattern write-and-read cycles with a read/write sequencing map onto the "first write and read cycles and second write and read cycles" of claim 5.
• Claim 1 (partial). Address LFSR + data LFSR + write/read/compare; but '487 checks with ECC or a comparator, not a parallel signature analyzer and not an on-chip decoder holding a predetermined correct signature — so claim 1's (e)/(f) elements are not met.

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3. US 4,433,413 — "Built-in Apparatus and Method for Testing a Microprocessor System" ⭐ same inventor; closest on the control-logic architecture

Description. Adds a pseudo-random pattern generator (PRPG), a signature register (SR), supplemental control logic, serial/parallel I/O port test logic, and a display to a microprocessor system (RAM + PROM). Test input data comes from the test instructions in PROM and the PRPG; test output is processed by the SR and the microprocessor, with results on a display. The background of '619 itself cites this patent as the starting point for its own technique.

Claims potentially anticipated:

• Claim 1 (partial). Supplies the PRPG + signature register + control-logic combination and the internal-pattern-generation concept, but the signature evaluation is not done by an on-chip decoder against a hard-wired known-correct signature (the microprocessor reads out and processes it off the SR), and there is no address-PRPG/data-PRPG/PSA-PRPG slice triad.
• Claim 14 (partial/conceptual). The general PRPG-plus-signature-bits-plus-known-correct-signature-for-comparison methodology is disclosed; the slice replication and feedback-tap derivation steps are not.

Because '619's independent claims are directed to architecture rather than to the general PRPG/signature concept, '413 is best characterized as § 103 background art for claim 1 rather than a § 102 anticipation.

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4. US 4,788,684 — "Memory Test Apparatus"

Description. Memory test apparatus with an algorithmic pattern generator applied to the memory under test and an auxiliary pattern generator that stores the expected values, against which the memory output is compared — i.e., a built-in comparator/expected-value architecture. (This reference is also cited by the examiner against the IBM EP 0472818 family, confirming its subject matter.)

Claims potentially anticipated:

• Claim 1 (partial). On-chip pattern generation into the memory plus on-chip comparison of memory output to expected data maps to elements (b), (c)/(d) and (f) in functional terms. It does not disclose a PSA/MISR compression register, a signature bus, or a decoder containing a predetermined known correct signature (it stores expected values, not a compressed signature).

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5. US 4,888,772 — "Testing Circuit for Random Access Memory Device"

Description (lower confidence — abstract not independently retrieved). An on-chip testing circuit for a RAM, of the type that supplies test data/addresses to a RAM and evaluates the read-out response. Companion in the same technical neighborhood as '3785 and the NEC '403 family.

Claims potentially anticipated:

• Claim 1 (partial, low confidence). Plausibly reads on the memory-plus-test-circuit combination and possibly on on-chip signature/compare logic; I could not verify the internal structure (slice replication, feedback circuit, PSA bus) and therefore do not assert anticipation on this reference.

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6. US 4,788,785 — "Method and Apparatus for Diagnosis of Logical Circuits"

Description (lower confidence). Diagnosis of logic circuits using compressed-response / signature-style analysis. Relevant to the general signature-compression principle underlying the PSA.

Claims potentially anticipated: Claim 1 only weakly (signature-compression concept). No slice architecture, no memory address/data PRPG pair, no on-chip decoder-against-known-signature. Not an anticipation.

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7. US 4,835,774 — "Semiconductor Memory Test System"

Description. External/ATE-type semiconductor memory test system (pattern generation and address scrambling for a memory tester). This is automatic test equipment, not embedded on-chip BIST.

Claims potentially anticipated: None credibly. '619 claims an integrated circuit self-testing memory (on-chip). Off-chip tester art does not anticipate the "integrated circuit ... comprising a random access memory ... connected to said memory by a parallel address bus" limitations. Relevant only as background/§ 103 context.

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8. US 4,876,685 — "Failure Information Processing in Automatic Memory Tester"

Description. Failure-data capture/redundancy analysis in ATE memory testers. Off-chip tester art.

Claims potentially anticipated: None credibly (same reasoning as '5774 — this is external test equipment, not on-chip BIST). Background only.

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9. US 4,369,511 — "Semiconductor Memory Test Equipment"

Description (low confidence). External semiconductor memory test equipment — address/data pattern generation and error detection for discrete memory devices under external control.

Claims potentially anticipated: None credibly. External tester; does not disclose the on-chip integrated self-test architecture of claim 1.

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10. US 4,370,746 — "Memory Address Selector"

Description. A memory address selector — address-generation/selection circuitry for accessing a memory.

Claims potentially anticipated: Claim 1 only as to the generic "address bits to the memory" element. No pseudo-random pattern generation, no slices, no feedback circuit, no signature analyzer, no decoder. Not an anticipation; boilerplate address-path art.

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11. US 4,603,683 — "Test Apparatus for Digital Speech Interpolator for Use in Time Division Multiple Access Scheme"

Description. Test apparatus for a digital speech interpolator used in TDMA — audio/DSP-specific test circuitry, not RAM BIST.

Claims potentially anticipated: None. Different art (telephony/DSP test). This appears to be a mis- or broadly-classified citation; it is not § 102 art against any of claims 1–15 on its face.

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12. US 4,195,770 — "Test Generator for Random Access Memories"

Description. A RAM test generator that produces both the input data and the address inputs to a memory under test, operating under computer control. Data selector means responsive to a pattern counter couples one of the RAM address lines to the memory input logic, so that each data bit's binary value is a function of the address line signal level (walking/alternating address-derived patterns such as 1010, 1100, 1111… ). Includes an address counter and error-detection logic that compares RAM outputs F0–F3 against generator inputs I0–I3 via exclusive-NOR gates.

Claims potentially anticipated:

• Claim 1 (partial, weak). Discloses internally generated addresses and data feeding a RAM plus on-chip/at-tester comparison (EX-NOR equality check), which touches elements (b), (c)/(d) and (f). But the data is a deterministic function of the address lines, not a pseudo-random data PRPG with its own feedback circuit; there is no PSA/MISR and no predetermined-signature decoder.
• Claims 12/13 (weak). Uses an address counter, not an A+1-stage LFSR address PRPG.
• Relevant chiefly as evidence that "pattern generator feeds addresses + data + comparison logic" was long known.

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C. Non-Patent Literature (printed publications)

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D. Bottom line

1. No single reference in the cited set appears to anticipate claim 1 in full. The independent apparatus claim requires the combination of (i) three separate PRPGs (address, data, PSA) each built from substantially identical replicated slices, (ii) three feedback circuits tapping selected stages, (iii) an on-chip decoder holding a predetermined known-correct signature that drives a dedicated BIST error-flag output pin, and (iv) control logic keyed to a BIST-select input providing a seed. No cited reference shows the replicated-slice/feedback-tap architecture, and none shows the PSA-plus-known-signature decoder.

2. Anticipation risk concentrates in the dependent claims:

• Claims 12 and 13 (A+1 addressing stages) — highest § 102 risk, squarely met by US 4,903,266 (claim 8/10: at least/exactly one RPG stage beyond the address lines, to guarantee all addresses including all-zero are generated).
• Claims 4 and 5 (seed/complement + write/read cycle sequencing) — high § 102 risk, squarely met by US 4,782,487 (write pseudo-random pattern, then write its complement in the same pseudo-random address sequence, with read-and-check in between).
• Claim 11 (data/PSA stages = M) — moderate risk via US 4,903,266 (data input shift register with n stages for n input lines; MISR with stages matched to output lines).

1. The realistic validity exposure is § 103, not § 102. A combination of US 4,903,266 (LFSR address + data generator, MISR output compression, on-chip) with US 4,433,413 (Fasang's own PRPG + signature register + control logic) and, for the seed/complement step, US 4,782,487, supplies nearly every element of claim 1. The '619 claim-set survives mainly on the slice-replicated modular architecture and the single-pin BIST-select with on-chip known-signature decoder — neither of which is shown in any cited reference.

2. References contributing essentially nothing: US 4,603,683 (digital speech interpolator), US 4,370,746 (address selector), US 4,369,511 / 4,835,774 / 4,876,685 (external ATE testers). These are cited for completeness of the field and cannot anticipate the on-chip integrated-self-testing-memory limitations of claim 1.

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E. Discrepancies flagged (not silently corrected)

• Abadir & Reghbati pagination: the '619 specification cites "pp. 175-98"; the PTO reference list for the same article gives "pp. 118-139." These cannot both be right for the same Sep. 1983 Computing Surveys Vol. 15, No. 3 article. Reported as each record prints.
• Assignee of US 4,433,413: the PTO/Unified citation record lists Siemens Corp., while the patent's inventor is Patrick P. Fasang (the same '619 co-inventor). I could not independently confirm the assignee in the retrieved snippets — treat as moderate confidence.
• One-day date variances persist across sources for several references (e.g., US 4,190,113 → '770: 1978-10-23 vs 10-24; US 4,370,746: 1980-12-23 vs 12-24; US 4,782,487: 1987-05-14 vs 05-15; US 4,903,266: 1988-04-28 vs 04-29). I have used the PTO-record date first and noted the variant.
• '619's own dates: confirmed again that Unified Patents lists priority/application 1990-02-14 and grant 1992-08-10, versus Google Patents' 1990-02-15 / 1992-08-11 — consistent with the discrepancy already flagged in the earlier sections.
• Claim 1 / claim 9 typography defects ("said data PRPG comprising:" standing in for said PSA PRPG; "having and clocked by") are reproduced in the published text and are not corrected here, per your literal-identifier rule. They matter for § 112, not § 102.

I'll ground this analysis by checking the prior-art record for this patent and the cited non-patent literature.

Let me check the examiner-cited references of record and two supplemental references that surfaced.

Obviousness Analysis — U.S. Pat. No. 5,138,619 (Fasang & Bridgewater) under 35 U.S.C. § 103

Builds on the earlier bibliographic/claim/technical sections; those are not repeated. Source of record: the authoritative Google Patents text supplied, https://patents.google.com/patent/[US5138619](/patent/US5138619)/en.

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0. Preliminary flags and scope

⭐ Contradiction flagged (dates). The system header for this session states today is 2026-09-21 (and the Google Patents fetch is stamped 2026-09-21T16:00:07.879Z), but this task specifies Current Date: April 26, 2026, and the previously generated litigation section uses April 26, 2026. I use April 26, 2026 as the task's controlling date and note the discrepancy rather than resolving it. Nothing in the analysis turns on it.

⭐ Contradiction flagged (prior-art record). The task says "use the results from the Prior Art section of this page." The page as supplied contains no examiner "References Cited" table. What it actually contains is:

• a machine-generated "Prior art keywords" field (prpg, data, slices, address, memory) — a Google Patents text-extraction artifact, not a reference;
• four references named in the Background of the Invention: US 4,433,413 (Fasang), Abadir & Reghbati (1983), Scholz et al. (1989), Nadeau-Dostie et al. (CICC 1989); and
• a "Cited By (162)" list, which is forward citation only.

Every document in the "Cited By (162)" list postdates the 1990-02-15 filing (the earliest, US 5,278,839, has priority 1990-04-18). None of the 162 is prior art to '619 under pre-AIA § 102(a)/(b)/(e). I therefore do not rely on them for § 103. The earlier litigation section correctly identified these forward citations as a recurring source of false-positive "litigation" hits; the same caution applies to false-positive "prior art" hits.

Governing law. Effective filing 1990-02-15 → pre-AIA § 103(a). The Graham v. John Deere factors and the KSR Int'l v. Teleflex rationales (as codified in MPEP 2143) control.

PHOSITA (proposed). A design/test engineer with a B.S. in EE (or equivalent) and roughly 3–5 years of ASIC design-for-test experience, familiar with: LFSR/PRPG construction and primitive-polynomial tap tables; single- and multiple-input signature registers (SISR/MISR); macrocell ("standard cell") libraries and silicon compilers; and standard RAM functional-test algorithms.

Supplemental prior art I located independently (provenance flagged). Because the page's own record is thin, I confirmed two additional pre-1990 references by search and use them as secondary art. Both are clearly § 102(b) art and both are ones a challenger would actually run:

• U.S. Pat. No. 4,340,857, "Device for testing digital circuits using built-in logic block observers (BILBO's)" — issued 1982-07-20, priority 1980-04-11. https://patents.google.com/patent/[US4340857](/patent/US4340857) ; https://insight.rpxcorp.com/patent/[US4340857A](/patent/US4340857A)
• U.S. Pat. No. 4,969,148 / EP 0 385 591 A2, Nadeau-Dostie, Silburt & Agarwal, "Serial testing technique for embedded memories" — US filed 1989-03-07 (→ pre-AIA § 102(e) art), EP priority CA 592307 of 1989-02-28. https://SumoBrain.com/patents/us/Serial-testing-technique-embedded-memories/4969148.html ; http://data.epo.org/publication-server/rest/v1.2/patents/EP0385591NWA2/document.html

I also confirmed the content of Abadir & Reghbati (ACM Comput. Surv. 15(3):175-198, Sept. 1983; https://dl.acm.org/doi/pdf/10.1145/[356914](/patent/356914).[356916](/patent/356916)) and of the Nadeau-Dostie CICC paper (DOI 10.1109/CICC.1989.56808; https://ieeexplore.ieee.org/document/[5726275](/patent/5726275)/references). I could not independently retrieve the Scholz et al. text; I rely only on the characterization given in '619's own Background.

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1. Art chart (with statutory basis)

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2. Independent claim 1 — the primary combination

Combination A (primary): BILBO '857 in view of Fasang '413, further in view of Abadir & Reghbati and Nadeau-Dostie.

Construing claim 1: the printed text introduces the PSA element with "…said data PRPG comprising: a plurality of substantially identical, successively arranged PSA PRPG slices…" (an antecedent/typography defect noted in the earlier summary). Read literally-but-sensibly, that element is the PSA PRPG. Note also that the specification itself concedes the PSA "differs only slightly from the data PRPG" — i.e., PRPG and MISR are, in the patentee's own words, the same class of circuit.

Only two gaps remain after BILBO '857 + Fasang '413: (i) applying the scheme to a memory (RAM) rather than random logic, and (ii) the slice-replication style of construction. Gap (i) is closed by Fasang '413 (which already teaches on-chip BIST of a system containing RAM) and by Nadeau-Dostie/Scholz. Gap (ii) is closed by the patentee's own admissions: every slice is assembled from pre-existing National Semiconductor macrocells (C063, C056/X056, X930, C053/X053, C003/X003, X036, C036, C057, X970, C017, C001, C002, C008), and the specification states the slice technique "can readily be implemented either manually or on a general purpose computer running a silicon compilier."

Why the PHOSITA would have combined these (MPEP 2143 rationales):

1. Combining known elements by known methods, predictable result (2143(A)). Each element (LFSR PRPG, MISR/PSA, comparator against a stored signature, clocked control logic) was known; their assembly into a self-testing block yields only the expected aggregate function.
2. Simple substitution of one known element for another (2143(B)). Substituting Fasang's signature register with BILBO's parallel-input "second BILBO"/MISR, and Fasang's PRPG with an LFSR of the RAM's word width, is a substitution of equivalents. The patentee concedes the point by stating the PSA "differs only slightly from the data PRPG."
3. Applying a known technique to a known device ready for improvement (2143(C)/(D)). BILBO is logic-block BIST; Fasang already proved the technique transfers to memory-bearing systems; the ASIC embedded-RAM macrocell of the late 1980s was precisely "a known device ready for improvement," and Scholz and Nadeau-Dostie supply the express ASIC/embedded-RAM motivation.
4. Design incentives and market forces (KSR). The patent itself recites the operative pressures as advantages: stand-alone operation with no external test equipment, minimized added pins, and modularity/extensibility for any N-word × M-bit RAM. Where the inventor's stated benefits are pin-count, area, and auto-generation, those benefits are the incentive to combine, not evidence of non-obviousness. Nadeau-Dostie independently states the same three drivers (minimal pins, shared/minimal interconnect, circuit reuse in mission mode).
5. Obvious to try / finite predictable solutions (KSR). Given a need for an on-chip address and data stimulus and an on-chip response compressor, the artisan's menu was short and well catalogued: counter vs. LFSR for addressing; SISR vs. MISR for compression. Choosing the LFSR/MISR pairing is a selection among a finite number of identified, predictable solutions.

Combination A is the strongest § 103 attack on claim 1 because BILBO '857 alone supplies the claim's novelty-bearing core (PRPG → PSA → decoder-with-predetermined-correct-signature → pass/fail flag → clocked control), and it is § 102(b) art that cannot be antedated.

Alternative combinations (all viable):

• Combination B: BILBO '857 + Nadeau-Dostie (CICC '89 / '148) + Abadir & Reghbati — drops Fasang; Nadeau-Dostie supplies the embedded-RAM BIST context and the on-chip mission/test multiplexing; Abadir supplies the pattern content.
• Combination C: Fasang '413 + Scholz + BILBO '857 — uses the patent's own Background references for the ASIC-BIST motivation, with BILBO supplying the PSA/decoder subcombination.
• Combination D (for the slice internals): any of A–C + the assignee's own published macrocell library (ASIC Design Manual No. 400010, Rev. 1, 1987), which the specification cites as the source of every building block.

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3. Dependent claims 2–13

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4. Independent method claims 14–15

Claims 14–15 are directed to a method of designing the BIST circuit: replicate a slice per bus width, serially interconnect to form each PRPG, derive the feedback signal from selected stage outputs, and provide a known-correct signature for comparison.

This is the weakest set of claims from the patentee's standpoint, for three reasons:

1. Nadeau-Dostie CICC '89 expressly teaches automatic generation. The abstract states: "Automatically generated BIST circuits, which embed an algorithm suited for the application with the RAM, have been developed," and the paper describes a circuit hierarchy deliberately arranged so blocks can be shared/reused, with "simple guidelines" for assemblage. That is the design methodology of claim 14 in substance.
2. The specification concedes routineness: "The slice technique can readily be implemented … on a general purpose computer running a silicon compilier."
3. The method steps are themselves the standard LFSR design procedure. "Take outputs of stage(s) and feed them back to stage 1 in accordance with a tap table" is precisely the classical primitive-polynomial LFSR synthesis, and BILBO '857 confirms that "[t]hese combinations of outputs are known in the electronic field and are dependent on the number of D-type flip-flops" (per the related EP 0 190 494 B1 disclosure of the BILBO). Claim 15's counts (A+1, M, M) are the same arithmetic recited in claims 11–13.

Under MPEP 2144.04/2144.01 and KSR, where the resulting apparatus is obvious and the recited design steps are conventional design-automation steps applied to known building blocks, the method claims fall with the apparatus.

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5. Where the record does not support obviousness (honest limits)

• No reference in the supplied record expressly discloses complementing the LFSR seed mid-test via a control bit (PCB) so that the second fill writes the complement sequence. Abadir & Reghbati supplies the reason (both-polarity storage), and the implementation is a single EXOR gated with a mode bit, but a challenger must bridge that with the "predictable implementation of a known testing requirement" rationale. This is the best non-obviousness argument for claims 4–5, and it is still weak.
• No reference in the record addresses LFSR address-generation coverage — i.e., the A+1 sizing of claims 12–13. Again weak, since it is a consequence of a property inherent in the chosen generator.
• I have not independently verified the content of Scholz et al. (1989); only '619's Background describes it. Do not treat my characterization of Scholz as record-verified.
• I found no secondary considerations of record — no unexpected results, no long-felt-but-unsolved need, no licensing, no industry praise. The 162 forward citations show the patent became a landmark reference in BIST; under Graham that is not a secondary consideration, and the patentee's own touted advantages (stand-alone, minimal pins, modular) are the design incentives that supply motivation to combine, not evidence of non-obviousness. The EveryPatent text of US 6,000,048 (post-dating, cited only as context, http://www.everypatent.com/comp/pat6000048.html) characterizes the '619 approach as PRPG-based and "relatively rigid" — useful color on how the field viewed it, but not prior art.

Antedating note with practical bite: the 1989 references (Scholz, Nadeau-Dostie) are § 102(a) art within one year of the 1990-02-15 filing and could be attacked by a 37 CFR 1.131 swear-behind. Fasang '413 (1984), BILBO '857 (1982), and Abadir & Reghbati (1983) are § 102(b) art and cannot be sworn behind. A challenger should therefore lead with Combination A/B (BILBO + Fasang + Abadir) to survive a swear-behind.

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6. Bottom line

• Claim 1: likely obvious. Combination A (US 4,340,857 + US 4,433,413 + Abadir & Reghbati + Nadeau-Dostie), or Combinations B/C, supplies every element with articulated KSR/MPEP-2143 motivations (knowledge substitution, known-device-ready-for-improvement, design incentives of pin count/area/auto-generation, and a finite predictable menu of LFSR/MISR choices).
• Claims 2–3, 6–11: likely obvious (standard counter design; macrocell-library multiplexed flip-flops; directly taught mission/test multiplexing).
• Claims 4–5, 12–13: colorable but weak — the only limitations for which no reference on the page is squarely on point; each is nonetheless an obvious implementation of a known requirement (both-polarity storage; the 2ⁿ−1 maximal-length property).
• Claims 14–15 (design method): likely obvious, given Nadeau-Dostie's express teaching of automatically generated RAM BIST circuits plus the patent's own admission that the slice technique is a silicon-compiler task.
• This analysis addresses § 103 only. I express no opinion on § 102, § 112, or inequitable conduct, and — consistent with the earlier litigation section — the patent has been expired since 2010-02-15, so any § 103 holding would be retrospective (e.g., prior-art characterization) rather than affecting a live infringement claim.