Invalidity dossier
US 12154652
Dynamic random access memory applied to an embedded display port
Current assignee: Wecrevention Inc
Added 5/12/2026, 11:38:35 PM
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Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Here's a concise summary of US patent 12154652:
US Patent 12154652: Dynamic random access memory applied to an embedded display port
- Title: Dynamic random access memory applied to an embedded display port
- Current Assignee: Wecrevention Inc
- Inventors: Der-Min Yuan, Yen-An Chang, Wei-Ming Huang
- Filing Date: 2023-12-15
- Issue Date: 2024-11-26
- Abstract: A dynamic random access memory applied to an embedded display port includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V. The input/output unit is electrically connected to the memory core unit and the peripheral circuit unit for operating in a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.
Independent Claims Overview:
- Claim 1: This claim describes a Dynamic Random Access Memory (DRAM) that includes a DRAM core cell operating at a first voltage lower than 1.1V and an input/output circuit connected to the core cell, operating at a third voltage also lower than 1.1V. Both the core cell and the input/output circuit are on a single chip, the input/output circuit is external to the core cell, and the first voltage is different from the third voltage.
- Claim 2: This claim is similar to Claim 1, describing a DRAM with a core cell operating at a first voltage lower than 1.1V and an input/output circuit operating at a third voltage lower than 1.1V. The key distinction is that the first voltage (for the core cell) is greater than the third voltage (for the input/output circuit). Both are formed on a single chip, and the input/output circuit is external to the core cell.
- Claim 3: This claim describes a DRAM comprising a DRAM core cell and an input/output circuit electrically connected to it. The input/output circuit operates at a third voltage lower than 1.1V. A key aspect is that the first voltage (for the core cell) is greater than the third voltage (for the input/output circuit), and the entire DRAM is designed for use in an embedded display port (eDP).
Litigation Information:
A search of CAFC 2026 dockets for patent number 12154652 did not yield any direct results as of April 26, 2026. However, the Google Patents page for US12154652 indicates that the patent family has litigation, with US cases filed in the Texas Eastern District Court (e.g., 2:25-cv-00951, 2:25-cv-01040, 2:25-cv-01008) and the Texas Western District Court (7:25-cv-00458), and a PTAB case IPR2026-00243 filed (pending). No CAFC cases were explicitly listed in the search results for this specific patent number.
Generated 5/29/2026, 12:48:32 AM