US 12154652

Here's a concise summary of US patent 12154652:

US Patent 12154652: Dynamic random access memory applied to an embedded display port

• Title: Dynamic random access memory applied to an embedded display port
• Current Assignee: Wecrevention Inc
• Inventors: Der-Min Yuan, Yen-An Chang, Wei-Ming Huang
• Filing Date: 2023-12-15
• Issue Date: 2024-11-26
• Abstract: A dynamic random access memory applied to an embedded display port includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V. The input/output unit is electrically connected to the memory core unit and the peripheral circuit unit for operating in a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.

Independent Claims Overview:

• Claim 1: This claim describes a Dynamic Random Access Memory (DRAM) that includes a DRAM core cell operating at a first voltage lower than 1.1V and an input/output circuit connected to the core cell, operating at a third voltage also lower than 1.1V. Both the core cell and the input/output circuit are on a single chip, the input/output circuit is external to the core cell, and the first voltage is different from the third voltage.
• Claim 2: This claim is similar to Claim 1, describing a DRAM with a core cell operating at a first voltage lower than 1.1V and an input/output circuit operating at a third voltage lower than 1.1V. The key distinction is that the first voltage (for the core cell) is greater than the third voltage (for the input/output circuit). Both are formed on a single chip, and the input/output circuit is external to the core cell.
• Claim 3: This claim describes a DRAM comprising a DRAM core cell and an input/output circuit electrically connected to it. The input/output circuit operates at a third voltage lower than 1.1V. A key aspect is that the first voltage (for the core cell) is greater than the third voltage (for the input/output circuit), and the entire DRAM is designed for use in an embedded display port (eDP).

Litigation Information:

A search of CAFC 2026 dockets for patent number 12154652 did not yield any direct results as of April 26, 2026. However, the Google Patents page for US12154652 indicates that the patent family has litigation, with US cases filed in the Texas Eastern District Court (e.g., 2:25-cv-00951, 2:25-cv-01040, 2:25-cv-01008) and the Texas Western District Court (7:25-cv-00458), and a PTAB case IPR2026-00243 filed (pending). No CAFC cases were explicitly listed in the search results for this specific patent number.

As of April 26, 2026, the following litigation involving US patent 12154652 is known:

District Court Cases:

• Jurisdiction: Texas Eastern District Court

  • Case Number: 2:25-cv-00951
  • Filing Date: Not explicitly provided, but the Unified Patents portal indicates "US case filed in Texas Eastern District Court" for this case, implying a filing sometime in 2025.
  • Status: Active

• Jurisdiction: Texas Western District Court

  • Case Number: 7:25-cv-00458
  • Filing Date: Not explicitly provided, but the Unified Patents portal indicates "US case filed in Texas Western District Court" for this case, implying a filing sometime in 2025.
  • Status: Active

• Jurisdiction: Texas Eastern District Court

  • Case Number: 2:25-cv-01040
  • Filing Date: Not explicitly provided, but the Unified Patents portal indicates "US case filed in Texas Eastern District Court" for this case, implying a filing sometime in 2025.
  • Status: Active

• Jurisdiction: Texas Eastern District Court

  • Case Number: 2:25-cv-01008
  • Filing Date: Not explicitly provided, but the Unified Patents portal indicates "US case filed in Texas Eastern District Court" for this case, implying a filing sometime in 2025.
  • Status: Active

Patent Trial and Appeal Board (PTAB) Cases:

• Case Type: IPR (Inter Partes Review)
  • Case Number: IPR2026-00243
  • Filing Date: Not explicitly provided.
  • Status: Pending

The Unified Patents portal indicates that there has been a "First worldwide family litigation filed" related to this patent family, providing a link to Darts-ip for more details on global patent litigation. However, the provided information does not explicitly name the plaintiff(s) and defendant(s) for the district court cases, nor the petitioner(s) and patent owner(s) for the PTAB case. The current assignee of the patent is Wecrevention Inc.

Proceedings overview

There is one AIA trial proceeding on file for US patent 12154652, which is currently pending institution. This means the patent claims have not yet been challenged in a final written decision, and the patent's defensive posture is untested by PTAB review.

IPR2026-00243 — [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.) v. Wecrevention Inc.

• Type: Inter Partes Review
• Filed: 2026-02-13
• Status: Pending. The petition has been filed and is awaiting a decision on institution from the PTAB.
• Judge panel: Not yet publicly available as the institution decision is pending.
• Petition grounds: The petition filed by Apple Inc. challenges claims 1-6 of US12154652. The grounds include anticipation under 35 U.S.C. § 102 and obviousness under 35 U.S.C. § 103, citing various prior art references including US20050133852A1 and US20100290300A1.
• Institution decision: Not yet issued. The statutory deadline for the institution decision is 6 months from the filing date, which would be around August 13, 2026.
• Final Written Decision: Not applicable; the proceeding is pending institution.
• Settlement / termination: Not applicable at this stage.
• Appeal: Not applicable at this stage.
• Defensive value: This proceeding is in its early stages. If the IPR is instituted, the patent owner will need to defend the challenged claims. Until an institution decision or a Final Written Decision is rendered, the claims of US12154652 remain active and have not been modified by PTAB review.

Strategic summary

All six claims (claims 1-6) of US12154652 are currently being challenged in IPR2026-00243, but no claims have yet been canceled or sustained by a Final Written Decision. As the IPR is still in the pre-institution phase, all claims remain active and untested by PTAB review. There is no estoppel landscape established yet, as the proceeding has not reached an institution decision or Final Written Decision. Apple Inc. is the petitioner in the sole pending IPR.

Recommended next steps

• The institution decision for IPR2026-00243 is expected around August 13, 2026. Monitor the PTAB E2E system for updates on this proceeding, as the institution decision will be a critical milestone determining if the challenged claims will proceed to trial.
• If you are a defendant facing assertion of this patent, understanding the specific arguments and prior art presented in Apple Inc.'s petition for IPR2026-00243 (available on the PTAB E2E system) would be crucial to assess the strength of the challenge.

Inventors

• Der-Min Yuan (Employer: Etron Technology Inc.)
• Yen-An Chang (Employer: Etron Technology Inc.)
• Wei-Ming Huang (Employer: Etron Technology Inc.)

Original assignee

The original assignee listed on the patent is Etron Technology Inc. Etron Technology Inc. is a Taiwanese fabless IC design company that designs and develops integrated circuits, primarily focusing on memory products such as DRAM, USB 3.0, and Flash. As of the current date, Etron Technology Inc. is an operating company.

Assignment timeline

• 2023-05-18 (executed) / recorded 2025-09-08 — Reel 072191/0362
  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: ETRON TECHNOLOGY, INC.
  • Assignee: VALUECREATION TECHNOLOGY, INC.
  • Correspondent: ROBERT J. WONG, WONG CABELLO LUTSCH PATTERSON & GRAF, L.L.P., 20333 SH 249, SUITE 600, HOUSTON, TX 77070.
  • Context: Transfer of rights to the invention from the original developer to a new entity, effective prior to this patent's filing.
• 2025-05-01 (executed) / recorded 2025-09-11 — Reel 072228/0449
  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: VALUECREATION TECHNOLOGY, INC.
  • Assignee: WECREVENTION, INC.
  • Correspondent: BRIAN KOWERT, KOWERT, HOOD, MUNYON, RANKIN & GOETZ, P.C., P.O. BOX 398, AUSTIN, TX 78767-0398.
  • Context: Transfer of patent rights between entities, ultimately to the current assignee.

Timeline diagram

timeline
    title Ownership of US 12154652
    2023-05-18 : Rights to invention assigned to VALUECREATION TECHNOLOGY
    2023-12-15 : Patent application filed
    2024-11-26 : Patent issued
    2025-05-01 : Assigned to WECREVENTION INC

NPE / troll-pattern signals

1. Shell-entity transfer — present. The patent was transferred from Etron Technology Inc., an operating company, to VALUECREATION TECHNOLOGY, INC. (Reel 072191/0362), and subsequently to WECREVENTION, INC. (Reel 072228/0449). Both "VALUECREATION TECHNOLOGY, INC." and "WECREVENTION, INC." have names suggestive of non-operating, licensing, or holding companies.
2. Known asserter in the chain — present. WECREVENTION, INC. is the current assignee and the patent is currently involved in multiple US District Court litigations (e.g., 2:25-cv-00951, 7:25-cv-00458) and a PTAB IPR (IPR2026-00243). This indicates WECREVENTION, INC. is an active asserter.
3. Repeat correspondent across the chain — not present. The correspondent for the first assignment (Reel 072191/0362) was Robert J. Wong of Wong Cabello Lutsch Patterson & Graf, L.L.P., while the correspondent for the second assignment (Reel 072228/0449) was Brian Kowert of Kowert, Hood, Munyon, Rankin & Goetz, P.C. These are different individuals and firms.
4. Cascading transfers — not present. The two recorded assignments are separated by an execution date difference of approximately two years (2023-05-18 to 2025-05-01), which does not constitute cascading transfers.
5. Pre-litigation transfer — present. The assignment to WECREVENTION, INC. was executed on 2025-05-01 (Reel 072228/0449). Multiple infringement suits in US District Courts began to be filed in 2025, closely following the execution date of this transfer.
6. Bankruptcy fire-sale — not present. There is no indication that Etron Technology Inc. underwent bankruptcy proceedings.
7. Privateering — unclear. While the transfer is from an operating company (Etron) to apparent shell entities, there is no direct evidence (e.g., SEC filings or public reports) confirming a privateering arrangement where Etron is covertly benefiting from the assertions.
8. Defensive aggregator (anti-NPE) — not present. The chain terminates with WECREVENTION, INC., which is an active asserter, not a defensive aggregator.

Verdict

NPE — high confidence
Justification: The patent demonstrates strong NPE patterns, including transfers from an operating company (Etron Technology Inc.) to apparent shell entities (VALUECREATION TECHNOLOGY, INC. and WECREVENTION, INC.). The current assignee, WECREVENTION, INC., is actively asserting the patent in multiple district court litigations, and the final assignment to WECREVENTION, INC. (executed 2025-05-01, Reel 072228/0449) closely precedes these assertions.

USPTO Assignment Center Search: US12154652

To identify the most relevant prior art for US patent 12154652, I will examine the patent citations listed on the Google Patents page for US12154652. For each cited patent, I will provide its full citation, publication/filing date, a brief description, and discuss which claim(s) of US12154652 it potentially anticipates under 35 U.S.C. § 102.

The USPTO provides a Patent Public Search tool to search its database. Prior art consists of publicly available information before the effective filing date of a patent application, including U.S. patents and published patent applications, foreign patents, and scientific literature. The goal of a prior art search is to determine if an invention is novel and non-obvious.

The priority date for US12154652 is July 17, 2012. Therefore, any prior art must have a publication or priority date before this date.

Here are the patent citations listed for US12154652 and an analysis of their potential relevance:

Patent Citations for US12154652:

• US20050133852A1

  • Full Citation: US20050133852A1 - High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
  • Publication Date: 2005-06-23 (Priority date: 1996-05-24)
  • Brief Description: This patent application describes high-performance embedded semiconductor memory devices, specifically focusing on DRAMs with multiple dimension first-level bit-lines to enhance performance. The abstract mentions the memory cell array being formed in a core region and having at least two dimensions of first-level bit-lines.
  • Potential Anticipation: This reference predates US12154652 and discusses embedded DRAM, which is the broad field of the invention. While it focuses on bit-line architecture for performance, it lays groundwork for the concept of embedded memory. It doesn't specifically address the multiple voltage domains or the application to an embedded display port with specific voltage levels lower than 1.1V for peripheral and I/O units, which are central to claims 1, 2, and 3 of US12154652. However, the concept of an "embedded semiconductor memory device" could be considered relevant to the "DRAM comprised in the DRAM" language in claims 1, 2, and 3.

• US20090122620A1

  • Full Citation: US20090122620A1 - Systems and Methods for Low Power, High Yield Memory
  • Publication Date: 2009-05-14 (Priority date: 2007-11-08)
  • Brief Description: This patent application describes systems and methods for low power, high yield memory. It particularly focuses on reducing power consumption by controlling supply voltages to different memory components based on performance requirements. For example, it discusses reducing voltage during standby or low-performance modes.
  • Potential Anticipation: This patent is highly relevant as it explicitly addresses low power memory, a primary objective of US12154652. The disclosure of dynamically adjusting supply voltages to memory components for power reduction could potentially anticipate aspects of claims 1, 2, and 3 of US12154652, particularly the concept of operating memory units (core, peripheral, I/O) at different, potentially lower, voltages. While it doesn't specify an "embedded display port" application, the general principle of low-power operation through voltage control is a strong point of overlap. The "third voltage is lower than 1.1V" for the input/output circuit in claims 1, 2, and 3, and the "first voltage is lower than 1.1V" in claims 1, 2, and 4, and "second voltage is lower than 1.1V" in claim 5 are specific voltage limitations that might not be explicitly found in this reference but the underlying motivation for low power through voltage control is present.

• US20100290300A1

  • Full Citation: US20100290300A1 - Semiconductor integrated device
  • Publication Date: 2010-11-18 (Priority date: 2009-05-14)
  • Brief Description: This patent application describes a semiconductor integrated device that includes a plurality of circuit blocks and a power supply control circuit. It discusses providing different voltages to different circuit blocks, including a memory circuit, for power saving.
  • Potential Anticipation: Similar to US20090122620A1, this reference addresses power saving in semiconductor devices by supplying different voltages to different circuit blocks, including memory. This aligns with the fundamental concept of US12154652 to operate different units (memory core, peripheral, I/O) at distinct and lower voltages to reduce power consumption. This could potentially anticipate aspects of claims 1, 2, and 3, particularly the idea of providing different operating voltages to different parts of the DRAM for power efficiency. The specific voltage thresholds of "lower than 1.1V" for certain units would need to be directly found to be fully anticipatory under 35 U.S.C. § 102.

Other Patent Citations (Less Direct Relevance to Core Claims):

• US5928336A

  • Full Citation: US5928336A - PC card and peripheral device
  • Publication Date: 1999-07-27 (Filing Date: 1996-07-15)
  • Brief Description: This patent describes a PC card and a peripheral device, focusing on interfaces and connections for such devices.
  • Potential Anticipation: This patent is broadly related to peripheral device interfaces but does not appear to directly address the specific low-voltage DRAM architecture or its application in an embedded display port as claimed in US12154652.

• US6097070A

  • Full Citation: US6097070A - MOSFET structure and process for low gate induced drain leakage (GILD)
  • Publication Date: 2000-08-01 (Filing Date: 1999-02-16)
  • Brief Description: This patent is concerned with MOSFET structures and processes for reducing gate-induced drain leakage.
  • Potential Anticipation: This patent relates to semiconductor device manufacturing and leakage current reduction, which are fundamental to power consumption. However, it does not describe the architectural features of the DRAM or its application as claimed in US12154652. It might be relevant as background technology but not directly anticipatory of the claims.

• US6363014B1

  • Full Citation: US6363014B1 - Low column leakage NOR flash array-single cell implementation
  • Publication Date: 2002-03-26 (Filing Date: 2000-10-23)
  • Brief Description: This patent describes a NOR flash array designed for low column leakage.
  • Potential Anticipation: This patent focuses on NOR flash memory, which is a different type of memory than DRAM. While it addresses low leakage (related to power), its specific implementation and memory type differ from the claimed invention.

• US20030031043A1

  • Full Citation: US20030031043A1 - Integrated dynamic memory, and method for operating the integrated dynamic memory
  • Publication Date: 2003-02-13 (Filing Date: 2001-08-13)
  • Brief Description: This patent application describes an integrated dynamic memory and a method for operating it.
  • Potential Anticipation: This is a general reference to integrated dynamic memory. Without further details on voltage operation or specific architectural divisions for power saving, it is unlikely to directly anticipate the specific claims of US12154652 that define voltage levels for different units.

• US6551896B2

  • Full Citation: US6551896B2 - Capacitor for analog circuit, and manufacturing method thereof
  • Publication Date: 2003-04-22 (Filing Date: 1999-12-17)
  • Brief Description: This patent describes a capacitor for analog circuits and its manufacturing method.
  • Potential Anticipation: This patent is related to basic circuit components and manufacturing, not directly to the DRAM architecture or power management strategies of US12154652.

• US6570787B1

  • Full Citation: US6570787B1 - Programming with floating source for low power, low leakage and high density flash memory devices
  • Publication Date: 2003-05-27 (Filing Date: 2002-04-19)
  • Brief Description: This patent describes programming techniques for low power, low leakage, and high-density flash memory devices.
  • Potential Anticipation: This patent focuses on flash memory, which is distinct from DRAM, and its programming methods. While it addresses low power and low leakage, the specific memory technology and the claimed architecture of US12154652 are different.

• US20050010746A1

  • Full Citation: US20050010746A1 - Method for dynamically building acpi architecture
  • Publication Date: 2005-01-13 (Filing Date: 2003-07-07)
  • Brief Description: This patent application describes a method for dynamically building ACPI (Advanced Configuration and Power Interface) architecture.
  • Potential Anticipation: This relates to power management at a system level (ACPI) rather than the specific internal architecture and voltage regulation of a DRAM for an embedded display port as claimed in US12154652.

• US20060047985A1

  • Full Citation: US20060047985A1 - Data storage apparatus and control method thereof
  • Publication Date: 2006-03-02 (Filing Date: 2004-08-31)
  • Brief Description: This patent application describes a data storage apparatus and its control method.
  • Potential Anticipation: This is a broad title that likely covers various data storage methods. Without further details, it's difficult to assess direct anticipation of US12154652's specific claims regarding low-voltage DRAM for eDP.

• US20060120138A1

  • Full Citation: US20060120138A1 - Semiconductor memory with volatile and non-volatile memory cells
  • Publication Date: 2006-06-08 (Filing Date: 2004-10-29)
  • Brief Description: This patent application describes a semiconductor memory device that includes both volatile and non-volatile memory cells.
  • Potential Anticipation: While it deals with semiconductor memory, the combination of volatile and non-volatile cells is not a central feature of US12154652's claims, which focus on low-voltage operation of a DRAM.

• US20060140004A1

  • Full Citation: US20060140004A1 - Semiconductor device
  • Publication Date: 2006-06-29 (Filing Date: 2000-03-09)
  • Brief Description: This patent application describes a general semiconductor device.
  • Potential Anticipation: This is a very broad reference and unlikely to anticipate the specific architectural and voltage-related claims of US12154652 without more specific details.

• US20060192282A1

  • Full Citation: US20060192282A1 - Semiconductor device
  • Publication Date: 2006-08-31 (Filing Date: 2005-02-25)
  • Brief Description: This patent application describes a general semiconductor device.
  • Potential Anticipation: Similar to the above, this broad reference is unlikely to directly anticipate the specific claims of US12154652.

• US20060259679A1

  • Full Citation: US20060259679A1 - Method and system for memory access
  • Publication Date: 2006-11-16 (Filing Date: 2005-05-11)
  • Brief Description: This patent application describes a method and system for memory access.
  • Potential Anticipation: This is a general reference to memory access. It's unlikely to anticipate the specific low-voltage DRAM architecture for eDP as claimed in US12154652.

• US7295036B1

  • Full Citation: US7295036B1 - Method and system for reducing static leakage current in programmable logic devices
  • Publication Date: 2007-11-13 (Filing Date: 2005-11-30)
  • Brief Description: This patent describes a method and system for reducing static leakage current in programmable logic devices.
  • Potential Anticipation: While addressing leakage current (related to power), this patent focuses on programmable logic devices, which are different from DRAM. Its specific techniques might not directly apply to or anticipate the architectural claims of US12154652.

• US20080117700A1

  • Full Citation: US20080117700A1 - Dynamic semiconductor storage device and method for operating same
  • Publication Date: 2008-05-22 (Filing Date: 2006-11-20)
  • Brief Description: This patent application describes a dynamic semiconductor storage device and a method for operating it, focusing on improving refresh operations and reducing power consumption during such operations.
  • Potential Anticipation: This reference addresses power consumption in dynamic semiconductor storage devices (like DRAM), particularly concerning refresh. While relevant to power, it might not explicitly disclose the distinct low-voltage operation for memory core, peripheral, and I/O units, and the application to an embedded display port, as precisely defined in US12154652's claims.

• US20090067217A1

  • Full Citation: US20090067217A1 - Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same
  • Publication Date: 2009-03-12 (Filing Date: 2007-02-27)
  • Brief Description: This patent application describes methods for supplying power supply voltages in semiconductor memory devices. It focuses on generating and supplying appropriate internal voltages based on operating modes to reduce power consumption.
  • Potential Anticipation: This patent is relevant because it deals with supplying power supply voltages in semiconductor memory devices to reduce power consumption. This general concept of differentiated voltage supply for power saving could potentially anticipate the principles behind claims 1, 2, and 3 of US12154652. However, the specific voltage levels ("lower than 1.1V") and the application to an embedded display port would need to be present for direct anticipation.

• US20100005439A1

  • Full Citation: US20100005439A1 - Designing method of semiconductor integrated circuit
  • Publication Date: 2010-01-07 (Filing Date: 2007-03-27)
  • Brief Description: This patent application describes a designing method for a semiconductor integrated circuit.
  • Potential Anticipation: This is a broad reference to design methods and unlikely to anticipate the specific architectural and voltage-related claims of US12154652.

• US20100008172A1

  • Full Citation: US20100008172A1 - Dynamic type semiconductor memory device and operation method of the same
  • Publication Date: 2010-01-14 (Filing Date: 2008-07-14)
  • Brief Description: This patent application describes a dynamic type semiconductor memory device and its operation method.
  • Potential Anticipation: Similar to other general memory references, it's unlikely to anticipate the specific low-voltage DRAM architecture for eDP as claimed in US12154652 without more detailed disclosure.

• US20100074043A1

  • Full Citation: US20100074043A1 - Semiconductor device
  • Publication Date: 2010-03-25 (Filing Date: 2008-09-19)
  • Brief Description: This patent application describes a general semiconductor device.
  • Potential Anticipation: A broad reference, unlikely to anticipate the specific claims of US12154652.

• US7692979B2

  • Full Citation: US7692979B2 - Memory readout circuit and phase-change memory device
  • Publication Date: 2010-04-06 (Filing Date: 2006-11-21)
  • Brief Description: This patent describes a memory readout circuit and a phase-change memory device.
  • Potential Anticipation: This patent focuses on phase-change memory, a non-volatile memory technology, and its readout circuits, which is distinct from the DRAM technology of US12154652.

• US20100095137A1

  • Full Citation: US20100095137A1 - Dynamic Frequency And Voltage Scaling For A Computer Processor
  • Publication Date: 2010-04-15 (Filing Date: 2008-10-13)
  • Brief Description: This patent application describes dynamic frequency and voltage scaling for a computer processor.
  • Potential Anticipation: This reference is related to power management at the processor level using dynamic voltage and frequency scaling. While it involves voltage control for power saving, it's applied to a processor, not specifically the internal architecture and distinct voltage domains of a DRAM as claimed in US12154652.

• US7894294B2

  • Full Citation: US7894294B2 - Operational mode control in serial-connected memory based on identifier
  • Publication Date: 2011-02-22 (Filing Date: 2008-01-23)
  • Brief Description: This patent describes controlling operational modes in serial-connected memory based on an identifier.
  • Potential Anticipation: This patent focuses on operational modes and identifiers for serial-connected memory, not the specific low-voltage DRAM architecture or its application in an embedded display port as claimed in US12154652.

• US20110069562A1

  • Full Citation: US20110069562A1 - Low consumption voltage regulator for a high voltage charge pump, voltage regulation method, and memory device provided with the voltage regulator
  • Publication Date: 2011-03-24 (Filing Date: 2009-09-18)
  • Brief Description: This patent application describes a low-consumption voltage regulator for a high-voltage charge pump, a voltage regulation method, and a memory device using it.
  • Potential Anticipation: This reference is relevant to voltage regulation and low consumption in memory devices. It could be considered relevant to the "peripheral circuit unit" which often includes voltage generation/regulation, and therefore could be broadly relevant to the power-saving aspects of US12154652, especially claims involving a peripheral circuit unit operating at a low voltage.

• TW201123198A

  • Full Citation: TW201123198A - Memory power supply circuit
  • Publication Date: 2011-07-01 (Filing Date: 2009-12-18)
  • Brief Description: This Taiwanese patent application describes a memory power supply circuit.
  • Potential Anticipation: As a memory power supply circuit, it directly addresses power delivery to memory. Depending on the specifics of its voltage output levels and how it supplies different memory components, it could potentially anticipate the low-voltage operation aspects of US12154652's claims. Without the full text, a precise assessment is difficult.

• CN102187323A

  • Full Citation: CN102187323A - Dynamic utilization of power-down modes in multi-core memory modules
  • Publication Date: 2011-09-14 (Filing Date: 2008-08-13)
  • Brief Description: This Chinese patent application describes dynamic utilization of power-down modes in multi-core memory modules.
  • Potential Anticipation: This reference is relevant to power saving in memory, specifically through power-down modes. While not directly about distinct voltage domains for active operation as in US12154652, the broader goal of reducing power consumption in memory modules is shared.

• US20110252253A1

  • Full Citation: US20110252253A1 - Energy saving circuit of motherboard
  • Publication Date: 2011-10-13 (Filing Date: 2010-04-09)
  • Brief Description: This patent application describes an energy-saving circuit of a motherboard.
  • Potential Anticipation: This relates to system-level energy saving on a motherboard, not the internal architecture and voltage regulation of a DRAM as claimed in US12154652.

• US20110292448A1

  • Full Citation: US20110292448A1 - Program execution control method
  • Publication Date: 2011-12-01 (Filing Date: 2010-05-28)
  • Brief Description: This patent application describes a program execution control method.
  • Potential Anticipation: This reference is to a software-related control method and is unlikely to anticipate the hardware architecture of US12154652.

• US20120182076A1

  • Full Citation: US20120182076A1 - Limiter circuit and voltage controlled oscillator including the same
  • Publication Date: 2012-07-19 (Filing Date: 2011-01-14)
  • Brief Description: This patent application describes a limiter circuit and a voltage-controlled oscillator.
  • Potential Anticipation: This is a basic circuit design reference and is unlikely to anticipate the specific low-voltage DRAM architecture for eDP as claimed in US12154652. Note that its publication date is after the priority date of US12154652 (July 17, 2012) if the provisional applications are considered, but before the June 19, 2013 filing date of the parent application US13/922,242. If the effective priority date of US12154652 is considered to be the provisional application date of July 17, 2012, then this reference would not be prior art under 35 U.S.C. § 102.

• US20130046941A1

  • Full Citation: US20130046941A1 - Write circuit, read circuit, memory buffer and memory module
  • Publication Date: 2013-02-21 (Filing Date: 2011-07-11)
  • Brief Description: This patent application describes write circuits, read circuits, memory buffers, and memory modules.
  • Potential Anticipation: This reference describes memory circuits and modules. Since its publication date is after the priority date of US12154652 (July 17, 2012), it would not be considered prior art for US12154652 under 35 U.S.C. § 102, assuming the priority date relates to the content of the claims.

• US20130132660A1

  • Full Citation: US20130132660A1 - Data read/write system
  • Publication Date: 2013-05-23 (Filing Date: 2011-07-11)
  • Brief Description: This patent application describes a data read/write system.
  • Potential Anticipation: Similar to US20130046941A1, its publication date is after the priority date of US12154652 (July 17, 2012). Thus, it would not be considered prior art for US12154652 under 35 U.S.C. § 102, assuming the priority date relates to the content of the claims.

• US20130135955A1

  • Full Citation: US20130135955A1 - Memory device including a retention voltage resistor
  • Publication Date: 2013-05-30 (Filing Date: 2011-11-29)
  • Brief Description: This patent application describes a memory device including a retention voltage resistor.
  • Potential Anticipation: Its publication date is after the priority date of US12154652 (July 17, 2012). Thus, it would not be considered prior art for US12154652 under 35 U.S.C. § 102, assuming the priority date relates to the content of the claims.

Family Cites Families:

• TWM276302U

  • Full Citation: TWM276302U - DRAM of a 3-transistor cell
  • Publication Date: 2005-09-21 (Priority Date: 2005-04-08)
  • Brief Description: This Taiwanese utility model describes a DRAM with a 3-transistor cell.
  • Potential Anticipation: This reference describes a specific DRAM cell architecture. While it is a type of DRAM, it does not appear to directly disclose the multiple voltage domains for power saving or the application to an embedded display port as claimed in US12154652.

• TWI355590B

  • Full Citation: TWI355590B - Common module for DDRI SDRAM and DDRIII SDRAM
  • Publication Date: 2012-01-01 (Priority Date: 2007-05-15)
  • Brief Description: This Taiwanese patent describes a common module for DDR1 SDRAM and DDR3 SDRAM, allowing for compatibility.
  • Potential Anticipation: This patent focuses on compatibility between different DDR generations of SDRAM. While it mentions DDR I and DDR III specifications, which are also mentioned in US12154652 as compatible modes, it doesn't appear to directly address the low-voltage operation for distinct internal units or the specific application in an embedded display port as the primary inventive features of US12154652's claims.

Most Relevant Prior Art:

Based on the descriptions, the most relevant prior art documents appear to be those that broadly address power reduction in memory by controlling supply voltages to different components:

1. US20090122620A1 (Systems and Methods for Low Power, High Yield Memory): This reference directly addresses low power memory and controlling supply voltages to different memory components. This aligns strongly with the core concept of US12154652, particularly claims 1, 2, and 3, which specify distinct voltage operations for the memory core, peripheral, and I/O units to reduce power consumption.
2. US20100290300A1 (Semiconductor integrated device): This patent also focuses on power saving in semiconductor devices, including memory, by providing different voltages to different circuit blocks. This further supports the idea of varying operating voltages within a memory device for power efficiency, which is central to claims 1, 2, and 3 of US12154652.
3. US20090067217A1 (Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same): This reference is also highly relevant due to its focus on methods for supplying power supply voltages to semiconductor memory devices to reduce power consumption. This directly relates to the voltage control aspects in claims 1, 2, and 3.

These three patents (US20090122620A1, US20100290300A1, and US20090067217A1) lay the foundational concept of power reduction in memory through differential voltage supply, which is a key element of US12154652. While US12154652 adds specific voltage thresholds and the application to an embedded display port, these prior art documents could be used to argue obviousness under 35 U.S.C. § 103, or potentially anticipate if more specific disclosures regarding voltage levels and partitions are found within their full texts. For direct anticipation under 35 U.S.C. § 102, a prior art reference must disclose every element of the claimed invention. Without a detailed analysis of the full text of these references against each claim, it's challenging to definitively state anticipation. However, the core concept of low-voltage operation for different memory sections for power saving is strongly present.

Obviousness Analysis of US12154652 Under 35 U.S.C. § 103

This analysis identifies combinations of prior art references that would render the claims of US patent 12154652 obvious to a person having ordinary skill in the art (PHOSITA). The PHOSITA in this field would be an electrical engineer or memory designer with knowledge of Dynamic Random Access Memory (DRAM) architecture, power management techniques, and display interface standards. The primary motivation for combining these references would be to address the known problem of reducing power consumption in DRAMs, particularly when used as frame buffers for embedded display ports (eDP) with Panel Self Refresh (PSR) functionality, as explicitly outlined in the background of US12154652 itself.

Background and Motivation for a PHOSITA

The background section of US12154652 establishes that embedded display port (eDP) version 1.3, with its Panel Self Refresh (PSR) function, significantly reduces the power consumption of a Graphics Processing Unit (GPU). However, a timing controller supporting the PSR function requires a frame buffer, typically a DRAM, which can increase the timing controller's power consumption. The patent explicitly states that the operation voltages specified by the Joint Electron Device Engineering Council (JEDEC) for standard DDR and low-power DDR specifications (e.g., 1.8V, 2.5V, 3.3V) "can not satisfy requirements... of the embedded display port (eDP) version 1.3." This creates a clear motivation for memory manufacturers to design a frame buffer (DRAM) that significantly reduces the power consumption of the timing controller, necessitating low operation and standby power consumption for the DRAM. Lowering operating voltages is a well-known and conventional approach to reduce power consumption in semiconductor devices.

Combinations of Prior Art References and Obviousness Arguments

The following prior art references, individually or in combination, teach or render obvious the elements of the independent claims of US12154652.

Prior Art References Utilized:

1. US20030031043A1 to Pochmuller ("Integrated dynamic memory, and method for operating the integrated dynamic memory"): This patent teaches an integrated dynamic memory with memory cells and peripheral circuits, featuring a memory-cell voltage generator and a peripheral voltage generator. Crucially, it discloses that in a low-power mode, the memory-cell voltage (equivalent to the DRAM core cell voltage) is reduced to a value below 1V.
2. US20090122620A1 to Qualcomm Incorporated ("Systems and Methods for Low Power, High Yield Memory"): This reference describes a memory device including a memory array (core) and an interface circuit (input/output) that operate at a "reduced voltage relative to a standard operating voltage" for low power.
3. US20090067217A1 to [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) ("Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same"): This patent teaches a semiconductor memory device where a cell array (core) is supplied with a first voltage, and a peripheral circuit is supplied with a second voltage. It explicitly states that "The first voltage is less than the internal voltage" (where internal voltage is the second voltage for the peripheral circuit), demonstrating the use of different voltages for different DRAM units.
4. Iyer, S.S. and Kalter, H.L., "Embedded DRAM technology: opportunities and challenges" (1999): This non-patent literature discusses "Embedded DRAM technology," confirming the concept of integrating DRAM components onto a single chip with other logic.

Obviousness of Independent Claim 1:

Claim 1 describes a DRAM comprising a DRAM core cell operating at a first voltage lower than 1.1V and an input/output circuit operating at a third voltage also lower than 1.1V. Both are on a single chip, the I/O circuit is external to the core cell, and the first voltage is different from the third voltage.

1. DRAM core cell (volatile memory cell) supplied with a first voltage lower than 1.1V: Pochmuller teaches an integrated dynamic memory where, in a low-power mode, the memory-cell voltage (equivalent to the DRAM core cell voltage) is reduced to a value below 1V. The volatile nature of a DRAM cell is inherent and well-known in the prior art.
2. Input/output circuit electrically connected to the DRAM core cell, supplied with a third voltage lower than 1.1V: Qualcomm teaches an "interface circuit" (analogous to an input/output circuit) operating at a "reduced voltage relative to a standard operating voltage" for low power. Given Pochmuller's teaching of a sub-1V core voltage and the explicit motivation in US12154652's background to achieve significant power reduction for eDP applications (which JEDEC standard voltages cannot meet), a PHOSITA would be motivated to reduce the I/O circuit's operating voltage to below 1.1V. The electrical connection between core and I/O is a fundamental aspect of DRAM architecture.
3. DRAM core cell and the input/output circuit formed on a single chip, the input/output circuit is external to the DRAM core cell: Pochmuller discloses an "integrated dynamic memory." Iyer et al. discuss "embedded DRAM technology." These references establish the prior art concept of integrating DRAM components on a single chip. It is a conventional architectural arrangement for an input/output circuit to be physically external to the memory core cell array but integrated on the same semiconductor chip.
4. The first voltage is different from the third voltage: Samsung explicitly teaches supplying a cell array (core) with a first voltage and a peripheral circuit with a second voltage, where these voltages can be different (e.g., first voltage less than internal/second voltage). Pochmuller also supports this by describing separate voltage generators for the memory cell and peripheral circuits. Therefore, using different voltages for the core and I/O circuits would be an obvious design choice for a PHOSITA.

Motivation for Combination: A PHOSITA, seeking to reduce power consumption in a DRAM for an eDP application (as motivated by US12154652's background), would combine the low-voltage core operation of Pochmuller with the low-voltage interface operation of Qualcomm. The desire for optimal power savings would lead the PHOSITA to set both voltages below a conventional threshold like 1.1V, recognizing that standard JEDEC voltages are insufficient for the eDP 1.3 PSR requirements. The integration on a single chip and differential voltages are well-established architectural and power management techniques shown in Iyer et al., Pochmuller, and Samsung.

Obviousness of Independent Claim 2:

Claim 2 is similar to Claim 1 but specifies that the first voltage (for the core cell) is greater than the third voltage (for the input/output circuit).

1. All elements of Claim 1, except for the voltage relationship: As established above, the elements of Claim 1 are obvious.
2. The first voltage is greater than the third voltage: While Samsung teaches a core voltage less than a peripheral voltage, the patent US12154652 itself, in its detailed description (specifically Table III), illustrates an embodiment where the memory core unit (first predetermined voltage) operates at 1.8V±0.1V while the peripheral circuit unit and input/output unit (second and third predetermined voltages) operate at less than 1.1V. The patent explains that this configuration provides "higher charge pump efficiency" for the memory core unit, while still achieving lower access and input/output power consumption. A PHOSITA, aiming for overall power reduction and efficiency in an eDP application, would be motivated to adopt such a differential voltage scheme, recognizing that maintaining a slightly higher core voltage could optimize certain internal operations (like charge pump efficiency) without sacrificing the significant power savings achieved by operating peripheral and I/O units at very low voltages (e.g., <1.1V).

Motivation for Combination: The motivation remains power reduction for eDP applications. The specific voltage relationship (core voltage > I/O voltage) is explicitly disclosed as a viable and beneficial design choice within the patent's own description (Table III) to optimize efficiency, and would be obvious to a PHOSITA implementing low-power DRAMs.

Obviousness of Independent Claim 3:

Claim 3 describes a DRAM with a DRAM core cell and an input/output circuit, where the input/output circuit operates at a third voltage lower than 1.1V, the first voltage (core) is greater than the third voltage, and the DRAM is capable of being applied to an embedded display port (eDP).

1. DRAM core cell (volatile memory cell) and input/output circuit supplied with a third voltage lower than 1.1V: As established for Claim 1, this is rendered obvious by Pochmuller's sub-1V core and Qualcomm's reduced-voltage interface circuits, combined with the motivation for significant power reduction in eDP.
2. The first voltage is greater than the third voltage: As established for Claim 2, this specific voltage relationship, offering benefits like "higher charge pump efficiency" while still achieving overall power reduction, is taught by US12154652's own description (Table III).
3. The DRAM is capable to be applied to an embedded display port (eDP): The background section of US12154652 extensively details the use of DRAM as a frame buffer for a timing controller in a liquid crystal display with an eDP and PSR function. The entire problem statement and motivation for the patent revolve around adapting DRAM for this specific application to achieve power savings. It would therefore be obvious to a PHOSITA to apply known low-power DRAM techniques, including the specified low-voltage operations, to a DRAM intended for an eDP.

Motivation for Combination: The fundamental motivation is to overcome the power consumption challenges of DRAMs when used as frame buffers in eDP 1.3 PSR systems. The PHOSITA would combine the known architectural elements of DRAM, the established need for extremely low power in eDP contexts (from US12154652's background), and the teachings of low/differential voltage operations from Pochmuller, Qualcomm, and Samsung, to arrive at a DRAM capable of meeting the power efficiency demands of an eDP.

Obviousness of Dependent Claim 4:

Claim 4 depends on Claim 3 and states, "wherein the first voltage is lower than 1.1V."

1. First voltage (core) lower than 1.1V: This is directly taught by Pochmuller, which discloses a memory-cell voltage (core voltage) reduced to a value below 1V in a low-power mode for an integrated dynamic memory.

Motivation for Combination: As an alternative to a higher core voltage (as in Claim 3), a PHOSITA would be motivated by the overarching goal of power reduction to implement a core voltage below 1.1V, as taught by Pochmuller, particularly when designing for applications like eDP that demand minimal power consumption.

Obviousness of Dependent Claim 5:

Claim 5 depends on Claim 3 and adds "a peripheral circuit comprised in the DRAM, wherein the peripheral circuit is electrically connected to the DRAM core cell, and the peripheral circuit is supplied with a second voltage to make the peripheral circuit operate at the second voltage, wherein the second voltage is lower than 1.1V."

1. Peripheral circuit in DRAM, electrically connected to core cell: Pochmuller teaches an integrated dynamic memory with "peripheral circuits" and a "peripheral voltage generator." The electrical connection between peripheral circuits and the core cell is standard DRAM architecture.
2. Peripheral circuit supplied with a second voltage lower than 1.1V: Qualcomm teaches "core driver circuit" (analogous to a peripheral circuit) operating at a "reduced voltage relative to a standard operating voltage" for low power. Given the strong motivation from US12154652's background to significantly reduce power consumption for eDP, and the practice of lowering voltages for power savings, a PHOSITA would find it obvious to apply a voltage below 1.1V to the peripheral circuit, similar to the I/O circuit, to achieve the desired power efficiency.

Motivation for Combination: The motivation to reduce power consumption of the DRAM in eDP applications would drive a PHOSITA to apply low-voltage operation to all relevant functional units, including the peripheral circuits, using known techniques as taught by Pochmuller (peripheral circuits and generators) and Qualcomm (reduced voltage for core drivers).

Obviousness of Dependent Claim 6:

Claim 6 depends on Claim 5 and states, "wherein the first voltage is different from the second voltage."

1. First voltage (core) is different from the second voltage (peripheral): Samsung explicitly teaches a semiconductor memory device where the cell array (core) is supplied with a first voltage and the peripheral circuit is supplied with a second voltage, stating that "The first voltage is less than the internal voltage" (which is the second voltage for the peripheral circuit). Pochmuller also supports this with separate voltage generators for memory cells and peripheral circuits, enabling different operating voltages.

Motivation for Combination: A PHOSITA would be motivated to use different voltages for the core and peripheral circuits to optimize power consumption and performance characteristics of each unit, as demonstrated by Samsung and Pochmuller. This allows for tailored voltage scaling for different parts of the DRAM, a common power management strategy.

Conclusion

The claims of US12154652 are rendered obvious by combining the identified prior art references. The background of US12154652 itself establishes the clear motivation for a PHOSITA to reduce DRAM power consumption for eDP applications, recognizing the inadequacy of standard JEDEC voltages. The prior art teaches the fundamental components of DRAM (core, peripheral, I/O), their integration on a single chip, and various techniques for operating them at reduced or differential voltages, including sub-1V for the core. A PHOSITA would have been motivated to combine these known techniques and architectural elements in a DRAM designed for an eDP to achieve the desired low-power operation, with the specific voltage thresholds (e.g., <1.1V) being a matter of routine optimization in pursuit of the stated goal of significantly reduced power consumption.