US 12107587

Here is a concise summary of US Patent 12107587:

US Patent 12107587 Summary

• Title: Field programmable gate array with internal phase-locked loop

• Assignee: HFT Solutions LLC

• Inventor: Nima Badizadegan

• Filing Date: 2022-04-18

• Issue Date: 2024-10-01

• Abstract: The present invention generally relates to a field programmable gate array system, and more specifically, to a field programmable gate array and an external or internal phase controller providing phase matching between a receiver clock and a transmitter clock used in the field programmable gate array. The invention addresses technological challenges in synchronizing receiver and transmitter side clock signals within an FPGA without introducing unnecessary processing delays.

• CAFC 2026 Dockets: I do not have access to live CAFC 2026 dockets to determine if US Patent 12107587 is involved in any current litigation.

• Plain-Language Overview of Independent Claims (derived from the detailed description of the invention as authoritative claims):

  Independent Claim 1 (System - General Internal/External Phase Control):
  This claim describes a Field Programmable Gate Array (FPGA) system designed for high-speed data processing, particularly for applications like market data and order entry. The FPGA includes an interface with pins for receiving a first clock signal (first frequency, first phase) and a first serial data stream, and for transmitting a second serial data stream. A deserializer converts the incoming serial data into parallel streams using a receiver-side clock, and computational circuitry processes these parallel streams without needing clock domain crossing operations that would introduce delay. A serializer converts the processed parallel data back to a serial stream using a transmitter-side clock. Crucially, the system includes a phase detector that measures the phase difference between the receiver-side clock and the transmitter-side clock. An internal phase controller, based on this phase difference, generates adjustment information which is used by an adjustable oscillator (either within the FPGA's core PLL or its transceiver PLL, or external to the FPGA) to align the phase of the transmitter-side clock with the receiver-side clock, thereby minimizing latency. This system specifically avoids clock domain crossing operations for speed.

  Independent Claim 2 (System - Internal Transceiver PLL with Phase Adjustment):
  This claim focuses on an FPGA system similar to Claim 1, but specifically details an internal transceiver phase-locked loop (PLL) that is operatively connected to a second reference clock pin. This transceiver PLL is configured to receive a second clock signal and generate a "wire rate clock signal" for the serializer. The phase detector and internal phase controller work together to provide adjustment information (e.g., to set oscillator bias, divider ratio, or delay) to the transceiver PLL, allowing it to adjust the phase of the transmitter-side clock for alignment. The claim highlights that the first set of operations does not include clock domain crossing operations, emphasizing low latency.

  Independent Claim 3 (Method - Internal Transceiver PLL with Phase Adjustment):
  This claim outlines a method for processing market data into order entry data using an FPGA system. The method involves:
  a. Receiving a first serial market data stream at data pins.
  b. Receiving a first clock signal at a reference clock pin.
  c. Transmitting the data and clock signals to a deserializer.
  d. Generating a receiver-side clock and converting the serial data into parallel streams using the deserializer.
  e. Processing the parallel data using computational circuitry without clock domain crossing operations.
  f. Generating an interim transmitter-side clock signal.
  g. Serializing the processed data using the interim transmitter-side clock.
  h. Transmitting the serialized order entry data.
  i. Generating a transmitter-side clock signal using a phase-locked loop on the FPGA (or within the FPGA's transceiver PLL) based on a second clock signal received via a second reference clock pin.
  j. A phase detector (on or off-chip) then compares the receiver-side clock and the transmitter-side clock to generate adjustment information. This information is used to adjust an adjustable oscillator (internal or external) which influences the transmitter-side clock generation, aligning the phases to minimize delay.

  Independent Claim 4 (System - External Phase Detector with Zero-Delay Buffers):
  This claim describes an FPGA system where the phase detector is not located on the FPGA but is external. The FPGA includes zero-delay buffer PLLs connected to clock output pins (a first for the receiver-side clock and a second for the transmitter-side clock). These zero-delay buffer PLLs transmit the clocks to the external phase detector. An internal phase controller within the FPGA receives adjustment information from the external phase detector and uses it to control an adjustable oscillator (which may be external or part of the internal transceiver PLL) to adjust the phase of the transmitter-side clock, ensuring phase matching while minimizing latency by avoiding clock domain crossing operations.

  Independent Claim 5 (Method - External Phase Detector with Zero-Delay Buffers):
  This method claim details processing market data to order entry data in an FPGA system, specifically featuring an external phase detector. Similar to Method Claim 3, it involves deserialization, computation without clock domain crossing, and serialization. The key difference is that the receiver-side and transmitter-side clock signals are transmitted off the FPGA via output pins (potentially through zero-delay buffer PLLs within the FPGA) to an external phase detector. This external phase detector then generates adjustment information, which is fed back to the FPGA to control an adjustable oscillator (e.g., for the wire rate clock generation or the transceiver PLL) to achieve phase alignment between the internal receiver and transmitter clocks.

  Independent Claim 6 (System - Single Reference Clock for both Deserializer and Transceiver PLL):
  This claim describes an FPGA system where both the deserializer and the transceiver PLL receive the same first clock signal from a first reference clock pin (the second reference clock pin is configured to receive the first clock signal). The rest of the system operates similarly to previous claims, with a deserializer, computational circuitry (without clock domain crossing), a serializer, a phase detector, and an adjustable oscillator. The phase detector compares the receiver-side clock and the transmitter-side clock, and an internal phase controller uses this information to adjust the oscillator controlling the transmitter-side clock, ensuring phase alignment. The phase detector can be internal or external to the FPGA.

  Independent Claim 7 (Method - Single Reference Clock for both Deserializer and Transceiver PLL):
  This method claim corresponds to System Claim 6, detailing the process of using a single reference clock for both the deserializer and the generation of the transmitter-side clock via a PLL. It involves receiving market data and a first clock signal, generating a receiver-side clock, processing data without clock domain crossing, and generating an interim transmitter-side clock. A phase detector (internal or external) compares the receiver-side and transmitter-side clocks, and based on the detected phase difference, an adjustable oscillator is controlled to align the phases of the clocks used by the serializer, ultimately producing order entry data with minimized latency.