US 11329655

US Patent 11329655: Field Programmable Gate Array with Internal Phase-Locked Loop

Title: Field programmable gate array with internal phase-locked loop

Assignee: HFT Solutions LLC

Inventor: Nima Badizadegan

Filing Date: April 21, 2021

Issue Date: May 10, 2022

Abstract:
The present invention generally relates to a field programmable gate array (FPGA) system and a method for processing a data stream using such a system. It specifically addresses the technological challenge of phase matching receiver-side and transmitter-side clock signals within an FPGA without introducing unnecessary processing delays. The system incorporates an external or internal phase controller that provides phase matching between a receiver clock and a transmitter clock used in the FPGA. This approach aims to synchronize receiving and transmitting clock signals, particularly in applications requiring fast processing like high-frequency trading, by avoiding the latency typically associated with conventional clock domain crossing operations. [cite: The abstract is derived from the "Definitions" section of the provided patent text, which describes the invention's purpose and scope, as a formal "Abstract" section was not explicitly labeled in the provided text.]

Plain-Language Overview of Independent Claims:

Please note: The full, formal claims section was not explicitly provided in the initial patent text. The following plain-language overview of the independent claims is therefore derived from the comprehensive "Definitions" section which details the core components and methods of the invention.

• Independent Claim 1 (System Claim - Inferred):
  A field programmable gate array (FPGA) system is claimed. This system includes an FPGA with a first interface designed to receive a first clock signal and a first serial data stream, and to transmit a second serial data stream. The FPGA also features a deserializer connected to the first interface, configured to convert the incoming serial data stream into parallel data streams and generate a first receiver-side clock signal based on the received first clock signal. Importantly, the FPGA includes computational circuitry to process these parallel data streams without needing clock domain crossing operations, thus minimizing delay. A serializer is also included to convert the processed parallel data streams back into a second serial data stream for transmission. A critical aspect is the inclusion of a phase-locked loop (PLL) within the FPGA, or an adjustable transceiver PLL, that generates a first wire rate clock signal based on a second reference clock signal and transmits it to the serializer. This PLL is configured to adjust the phase and/or frequency of the transmitter-side clock to align it with the receiver-side clock, facilitated by an internal phase controller and a phase detector that measures the difference between the receiver and transmitter clocks. [cite: The structure and components of this system claim are inferred from the "Definitions" section, specifically the entries describing "a field programmable gate array system," "deserializer," "computational circuitry," "serializer," and "a phase lock loop configured to: receive the second clock signal..."]

• Independent Claim 2 (Method Claim - Inferred):
  A method for processing a first serial data stream (e.g., market data) using an FPGA system to generate a second serial data stream (e.g., order entry data) is claimed. This method involves several steps: receiving the first serial data stream and a first clock signal by the FPGA's interface; transmitting these to a deserializer; the deserializer generating a first receiver-side clock signal and converting the serial data into parallel data streams; processing these parallel data streams by computational circuitry (without clock domain crossing delays); generating an interim transmitter-side clock signal and converting the parallel data back to a second serial data stream by a serializer; and then transmitting the second serial data stream from the FPGA. A key part of this method involves comparing the phase of the first receiver-side clock signal with the phase of the interim transmitter-side clock signal using a phase detector. Based on this comparison, adjustment information is generated and used to control an adjustable oscillator or a transceiver PLL within or connected to the FPGA, thereby adjusting the phase of the interim transmitter-side clock signal to achieve phase alignment. [cite: The steps of this method claim are inferred from the "Definitions" section, specifically the entries describing "a method for processing a first serial data stream," "receiving," "transmitting," "generating, by the deserializer," "converting," "performing a first set of operations," "generating, by a serializer," "transmitting, from the serializer," and the detailed description of the phase adjustment process using a phase detector and adjustable PLLs.]

CAFC 2026 Dockets:
A search of the CAFC 2026 dockets for patent number 11329655 did not return any specific results. This indicates that there are no cases directly involving this patent scheduled in the publicly available CAFC dockets for 2026 as of the current date.