US 11018678

US Patent 11018678, titled "Field programmable gate array with internal phase-locked loop," was issued to HFT Solutions LLC on May 25, 2021, with an anticipated expiration date of October 31, 2039. The inventor is Nima Badizadegan, and the application was originally filed on July 23, 2020. The patent's legal status is active.

As of April 26, 2026, a search of the CAFC 2026 dockets for patent US11018678B1 did not reveal any directly scheduled cases.

Abstract:
A field programmable gate array system includes a field programmable gate array (FPGA) comprising a first interface including a first reference clock pin, a second reference clock pin, a first plurality of data pins, and a second plurality of data pins. A deserializer is operationally connected to the first reference clock pin to receive a first clock signal and to the first plurality of data pins to receive a first serial data stream. The deserializer is configured to convert the first serial data stream into a first plurality of parallel data streams and to generate a first receiver side clock signal. Computational circuitry is operationally connected to the deserializer to receive the first plurality of parallel data streams and the first receiver side clock signal. A serializer is operationally connected to the computational circuitry to receive a second plurality of parallel data streams and a first transmitter side clock signal. A phase detector is operationally connected to the deserializer and the serializer to receive the first receiver side clock signal and the first transmitter side clock signal. An internal phase controller is operationally connected to the phase detector and to an adjustable phase lock loop (PLL) to receive an output of the phase detector and to provide adjustment information to the adjustable PLL to adjust a phase of a first wire rate clock signal.

Plain-Language Overview of Independent Claims:

• Claim 1: Field Programmable Gate Array System (Internal PLL)
  This claim describes an FPGA system that includes an FPGA chip. This chip has interfaces for receiving incoming and transmitting outgoing data and clock signals. Inside, a deserializer converts high-speed serial input data into slower parallel data streams, generating a receiver-side clock. Computational logic processes this parallel data. A serializer then converts the processed parallel data back into a high-speed serial output, using a transmitter-side clock. A crucial aspect is an internal phase detector that compares the receiver-side and transmitter-side clocks to identify any phase difference. This difference is fed to an internal phase controller, which then instructs an adjustable Phase-Locked Loop (PLL) (also within the FPGA) to adjust the phase of the clock signal used by the serializer, aiming to align the transmit and receive clocks.

• Claim 11: Field Programmable Gate Array System (External Phase Detector)
  Similar to Claim 1 in its core FPGA components (interfaces, deserializer, computational logic, serializer), this claim distinguishes itself by placing the phase detector outside the FPGA. The receiver-side and transmitter-side clock signals are routed off the FPGA to this external phase detector. An internal phase controller on the FPGA receives the phase difference information from this external detector and uses it to provide adjustment information to an adjustable oscillator (which may also be external to the FPGA). This external oscillator then generates an adjusted clock signal for the serializer, thus controlling the transmit clock's phase.

• Claim 18: Method for Processing Data (Internal Phase Detector)
  This claim outlines a method for using an FPGA system to process market data into order entry data. It involves: receiving market data and a clock signal, deserializing the data, performing calculations, and generating an interim transmitter clock signal. The method then describes an internal phase detector on the FPGA comparing the receiver and interim transmitter clocks. An internal phase controller generates adjustment data based on this comparison, which is used to modify an internal adjustable oscillator. This adjusted clock then dictates the final serialization of the order entry data for transmission.

• Claim 24: Method for Processing Data (External Phase Detector)
  This method claim also focuses on processing market data into order entry data. However, it specifies that the receiver-side and interim transmitter-side clock signals are sent off the FPGA to an external phase detector. The phase difference detected externally is communicated back to an internal phase controller on the FPGA. This controller then sends adjustment information to an external adjustable oscillator. The externally adjusted clock signal is then routed back into the FPGA to the serializer, which uses it to transmit the order entry data.

• Claim 29: Field Programmable Gate Array System (First Clock for Second Pin)
  This claim describes an FPGA system structurally similar to Claim 1, including internal phase detection and adjustment. The unique aspect here is that the FPGA's second reference clock pin, which would typically receive a separate transmit clock input, is instead configured to receive the same first clock signal that the first reference clock pin uses for the deserializer. This suggests that both the receive and transmit timing might originate from a single external clock source, with the internal adjustable PLL then managing the phase alignment of the serializer's clock relative to this common source.