US 10763865

US patent 10763865, titled "Field programmable gate array with internal phase-locked loop," was filed on May 29, 2020, by inventor Nima Badizadegan, and issued on September 1, 2020. The current assignee is HFT Solutions LLC, effective April 4, 2022. The original assignee was listed as an individual.

Abstract:
The patent describes a field programmable gate array (FPGA) system and a method for processing a data stream using it. The system includes an FPGA with a first interface for receiving a first clock signal and a first serial data stream, and for transmitting a second serial data stream. A deserializer converts the received serial data into parallel streams and generates a receiver-side clock. Computational circuitry processes these parallel data streams without clock domain crossing operations that would introduce delay. A serializer converts the processed parallel data back into a second serial data stream. A phase detector compares the receiver-side clock signal and an interim transmitter-side clock signal. An internal phase controller, based on the phase detector's output, provides adjustment information to either an internal phase-adjustable PLL or an adjustable oscillator outside the FPGA, to align the phases of the receiver and transmitter clocks. The method outlines the steps for this data processing and clock synchronization.

Independent Claims Overview:

• Claim 1 (System Claim): This claim describes a field programmable gate array (FPGA) system. It comprises an FPGA with a first interface, including pins for receiving a first clock signal and a first serial data stream, and for transmitting a second serial data stream. The FPGA also contains a deserializer that converts the incoming serial data into parallel streams and generates a receiver-side clock. Computational circuitry then processes these parallel data streams without introducing delays from clock domain crossing. A serializer converts the processed parallel data back into a serial stream for transmission. Crucially, the system includes a phase detector (either on or off the FPGA) that compares the deserializer's receiver-side clock with an interim transmitter-side clock from the serializer. Based on this comparison, an internal phase controller provides adjustment information to either a phase-adjustable Phase-Locked Loop (PLL) located within the FPGA core or an adjustable oscillator (inside or outside the FPGA) to synchronize the phases of the receiver and transmitter clocks. The adjustment information can set an oscillator's bias, a divider ratio, or a delay.

• Claim 17 (Method Claim): This claim outlines a method for processing a first serial data stream (e.g., market data) using an FPGA system to generate a second serial data stream (e.g., order entry data). The method involves receiving the first serial data stream and a first clock signal at the FPGA, then transmitting them to a deserializer. The deserializer generates a receiver-side clock and converts the serial data into parallel streams. These parallel streams are processed by computational circuitry without clock domain crossing. An interim transmitter-side clock signal is generated and used by a serializer to convert the parallel data back into a second serial data stream. A phase detector (on or off the FPGA) compares the receiver-side and interim transmitter-side clock signals, and an internal phase controller generates adjustment information. This information is used to adjust an adjustable PLL (on or off the FPGA) or an adjustable oscillator (on or off the FPGA) to align the phases of the receiver and transmitter clocks, thereby generating a final transmitter-side clock signal.

• Claim 33 (System Claim - Variation): This claim describes an FPGA system similar to Claim 1, but specifically states that the FPGA further includes a transceiver phase locked loop (which itself can be adjustable) operationally connected to the second reference clock pin and configured to receive a second clock signal to generate the first wire rate clock signal that is transmitted to the serializer. The system also includes an internal phase controller and phase detector which, based on the difference between the receiver and transmitter clocks, provides adjustment information to this transceiver PLL to align the clock phases.

• Claim 49 (Method Claim - Variation): This claim outlines a method similar to Claim 17, but specifies that generating the first wire rate clock signal involves a transceiver phase lock loop receiving and processing a second clock signal and providing the first wire rate clock signal to the serializer. The phase detector and internal phase controller then work to adjust this transceiver PLL to align the receiver and transmitter clock phases.

• Claim 65 (System Claim - External Phase Detector): This claim details an FPGA system similar to Claim 1, but explicitly states that the phase detector is not on the field programmable gate array. Instead, it is operationally connected to output pins on a second interface of the FPGA that transmit the receiver-side and transmitter-side clock signals. The internal phase controller still uses the phase detector's output to provide adjustment information to either an internal phase-adjustable PLL or an adjustable oscillator (internal or external to the FPGA).

• Claim 81 (Method Claim - External Phase Detector): This claim describes a method similar to Claim 17, but explicitly states that the phase detector is not on the field programmable gate array. The method involves transmitting the receiver-side and interim transmitter-side clock signals from the FPGA, via output pins, to this external phase detector. The phase detector then generates a phase difference indicator signal, which the internal phase controller uses to provide adjustment information to adjust the clock generation.

• Claim 97 (System Claim - Single Reference Clock): This claim describes an FPGA system where the FPGA's first interface includes a first reference clock pin to receive a first clock signal and a second reference clock pin configured to receive the same first clock signal. An adjustable transceiver phase locked loop is operationally connected to this second reference clock pin to generate the first wire rate clock signal transmitted to the serializer. An internal phase controller and phase detector work to align the receiver and transmitter clock phases by providing adjustment information to this adjustable transceiver PLL.

• Claim 113 (Method Claim - Single Reference Clock): This method claim outlines a process where the FPGA receives a first clock signal via both a first and second reference clock pin. An adjustable phase lock loop (which may be a transceiver phase lock loop) generates the second clock signal based on the received first clock signal. The method then proceeds similarly to Claim 49, with a phase detector and internal phase controller providing adjustment information to the adjustable phase lock loop to align the clock phases.

CAFC 2026 Dockets:
A search of the CAFC 2026 dockets (as of April 26, 2026) did not specifically return any results directly referencing US patent 10763865. The search results provided general scheduled cases for May, June, and July 2026, but no specific patent numbers were listed in a way that could be definitively linked to a particular case without further detailed investigation into each case's filings.