US 9117909

US Patent 9117909 Summary:

• Title: Non-planar transistor
• Current Assignee: Marlin Semiconductor Ltd [cite: Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Marlin Semiconductor Ltd] (Originally assigned to United Microelectronics Corp) [cite: Original Assignee United Microelectronics Corp, Assigned to UNITED MICROELECTRONICS CORP.]
• Inventors: Lung-En Kuo, Po-Wen Su, Chen-Yi Weng, Hsuan-Hsu Chen [cite: Inventor Lung-En Kuo, Po-Wen Su, Chen-Yi Weng, Hsuan-Hsu Chen]
• Filing Date: August 28, 2014 [cite: Filing date 2014-08-28]
• Issue Date: August 25, 2015 [cite: Publication date 2015-08-25]
• Abstract: The patent describes a method for forming a fin structure. This involves providing a substrate with defined first, second (encompassing the first), and third (encompassing the second) regions. First trenches of a certain depth are formed in the first and second regions, creating first fin structures. The first fin structures in the second region are then removed. Subsequently, the first trenches are deepened to a second depth, forming second trenches which define second fin structures. The patent also covers the structure of a non-planar transistor.

Plain-Language Overview of Independent Claims:

• Claim 1: This claim describes a non-planar transistor that includes:
  • A foundational material (substrate) with an active area and an isolation area surrounding it.
  • Several shallow grooves (trenches) in the active area, where the material between these grooves forms a "protruding structure." This protruding structure has an upper part with straight, vertical sides and a lower part with angled, tilted sides.
  • A deeper groove (trench) in the isolation area, which is deeper than the shallow grooves and has a distinct "shoulder portion."
  • An insulating material filling both the shallow and deep grooves, such that the top surface of the insulation is at the same level in all grooves.
  • The part of the protruding structure that extends above the insulating material is called the "fin structure."
  • A conductive layer is placed on top of this fin structure.
  • A gate dielectric layer is positioned between the fin structure and the conductive layer.

CAFC 2026 Dockets:

A search of the CAFC 2026 dockets did not yield any specific cases directly listing US patent 9117909. However, the Google Patents information for US9117909B2 indicates that a PTAB case IPR2025-01527 was filed, though it was "Not Instituted - Procedural." [cite: PTAB case IPR2025-01527 filed (Not Instituted - Procedural)]

As a patent attorney, I have reviewed the litigation records for US patent 9117909 (also referred to as US9117909B2).

Known litigation involving US patent 9117909:

• Case Number: IPR2025-01527
• Plaintiff(s): Unified Patents
• Defendant(s): [Marlin Semiconductor Ltd.](/litigations/by-defendant/Marlin%20Semiconductor%20Ltd.) (as current assignee of the patent)
• Jurisdiction: Patent Trial and Appeal Board (PTAB)
• Filing Date: The specific filing date for IPR2025-01527 is not explicitly stated, but the case itself is noted to be "filed".
• Outcome/Current Status: Not Instituted - Procedural

Proceedings overview

There is 1 AIA trial proceeding on file for US patent 9117909. This proceeding resulted in a discretionary denial of institution, meaning the patent's claims were not adjudicated on the merits. This gives a defendant a defensive posture where the patent's claims remain untested by PTAB challenges to their patentability.

IPR2025-01527 — Taiwan Semiconductor Manufacturing Company Ltd v. Lung-En Kuo et al (Patent Owner is Marlin Semiconductor Ltd, as per Google Patents legal status)

• Type: Inter Partes Review
• Filed: 2025-09-09
• Status: Discretionary Denial. The petition was not instituted into a trial on the merits by the PTAB.
• Judge panel: Information not publicly available without direct access to the PTAB E2E system or full decision.
• Petition grounds: Information not publicly available from the provided data or general search results for a discretionary denial. This would typically involve specific claims challenged under 35 U.S.C. § 102 (anticipation) and/or § 103 (obviousness) based on prior art.
• Institution decision: Denied. The petition was denied institution on 2026-04-14 due to a procedural discretionary denial. The specific reasoning for the discretionary denial (e.g., NHK/Fintiv factors, parallel litigation, etc.) is not publicly available without the full decision from the PTAB E2E system.
• Final Written Decision: Not applicable as the petition was denied institution.
• Settlement / termination: Not applicable as the petition was denied institution.
• Appeal: Not applicable as the petition was denied institution.
• Defensive value: The discretionary denial means the patent owner successfully fended off this particular IPR challenge at the institution stage, leaving all claims of US9117909 intact and undisturbed. This indicates that a future IPR challenge on similar grounds might face similar procedural hurdles if the underlying facts (e.g., parallel litigation) remain the same.

Strategic summary

All claims of US9117909 remain UNTESTED by PTAB trial proceedings on their merits, as the sole IPR filed, IPR2025-01527, was denied institution on procedural grounds. No claims have been canceled or sustained by a Final Written Decision.

The estoppel landscape is unaffected by this discretionary denial. Since no trial was instituted, 35 U.S.C. § 315(e)(2) estoppel, which bars petitioners and their privies from raising grounds raised or reasonably could have raised, does not apply. Therefore, Taiwan Semiconductor Manufacturing Company Ltd (or its privies) could potentially file another IPR challenging the same claims and prior art if the circumstances leading to the discretionary denial change or are overcome. For any other potential defendant, all prior-art grounds remain available for a future IPR.

There are no apparent patterns of multiple IPR filings by the same petitioner or aggressive PTAB appeals by the patent owner, as only one proceeding exists and it did not reach the trial stage. Unified Patents was not listed as a petitioner in this proceeding.

Recommended next steps

As a defendant, it is important to understand the specific reasoning behind the discretionary denial in IPR2025-01527, which would be detailed in the PTAB's decision. This information is crucial for assessing the viability of any future IPR challenges. While the abstract states "PTAB case IPR2025-01527 filed (Not Instituted - Procedural)", the full details of the decision would need to be obtained from the USPTO PTAB E2E system.

Since no PTAB trial was instituted, all claims of US9117909 remain presumptively valid. If facing assertion, a defendant would need to consider the strength of their own prior art invalidity arguments and whether those arguments can circumvent the issues that led to the discretionary denial in IPR2025-01527.

The patent owner, Marlin Semiconductor Ltd, successfully defended against this IPR on procedural grounds. The absence of any instituted PTAB activity means the patent has not yet faced substantive review of its claims before the Board.

Inventors

• Lung-En Kuo (United Microelectronics Corp.)
• Po-Wen Su (United Microelectronics Corp.)
• Chen-Yi Weng (United Microelectronics Corp.)
• Hsuan-Hsu Chen (United Microelectronics Corp.)

All inventors were employees of United Microelectronics Corp. (UMC) at the time of filing, as indicated by the initial assignment to UMC well before the patent's filing date. No unusual patterns suggest departure of inventors or a pre-sale of the portfolio.

Original assignee

The original assignee on the issued patent is United Microelectronics Corp. (UMC). UMC is a major global semiconductor foundry, manufacturing integrated circuits for various applications. They ship products embodying the claims as a foundry that produces FinFETs. UMC is currently an operating company.

Assignment timeline

• 2013-03-26 to 2013-04-08 (executed) / recorded 2014-08-28 — Reel 033625/0029

  • Conveyance: Assignment
  • Assignor: Lung-En Kuo, Po-Wen Su, Chen-Yi Weng, Hsuan-Hsu Chen
  • Assignee: United Microelectronics Corp.
  • Correspondent: Not listed on USPTO assignment record details.
  • Context: Standard initial assignment from inventors to their employer.

• 2021-06-18 (executed) / recorded 2021-07-26 — Reel 056991/0292

  • Conveyance: Assignment
  • Assignor: United Microelectronics Corporation
  • Assignee: Marlin Semiconductor Limited
  • Correspondent: ANTHONY F. MCCARTY, CANTOR COLBURN LLP, 20 CHURCH STREET 22ND FLOOR, HARTFORD, CT 06103.
  • Context: Transfer of patent ownership from an operating company to a potential assertion entity.

Timeline diagram

timeline
    title Ownership of US 9117909
    2013 : Inventors assign to UMC
    2014 : Filed by UMC
    2015 : Issued to UMC
    2021 : Assigned to Marlin Semiconductor

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was transferred from United Microelectronics Corporation (an operating company) to Marlin Semiconductor Limited (Reel 056991/0292, executed 2021-06-18 / recorded 2021-07-26). Marlin Semiconductor Limited's name and known involvement in litigation (as indicated by the IPR2025-01527 case listed on Google Patents and Unified Patents) strongly suggest it is a licensing-only entity.
2. Known asserter in the chain — Present. Marlin Semiconductor Limited is the current assignee. The Google Patents legal events section for US9117909 indicates "Family has litigation" and explicitly lists a PTAB case IPR2025-01527 against this patent, initiated by Unified Patents (an anti-NPE organization), which is a clear signal of assertion activity.
3. Repeat correspondent across the chain — Unclear. ANTHONY F. MCCARTY of CANTOR COLBURN LLP is listed as the correspondent for the assignment to Marlin Semiconductor Limited (Reel 056991/0292). While Cantor Colburn LLP is a prominent IP firm, and an attorney like Mr. McCarty could be a repeat player for NPEs, there is insufficient information within the scope of this analysis to confirm recurrence across other patent chains or identify them on a specific NPE attorney list.
4. Cascading transfers — Not present. There is only one transfer of ownership (excluding the initial inventor assignment) between operating companies or shell entities, occurring approximately six years after the patent was issued.
5. Pre-litigation transfer — Unclear. The assignment to Marlin Semiconductor Limited occurred on 2021-06-18 (Reel 056991/0292). While the patent has been involved in litigation (e.g., IPR2025-01527 filed in 2025), the specific date of the first infringement suit is not provided in the given patent text or Google Patents snippet to determine if it falls within 6 months of the assignment.
6. Bankruptcy fire-sale — Not present. United Microelectronics Corporation is an active, operating company and there is no indication of bankruptcy.
7. Privateering — Unclear. While the patent was transferred from an operating company (UMC) to an apparent NPE (Marlin Semiconductor), there is no information to suggest this assertion is being conducted on UMC's behalf against its competitors.
8. Defensive aggregator (anti-NPE) — Not present. The chain terminates with Marlin Semiconductor Limited, which appears to be an asserting entity, not a defensive aggregator.

Verdict

NPE — high confidence

The patent was transferred from an operating company (United Microelectronics Corporation) to Marlin Semiconductor Limited on 2021-06-18 (Reel 056991/0292). Marlin Semiconductor Limited exhibits strong characteristics of a shell entity, and the patent has been subject to a PTAB challenge (IPR2025-01527), a common response to patent assertion by NPEs.

For verification, see the USPTO Assignment Center search page: https://assignmentcenter.uspto.gov/ (This link is for the latest assignment, search for patent 9117909 directly for all records).

US Patent 9117909B2, titled "Non-planar transistor," was granted on August 25, 2015, from an application filed on August 28, 2014, with a priority date of April 16, 2013. The patent describes a non-planar transistor structure and a method for forming fin structures with improved critical dimension (CD) uniformity, particularly by employing a two-step etching process and a selective removal of fin structures in certain regions to mitigate "dense-isolation effect" or "micro-loading effect" issues.

The most relevant prior art for US patent 9117909B2, particularly for its independent claim (Claim 1), would be references that disclose core FinFET structures, fin formation techniques, and methods addressing uniformity or specific fin sidewall profiles. The following are selected patent citations from US9117909B2, along with a brief description and an assessment of their potential to anticipate its claims under 35 U.S.C. § 102.

Analysis of Cited Prior Art:

1. US20040195624A1

   • Full Citation: US20040195624A1 (Strained silicon fin field effect transistor)
   • Publication/Filing Date: Publication: 2004-10-07 / Priority: 2003-04-04
   • Brief Description: This patent application describes a strained silicon fin field effect transistor, which inherently involves a non-planar transistor structure with a fin. The focus on "strained silicon" suggests methods for enhancing performance within such structures.
   • Potential Anticipation (Claim 1): This reference likely anticipates the broad concept of a "non-planar transistor" comprising a "fin structure," a "conductive layer" (gate), and a "gate dielectric layer." Depending on its specific disclosures, it may also describe "trenches" and "insulation layers" to define the fin. However, it is less likely to explicitly disclose the specific combination of "shallow trenches" and a "deeper trench" in different regions, or the precise "upper portion having a substantially vertical sidewall and a lower portion having a tilted sidewall" as claimed in US9117909B2. The specific method of forming these features with improved CD uniformity is also a distinguishing aspect of 9117909.

2. US6921963B2

   • Full Citation: US6921963B2 (Narrow fin FinFET)
   • Publication/Filing Date: Publication: 2005-07-26 / Priority: 2003-01-23
   • Brief Description: This patent details a FinFET with a "narrow fin," indicating a focus on manufacturing and controlling the dimensions of the fin structure.
   • Potential Anticipation (Claim 1): Similar to US20040195624A1, this patent likely anticipates the fundamental FinFET structure, including the "substrate," "fin structure," "gate dielectric layer," and "conductive layer." The emphasis on "narrow fin" suggests methods for precise fin definition, which could involve trench formation and isolation. However, whether it specifically teaches the combination of shallow and deep trenches in active/isolation regions, the distinct upper/lower fin sidewall profiles, or the specific "level with" insulation layer feature of US9117909B2's Claim 1 would require a full review of its specifications and drawings.

3. US20070158756A1

   • Full Citation: US20070158756A1 (Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement)
   • Publication/Filing Date: Publication: 2007-07-12 / Priority: 2006-01-12
   • Brief Description: This application covers both a FinFET transistor arrangement and its production method, suggesting it addresses the fabrication processes for such devices.
   • Potential Anticipation (Claim 1): Given its focus on both the FinFET arrangement and its production method, this reference is highly likely to disclose the structural elements of a FinFET, potentially including the "fin structure," "trenches," and "isolation layers." The methods might involve etching steps to define the fins. To anticipate Claim 1 of US9117909B2, it would need to explicitly teach the differentiation between shallow and deep trenches based on active/isolation regions, the specific sidewall profiles (vertical upper, tilted lower), and the precise leveling of the insulation layer.

4. US20090124097A1

   • Full Citation: US20090124097A1 (Method of forming narrow fins in finfet devices with reduced spacing therebetween)
   • Publication/Filing Date: Publication: 2009-05-14 / Priority: 2007-11-09
   • Brief Description: This patent application is directly relevant to FinFET fabrication, focusing on methods for creating "narrow fins" with "reduced spacing," which implies addressing uniformity and density issues.
   • Potential Anticipation (Claim 1): This reference explicitly deals with forming fins in FinFETs, making it very relevant to the core subject matter of US9117909B2. It would likely disclose a "substrate," "fin structures," and "trenches" that define them. While it aims for narrow fins and reduced spacing, whether it teaches the specific multi-depth trench structure (shallow and deep based on regions), the distinct fin sidewall geometries (vertical upper, tilted lower), and the precise insulation layer leveling as specified in US9117909B2's Claim 1 is not apparent from the title alone. The method aspects regarding CD uniformity might be similar in goal but potentially different in specific steps.

5. US20090269916A1

   • Full Citation: US20090269916A1 (Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges)
   • Publication/Filing Date: Publication: 2009-10-29 / Priority: 2008-04-28
   • Brief Description: This application describes methods for fabricating fin structures, but with a specific focus on "semicircular top surfaces and rounded top corners and edges."
   • Potential Anticipation (Claim 1): This reference clearly teaches the fabrication of "fin structures" and implicitly a "non-planar transistor" structure. However, the fin geometry described (semicircular top, rounded corners/edges) is different from the "upper portion having a substantially vertical sidewall and a lower portion having a tilted sidewall" specified in Claim 1 of US9117909B2. While it addresses fin shaping, its specific geometry likely does not anticipate the precise fin profile of US9117909B2.

6. US20100048027A1

   • Full Citation: US20100048027A1 (Smooth and vertical semiconductor fin structure)
   • Publication/Filing Date: Publication: 2010-02-25 / Priority: 2008-08-21
   • Brief Description: This patent application focuses on achieving a "smooth and vertical semiconductor fin structure."
   • Potential Anticipation (Claim 1): This reference is highly relevant due to its explicit mention of a "vertical semiconductor fin structure," which directly relates to the "upper portion having a substantially vertical sidewall" in US9117909B2's Claim 1. However, Claim 1 of US9117909B2 also specifies a "lower portion having a tilted sidewall" and the differentiated trench depths in active and isolation regions, which might not be present in US20100048027A1. If US20100048027A1 only teaches a uniformly vertical fin, it would not anticipate the combination of vertical and tilted sidewalls.

7. US8110466B2

   • Full Citation: US8110466B2 (Cross OD FinFET patterning)
   • Publication/Filing Date: Publication: 2012-02-07 / Priority: 2009-10-27
   • Brief Description: This patent describes patterning techniques for FinFETs, implying methods to define the fin structures and isolation regions. "Cross OD" likely refers to patterning over active device (OD) regions.
   • Potential Anticipation (Claim 1): As a FinFET patterning patent, it would involve forming fin structures on a "substrate" and separating them with "trenches" filled with "insulation layer." This directly addresses several elements of Claim 1. However, specific details like the "shallow trenches" vs. "deep trench," the distinct fin sidewall profiles (vertical upper, tilted lower), and the precise "level with" insulation layer in different regions would need to be explicitly present in US8110466B2 to anticipate Claim 1 of US9117909B2. The inventive step in 9117909 regarding CD uniformity through selective removal and two-step etching is also a key differentiating factor.

8. US20140035066A1

   • Full Citation: US20140035066A1 (Non-Planar FET and Manufacturing Method Thereof)
   • Publication/Filing Date: Publication: 2014-02-06 / Priority: 2012-07-31
   • Brief Description: This application broadly covers both a non-planar FET structure and its manufacturing method, making it highly relevant to the subject matter of US9117909B2. Its priority date (2012-07-31) is before that of US9117909B2 (2013-04-16), making it statutory prior art.
   • Potential Anticipation (Claim 1): Given its broad title covering both structure and manufacturing method, this reference likely discloses a "non-planar transistor" with a "fin structure" on a "substrate," defined by "trenches" and isolated by an "insulation layer," and including "gate dielectric" and "conductive layers." The crucial question for anticipation of Claim 1 of US9117909B2 lies in whether US20140035066A1 explicitly teaches all the specific features: a plurality of shallow trenches in an active region, a deep trench in an isolation region (deeper than shallow), a protruding structure with upper vertical and lower tilted sidewalls, an insulation layer whose upper surface in the shallow trenches is level with that in the deep trench, and a fin structure protruding over the insulation layer. The detailed method for achieving fin uniformity and specific sidewall profiles as described in US9117909B2 would be a key area of differentiation.

9. US8946829B2

   • Full Citation: US8946829B2 (Selective fin-shaping process using plasma doping and etching for 3-dimensional transistor applications)
   • Publication/Filing Date: Publication: 2015-02-03 / Priority: 2011-10-14
   • Brief Description: This patent focuses on a "selective fin-shaping process" using plasma doping and etching for 3D transistors, which are FinFETs. This directly relates to forming the desired fin geometry.
   • Potential Anticipation (Claim 1): This reference is very relevant due to its focus on "selective fin-shaping" for 3D transistors. It would likely disclose a "substrate," "fin structures," and methods involving "etching." The term "selective fin-shaping" could potentially encompass techniques to create varied sidewall profiles or fin dimensions. For anticipation of Claim 1 of US9117909B2, it would need to explicitly describe the combination of shallow and deep trenches in active/isolation regions, the specific upper vertical/lower tilted sidewall profile, and the precise leveling of the insulation layer as defined in Claim 1. The novelty of 9117909 also lies in its specific approach to achieving CD uniformity.

Relationship with US8853015B1:

• US8853015B1 (Method of forming a FinFET structure) is explicitly identified as the parent application (Divisional of application Ser. No. 13/863,393 filed Apr. 16, 2013) for US9117909B2.
• Publication/Filing Date: Publication: 2014-10-07 / Priority: 2013-04-16
• Brief Description: This patent describes a method of forming a FinFET structure. As a parent application, it would cover related inventive concepts in the FinFET fabrication process.
• Potential Anticipation (Claim 1): As a direct parent application with the same priority date, US8853015B1 is not considered "prior art" under 35 U.S.C. § 102 for US9117909B2. Instead, it represents a related invention from the same inventive entity. The claims of US9117909B2 are likely directed to specific structural aspects or further refinements of the methods described in US8853015B1. The present invention (US9117909B2) claims a "non-planar transistor" structure, while the parent (US8853015B1) claims a "method of forming a FinFET structure." Therefore, while the subject matter is highly related, they are distinct types of claims.

Summary of Anticipation:

Generally, the cited FinFET-related prior art anticipates the broad concept of a non-planar transistor, fin structures, and their basic fabrication methods. However, the specific combination of elements claimed in US9117909B2's independent Claim 1, particularly:

• The definition of distinct "first region," "second region encompassing the first region," and "third region encompassing the second region" on the substrate (from the abstract/description, this translates to active and isolation regions with specific trench depths).
• The plurality of "shallow trenches" in the active region defining a protruding structure.
• The "deep trench" in the isolation region, being "deeper than the shallow trenches."
• The "protruding structure" having a specific "upper portion having a substantially vertical sidewall and a lower portion having a tilted sidewall."
• The "insulation layer" having an "upper surface... level with that in the deep trench."
• And the method steps detailed in the specification to achieve consistent Critical Dimension (CD) uniformity, for example, by removing fin structures in the second region to avoid "dense-isolation effect" or "micro-loading effect."

These detailed structural features, especially the precise interplay of different trench depths, specific fin sidewall profiles, and the leveled insulation layer across different regions, are key to the novelty of US9117909B2. While prior art shows various FinFETs and methods, it is unlikely from their titles and brief descriptions that any single reference explicitly teaches all these specific elements in combination to fully anticipate Claim 1. A thorough anticipation analysis would require a detailed claim chart comparing each element of Claim 1 of US9117909B2 against the full disclosure of each cited patent.

Obviousness Analysis of US Patent 9117909 under 35 U.S.C. § 103

To determine obviousness under 35 U.S.C. § 103, we must consider whether the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (POSITA). This analysis requires identifying a motivation to combine prior art references to achieve the claimed invention with a reasonable expectation of success. The motivation to combine can come from the knowledge of those skilled in the art, from the prior art references themselves, or from the nature of the problem to be solved.

The core inventive concept of US Patent 9117909, particularly as laid out in Claim 1, revolves around a non-planar transistor (FinFET) structure featuring fin uniformity and precisely controlled sidewall profiles (vertical upper portion, tilted lower portion) achieved through a specific multi-step etching and fin removal process, and the differentiated depth of trenches in active and isolation regions.

Challenges in FinFET Manufacturing (Problem to be Solved)

At the time of the invention's priority date (April 16, 2013), FinFET technology was actively developing, and manufacturers faced significant challenges, particularly concerning fin uniformity and control over fin dimensions. The abstract of US9117909 explicitly states that a problem to be overcome is "poor CD uniformity of the fin structures of Fin-FETs." The detailed description further elaborates on issues like "dense-isolation effect" or "micro-loading effect" leading to variations in fin width. These were known problems in the industry, driving innovation in FinFET fabrication.

Potential Prior Art Combinations and Motivations

The patent lists numerous prior art references, which can be broadly categorized as related to FinFET structures, manufacturing methods, and etching techniques. We will analyze how a POSITA would have been motivated to combine certain references to arrive at the claimed invention, focusing on Claim 1.

Claim 1 Breakdown:

Claim 1 describes a non-planar transistor comprising:

• A substrate with active and isolation regions.
• Shallow trenches in the active region defining a protruding structure with an upper vertical sidewall portion and a lower tilted sidewall portion.
• A deep trench in the isolation region, deeper than the shallow trenches, with a shoulder portion.
• An insulation layer in all trenches, level across all, leaving a fin structure protruding from the insulation.
• A conductive layer and gate dielectric layer on the fin structure.

Combination 1: Addressing Fin Uniformity and Sidewall Profile (Core of the Invention)

• Prior Art References:

  • US8310013B2 (Lin et al.): This patent, filed in August 2011, discusses problems associated with FinFET fabrication, specifically the inability of conventional methods to provide varied profiles, such as a square profile, of fin structure facets. It notes that "simply changing various process settings has proved incapable of significantly improving the ability to fabricate varied profiles." This directly highlights the problem of controlling fin profiles.
  • US20100048027A1 (International Business Machines Corporation): Titled "Smooth and vertical semiconductor fin structure," this publication suggests approaches for achieving desired fin sidewall characteristics.
  • General knowledge in the art: The "dense-isolation effect" or "micro-loading effect" were recognized challenges in semiconductor manufacturing leading to non-uniform etching and fin critical dimension (CD) variations.

• Motivation to Combine: A POSITA, facing the known challenges of poor CD uniformity and difficulty in achieving desired fin profiles in FinFETs (as highlighted by Lin et al. and industry knowledge), would be motivated to develop fabrication methods that offer better control over fin dimensions and sidewall shapes. The objective would be to improve device performance and yield, which are universal and common-sensical motivations in semiconductor manufacturing.

  The method described in US9117909 addresses these issues by:

  1. Initially forming first trenches and first protruding structures.
  2. Removing the first protruding structures in the second (isolation) region. This step is crucial for mitigating dense-isolation or micro-loading effects that would otherwise lead to wider fins in this region. The patent explicitly states this is done "to keep the CD uniformity of the fin structure 330."
  3. Deepening the remaining first trenches in a second etching step, which allows for better control of the fin's final shape. The patent notes that the lower portion can have tilted sidewalls due to a faster etching rate in the second step, while the upper portion retains vertical sidewalls, forming the actual fin structure. This two-step etching process (initial trenching, selective fin removal, then deepening) provides a more refined control over the fin's CD and profile compared to a single etching step that could result in tapered sidewalls.

  Therefore, a POSITA, motivated by the need for uniform and well-defined FinFET structures, would consider combining etching techniques known to produce smooth and vertical sidewalls (like those hinted at in US20100048027A1) with an understanding of how to counteract loading effects, potentially through selective removal or differential etching strategies. The explicit teaching in US9117909 to remove fins in certain regions to achieve uniformity directly addresses a known problem in the art.

Combination 2: Differentiated Trench Depths for Active and Isolation Regions

• Prior Art References:

  • US8853015B1 (United Microelectronics Corp.): This patent, a related parent application with the same priority date and assignee, is titled "Method of forming a FinFET structure." While not directly cited as prior art against US9117909 in the patent document itself, it represents related work by the same entity at the same time and could be considered relevant for understanding the knowledge of the inventors or the immediate prior art landscape.
  • US20140035066A1 (Tsai et al.): Titled "Non-Planar FET and Manufacturing Method Thereof," this publication, filed July 2012, further illustrates the ongoing development in FinFET manufacturing techniques.
  • General knowledge of STI (Shallow Trench Isolation) and deep trench isolation: The use of STI to isolate active regions in semiconductor devices was well-established. Different depths of trenches for isolation and active areas would be a known concept to a POSITA.

• Motivation to Combine: The concept of having different trench depths for isolation regions versus active regions is a fundamental aspect of semiconductor device fabrication, particularly for achieving effective electrical isolation and optimizing device performance. A POSITA would be motivated to integrate deeper trenches in isolation regions to ensure robust electrical isolation, especially as device dimensions shrink.

  Claim 1 of US9117909 specifies "a deep trench disposed in the substrate in the isolation region, wherein the deep trench is deeper than the shallow trenches." This differentiation is a logical engineering choice to enhance isolation, a common goal in device design. The teaching that "the insulation layer in the shallow trenches is level with that in the deep trench" further indicates a practical approach to planarization after trench filling, which is also a common objective in semiconductor processing. The "shoulder portion" of the deep trench could arise from specific etching profiles or subsequent processing steps, which a POSITA would be familiar with when creating trenches of varying depths.

Overall Obviousness Conclusion:

While US9117909 presents a specific combination of steps to achieve fin uniformity and controlled sidewall profiles, a POSITA, motivated by well-known challenges in FinFET manufacturing such as achieving critical dimension (CD) uniformity and desirable fin profiles, and the general need for effective isolation, would have found motivation to combine existing knowledge of multi-step etching, selective material removal, and differential trench depths. The patent itself highlights the "dense-isolation effect" and "micro-loading effect" as problems, and the solutions it proposes (selective fin removal and two-step etching for sidewall control) would be considered logical advancements by a POSITA seeking to overcome these recognized issues.

Specifically, the combination of a FinFET structure (known from various references like US8310013B2), techniques for achieving controlled etching profiles (as broadly discussed in the prior art for "smooth and vertical" structures), and the well-understood need for distinct isolation features (deep trenches for isolation, shallow trenches for active areas) with a planarized insulation layer, would likely render Claim 1 obvious. The specific method of removing fins in an intermediate step to ensure uniformity and then deepening the trenches to achieve the desired composite fin shape addresses known problems in a manner that a POSITA would likely contemplate when striving for improved FinFET device quality and uniformity.

It is important to note that merely asserting that references are similar or in the same field is insufficient for an obviousness finding; there must be an articulated reasoning with a rational underpinning for combining them. In this case, the problems addressed by US9117909 (CD uniformity, sidewall control, effective isolation in FinFETs) were prominent in the field, providing a strong motivation for a POSITA to combine known techniques to achieve the claimed structure.

Patent Term Adjustments (PTA) and Patent Term Extensions (PTE) for US9117909

The USPTO does not calculate expiration dates for patents but provides resources to help estimate them, including a patent term calculator. Patent Term Adjustment (PTA) can extend the term of a U.S. patent to compensate for certain delays by the USPTO during the prosecution of a utility or plant patent application. These delays include failing to: issue a first office action within 14 months of filing, respond to an applicant's reply within four months, act on an application within four months after a PTAB decision or federal court decision, or issue a patent within four months of payment of the issue fee. Additionally, PTA is granted if an application is pending for more than three years, excluding applicant-caused delays.

Patent Term Extension (PTE) is distinct from PTA and is available for patents on certain human drugs, food or color additives, medical devices, animal drugs, and veterinary biological products to restore time lost while awaiting premarket government approval from a regulatory agency.

For US Patent 9117909:

• Patent Term Adjustment (PTA): The Google Patents entry for US9117909B2 does not explicitly state any Patent Term Adjustment (PTA) days. To determine the precise PTA, one would typically need to examine the Issue Notification Letter for the patent, which includes the PTA calculation. Without this specific information, any PTA for US9117909 cannot be detailed.
• Patent Term Extension (PTE): Based on the subject matter of US9117909 (non-planar transistor, FinFET technology), it does not fall within the categories of patents eligible for PTE (e.g., human drugs, medical devices). Therefore, it is highly unlikely that US9117909 has received any PTE.

Continuation and Divisional Applications

• Continuation Applications: A continuation application allows an applicant to pursue additional patent claims while retaining the priority date of an earlier "parent" application. It must be filed before the parent application issues or is abandoned, and cannot introduce new subject matter.
• Divisional Applications: A divisional application arises when the USPTO issues a restriction requirement, determining that a single application contains two or more independent and distinct inventions. The applicant then pursues one invention in the parent and files one or more divisionals for the remaining inventions. Divisional applications are entitled to the parent's filing date.

For US9117909:

• Continuation Applications: The provided information indicates that US9117909B2 (Application No. US14/470,957) is a Divisional of application Ser. No. 13/863,393 filed Apr. 16, 2013 [cite: CROSS REFERENCE TO RELATED APPLICATIONS This application is a Divisional of application Ser. No. 13/863,393 filed Apr. 16, 2013, and included herein by reference.]. Therefore, US9117909B2 itself is not a continuation application, but a divisional. No continuation applications are explicitly listed as having been filed from US9117909B2 in the provided patent text.
• Divisional Applications: As stated in the "CROSS REFERENCE TO RELATED APPLICATIONS" section, US9117909 (Application No. US14/470,957) is a divisional application of application Ser. No. 13/863,393, which was filed on April 16, 2013. [cite: CROSS REFERENCE TO RELATED APPLICATIONS This application is a Divisional of application Ser. No. 13/863,393 filed Apr. 16, 2013, and included herein by reference.]

Related Family Members

The patent family for US9117909 includes the following:

• Parent Application: US 13/863,393, filed April 16, 2013, which issued as US8853015B1, titled "Method of forming a FinFET structure." [cite: CROSS REFERENCE TO RELATED APPLICATIONS This application is a Divisional of application Ser. No. 13/863,393 filed Apr. 16, 2013, and included herein by reference., US8853015B1 - Method of forming a FinFET structure]
• Other Published Applications: US20140367798A1, published December 18, 2014, is another version of the application leading to US9117909B2. [cite: Other versions US20140367798A1]

Projected Expiration Date

The term of a U.S. utility patent generally begins on the date the patent issues and ends twenty years from the date on which the earliest U.S. application was filed, from which benefit is claimed under 35 U.S.C. § 120, § 121, or § 365(c).

For US9117909:

• Earliest Priority Date: April 16, 2013 [cite: Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) 2013-04-16]
• Calculation: Twenty years from the earliest priority date of April 16, 2013, would be April 16, 2033.
• Anticipated Expiration: April 16, 2033. [cite: Anticipated expiration 2033-04-16]

This projected expiration date does not account for any potential Patent Term Adjustment (PTA) or Patent Term Extension (PTE), as specific PTA data is not provided, and PTE is not applicable to this patent's subject matter.