US 8712039

I'll search for the specific patent number and any litigation references before summarizing.

Let me check for the CAFC 2026 docket activity and the specific Texas case cited in the patent record.

Let me check specifically for Federal Circuit (CAFC) 2026 appellate dockets involving this patent or Malikie.

Summary of U.S. Patent No. 8,712,039

⚠️ Scope note on what I could verify: I used the full patent text (Google Patents/authoritative) plus open web searches of litigation databases (CourtListener, Unified Patents, PACER-derived aggregators). I did not have direct API access to USPTO Patent Center or to a dedicated CAFC docket system. Everything below is sourced as noted, and I flag every point of uncertainty rather than guessing.

Bibliographic Data

Uncertainty: The assignee field on the Google Patents page lists "Malikie Innovations Ltd"; the litigation documents confirm the chain of title Certicom → BlackBerry (Sept. 30, 2019) → Malikie (May 11, 2023). I did not independently verify the current recorded owner in USPTO's assignment database.

Abstract (as issued)

"An efficient implementation of SHA-512, and similarly SHA-384, on an ARM processor. The implementation maximizes reuse of the register values between iterations so as to minimize the need to load these values from memory. This is achieved by categorizing the iterations into even and odd ones such that the sequence of computation in the even iteration is reversed in the odd iteration and the register values at the end of one iteration are consumed at the beginning of the following one."

Plain-Language Overview

The patent addresses a practical problem: SHA-512 needs eight 64-bit state words (A–H) plus message-schedule words, but an ARMv5t-class processor has only 16 32-bit registers (minus the program counter and stack pointer, leaving 14 usable). The state doesn't fit in registers, so a naive implementation constantly shuttles values to and from the stack.

The inventors' approach: split the iterations into even and odd pairs and reverse the order of the arithmetic steps in the odd iteration relative to the even one. Because the last-computed values of one iteration are still sitting in registers, and the next iteration starts with the operations that need those same values, the even/odd pair reuses register contents instead of reloading from memory. The specification states this cuts the average number of A–H words loaded per iteration from eight to four — a one-half reduction, the exact figure recited in claim 1.

Secondary optimizations described: keeping a constant offset between the stack pointer and the w array location during the last 64 rounds; using a single register to hold the index j (which wraps mod 16) for both addressing and loop termination; assigning state-word register pairs R(d), R(d+1) with d even and ≠ 14 so ARM's LDRD/STRD doubleword instructions can be used; and using preload instructions plus instruction scheduling to hide memory latency.

Independent Claims (there are 3: claims 1, 11, 21)

Claim 1 — Method
A method for maximizing the number of registers holding useful values at the end of an iteration so they can be used in the next iteration. Three steps: (a) categorize and unroll the iterations of an "original secure hash algorithm" into even and odd iterations; (b) reverse the sequence of computations in the even iterations relative to the odd iterations — where the reversing results in the average number of words that must be loaded into registers per iteration being reduced by at least one-half versus the original algorithm; and (c) combine an even and an odd iteration to form one new loop iteration.

• Note: the "at least one-half" reduction is a quantitative result-based limitation with explicit support in the spec (8 loads → 4 loads), so it will likely be central to any validity/claim-construction fight.

Claim 11 — System
The apparatus counterpart of claim 1: a processing circuit configured to perform the same three operations — categorize/unroll into even and odd iterations, reverse the even-iteration computation sequence (with the same one-half load reduction), and combine an even and odd iteration into one loop iteration.

Claim 21 — Method
A narrower/alternative method claim that drops the quantitative "one-half" limitation and instead adds a specific structural feature: categorize and unroll into even/odd iterations; reverse (by a processing circuit) the computation sequence in the even iterations; combine an even and an odd iteration into one loop iteration; and, in the last 64 iterations of the secure hash algorithm, keep an offset constant between the location of the current 8 state words and the pointer to the current w word.

Dependent claims worth flagging: claim 2 (SHA-512 and/or SHA-384), claim 7 (constant-offset feature, same as claim 21's added element), claim 9 (16-iteration grouping governed by a w-index counter), claim 10 (register pairs R(d), R(d+1), d even ≠ 14, for doubleword instructions).

Litigation / Docket Findings

• Google Patents' litigation flag points to Texas Western District Court, case 7:25-cv-00567, corroborated by search results.
• Malikie Innovations Ltd. v. Foundry Digital LLC, W.D. Tex. No. 7:25-cv-00567-DC-DTG (filed Dec. 12, 2025; Judge David Counts, referred to Judge Derek T. Gilliland). Defendants include Foundry Digital LLC, Fortitude Mining LLC, Riot Platforms Inc., and Cipher Digital Inc. The docket shows active claim-construction and venue/discovery activity through mid-2026, plus a Sept. 1, 2026 joint motion to stay as to Cipher following settlement (CourtListener Dkt. 150). Per an Ex Parte complaint-analysis summary, this case asserts multiple patents (including '827, '197, '286, and '039) against Bitcoin mining ASICs/software.
• Related Malikie cases in the same W.D. Tex. campaign: Malikie v. Core Scientific, Inc., E.D. Tex. No. 2:25-cv-00519-JRG-RSP (an "Exhibit A" filed Dec. 3, 2025 in that case reproduces the '039 patent's front-page bibliographic data, confirming the patent is asserted there); and Malikie v. MARA Holdings, W.D. Tex. No. 7:25-cv-00222-DC-DTG. In the Foundry case, the parties agreed to adopt the claim constructions from the MARA case's March 12, 2026 claim-construction order (Dkt. 80) for certain terms.
• CAFC 2026 docket: I ran targeted searches for a Federal Circuit appeal involving 8712039 or Malikie and found no 2026 CAFC docket for this patent. Note that the Foundry-case briefing expressly preserves appeal rights on the adopted constructions, so a future appeal is plausible — but I cannot confirm any CAFC appeal exists as of today. Treat this as "not found," not "confirmed absent."

Additional uncertainty: The '039 patent was asserted against Bitcoin miners (SHA-256 ASIC context), even though the patent describes SHA-512/SHA-384 on ARM. How the plaintiffs map the ARM-register-reuse claims onto SHA-256 ASIC implementations is not something I could verify from the sources retrieved.

Bottom Line

US 8,712,039 is a Certicom-originated (now Malikie-owned) patent on even/odd iteration unrolling and computation-order reversal to halve register-load traffic when running SHA-512/SHA-384 on register-constrained ARM processors. It has three independent claims (method, system, method) and is currently being asserted in the W.D. Tex. Bitcoin-mining campaign (7:25-cv-00567 and companion suits). No Federal Circuit 2026 activity was located. If you need authoritative confirmation of current ownership, claim status, or docket completeness, the reliable sources would be USPTO Patent Center/Assignment Search and the court's PACER docket directly.

I'll search for litigation involving US patent 8712039. Let me start with several targeted searches.

Let me dig deeper into the specific cases and search for more.

I've found strong leads. Let me verify the MARA Holdings case and check for any other cases asserting the '039 patent.

Litigation Involving U.S. Patent No. 8,712,039

Patent identification (interpreted literally): U.S. Patent No. 8,712,039 B2, "Efficient Implementation of Hash Algorithm on a Processor," Application No. 13/440,264, filed April 5, 2012, issued April 29, 2014, priority date April 6, 2011. Inventors: Nevine Maurice Nassif Ebeid and Robert John Lambert. Original assignee Certicom Corp. → BlackBerry Limited (2019) → Malikie Innovations Limited (2023). The patent is asserted by the Malikie/Key Patent Innovations (KPI) NPE campaign against Bitcoin-mining and HPC operators, primarily on the theory that SHA-256/SHA-2 hash implementations in mining ASICs and related hardware/software practice the claimed even/odd iteration unrolling technique.

The Google Patents record itself flags a litigation link for this patent family on the Western District of Texas docket 7:25-cv-00567 (the Foundry Digital case below).

I identified the following matters. Note on dates: the docket data retrieved contains events dated well into 2026 (e.g., Markman and settlement activity in August–September 2026), which is later than the "today's date" stated in your prompt. I am reporting the docket events exactly as retrieved rather than reconciling that discrepancy.

1. Malikie Innovations Ltd. et al. v. Core Scientific, Inc.

• Plaintiff(s): Malikie Innovations Ltd. and Key Patent Innovations Ltd.
• Defendant(s): Core Scientific, Inc.; CoreWeave, Inc. was later added (by Plaintiff's Second Amended Complaint) and also appears as a third-party defendant (Core Scientific filed a third-party complaint against CoreWeave).
• Jurisdiction/Court: U.S. District Court for the Eastern District of Texas (Marshall Division); Judge J. Rodney Gilstrap, referred to Magistrate Judge Roy S. Payne. Case No. 2:25-cv-00519-JRG-RSP.
• Filing date: May 12, 2025.
• '039 patent involvement: The '039 patent was added by amendment. Per the Court's order on Document #53/69, Plaintiffs were granted leave to amend the complaint and infringement contentions "to assert U.S. Patent No. 8,712,039 against Defendant Core Scientific, Inc." (order signed February 19, 2026; leave granted on the earlier motion filed November 17, 2025). The Second Amended Complaint lists Exhibit 6 as the "'039 Patent." CoreWeave's motion to dismiss expressly states the '039 patent is "the fourth patent asserted against CoreWeave" and that CoreWeave has pled invalidity of the '039 patent.
• Outcome/current status: Pending. There is an outstanding motion activity on the '039 patent's companion patents (a § 101 motion to dismiss directed at the '960, '062, and '286 patents — expressly not the '039 patent), a venue-transfer motion, and amended infringement/invalidity contentions. No final judgment on the '039 patent.
• Sources:
  • https://www.courtlistener.com/docket/70244989/malikie-innovations-ltd-v-core-scientific-inc/
  • https://www.courtlistener.com/docket/70244989/53/malikie-innovations-ltd-v-core-scientific-inc/
  • https://www.courtlistener.com/docket/70244989/115/malikie-innovations-ltd-v-core-scientific-inc/
  • https://dockets.justia.com/docket/texas/txedce/2:2025cv00519/[237820](/patent/237820)
  • https://ai-lab.exparte.com/case/dct/txed/2:25-cv-00519/doc/analysis/52

2. Malikie Innovations Ltd. et al. v. Foundry Digital LLC et al.

• Plaintiff(s): Malikie Innovations Ltd. and Key Patent Innovations Ltd.
• Defendant(s): Foundry Digital LLC; Fortitude Mining, LLC; Riot Platforms, Inc.; and Cipher Digital Inc. f/k/a Cipher Mining Inc. (Shenzhen MicroBT Electronics Technology Co., Ltd. appears as a party in a related filing/third-party context).
• Jurisdiction/Court: U.S. District Court for the Western District of Texas, Midland-Odessa Division; Judge David Counts, referred to Magistrate Judge Derek T. Gilliland. Case No. 7:25-cv-00567-DC-DTG.
• Filing date: December 12, 2025.
• '039 patent involvement: The complaint expressly identifies U.S. Patent No. 8,712,039 (the "'039 Patent") as one of the "Asserted Patents." Riot Platforms' counterclaims (answered by Malikie) confirm the Asserted Patents are U.S. Patent Nos. 8,788,827; 8,806,197; 8,532,286; and 8,712,039.
• Outcome/current status: Pending. A Markman (claim construction) hearing was held September 2, 2026, with a Claim Construction Order entered September 3, 2026. Sealed Reports & Recommendations on motions to dismiss (venue) were issued around August 14–17, 2026; Riot's motion for intra-district transfer was denied (sealed order, August 12, 2026). Defendant Cipher Digital Inc. settled — a "Joint Motion to Stay and Notice of Settlement" as to Cipher was filed September 1, 2026, with dismissal expected. The case otherwise remains open against Foundry, Fortitude, and Riot.
• Sources:
  • https://www.courtlistener.com/docket/72028096/malikie-innovations-ltd-v-foundry-digital-llc/
  • https://www.courtlistener.com/docket/72028096/1/malikie-innovations-ltd-v-foundry-digital-llc/authorities/
  • https://www.courtlistener.com/docket/72028096/150/malikie-innovations-ltd-v-foundry-digital-llc/
  • https://cdn.pacermonitor.com/public/case/61786607/Malikie_Innovations_Ltd_et_al_v_Foundry_Digital_LLC_et_al
  • https://ai-lab.exparte.com/case/dct/txwd/7:25-cv-00567/doc/analysis/1
  • https://storage.courtlistener.com/recap/gov.uscourts.txwd.1172879815/gov.uscourts.txwd.1172879815.59.0.pdf

3. Malikie Innovations Ltd. v. MARA Holdings, Inc. — possible related assertion (UNCONFIRMED as to the '039 patent)

• Case No.: 7:25-cv-00222, U.S. District Court for the Western District of Texas.
• Context: A court filing in the Foundry case (Document #99, filed June 30, 2026) references a "Mara Case," Malikie Innovations Ltd. v. Mara Holdings, Inc., No. 7:25-cv-222, W.D. Tex., as the source of stipulated claim-construction briefing/order (constructions for the '286 and '062 patents). A Mondaq industry note characterizes the Core Scientific and MARA Holdings filings as "two in new Bitcoin litigation" brought in the same campaign.
• Caveat: I could not confirm from the retrieved sources that U.S. 8,712,039 is specifically asserted against MARA Holdings. The claim-construction material carried over from the MARA case concerns the '286 and '062 patents, not the '039 patent. Treat MARA as a related campaign case pending verification, not a confirmed '039 assertion.
• Sources:
  • https://www.courtlistener.com/docket/72028096/99/malikie-innovations-ltd-v-foundry-digital-llc/
  • https://webiis08.mondaq.com/unitedstates/patent/[1659406](/patent/1659406)/kpi-and-malikie-sue-three-more-in-its-existing-campaign-two-in-new-bitcoin-litigation

Limitations and confidence

• Confirmed '039 assertions: The two matters where I have direct, specific support that U.S. 8,712,039 is asserted are (1) Core Scientific (2:25-cv-00519, E.D. Tex.) and (2) Foundry Digital (7:25-cv-00567, W.D. Tex.).
• No final outcomes exist yet. Both confirmed cases are in mid-litigation (claim construction / dispositive-motion stages); the only resolution so far is the Cipher Digital settlement in the Foundry case (as to Cipher only).
• I did not find any decision by the Court of Appeals for the Federal Circuit, any IPR/PGR (post-grant) proceeding at the PTAB, or any ex parte reexamination specifically directed at the '039 patent. Note that Unified Patents has challenged other Malikie patents in this campaign (e.g., U.S. 7,372,960; U.S. 12,395,899), but I found no such challenge to the '039 patent.
• Regarding the other Malikie suits (e.g., v. Bumble, v. SAP America, v. Toyota, v. American Honda): these belong to Malikie's separate networking/Wi-Fi/communications campaign and I found no basis to assert U.S. 8,712,039 in those cases — they should not be reported as '039 matters.
• Because I was limited in the number of searches, a comprehensive PACER/RECAP sweep for every Malikie docket was not possible. If certainty is required, I recommend a direct PACER docket search for the string "8,712,039" across W.D. Tex., E.D. Tex., and N.D. Tex., plus a PTAB proceeding search on the patent number.

I'll start by verifying the structured "no PTAB activity" signal against live sources, then check related litigation-adjacent proceedings.

The first hit references a different '039 patent (Mobile Data Technologies, 30+ claims) — I must not conflate them. Let me run targeted searches specifically for US 8,712,039.

Proceedings overview

Total AIA trial proceedings on file for US 8,712,039: ZERO. The structured "PTAB proceedings on file" block — the canonical USPTO Open Data Portal list — returns no IPR, PGR, or CBM for this patent, and my independent web searches surfaced no PTAB trial numbers naming 8,712,039 or its application number 13/440,264. There is therefore no claims-invalidated, claims-sustained, settled, or institution-denied bucket to report: all 21 claims (1–21) remain unadjudicated and untested before the Board.

The bottom-line defensive posture this gives a defendant is not "the patent has survived IPRs and is hardened," and not "the claims are canceled." It is the third posture: the patent is a virgin at the PTAB. Every claim the plaintiff asserts is live, and no petitioner has yet burned prior art or created § 315(e)(2) estoppel on this record. That cuts both ways — it means no helpful FWD exists to lean on, but it also means the full universe of § 102/§ 103 patents-and-printed-publications art is still available to the first petitioner (subject to the § 315(b) clock, discussed below).

No proceeding-level detail to report — and an important de-confusion note

Because the list is empty, there are no {PROCEEDING_NUMBER} entries to populate. What my searches did surface were several look-alike "–039" proceedings that are NOT this patent. I flag them because they are easy to conflate and a defendant's outside counsel may be misled by a bare "039" search hit:

(Sources: PTAB petition document, IPR2024-00248 record; Azurity IPR2025-00427 papers; Hoang Declaration, Malikie v. Nintendo, Dkt. 60.)

Note also that the Google Patents litigation flag on 8712039 points to Malikie v. Foundry, and the docket confirms '039 is asserted in the W.D. Tex. Bitcoin-mining campaign with a parallel declaratory-judgment counterclaim of invalidity — but a DJ counterclaim is district-court litigation, not a PTAB proceeding. It does not populate this list.

Strategic summary

Claim status: all 21 claims UNTESTED. Nothing has been canceled, disclaimed, or held unpatentable at the Board. Independent claims 1, 11, and 21 and all dependents (including the quantitative "reduced by at least one-half" limitation in claims 1/11 and the constant-offset limitation in claims 7/17/21) stand exactly as issued on 2014-04-29. I found no certificate of correction, no disclaimer, and no reexamination certificate altering the claim set. (Caveat: I did not have direct API access to USPTO Patent Center, so a late-2026 reexam filing — which would be handled by the CRU, not the PTAB, and thus would not appear in the ODP AIA-trial list — cannot be affirmatively ruled out.)

Estoppel landscape: no estoppel exists. Because no IPR/PGR has been instituted against 8,712,039, there is no § 315(e)(2) estoppel binding anyone. Any defendant now being asserted against — Foundry Digital, Fortitude Mining, Riot Platforms, Cipher Digital (W.D. Tex. 7:25-cv-00567), Core Scientific (E.D. Tex. 2:25-cv-00519), MARA (W.D. Tex. 7:25-cv-00222) — retains the full prior-art arsenal available in an IPR: patents and printed publications under § 102 and § 103, 35 U.S.C. § 311(b). Grounds that are not available in an IPR regardless of estoppel: § 101 eligibility, § 112 written description/enablement, public-use/on-sale art, and system prior art. Those must be fought in district court — and the docket shows the defendants already are: Cipher's § 101 motion was denied without prejudice at the pleadings stage on 2026-07-07 (Dkt. 105, adopting the 2026-06-18 R&R, Dkt. 86), preserving eligibility for summary judgment. (R&R Dkt. 86; Order Dkt. 105.)

Pattern signals — and why the absence of IPRs may be about to end. The patent owner is a sophisticated serial enforcer: Malikie (with parent Key Patent Innovations) is running multi-defendant campaigns across W.D. Tex., E.D. Tex., and W.D. Wash., and it litigates PTAB challenges hard rather than settling them (see its Nintendo opposition to a stay pending IPR/reexam, and its separate IPR defense of U.S. 11,119,756 in IPR2026-00120, Vivint/NRG v. Malikie, where Reichman Jorgensen filed PO mandatory notices on 2025-11-24). But for this patent, no petitioner has yet pulled the trigger. There is no defensive aggregator (e.g., Unified Patents) in the chain that I could identify, and no serial petitioner. That is unusual for a patent this heavily asserted — which suggests either (a) defendants are pursuing invalidity in the DJ/§ 101 track instead, or (b) the § 315(b) window is still open.

The clock is the actionable fact. § 315(b) bars an IPR petition filed more than one year after service of a complaint alleging infringement. The Foundry complaint was filed 2025-12-12; service dates for the Foundry/Fortitude/Riot/Cipher defendants appear to fall in December 2025, which would put the IPR bar date in approximately December 2026; Core Scientific's suit (filed in E.D. Tex. in 2025) would carry a bar date in late 2026 as well. I could not confirm exact service dates from the sources retrieved — that must be verified from the dockets before relying on it. But the practical implication is stark: if a defendant in this campaign wants PTAB review of 8,712,039, the petition is due within roughly the next two to three months.

Recommended next steps

1. Treat "no PTAB activity" as the finding, but verify it at the source. The ODP list is the canonical structured feed and it is empty, but ODP ingest can lag new filings by weeks. Before finalizing any opinion, run the patent number through PTAB E2E (https://ptacts.uspto.gov/), the USPTO Patent Center "Patent Trial Proceedings" tab for 8,712,039, and the PTAB's public "Patent Trial Appeal Board Proceedings" search. Also check the CRU for any ex parte reexamination request under 35 U.S.C. § 302, which would not appear in the AIA-trial list but can still nix claims (an ex parte reexam route matters here because it is not subject to the § 315(b) bar and is not limited to patents/printed publications).
2. If you are a defendant in the Bitcoin-mining campaign (Foundry/Fortitude/Riot/Cipher; Core Scientific; MARA): calendar the § 315(b) bar date now from the actual date each of you was served with the complaint. If you intend to petition, the art-search, expert-declaration, and petition drafting must start immediately. Because no estoppel yet exists, you have maximum freedom of ground selection — that advantage disappears the moment a first petitioner files and the Board consolidates or a Fintiv/§ 325(d) fight enters the picture.
3. Note the fintiv/§ 325(d) risk created by the parallel litigation's progress. Claim construction in the Foundry case is well advanced (reply claim-construction brief filed 2026-08-18, Dkt. 141; venue and § 101 motions briefed). Under the USPTO's post-Fintiv "Interim Processes for PTAB Workload Management" guidance (cited in the Malikie v. Nintendo papers), a defendant who waits risks discretionary denial on investment/overlap grounds — and note that parallel defendants who stipulate under Sotera (as Meta did with a "Sotera-plus" stipulation in the unrelated Mobile Data Technologies matter) materially improve their institution odds.
4. Frame the merits for whoever eventually petitions. The validity fight on this patent will center on independent claim 1's result-based limitation — "an average number of words that need to be loaded into the registers per iteration being reduced by at least one-half compared to the original secure hash algorithm." That is a quantitative outcome limitation with only § 112/spec support at 4:x ("eight (sixteen 32-bit loads) to four (eight 32-bit loads)"). Any IPR must show the prior art teaches or renders obvious achieving that reduction, not merely even/odd unrolling generally. Expect the patent owner to argue the limitation is not disclosed by art that does not perform the reversal-based register reuse.
5. If you need a citable, non-fabricated disposition, there isn't one. There is no FWD to quote on any claim of 8,712,039, and no Federal Circuit appeal — consistent with the earlier analysis in this record, which likewise found no 2026 CAFC docket for this patent. Do not cite the Mobile Data Technologies IPR2024-00248 FWD (or its 2025-03-07 settlement) as if it addressed 8,712,039; it did not.

Confidence and limits: High confidence that no IPR/PGR/CBM exists as reflected in the ODP feed and in open web sources; moderate confidence it reflects the complete picture, because I could not directly query PTAB E2E or Patent Center in this session. The two items most worth a five-minute primary-source check are (a) PTAB E2E for any 2026 filing, and (b) CRU/reexam status for 8,712,039.

I'll research the assignment records for US 8,712,039. Let me run targeted searches.

I found the recorded assignment data in a court exhibit. Let me pull more detail on the correspondents of record.

Assignment Record — U.S. Patent No. 8,712,039

Data-source caveat (read first): I could not query the USPTO Assignment Center UI directly. The assignment data below is reconstructed from (a) the reel/frame entries in the Google Patents "Legal Events" and "Reassignment" tables (authoritative text supplied in this analysis), and (b) a court exhibit that reproduces the USPTO assignment abstract verbatim — Exhibit A, Core Scientific case (E.D. Tex. 2:25-cv-00519, Dkt. 56-2, filed 12/03/2025): https://www.courtlistener.com/docket/70244989/56/2/malikie-innovations-ltd-v-core-scientific-inc/. The exhibit's correspondent block is OCR-garbled, so I attribute correspondent fields with explicit hedging rather than asserting them. I did not fabricate any reel/frame; every number below matches either Google Patents or the exhibit.

Inventors

• Both inventors executed the inventor→assignee assignment on the same day, 2012-05-29, i.e., they were treated as a unit at filing. This is the normal Certicom employee-assignment pattern, not a departure signal.
• Employer nuance: By the 2011–2012 filing window, Certicom was already a Research In Motion / BlackBerry subsidiary (see below), which is why the recording correspondent on the very first assignment is coded to RIM ("Hamilton & Terrile LLP-RIM"). So the effective employer of record at filing was Certicom Corp., a BlackBerry (RIM) subsidiary.
• Unusual-pattern check — inventorship: I found no evidence that either inventor departed within 12 months of filing, and no evidence of a pre-filing fire-sale/abandonment pattern. I could not independently verify either inventor's tenure history beyond the assignment record itself; treat "remained with Certicom/BlackBerry" as not contradicted, not as affirmatively confirmed.

Original assignee

Certicom Corp. — named on the issued patent (front page lists Original Assignee: Certicom Corp.).

• Primary line of business: Cryptographic security — elliptic-curve cryptography (ECC), public-key and hash-algorithm implementations, licensed cryptographic toolkits/firmware and security software (Certicom was the leading commercial ECC house; its "Security Builder" toolkit line and ECC licensing were its core business).
• Did it ship a product embodying the claims? Unclear / plausible-but-unverified. The patent claims a software implementation technique (even/odd iteration unrolling of SHA-512/SHA-384 on ARM), which would be embodied in a cryptographic library rather than a standalone product. Certicom's crypto libraries and BlackBerry device firmware did implement SHA-2 hashing, so embodiment is plausible — but I could not verify from retrieved sources that a specific shipping Certicom/BlackBerry product practiced the claimed method. Do not treat as confirmed.
• Current status: Operating (as a subsidiary). Certicom Corp. was acquired by Research In Motion (RIM) — now BlackBerry Limited — the acquisition completed in 2009. Certicom has not been dissolved; it remains a BlackBerry-affiliated entity. (I am not asserting a specific acquisition price — sources conflict and I could not verify one.) Note: the patent left the Certicom/BlackBerry family in 2023 even though the Certicom corporate entity persists.

Assignment timeline

All four recordings are confirmed on both Google Patents and the court exhibit. Reel/frame numbers are given in the Google Patents format.

• 2012-05-29 (executed) / recorded 2012-05-31 — Reel 028294/0247

  • Conveyance: Assignment
  • Assignor: Ebeid, Nevine Maurice Nassif; Lambert, Robert John
  • Assignee: Certicom Corp., 2200 University Avenue East, Waterloo, Ontario, Canada N2K 0A7
  • Correspondent: Hamilton & Terrile, LLP – RIM, P.O. Box 203518, Austin, TX 78720. (Appears in the exhibit's correspondent block with the "-RIM" docketing tag.) This is the only appearance of Hamilton & Terrile in this chain; it is RIM/BlackBerry's outside patent counsel, so recurrence across this chain is not established.
  • Context: Initial inventor-to-company assignment at filing — standard employment/obligation assignment, not a sale.

• 2019-09-30 (executed) / recorded 2019-10-02 — Reel 050610/0937

  • Conveyance: Assignment (of Assignor's Interest)
  • Assignor: Certicom Corp.
  • Assignee: BlackBerry Limited, 2200 University Avenue East, Waterloo, Ontario, Canada N2K 0A7
  • Correspondent: Not cleanly recoverable from the OCR exhibit; Google Patents records the reassignment but not a correspondent. Flagged as unresolved.
  • Context: Internal corporate reorganization — consolidating a subsidiary's patent portfolio up to the parent (Certicom → BlackBerry), same Waterloo address.

• 2023-05-11 (executed) / recorded 2023-06-16 — Reel 064104/0103

  • Conveyance: Assignment (of Assignor's Interest)
  • Assignor: BlackBerry Limited
  • Assignee: Malikie Innovations Limited, The Glasshouses GH2, 92 Georges Street Lower, Dun Laoghaire, Dublin, Ireland A96 VR66
  • Correspondent: Exhibit's correspondent block shows Richard Botos, 430 Mountain Ave., Suite 401, New Providence, NJ 07090, alongside docketing labels "MALIK 9.0-003" and "BLACKBERRY LIMITED-KRISTA." I attribute the Botos entry to the Malikie recordings (Assignments 3/4) with moderate confidence, not certainty, because the OCR interleaves the fields. (The New Providence address is a New Jersey IP-office location; I could not verify the exact firm name from retrieved sources — verify independently before relying on it.) This is a different correspondent (and different state) from the Hamilton & Terrile entry — a correspondent change coinciding with the transfer to the monetization entity.
  • Context: Transfer-to-asserter. Sale of "substantially all" of BlackBerry's non-core patents to Malikie, a then-newly-formed unit of Irish patent-monetization firm Key Patent Innovations Ltd. (KPI). Deal terms per press: ~$170M cash at May 11, 2023 closing, ~$30M more by three years out, plus ongoing royalties to BlackBerry on profits — i.e., the seller retains a revenue share.

• 2023-05-11 (executed) / recorded 2023-06-19 — Reel 064271/0199

  • Conveyance: Nunc Pro Tunc Assignment
  • Assignor: BlackBerry Limited
  • Assignee: Malikie Innovations Limited (same Dublin address)
  • Correspondent: Same block as above (Botos / "MALIK 9.0-003").
  • Context: Correction/cleanup recording — a second, retroactive-dated recording of the same May 11, 2023 transfer. Not a separate economic transfer; it exists to make the assignment effective as of the intended date (a common curable defect when the bulk-reel assignment missed this asset). Flag: duplicate recording of a single transaction, not a cascade.

Cross-check / contradiction note: Google Patents dates the two Malikie recordings to 2023-06-16 and 2023-06-19; the court exhibit shows the same sequence (Assignment 3 then Assignment 4). No contradiction. One exhibit OCR shows the Certicom→BlackBerry reel as "80610/0937"; Google Patents' legal-events table gives 050610/0937, which I treat as authoritative.

Timeline diagram

timeline
    title Ownership of US 8712039
    2011 : Provisional application filed
    2012 : Application filed by Certicom
         : Inventors assign to Certicom
         : Pre-grant publication
    2014 : Patent granted as US 8712039
    2019 : Certicom assigns to BlackBerry
    2023 : BlackBerry assigns to Malikie
         : Nunc pro tunc cleanup recording
    2025 : First suits asserting the patent

NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT.
Reel 064104/0103 and 064271/0199 (executed 2023-05-11; recorded 2023-06-16/19) move the patent from an operating company (BlackBerry Limited) to Malikie Innovations Limited, described in contemporaneous press as a newly formed unit of patent-monetization firm Key Patent Innovations Ltd. Malikie has no products in commerce and exists to license/assert — the classic transfer-to-a-licensing-only entity. The Dublin "The Glasshouses GH2" address is a serviced-office/mailing address rather than a manufacturing site. (Naming alone is not the finding; the finding is the operating-company→monetization-unit transfer plus no-product, licensing-only status.)

2. Known asserter in the chain — PRESENT (with caveat).
The current assignee chain terminates at Malikie Innovations Limited / Key Patent Innovations Ltd., an entity tracked by RPX and Unified Patents as a high-volume patent plaintiff (its W.D./E.D. Tex. Bitcoin campaign asserts '039 alongside U.S. 8,788,827, 8,806,197, 8,532,286, etc.). Caveat: Malikie/KPI is a newer-generation NPE, not one of the legacy names on the classic list (Acacia, Marathon, IV, Wi-LAN, Conversant, Pendrell, Round Rock, etc.). Signal is present on conduct/profiling, not on matching an old list.

3. Repeat correspondent across the chain — WEAK / UNCLEAR.
Correspondents identified: Hamilton & Terrile, LLP – RIM (reel 028294/0247) and Richard Botos, New Providence, NJ (attributed to reels 064104/0103 and 064271/0199, with OCR-attribution uncertainty). The same correspondent (Botos) appears on both Malikie recordings, but those are two recordings of the same transaction, so this is not independent recurrence. There is no single attorney recurring across the different links (Certicom link vs. Malikie link) — they used different counsel. Marked unclear, pending direct Assignment Center confirmation of who signed each recording. The one thing worth flagging positively is the mid-chain correspondent change (Hamilton & Terrile → New Jersey IP office) that tracks the 2023 transfer-to-monetizer.

4. Cascading transfers — NOT PRESENT.
Only four recordings over 11 years, and two of them are the same 2023 transaction. No rapid chain of unrelated LLCs in <24 months. The only back-to-back pair (064104/0103 → 064271/0199) is a nunc-pro-tunc correction, not an economic cascade.

5. Pre-litigation transfer — NOT PRESENT (as to a 6-month window).
The transfer-to-asserter executed 2023-05-11; the earliest suit naming the '039 patent was filed 2025-05-12 (Core Scientific, E.D. Tex. 2:25-cv-00519; '039 added by later amendment), with the Foundry case filed 2025-12-12. That is ~24 months, outside the 6-month pre-litigation window. (The acquisition was admittedly made for monetization, so it is "pre-litigation" in the broad campaign sense — but the standard 6-month structural tell is absent.)

6. Bankruptcy fire-sale — NOT PRESENT.
Certicom/BlackBerry did not sell this patent in a bankruptcy. BlackBerry sold non-core patents in a negotiated portfolio transaction after its smartphone exit; the BlackBerry/Catapult IP Innovations deal collapsed for financing reasons and BlackBerry then sold to Malikie — a distressed-adjacent but not a Chapter 7/11 sale. (Separate, unrelated cloud on title: Catapult IP Innovations, Inc. v. Malikie Innovations Ltd., E.D. Va. 1:23-cv-00724, sought to unwind the BlackBerry→Malikie sale; Catapult voluntarily dismissed in July 2023, so title to this asset via Malikie was not disturbed.)

7. Privateering — PRESENT.
This is the strongest structural signal. An operating company (BlackBerry) sold this patent (with ~32,000 others) to an NPE (Malikie/KPI) that then asserts it, while BlackBerry retained a profit-participation royalty. Reported terms: ~$170M at closing + ~$30M later + annual cash royalties to BlackBerry on profits generated by the patents (press: Reuters/Yahoo Finance, The Globe and Mail, RPX, 2023-03-21/22 and RPX 2023-07-15). A seller that keeps a revenue share from the buyer's assertion profits is the textbook privateering/monetization arrangement — the operating company monetizes its portfolio off-balance-sheet through an NPE.

8. Defensive aggregator — NOT PRESENT.
The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. It terminates at an asserting entity (Malikie).

Verdict

NPE — high confidence.

Two or more strong signals are present and dated: (i) a transfer-to-asserter / shell-monetization move at reel 064104/0103 (and duplicate nunc-pro-tunc reel 064271/0199) executed 2023-05-11, shifting the patent from operating company BlackBerry to the no-product, licensing-only Malikie Innovations Limited (a newly formed unit of NPE Key Patent Innovations Ltd.); and (ii) a privateering arrangement in which the seller BlackBerry retained ongoing royalties on assertion profits (~$170M + ~$30M + royalty participation). Malikie then asserted the '039 patent in its Bitcoin-mining campaign (first '039 suit: Core Scientific, 2025-05-12). The earlier links (reel 028294/0247, standard inventor assignment; reel 050610/0937, Certicom→BlackBerry internal reorg) are ordinary and non-troll in character — the NPE character is entirely a function of the 2023 transaction.

Verification links: USPTO Assignment Center — https://assignmentcenter.uspto.gov/ ; legacy index — https://assignment.uspto.gov/patent/index.html (search by patent number 8712039). Reel/frame to confirm: 028294/0247, 050610/0937, 064104/0103, 064271/0199.

Open items I could not close: (a) exact correspondent of record for reel 050610/0937; (b) positive attribution of the "Richard Botos / New Providence NJ" and the unexplained "St Helier, JE1 1BL, Jersey" address entries in the exhibit to specific reels; (c) whether the Botos office is the recurring recording counsel for the broader Malikie/KPI portfolio (if it is, that would upgrade signal #3 from unclear to present — worth a targeted check across other Malikie reels).

I'll verify the patent and research each cited reference. Let me start with parallel searches.

Let me research the remaining cited references.

I hit the search-step limit partway through, so I have detailed, source-verified content for the five most technically relevant references and title/bibliographic data (from the authoritative patent record itself) for the rest. Below I separate the two, and I explicitly flag where I could not verify reference content.

Prior Art Analysis — U.S. Patent No. 8,712,039 B2

Patent under analysis: U.S. 8,712,039 B2, "Efficient implementation of hash algorithm on a processor," App. No. 13/440,264, filed Apr. 5, 2012, priority Apr. 6, 2011 (Prov. 61/472,422), issued Apr. 29, 2014. Inventors Ebeid & Lambert; original assignee Certicom Corp.

Source confirmation: The Google Patents record (https://patents.google.com/patent/[US8712039](/patent/US8712039)/en) and the Justia counterpart (https://patents.justia.com/patent/8712039) both reproduce the identical claim set (claims 1–21) and the identical "Patent Citations (13)" / "Non-Patent Citations (5)" lists analyzed below. I did not retrieve this directly from USPTO Patent Center; the citation list I rely on is the one printed in the authoritative full patent text supplied to me, which matches the two public mirrors.

Scope note on what "§ 102 anticipation" means here: Anticipation under 35 U.S.C. § 102 requires a single reference to disclose every limitation of a claim, arranged as claimed. The five most relevant references below are hash-implementation references, but on the verified text they are hardware (ASIC/FPGA) or ISA-instruction approaches, not the register-reuse-by-reversal technique claimed. My honest assessment, stated up front and defended below: none of the 13 cited references is a clean § 102 anticipatory reference against independent claims 1, 11, or 21. They are best characterized as § 103 obviousness/background art. I identify for each reference the claim(s) it could touch if combined, and I flag the two references whose dates disqualify them as prior art altogether.

A. The five most technically relevant references (content verified)

1. US 7,299,355 B2 — "Fast SHA1 implementation" (Broadcom Corp.)

• Full citation: U.S. Patent No. 7,299,355 B2, Zheng Qi, "Fast SHA1 implementation," assigned to Broadcom Corporation. App. No. 10/042,019, filed Jan. 8, 2002; prior publication US 2002/0184498 A1 (Dec. 5, 2002); patent issued Nov. 20, 2007. Priority Jan. 12, 2001. (Google Patents: https://patents.google.com/patent/US7299355)
• Marked "cited by examiner" in the '039 record.
• Brief description (verified): A hardware architecture for an authentication engine that speeds up SHA-1/HMAC multi-round processing, particularly for short IPSec packets. The core is a "combined adder tree" whose critical path uses a single 32-bit carry look-ahead adder (CLA); additions are performed in one clock cycle by rearranging the order of the CLA and circular-shift operations. It operates on the SHA-1/MD5 family (32-bit words), not SHA-512.
• § 102 relevance: Potentially touches claim 1's general notion of restructuring the order of operations ("rearranging the order of the CLA and circular shift operations") to improve efficiency. However, it does not disclose (i) SHA-512/SHA-384, (ii) categorizing/unrolling iterations into even and odd iterations, (iii) reversing the computation sequence in even vs. odd iterations, or (iv) the "average words loaded reduced by at least one-half" limitation. No anticipation of claims 1, 11, or 21; at most § 103 material against the generic "reorder operations" concept, and it is cumulative with the other SHA-hardware art.

2. US 2004/0260740 A1 — "System and method of efficiently implementing secure hash algorithm (SHA-1) in digital hardware…" (Yen-Fu Liu)

• Full citation: U.S. Pub. No. 2004/0260740 A1 (Yen-Fu Liu), pub. Dec. 23, 2004; App. No. 10/704,678 (filed Nov. 12, 2003); priority Jun. 19, 2003. Issued as U.S. 8,045,706 B2 (Oct. 25, 2011). (Google Patents: https://patents.google.com/patent/US20040260740)
• Brief description (verified): A digital-hardware SHA-1 engine completing SHA-1 in exactly 81 clocks. Uses two sets of five 32-bit synchronous registers (SHA-1 registers + message-digest registers), an asynchronous computation circuit, and a quad-output 16×32-bit circular-queue memory that supplies W(t−3), W(t−8), W(t−14), W(t−16) simultaneously. Explicitly premised on the problem that software SHA-1 is slow because "large amounts of software code … generate and reuse working data."
• § 102 relevance: Relevant background for claims 1 and 9 (message-schedule w-word management, 16-word circular buffer, using a counter to select parameters). But it is a SHA-1 hardware design with a register/memory architecture that is the opposite of the '039 approach (which keeps SHA-512 state in general-purpose ARM registers and minimizes loads). It does not disclose even/odd unrolling, reversal of computation order, or the one-half load reduction. No anticipation.

3. US 2010/0086127 A1 — "Efficient implementation of arithmetical secure hash techniques" (Mikhail Grinchuk)

• Full citation: U.S. Pub. No. 2010/0086127 A1 (Mikhail Grinchuk), pub. Apr. 8, 2010; priority Oct. 7, 2008. Issued as U.S. 8,160,242 B2 (Apr. 17, 2012). (Google Patents: https://patents.google.com/patent/US20100086127)
• Brief description (verified): A hardware implementation ("diagonal cut" technique) for the SHA-2 family including SHA-512 and SHA-384, plus SHA-1/MD5. It reduces scheme depth/area, eliminates storage of round constants, and uses a W-generation module. Explicitly states SHA-512 is a "variant of SHA-256 which operates with 64-bit words and performs 80 cycle rounds."
• § 102 relevance: The most on-point reference for subject matter — it expressly addresses efficient SHA-512 implementation and reduction of cost/area. It is nonetheless a logic-circuit optimization (diagonal cut, adder-tree/logic-cell reduction), not a processor-register-allocation / load-minimization technique. It does not disclose categorizing iterations into even/odd, reversing computation order between them, or reducing register loads by half. Potentially relevant as § 103 art against claim 1 if combined with a processor-register-teaching reference, but not anticipatory, and it does not touch the register/address claims (7–10, 21).

4. US 2010/0250966 A1 — "Processor and method for implementing instruction support for hash algorithms" (Olson et al.)

• Full citation: U.S. Pub. No. 2010/0250966 A1 (Christopher H. Olson, Jeffrey S. Brooks, Robert T. Golla), pub. Sep. 30, 2010; App. No. 12/415,403, filed Mar. 31, 2009. Issued as U.S. 8,832,464 B2 (Sept. 9, 2014), assigned to Oracle America, Inc. (Google Patents: https://patents.google.com/patent/US20100250966A1; patent PDF: https://patentimages.storage.googleapis.com/77/90/ea/f9260cab484354/[US8832464](/patent/US8832464).pdf)
• Marked "cited by examiner" in the '039 record.
• Brief description (verified): A processor with ISA-level hash instructions executable by a cryptographic unit. On a given hash instruction, the unit "retrieve[s] a set of input data blocks from a predetermined set of architectural registers of the processor, and generate[s] a hash value … according to a hash algorithm." The FGU logic is configured for SHA-1, SHA-256, SHA-512, and MD5.
• § 102 relevance: This is the closest processor-architecture reference, and it expressly names SHA-512 and discusses architectural-register usage. If anything could be argued as anticipatory to some of the '039's generic framing (claim 1's preamble "maximizing a number of registers at an end of an iteration … for use in a next iteration," and claim 3's "assigning state words to registers"), this is it. But it discloses hardware-ISA instructions and a cryptographic unit's internal register use — not the claimed software technique of unrolling into even/odd iterations, reversing the sequence of computations between them, and combining an even+odd pair into a new loop iteration. It does not disclose the one-half load reduction. No anticipation of claims 1/11/21; best § 103 art against claims 3–5 (assigning state words to registers, "advanced processor architecture," preloading/doubleword).

5. US 2011/0231636 A1 — "Apparatus and method for implementing instruction support for performing a cyclic redundancy check (CRC)" (Olson)

• Full citation: U.S. Pub. No. 2011/0231636 A1 (Christopher H. Olson), pub. Sep. 22, 2011; priority Mar. 16, 2010. (Google Patents: https://patents.google.com/patent/US20110231636A1)
• Marked "cited by examiner."
• Brief description (inferred from title/citation data only — I did not retrieve the body text): A companion to the Olson hash-instruction family above, directed to processor instruction support for CRC computation. It shares the "ISA instructions execute a checksum/crypto primitive in processor logic" architecture.
• § 102 relevance: Tangential. CRC is not SHA-512. Relevant, if at all, only cumulatively with US 2010/0250966 A1 on the general theme of processor instruction support for integrity primitives. No anticipation of any claim; the '039 claims are all directed to SHA (claims 2/12 recite SHA-512/SHA-384), and CRC does not teach the even/odd reversal.

B. Remaining cited references — bibliographic data verified from the patent record; body content NOT independently verified

For the following I relied solely on the citation data printed in the authoritative patent text (full citation, dates, assignee, title). I could not retrieve or verify the substantive disclosures before reaching the search-step limit, so I mark descriptions as inferred from title and do not assert § 102 anticipation.

(Rows 4, 9, 10, 11 are the references covered in Section A and are not repeated here.)

C. Non-Patent Citations (5)

All five appear as "cited by examiner" in the '039 record. I did not retrieve full text of these, so descriptions are as titled.

1. "Cryptanalysis of EnRUPT," D. Khovratovich & I. Nikolić, IACR Cryptology ePrint Archive 2008/467 (Jan. 2008). — Cryptanalysis of a different (non-SHA) cipher; security analysis, not implementation. No § 102 relevance.
2. "FPGA Implementation of MD5 Hash Algorithm," J. Deepakumara, H.M. Heys, R. Venkatesan, Proc. IEEE CCECE 2001, Toronto (2001). — FPGA hardware MD5. Background; MD5 is 32-bit/64-round, not SHA-512. At most § 103 background for "hardware hash implementation," no anticipation.
3. "Hardware Implementation of the Salsa20 and Phelix Stream Ciphers," J. Yan & H.M. Heys, Memorial University of Newfoundland (2007). — Stream ciphers, not hash functions. No § 102 relevance.
4. "High-Speed Hardware Architectures of the Whirlpool Hash Function," M. McLoone, C. McIvor, A. Savage, Queen's University Belfast (2005). — Whirlpool is a different, AES-based hash. Background only. No § 102 relevance.
5. International Search Report and Written Opinion, PCT/CA2012/050219, mailed May 25, 2012. — The ISR for this very application (the '039's PCT counterpart, WO2012135958A1). This is a procedural document identifying the examiner's cited art; it is not itself prior art.

D. Bottom-line § 102 assessment

• Anticipation of claim 1, 11, or 21: none of the cited references. Each independent claim requires (a) categorizing and unrolling SHA iterations into even and odd iterations, (b) reversing the sequence of computations in the even iterations relative to the odd ones, with the result that the average words loaded per iteration is reduced by at least one-half, and (claims 1/11) or an added constant-offset limitation (claim 21). No cited reference — including the SHA-512-specific Grinchuk reference and the processor-register Olson reference — discloses even/odd unrolling coupled with computation-order reversal to halve register-load traffic on a register-constrained processor.
• Which references are not prior art at all: US 2013/0108038 A1 (Apple Collatz) is disqualified by its post-'039 priority date (Nov. 1, 2011). US 2012/0144203 A1 (AT&T) reaches the '039 only as an earlier-filed U.S. application publication (potential § 102(a)(2)/pre-AIA § 102(e) art), and its subject matter appears unrelated.
• Strongest § 103 (not § 102) candidates: US 2010/0086127 A1 (Grinchuk, SHA-512 hardware optimization) and US 2010/0250966 A1 (Olson, processor-register hash instruction support), potentially combined with a register-allocation/unrolling teaching; and the SHA-1 hardware references (US 7,299,355 B2, US 2004/0260740 A1) for the generic "reorder operations / manage message-schedule buffer" concept. But combining hardware-ASIC art with processor-register art is exactly the kind of combination a patent owner will attack for lack of a motivation to combine and for hindsight.
• One reference I would pull in full before finalizing: US 2010/0049986 A1 (Hitachi, "Hash value generator," pub. 2010-02-25). It is the only unverified reference in the list whose title suggests a hash-architecture disclosure, and it pre-dates the '039 priority date. I could not retrieve its body within the search budget.

Caveats and confidence: High confidence in the bibliographic data, the two disqualifying-timing findings, and the "no clean § 102 reference" conclusion, all of which rest on the authoritative patent text and the verified pre-'039 dates. Lower confidence on the disclosures of the five references I could not open (Sharp, Renesas, Sudia, Auckland, Hitachi, AT&T) and on the non-patent citations; those descriptions are title-based inferences and must be confirmed against the full documents before being used in any invalidity contention. I did not query USPTO Patent Center or PTAB E2E directly — live-verify the citation list at https://patents.google.com/patent/US8712039/en or via Patent Center if primary-source confirmation is required.

I'll ground this obviousness analysis in the actual prior-art references of record, then build the § 103 combinations. Let me pull the disclosures of the key cited references.

Let me gather more on the ARM-specific techniques and the remaining cited references.

Obviousness Analysis — U.S. Patent No. 8,712,039 under 35 U.S.C. § 103

Sources used: the patent's own "Prior Art"/"Citations" and "Non-Patent Citations" blocks (as reproduced in the record you supplied), cross-checked against live patent text where retrievable. Grounding URLs are cited inline.

Two housekeeping flags before the analysis:

1. Date discrepancy. Your task states "Current Date: April 26, 2026," but the system date for this session is 2026-09-28, and the previously generated litigation sections in this record describe docket events into September 2026. That is a contradiction I am flagging rather than reconciling. It does not affect this analysis, because the § 103 critical date is the patent's own priority/filing date, not 2026.
2. Forward citations are not prior art. The "Families Citing this family" block (Intel US 9,251,377 / 8,924,741; 21 Inc. US 9,659,123; Micron; IBM, etc.) and the "Cited By" list are post-dated relative to the '039's 2012-04-05 filing and, with one exception noted below, cannot be § 102/§ 103 art against it. I exclude them.

1. Legal framework and the critical date

The '039 patent has a priority date of 2011-04-06 (provisional 61/472,422) and a filing date of 2012-04-05 — both before the AIA's 2013-03-16 changeover. Pre-AIA § 102/§ 103 governs. The inquiry is Graham v. John Deere: scope and content of the prior art, differences between the prior art and the claims, level of ordinary skill, and secondary considerations — with KSR Int'l v. Teleflex supplying the "expansive and flexible" obviousness standard, including the "finite number of identified, predictable solutions" and "obvious to try" rationales (MPEP 2144.05). The § 103 critical date is 2011-04-06.

Prior-art status of each cited reference:

⚠️ Flag: US 2013/0108038 A1 (Apple) and the entire "Cited By" block must be dropped from any invalidity theory. A defendant who cites them invites an easy priority rebuttal.

2. What the claims actually add over the admitted prior art

The specification concedes the starting point. SHA-512 is FIPS 180-3: "80 rounds of repeated operations on a state consisting of eight 64-bit words," and "Pseudocode 1. Pseudocode of SHA-2 iterations" is presented as the classical implementation. The specification also concedes the hardware environment: an ARMv5t-class core "comprises sixteen 32-bit registers of which one is the program counter (PC) and the other is the stack pointer (SP)," so "the SHA-512 state cannot be entirely kept in the 14 working registers." And it concedes the ARMv5te features — LDRD/STRD and preload — exist and are a matter of design choice ("the register assignment takes into consideration the possibility of leveraging the capabilities of more advanced processor features").

So the only subject matter left to sustain patentability is the optimization itself. The asserted advance, per the spec, is quantitative: "The average number of words A-H loaded per original iteration in our new implementation is four (eight 32-bit loads), instead of eight (sixteen 32-bit loads)."

3. The three strongest references — what each actually teaches

(a) Broadcom US 7,299,355 B2 — "Fast SHA1 implementation" (primary reference for the pairing concept)

Direct quotes from the record: the architecture applies techniques including "collapsing two SHA-1 authentication algorithm processing rounds into one"; and "reducing operational overhead by ordering the additions required by an SHA-1 authentication algorithm in such a manner as to reduce the overall critical timing path ('hiding the adds')." Claim 9 recites "five hash state registers; one critical and four non-critical data paths associated with the five registers, such that in successive SHA1 rounds, registers having the critical path are alternate."

Why this matters: this is the closest teaching of the two central ideas — (i) processing two adjacent hash iterations as a unit, and (ii) alternating register roles between adjacent rounds so that values produced in one round are consumed in the next. It is the functional ancestor of "an even and an odd iteration form together a new iteration of the loop."
Source: https://patents.google.com/patent/US7299355

(b) Grinchuk US 2010/0086127 A1 / US 8,160,242 — "Efficient implementation of arithmetical secure hash techniques"

Expressly covers the SHA-2 family "e.g., SHA-224, SHA-256, SHA-384, SHA-512" and states "SHA-512 is a variant of SHA-256 which operates with 64-bit words and performs 80 cycle rounds instead of 64." Its core technique is a "diagonal cut technique that simultaneously uses values from a plurality of different cycle rounds in a single cycle round analog" — i.e., restructuring the round computation so that values from different rounds are brought together and reused, precisely the operation-reordering insight the '039 claims. Its stated objects include "reduc[ing] cost," "reduc[ing] area used," and "eliminat[ing] storage of constants."
Sources: https://patents.google.com/patent/US20100086127 ; https://patents.justia.com/patent/[8160242](/patent/8160242)

(c) Olson US 2010/0250966 A1 / US 8,832,464 — "Processor and method for implementing instruction support for hash algorithms"

Discloses a processor whose cryptographic unit, on receiving a SHA512 instruction, "may retrieve a set of input data blocks from a predetermined set of architectural registers of the processor, and generate a hash value of the set of input data blocks." The disclosed instruction set includes MD5, SHA-1, SHA-256 and SHA-512.
Source: https://patents.google.com/patent/US20100250966A1

(d) Liu US 2004/0260740 A1 / US 8,045,706 B2 — "SHA-1 … optimal computation speed using minimal hardware resources"

Discloses a 16×32-bit circular queue memory used as the Wt buffer "to supply the Wt-3, Wt-8, Wt-14, and Wt-16 data parameters simultaneously," and "a combination of a counter circuit and a decoder/encoder circuit to control selecting data parameters and sequencing the 81-step SHAA-1 computation." The related application US 2009/0161863 A1 discloses mod-16 counters for the same purpose. This is the direct answer to claims 8/9/18/19.
Source: https://patents.google.com/patent/US20040260740

(e) ARM Architecture Reference Manual (ARMv5TE) — for claims 4, 5, 10, 14, 15, 20 and as the admission anchor

The ARM ARM literally specifies: LDRD/STRD — " … must be even-numbered and not R14," " must be <R(t+1)>"; and PLD "Preload Data." That is a verbatim match to claim 10's "R(d), R(d+1) … d is even and not equal to 14" and claim 5's "data preloading and doubleword loading and storing."
Sources: https://documentation-service.arm.com/static/5e9737569931941038dcef69 ; ARM DDI 0406B § A8 (LDRD encoding A1, ARMv5TE).

4. The § 103 combinations

Combination A — Broadcom '355 + Olson '966 + ARM ARM

Targets claims 1, 3–6, 10, 11, 13–16, 20 (the "reuse registers between paired iterations" family).

• Broadcom '355 supplies the pairing ("collapsing two … rounds into one") and the alternation of register roles between adjacent rounds ("registers having the critical path are alternate").
• Olson '966 supplies a processor/processing-circuit that computes SHA-512 by pulling state from a predetermined set of architectural registers, establishing that the register-residency problem and its hardware solution were known in the hash context.
• ARM ARM supplies the doubleword/preload capabilities and the register-pair constraint.

Motivation to combine: (i) the art recognizes the identical problem — Broadcom's stated goal is "reduc[ing] operational overhead" and "hiding the adds," Olson's is instruction-level acceleration of hashing; (ii) the '039's own specification concedes the ARM register scarcity that drives the need; (iii) KSR's "finite number of identified, predictable solutions" — the only viable levers on a 14-register core are loop unrolling, operation reordering, and register-pair loads/stores. The result (fewer loads) is the predictable consequence of reuse and is thus a result-effective variable, obvious to optimize (MPEP 2144.04/2144.05).

Weakness: Broadcom and Olson are hardware accelerators; the '039 claims a software scheduling technique. This is the seam the patentee will exploit (§ 5, below).

Combination B — Grinchuk '127 + Liu '740 + ARM ARM

Targets claims 1, 2, 7–9, 11, 12, 17–19, 21 (the "SHA-2 message-schedule / constant-offset" family).

• Grinchuk '127 supplies the SHA-512 substrate, the applicability of cross-round value reuse ("diagonal cut"), and the express motivation to reduce register/logic cost — which on a register-starved core means reducing loads/stores.
• Liu '740 supplies the 16-entry circular W buffer with simultaneous multi-W retrieval, and the counter/sequencer for the W index — the substance of claim 9/19 and claim 8/18.
• ARM ARM supplies the addressing and pair constraints.

Motivation: Grinchuk's own recitation of objects — reduce cost, reduce area, support high-frequency designs — is a stated incentive to do exactly what the '039 does. Liu demonstrates that W-index sequencing and multi-W addressing are old. Combining them to eliminate a per-iteration W-address register (the '039's "no other register is used to contain the address of w[j]") is a routine, results-driven optimization under a constant stack-pointer offset.

Combination C — Olson '966 + Grinchuk '127 + Liu '740 + Broadcom '355 + ARM ARM (omnibus, all claims)

Because claims 1 and 11 are apparatus/method counterparts, one should present C as the belt-and-suspenders case so that no dependent claim is left unmapped. Optional secondary references: US 2010/0049986 A1 (Hitachi, hash value generator) for register-buffered hash state, and general compiler loop-unrolling / software-pipelining texts (see § 5). The five NPL items are only marginally relevant (Whirlpool/Salsa20/EnRUPT are not SHA-2 and would serve at most as § 103 "analogous art / level of skill" background).

5. Claim-chart summary (for a petition draft)

6. Where the patentee will fight — and what a petitioner must add

The hard kernel is the quantitative result in claims 1 and 11 — the reversal must produce "an average number of words that need to be loaded into the registers per iteration being reduced by at least one-half." Three observations:

1. No reference of record expressly reports that number. A petitioner must either (a) show the prior-art combination inherently/specifically achieves the reduction, or (b) frame it as a result-effective variable under MPEP 2144.04 — a predictable consequence of the disclosed reuse, which is per se obvious to optimize. The specification's own math (8 → 4) makes (b) attractive.
2. The hardware/software gap is real. Broadcom, Grinchuk, Liu and Olson are all hardware implementations; the '039 claims a scheduling/register-allocation method for a compiler or hand-written routine. The combination is vulnerable unless the petitioner supplies art on loop unrolling and software pipelining / register-pressure scheduling in the hash context. That art is abundant in the general compiler literature but is not in the '039 record — I could not verify a specific pre-2011 software-pipelining reference from this page, so I am not asserting one exists as a matter of record. This is the single most important gap to fill.
3. The "reverse the order of computation in alternating iterations" step has no express antecedent in the cited art. Broadcom teaches alternating register roles between adjacent rounds; Grinchuk teaches reusing values from different rounds; but neither expressly says "reverse the step sequence in odd iterations." The petitioner must argue that reversal is an obvious design permutation once one decides to pair iterations and reuse results — which is a KSR "obvious to try / predictable variation" argument rather than a clean anticipation-style showing.

Secondary-consideration posture: none of unexpected results, long-felt need, or industry praise is apparent from the record; the 2× load reduction is presented as the expected arithmetic consequence of reuse, not a surprising one. Licensing/indicia of the Malikie campaign are litigation artifacts, not § 103 secondary considerations, though a petitioner could look for copying/industry-acclaim evidence in discovery.

7. Honest limitations of this analysis

• I could retrieve full text for Broadcom '355, Grinchuk '127/8,160,242, Olson '966/8,832,464, and Liu '0740/8,045,706, and the ARM ARM. I could not retrieve US 2010/0049986 A1 (Hitachi) or the lesser-cited items (Sudia, Auckland, Fiske, AT&T); their treatment above rests on titles/context and should be verified before filing.
• The five non-patent citations in the record (EnRUPT cryptanalysis, MD5 FPGA, Salsa20/Phelix, Whirlpool, and the '039's own ISR) are, on their face, not squarely on point for SHA-2 register-reuse; the MD5 FPGA and Whirlpool papers are at most analogous-art background. I would not build a primary theory on them.
• Do not quote the "Cited By" hardware and the Apple Collatz application as prior art. They post-date the critical date (Apple US 2013/0108038 has a 2011-11-01 filing, after the 2011-04-06 priority), and citing them would undercut the petition's credibility.
• The strongest, most defensible theory is Combination A for claims 1/3–6/10/11/13–16/20 and Combination B for claims 7–9/17–19/21, presented jointly (Combination C) so every dependent claim is mapped — provided a software-pipelining/loop-unrolling reference is added to bridge the hardware/software gap.