US 8659093

I'll search for this patent number across sources, including any CAFC 2026 docket activity.

Let me search specifically for litigation/docket activity and assignee details.

US Patent 8,659,093 — Analyst Summary

Search scope note: I searched for the literal number "8659093" / "8,659,093." I found no 2026 CAFC docket activity, and no docket activity at all tied to this specific number. Please treat the litigation/docket portion below as negative/uncertain, not as confirmation that none exists.

Bibliographic Data (from the patent record at patents.google.com/patent/US8659093)

Prosecution/family history (important — this is a continuation, not the original):

• Parent: US 12/198,592, filed 2008-08-26 → issued as US 8,169,031 ("Continuous metal semiconductor alloy via for interconnects"). US 8,659,093 is a continuation of Ser. No. 12/198,592 (stated in the "Related Application" section).
• Sibling continuation: 13/405,598 → US 8,530,293.
• Child continuation: 14/188,028 → US 2014/0167109 A1 (abandoned).
• Assignment chain: IBM → GLOBALFOUNDRIES U.S. 2 LLC (2015) → GLOBALFOUNDRIES Inc. (2015) → AURIGA INNOVATIONS, INC. (effective 2016-12-07, recorded 2017-02-24).

Abstract (as granted)

A contact structure is disclosed in which a continuous metal semiconductor alloy is located within a via contained within a dielectric material. The continuous semiconductor metal alloy is in direct contact with an upper metal line of a first metal level located atop the continuous semiconductor metal alloy and at least a surface of each source and drain diffusion region located beneath the continuous metal semiconductor alloy. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each source and drain region, and a vertical pillar portion extending upward from the lower portion.

Plain-Language Overview of the Independent Claim

The patent has 9 claims, with a single independent claim (claim 1). Claims 2–9 all depend from claim 1.

Claim 1 — Structure

A semiconductor structure comprising:

1. A field-effect transistor (FET) on a semiconductor substrate, including a gate electrode, a source region, a drain region, and a spacer on an exposed sidewall of the gate electrode.
2. A "continuous metal semiconductor alloy" made of a single-crystal metal semiconductor alloy, comprising:
   • a lower portion sitting within the upper surface of the source and drain regions, and
   • a vertical pillar portion rising up from that lower portion,
   • where the lower portion and pillar are of unitary construction with no material interface between them (i.e., one continuous piece, not a silicide layer plus a separately deposited metal via);
   • the pillar maintains the same cross-section along the vertical axis (i.e., it is not tapered — a nod to the nanowire/epitaxial origin of the pillar);
   • the pillar does not contact the outer surface of the gate spacer; and
   • the pillar is narrower than the lower portion.
3. A dielectric material whose upper surface extends above the topmost surface of the FET, located on the substrate surface, which embeds the vertical pillar — with the top of the pillar directly contacting and exposed at the dielectric's upper surface.
4. A metal line (first metal level) sitting on the exposed top of the pillar and on the dielectric upper surface.

Concept in one sentence: Instead of filling a via with tungsten/copper and forming a separate silicide at the via bottom (two dissimilar materials = an interface and contact resistance), the contact itself is grown as a single-crystal semiconductor pillar (nanowire or epitaxial) and then fully converted by silicidation into one continuous, interface-free single-crystal silicide/germanide that runs from inside the source/drain up to the overlying metal line.

Dependent claims (2–9), summarized:

• 2 — the single-crystal alloy is a metal silicide.
• 3 — the single-crystal alloy is a metal germanide.
• 4 — the alloy forms a conductive path between the source region and the metal line.
• 5 — that conductive path is ohmic.
• 6 — that path exhibits linear electrical-potential variation (i.e., no junctions from dissimilar materials).
• 7 — the substrate is Si with a (100) crystal orientation.
• 8 — a continuous single-crystal metal semiconductor alloy is also located atop the gate electrode.
• 9 — the continuous metal semiconductor alloy comprises a metal semiconductor alloy nanowire.

Technical Background Reflected in the Specification

• Motivated by scaling problems: 20–30 nm vias show resistance increases from sidewall roughness and polycrystalline metal grains; carbon-nanotube (CNT) replacements were problematic because CNT synthesis exceeds 700 °C versus the ~400 °C BEOL thermal budget, and CNTs are incompatible with O₂-plasma resist strip and some PECVD steps.
• Two disclosed fabrication routes: (a) VLS (vapor-liquid-solid) grown semiconductor nanowires (e.g., Si from SiH₄ at 370–500 °C; Ge from GeH₄ at ~300 °C) converted by salicidation; and (b) epitaxial semiconductor growth inside a sacrificial-dielectric via, followed by removal of the sacrificial dielectric and salicidation.
• Metals for silicidation listed: Ti, Ni, Pt, W, Co, Ir (NiSi noted at ~400–450 °C RTA).
• FIGs. 3A–3E address a (111) Si layer on (100) Si hybrid substrate to control nanowire growth orientation while keeping a (100) channel.

Litigation / Docket Findings (with explicit uncertainty)

• No CAFC 2026 docket entry for 8,659,093 was found. I cannot confirm any 2026 appellate activity for this patent. I also could not verify any CAFC appeal involving this number in any year.
• Assignee entity context: Auriga Innovations, Inc. is a known patent-holding entity. Public reporting identifies Auriga Innovations, Inc. v. Intel Corporation et al. (Intellectual Property – Patent lawsuit filed August 25, 2020, U.S. District Court for the Western District of Texas; defendants listed as Intel, HP Inc., and Hewlett Packard Enterprise), asserting seven microprocessor/semiconductor patents acquired by Auriga, with reporting tying the theory to FinFET technology.
• I could not confirm that US 8,659,093 was one of the seven asserted patents in that case, nor that it has ever been asserted. This is an explicit uncertainty, not a negative finding.
• The patent's own "Families Citing"/"Similar Documents" listings show later IBM/Auriga-family and Applied Materials/Micromaterials self-aligned-via references — these are citation relationships only, not litigation.

Caveats

1. Assignee: The Google Patents "current assignee" field says Auriga Innovations Inc.; Google itself disclaims accuracy of assignee listings, and the maintenance-fee lapse (2022) means ownership at lapse may not have changed. Not legal advice.
2. Priority/continuation: US 8,659,093's effective filing date for prior-art purposes traces to 2008-08-26 through the 12/198,592 continuation, even though its own filing date is 2012-02-27.
3. "Continuous metal semiconductor alloy" is a coined term in this patent meaning a silicide/germanide whose lower portion and vertical pillar are one unitary piece with no material interface.
4. Any docket conclusions above should be re-verified against PACER/Docket Alarm and the CAFC docket for the exact number before being relied upon; my searches surfaced no such hits.

I'll search for litigation involving US patent 8659093.

Let me search more specifically for this patent in litigation databases.

Let me dig into the Auriga Innovations cases and check patent-specific litigation databases.

Summary of Findings

I searched for litigation specifically involving U.S. Patent No. 8,659,093 ("Continuous metal semiconductor alloy via for interconnects"). Here is what I found — and, importantly, what I could not confirm.

Bottom line

I did not locate any court filing that specifically and verifiably identifies U.S. Patent No. 8,659,093 as an asserted patent in litigation. No CAFC appeal, no PACER complaint, and no litigation-database entry naming the '093 patent was returned in my searches.

What the searches did surface

1. US 8,659,093 is a real, granted, IBM-originated patent. Per the Google Patents family data:

   • Priority date 2008-08-26; granted 2014-02-25; application US 13/405,739.
   • Original assignee IBM → reassigned to GlobalFoundries (2015) → reassigned to Auriga Innovations, Inc. (recorded 2017-02-24, effective 2016-12-07).
   • Legal status: Expired – Fee Related (lapsed 2022-02-25 for failure to pay maintenance fees).
   • It is part of a family including US 8,169,031 (US 12/198,592), US 8,530,293 (US 13/405,598), and US 2014/0167109 (US 14/188,028).

   This is relevant context because the current owner, Auriga Innovations, is a known patent-assertion entity — so this is a plausible candidate for litigation, but plausibility is not evidence.

2. Auriga Innovations, Inc. v. Intel Corporation et al. — W.D. Tex., Case No. 6:20-cv-00779, filed 2020-08-25, assigned to Judge Alan D. Albright, against Intel Corporation, HP Inc., and Hewlett Packard Enterprise Company. Status: closed (notice of voluntary dismissal filed ~2020-10-01).

   • ⚠️ I could not confirm which patents were asserted in this case. My searches did not return the complaint's patent list, so I cannot state that '093 was among them. This case is a candidate lead only.

3. No other Auriga Innovations litigation involving '093 was returned, and no IPR/PTAB proceeding naming '093 appeared.

Important caveats (please read)

• My search was not exhaustive. I was cut off before completing targeted queries against the Unified Patents litigation portal (portal.unifiedpatents.com/litigation/caselist), RPX Insight (insight.rpxcorp.com), Docket Alarm, and PACER directly. Those are the sources most likely to confirm or rule out a case, and they were not fully queried.
• Near-miss results should be ignored. Several hits involved similarly numbered but different patents (e.g., US 8,646,093 in BMC Software v. ServiceNow; US 6,811,898-line patents in Sony v. BMW/Mazda). None of these involve US 8,659,093.
• Search snippets are not authoritative. Results from CourtListener, UniCourt, and PTAB filings mention many patents; I did not find '093 cited in any of them.

Recommended verification steps

To definitively answer this, the following should be checked directly:

1. Unified Patents litigation portal – search "8659093" under the specific patent filter.
2. RPX Insight – patent profile for US 8,659,093 (shows all cases where it was asserted).
3. PACER / CourtListener RECAP – full-case docket for Auriga Innovations, Inc. v. Intel Corp. et al., 6:20-cv-00779 (W.D. Tex.) to read the complaint's asserted-patent list.
4. USPTO assignment + Patent Center – to confirm chain of title and any post-2017 assertions tied to the Auriga entity.

Honest conclusion

On the current record, there is no confirmed litigation involving US Patent No. 8,659,093 that I can report with the required (plaintiff / defendant / jurisdiction / case number / filing date / outcome) specificity. The one lead — Auriga Innovations, Inc. v. Intel Corp. et al., 6:20-cv-00779 (W.D. Tex.), filed 2020-08-25, voluntarily dismissed 2020-10-01 — is unverified as to whether '093 was asserted, and I am flagging it as a lead rather than a confirmed result. I would rather state this uncertainty than fabricate a case.

I'll verify the structured data against public sources before drafting.

Let me run additional targeted searches to confirm the absence of proceedings.

Let me check for any litigation or PTAB filings associated with this patent and its owner.

PTAB Proceedings — U.S. Patent No. 8,659,093 B2

"Continuous metal semiconductor alloy via for interconnects" — Appl. No. 13/405,739; filed 2012-02-27; granted 2014-02-25; priority 2008-08-26; inventors Cohen, Dimitrakopoulos, Grill; current owner of record Auriga Innovations, Inc.

Proceedings overview

Total AIA trial proceedings on file: 0. There are no IPRs, PGRs, or CBM reviews involving US 8,659,093 — not active, not invalidated, not sustained, not settled, not denied, because none was ever filed. The USPTO Open Data Portal structured block for this patent returns no AIA trial proceedings, and independent web searches of PTAB public materials (PTACTS, the Board's decision library, and secondary coverage) surfaced no petition, institution decision, or final written decision naming this patent. Note the search-space hazard here: several IPRs exist against other patents colloquially called "the '909 patent" — e.g., U.S. Patent 11,968,909 (Western Digital v. Godo Kaisha IP Bridge) and a fin-structure patent with a patent owner's brief referencing "the '909 patent" in its prosecution history. None of those involve US 8,659,093. Do not let a keyword hit mislead you.

Bottom-line defensive posture: The materially more important fact for a defendant is not the empty PTAB docket — it is the legal status line. US 8,659,093 is "Expired - Fee Related": maintenance fees went unpaid, the lapse event is recorded at 2022-04-04 with an effective date of 2022-02-25, and the patent's anticipated expiration was 2028-08-26. In other words, the patent died early — roughly six and a half years before its nominal term — for nonpayment. That is the single most consequential entry in the file: the enforceable term ended 2022-02-25, so no act after that date can infringe, and any damages sought today are confined to the pre-lapse window (and further capped by the § 286 six-year lookback). There is no hardening story here and there is no invalidation story here, because no adversarial PTAB test was ever run. The claims are untested at the Board and were never cancelled.

Proceedings (most-impactful first)

None to report. There are no proceeding entries to populate. I am deliberately not generating placeholder headers for IPR numbers, panels, grounds, institution dates, or FWDs — inventing a proceeding number or panel is the one failure mode this exercise is designed to prevent. The structured block is the canonical source and it is empty; the web corroborates emptiness rather than filling it.

Two adjacent items that are not PTAB proceedings but belong in a defendant's file, with my confidence flagged:

1. Auriga Innovations, Inc. v. Intel Corporation et al, No. 6:20-cv-00779 (W.D. Tex., Judge Alan D. Albright), filed 2020-08-25 against Intel, HP Inc., and Hewlett Packard Enterprise; voluntarily dismissed by Auriga on 2020-10-01 (D.I. 22), before any answer was due. Reported by UniCourt: https://unicourt.com/case/pc-db5-auriga-innovations-inc-v-intel-corporation-et-al-[654424](/patent/654424). Confidence that this case asserted US 8,659,093: low. I could not verify which patent(s) were in suit — Auriga holds a portfolio (it acquired the IBM/GlobalFoundries semiconductor families in the 2017 assignment recorded at Reel/Frame 041804/0940), and the complaint is not in my searchable sources. Do not cite this as a lawsuit over the '093 patent without pulling the complaint from PACER or the W.D. Tex. docket first. The notable pattern is the shape: a short-lived assertion campaign followed by voluntary dismissal, with no IPR counterattack — consistent with a monetization entity testing the waters rather than a sustained campaign.

2. Any terminated IPR on a family member? The related patents in this family — US 8,169,031 (parent, 12/198,592) and US 8,530,293 (13/405,598) — should be checked separately if you are facing a demand that cites the family. My searches did not surface proceedings against those either, but I did not exhaustively verify them and you should treat that as an open item rather than a finding.

Strategic summary

Claim status: all nine claims UNTESTED, none cancelled, none sustained. US 8,659,093 issued with exactly nine claims (claim 1 independent; claims 2–9 dependent). Because no AIA trial was ever instituted, there is no claim-level record whatsoever — no cancellation under § 318(a), no patentability holding, no adverse judgment, no disclaimer entered during a trial. If you are being told claims 1–9 were "invalidated at the PTAB," that statement is false as to this patent. Equally, if someone tells you the claims are "PTAB-hardened," that is also false — an untested claim is simply untested. The complete absence of PTAB proceedings means the claims' validity rests entirely on the original 2008–2012 prosecution. Notably, the file shows two rounds of amendment-driven allowance on the parent family (a point a "the Examiner never saw this art" argument can exploit), but I have not verified the '093 prosecution history itself and would not represent it as a finding.

Estoppel landscape: clean slate. Because no IPR, PGR, or CBM was filed, § 315(e)(2) estoppel attaches to no one. There is no petitioner, no real party in interest, and no privy who is barred from raising any ground in a district court or ITC proceeding. Every § 102/§ 103 combination in the printed-publication and patent universe is available to a defendant today, unencumbered by prosecution-history estoppel, IPR estoppel, or an adverse FWD. The corollary constraint is procedural, not estoppel-based: if a defendant itself wants to file an IPR, § 315(b)'s one-year bar runs from service of the complaint, and § 315(a)(1) bars an IPR filed by a party that already filed a civil action challenging validity. Also bear in mind that PGR is permanently unavailable for this patent (it issued from a 2012-filed continuation of a 2008 application, so it is not PGR-eligible), and CBM review is both inapplicable to this subject matter and sunset as of 2020-09-16.

The expiration dominates everything. US 8,659,093 lapsed for failure to pay maintenance fees, effective 2022-02-25, with the lapse recorded 2022-04-04 and the "FP — Lapsed due to failure to pay maintenance fee" event stamped 2022-04-26. Practical consequences a defendant should press hard:

• No prospective infringement. Any product made, used, sold, or imported on or after 2022-02-25 cannot infringe this patent. An injunction demand is a non-starter.
• Damages are a closed, shrinking window. Recovery is limited to acts before 2022-02-25 and, under § 286, to acts within six years before the filing of any suit. A complaint filed today (2026-10-01) reaches back only to 2020-10-01 — so the entire damages-eligible period is a roughly 17-month sliver from 2020-10-01 to 2022-02-25, and it shrinks every day.
• The accused-product question is narrow. Only products shipped in that window matter, which frequently makes discovery disproportionate to any realistic recovery.
• Revival is theoretically possible but factually unlikely. The maintenance-fee lapse could in principle be addressed by petition, but reviving a patent that has been lapsed since 2022 for the purpose of reviving a ~17-month damages tail is rarely worth a patent owner's effort.

Pattern signals. (a) Same petitioner, multiple IPRs? No — there is no petitioner at all. (b) Patent owner pursuing PTAB appeals aggressively? No Federal Circuit appeal exists, because no Board decision exists to appeal. (c) Defensive aggregator in the chain? No evidence of Unified Patents or any similar entity ever challenging this patent; the only recorded ownership changes are the corporate chain IBM → GLOBALFOUNDRIES U.S. 2 LLC (2015-09-03) → GLOBALFOUNDRIES Inc. (2015-10-05) → AURIGA INNOVATIONS, INC. (recorded 2017-02-24, effective 2016-12-07). This is a standard divestiture chain, not a PAE-formation or aggregator-defended chain.

Recommended next steps

1. Lead with expiration, not with PTAB. Request the maintenance-fee/lapse record from PatentCenter (https://patentcenter.uspto.gov/) — the transaction history showing the 2022-04-04 lapse and the 2022-02-25 effective date — and make it Exhibit A in any response. It is public, dispositive as to prospective liability, and collapses the damages period.
2. Do not build a defense around an IPR that does not exist. There is no FWD to cite, and no claim to quote as cancelled. If opposing counsel represents that claims 1–9 were invalidated at the PTAB, demand the proceeding number and the paper — there is none.
3. If the demand letter cites the family, check the siblings. US 8,169,031 and US 8,530,293 share the 2008-08-26 priority date and would carry the same ~2028 nominal expiration, but each has its own maintenance-fee history. Verify each separately in PatentCenter before assuming the same lapse. I did not verify their status.
4. If you want an adversarial adjudication anyway (e.g., a client needs a clean invalidity judgment, or the demand is aggressive), the remaining options are an ex parte reexamination under § 302 (available to anyone, including a third party, throughout the life of the patent — and note that PTO practice permits reexam of expired patents) or a district court/ITC invalidity defense. Neither is subject to the § 315(e)(2) estoppel analysis, because that estoppel provision presupposes an AIA trial that never happened.
5. Verify the Auriga v. Intel lead before relying on it. Pull the complaint and any Rule 7.1/corporate disclosures from the W.D. Tex. docket (6:20-cv-00779) or PACER to confirm which patents were asserted and whether 8,659,093 was among them. Until then, treat the connection as unconfirmed.

Confidence and sourcing notes

• High confidence: zero AIA trial proceedings on file (structured ODP block; corroborated by searches); grant, filing, priority, inventorship, and the IBM → GlobalFoundries → Auriga assignment chain (patent record, https://patents.google.com/patent/[US8659093B2](/patent/US8659093B2)/en); the maintenance-fee lapse and its dates; nine claims with claim 1 independent.
• Low confidence / unverified: whether the 2020 W.D. Tex. Auriga case asserted this patent; whether related family members US 8,169,031 or US 8,530,293 were ever challenged; whether the '093 prosecution history contains the two-amendment allowance pattern described in my search results for a different "909" patent (I saw that description in a third-party petition exhibit, not in the '093 file).
• Not fabricated: I have not supplied proceeding numbers, panels, grounds, institution dates, or FWD dispositions, because none exist. Where the requested format calls for facts that a nonexistent proceeding cannot supply, I have said so rather than filling the template.

Authoritative links: patent — https://patents.google.com/patent/US8659093B2/en; PTAB E2E proceeding search — https://ptacts.uspto.gov/ptacts/; USPTO PatentCenter — https://patentcenter.uspto.gov/; PTAB decisions — https://www.uspto.gov/patents/ptab/decisions; Federal Circuit opinions — https://www.courtlistener.com/?type=o&court=cafc.

I'll research the assignment records now. Let me run several targeted searches in parallel.

Strong leads. Let me dig into the specific assignment records and correspondents.

Inventors

All three are the named inventors on the whole family (parent US 12/198,592 → US 8,169,031; the instant continuation US 13/405,739 → US 8,659,093; sibling US 13/405,598 → US 8,530,293).

Pattern note — "inventors departing within 12 months": Not determinable from the records I retrieved. I could not pull the original inventor→IBM assignment record (reel/frame) for the parent filing, so I cannot verify departure timing, and I did not find corroborating evidence of a mass inventor exodus around the 2008 priority date. Do not treat inventor attrition as a finding here. The "fire-sale" character of this chain is instead evidenced by the assignee history (below), which is fully documented.

Original assignee

International Business Machines Corporation (IBM). Named on the face of US 8,659,093 (Google Patents lists "Original Assignee: International Business Machines Corp").

• Primary line of business: diversified IT — hardware, software, and IT services; at filing it operated a semiconductor manufacturing business (IBM Microelectronics), and this patent (grown-nanowire / epitaxial silicide vias and contacts) sits squarely in that division's process-technology R&D.
• Did they ship a product embodying the claims? Probable but not confirmed. IBM was a vertically integrated chip manufacturer at filing and the claimed structure (a continuous single-crystal metal-semiconductor-alloy via) is a manufacturable interconnect, so it is plausible it was practiced in IBM's advanced nodes — but I found no specific product documentation tying an IBM part to claim 1. Mark this unclear.
• Current status: IBM is operating (not acquired, dissolved, or in bankruptcy). However, the business unit that owned this patent was divested: in 2015 IBM sold its Microelectronics Division — together with >16,000 patents and applications — to GLOBALFOUNDRIES. That divestiture is the origin of the assignment chain below. It was a corporate asset sale, not a bankruptcy fire-sale.

Assignment timeline

The USPTO Assignment Center does contain records for this patent; three post-issuance links are documented in the patent's own legal-events record. Caveat on correspondent data: my retrieval (Google Patents legal events + Plainsite + press) surfaced the reel/frame numbers, execution dates, and recording dates, but I was unable to retrieve the "correspondent of record" field (the recording attorney/agent and firm) for any of the three links. I therefore cannot perform the repeat-correspondent analysis properly, and I explicitly flag that below rather than guessing.

• 2015-06-29 (executed) / recorded 2015-09-03 — Reel 036550/0001

  • Conveyance: Assignment
  • Assignor: International Business Machines Corporation
  • Assignee: GLOBALFOUNDRIES U.S. 2 LLC (New York)
  • Correspondent: Not retrieved — could not confirm.
  • Context: Divestiture/fire-sale-scale asset transfer — part of IBM's sale of its Microelectronics Division and >16,000 patents to GlobalFoundries. This is a bulk portfolio assignment; US 8,659,093 is one asset among thousands.

• 2015-09-10 (executed) / recorded 2015-10-05 — Reel 036779/0001

  • Conveyance: Assignment
  • Assignors: GLOBALFOUNDRIES U.S. 2 LLC and GLOBALFOUNDRIES U.S. INC.
  • Assignee: GLOBALFOUNDRIES INC. (Cayman Islands)
  • Correspondent: Not retrieved — could not confirm.
  • Context: Internal corporate reorganization — consolidation of the U.S. entities' holdings into the Cayman parent. No change in ultimate beneficial owner.

• 2016-12-07 (executed) / recorded 2017-02-24 — Reel 041804/0940

  • Conveyance: Assignment
  • Assignor: GLOBALFOUNDRIES INC.
  • Assignee: AURIGA INNOVATIONS, INC. (Canada listing per Google; the litigating entity is a Delaware corporation with principal place of business in Ottawa, Canada)
  • Correspondent: Not retrieved — could not confirm. (This is the single most important missing data point for the "repeat correspondent" test; it should be pulled directly from Assignment Center.)
  • Context: Transfer-to-asserter. Auriga Innovations, Inc. is a wholly-owned subsidiary of Wi-LAN Inc., a Quarterhill company — a publicly traded patent-monetization business. The transfer was publicly announced by WiLAN on 2016-12-13 as the acquisition of a ~75-asset semiconductor-process patent portfolio from GlobalFoundries (per Mondaq's coverage of the Auriga v. Intel complaint).

Missing link: I could not locate the original inventor→IBM assignment (typically recorded shortly after the 2008-08-26 parent filing of 12/198,592). The Google Patents legal-events record starts at grant (2014-02-05, "STCF – patent grant") and shows only the three post-issuance transfers above; no pre-grant inventor assignment appears. Assume one exists but treat it as unverified.

Chain-of-title continuity note: The sibling US 13/405,598 → US 8,530,293 and the parent US 12/198,592 → US 8,169,031 carry the same title and traveled the same assignment chain, so the three recordings above should be expected to cover all family members.

Timeline diagram

timeline
    title Ownership of US 8659093
    2008 : Filed by IBM inventors
    2012 : Continuation application filed by IBM
    2014 : Patent US 8659093 issued
    2015 : IBM assigns to GlobalFoundries
         : Internal GF transfer to parent
    2016 : GlobalFoundries assigns to Auriga
    2017 : Assignment recorded at USPTO
    2020 : Auriga sues Intel and HP HPE
    2022 : Patent lapses for unpaid fee

NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT.
Patent moved out of an operating manufacturer into a licensing-only vehicle: Reel 041804/0940 conveys US 8,659,093 from GLOBALFOUNDRIES INC. to AURIGA INNOVATIONS, INC. (executed 2016-12-07). Auriga is not an operating company: it is (a) a wholly-owned subsidiary of Wi-LAN/Quarterhill, a patent-monetization business; (b) described in its own complaint as a Delaware corporation whose principal place of business is Ottawa, Canada (i.e., the parent's address, not a manufacturing site); and (c) a single-purpose litigation vehicle — it holds the ~75-asset GF portfolio and its only visible activity is suing. All three "tells" are documented, not inferred from the name.

2. Known asserter in the chain — PRESENT.
The current owner sits in the Wi-LAN corporate family. Wi-LAN Inc. / Quarterhill is explicitly on the reference NPE list provided in this task (Wi-LAN is named; Conversant/Mosaid and Quarterhill are the same lineage). Corroborated by press: WiLAN described itself as "one of the most successful patent monetization companies in the world." This is a direct list match, not a naming inference.

3. Repeat correspondent across the chain — UNCLEAR (data gap).
I could not retrieve the correspondent-of-record for Reels 036550/0001, 036779/0001, or 041804/0940. Without the recording attorney's name I cannot test recurrence. Recommend a direct pull from Assignment Center for these three reel/frames. Flagging this as an unresolved query, not a negative finding.

4. Cascading transfers — PARTIAL / WEAK.
Three recorded assignments in ~18 months (2015-06-29 → 2015-09-10 → 2016-12-07). However, the middle link (Reel 036779/0001) is a same-ownership internal reorganization, so the "chained unrelated LLCs" pattern is only partly present. The economically meaningful cascade is a single real transfer: IBM → GF (2015) → Auriga (2016).

5. Pre-litigation transfer — NOT PRESENT (for this patent).
Auriga took the portfolio 2016-12-07; the first and only Auriga suit, Auriga Innovations, Inc. v. Intel Corporation, HP Inc., and Hewlett Packard Enterprise Co., No. 6:20-cv-00779 (W.D. Tex., filed 2020-08-25), came ~44 months later — far outside the 6-month window. More importantly, US 8,659,093 was NOT among the asserted patents. The seven asserted patents were 7,763,932; 7,888,736; 8,234,594; 8,901,738; 8,957,479; 9,000,537; and 9,362,229. This resolves the uncertainty flagged in the earlier summary: US 8,659,093 was part of the Auriga portfolio but was not asserted in the 2020 Intel/HP/HPE case. The case was voluntarily dismissed 2020-10-01 following a WiLAN–Intel license agreement announced 2020-10-01.

6. Bankruptcy fire-sale — NOT PRESENT.
No assignor in the chain filed bankruptcy. The IBM→GF transfer was a business-unit divestiture (2015), and the GF→Auriga transfer was a portfolio monetization sale to WiLAN. None of these are Chapter 7/11 proceedings.

7. Privateering — PRESENT.
The chain runs from operating manufacturers (IBM, then GLOBALFOUNDRIES — a large foundry that continued to make chips after the assignment) into a monetization NPE (Auriga/WiLAN) that asserted the portfolio against Intel and its customers HP/HPE — i.e., against competitors in the semiconductor market. GF's dual role (operating foundry and seller of the asserted portfolio to an NPE) is the classic privateering shape. Note this is portfolio-level evidence: the Auriga v. Intel suit targeted seven sibling patents, not the '093 patent itself.

8. Defensive aggregator — NOT PRESENT.
The chain terminates at Auriga/WiLAN, an asserting NPE. It does not end at RPX, AST, LOT Network, Unified Patents, or OIN. No inverse/neutralization signal.

Additional signal — non-maintenance of the asset: the last recorded fee payment was the 4-year maintenance fee on 2017-08-10. No subsequent fee was paid; the patent lapsed for failure to pay maintenance fees, effective 2022-02-25 (recorded 2022-04-04, "LAPS"/"STCH"). A monetization vehicle letting the asset go is consistent with it never producing licensing revenue (it was not asserted in the 2020 campaign).

Verdict

NPE — high confidence.

Two independent strong signals are present and documented by reel/frame: (i) an operating-manufacturer-to-licensing-vehicle transfer — Reel 041804/0940, executed 2016-12-07, GLOBALFOUNDRIES INC. → AURIGA INNOVATIONS, INC., a Delaware shell with an Ottawa, Canada address that exists solely to hold and assert the ~75-asset portfolio; and (ii) a direct match to a listed NPE — Auriga is a wholly-owned subsidiary of Wi-LAN / Quarterhill, a self-described patent-monetization company. The privateering shape (IBM/GF → Wi-LAN affiliate → assertion against Intel/HP/HPE) and the unmaintained, never-asserted status of this specific patent reinforce the call. The only material gap is the correspondent-of-record data (Reels 036550/0001, 036779/0001, 041804/0940), which could add a third signal if pulled directly.

Verify at: USPTO Assignment Center — https://assignmentcenter.uspto.gov/ (search patent 8659093; alternatively https://assignment.uspto.gov/patent/index.html → search "8659093"). Search by the reel/frames above: 036550/0001, 036779/0001, 041804/0940.

Contradiction flag (resolved, not open): The earlier analysis section listed it as an explicit uncertainty whether US 8,659,093 was among the seven patents asserted in Auriga v. Intel. This analysis resolves that item: the seven asserted patents are 7,763,932; 7,888,736; 8,234,594; 8,901,738; 8,957,479; 9,000,537; and 9,362,229 — US 8,659,093 is not one of them. No other contradictions with the prior sections were found; the bibliographic, family, and status data all agree.

I'll verify the citation set against public sources before mapping each reference to the claims.

Let me verify a few more of the cited references' dates and disclosures.

Prior-Art Anticipation Analysis — US 8,659,093 B2 (§ 102)

Scope note. I searched for the literal number 8659093. The results returned the correct patent — "Continuous metal semiconductor alloy via for interconnects" — and no other patent. All identifiers below are reproduced literally; I have not auto-corrected anything. The "References Cited" set is taken from the patent's own face (Google Patents / Justia, which mirror the USPTO record) and from the authoritative full text in this file; I did not obtain a separate live PatentCenter "References Cited" printout, so treat the citation list as recorded-on-the-face, not as an independent database pull.

This section deliberately builds on — and does not repeat — the bibliographic, family, assignment, and § 103 work already produced.

1. The § 102 framework that controls this patent

Two structural facts drive the entire § 102 analysis:

1. All nine claims descend from claim 1. Claim 1 is the only independent claim. Therefore, no dependent claim can be anticipated unless claim 1's every limitation is first met by the same single reference. If no reference anticipates claim 1, no reference anticipates claims 2–9.
2. The critical date is 2008-08-26 — the '093 application (13/405,739, filed 2012-02-27) is a continuation of Ser. No. 12/198,592, filed 2008-08-26 (stated in "Related Application"). Pre-AIA § 102 governs (filed before 2013-03-16). So:
   • § 102(b): printed publication/patent more than one year before 2008-08-26, i.e., before 2007-08-26.
   • § 102(a): publication before 2008-08-26 but within one year.
   • § 102(e): U.S. patent/publication with an earlier effective U.S. filing date (does not reach foreign filings).

The claim-1 limitations that carry the weight (using the labels from the earlier § 103 section): A FET+gate+S/D+spacer on gate sidewall; B single-crystal metal semiconductor alloy; C lower portion inside the S/D upper surface; D vertical pillar of unitary construction containing no material interface with the lower portion; E pillar maintains the same cross-section along the vertical axis (non-tapered); F pillar does not contact the spacer's outer surface; G pillar narrower than the lower portion; H dielectric whose upper surface is above the FET's topmost surface, embedding the pillar, with the pillar top directly contacting and exposed at that upper surface; I metal line on the pillar top and on the dielectric upper surface.

2. Anticipation verdict, reference by reference

Bottom line up front: no single cited reference anticipates any of claims 1–9. Every reference fails at least one of B (single-crystal), D (unitary/no-interface), and the F/G geometry; most fail far more. The examiner's citation set is § 103 fodder, which is consistent with the § 103 combination analysis already produced. Below is the per-reference accounting.

2A. U.S. patents and pre-grant publications (the 15 "Patent Citations")

2B. Non-patent citations (the 3 "Non-Patent Citations")

Also cited within the '093 specification itself (not on the face): E. I. Givargizov, "Highly Anisotropic Crystals," Kluwer Academic Publishers, 1986 — § 102(b) printed publication; discloses the VLS (vapor–liquid–solid) mechanism for anisotropic nanowire growth generally. It anticipates no claim but supplies the growth-mechanism background.

3. The one serious § 102 argument — and why it still falls short

US 2007/0105333 A1 (Gutsche) is the only reference that can even be argued as anticipatory, and the argument runs on inherency:

• Gutsche discloses catalyst-mediated growth of a free-standing conductive nanoelement from a contact region in a semiconductor substrate, "a complete siliciding" of a silicon nanoelement, a silicide at the surface of the contact region, an SiO₂ ILD "planarized as far as the surface of the nanoelement," and a bit line connected above. Read generously, that is the architecture of claim 1's elements C, H, I and the process that yields E, F, G.
• To convert that into anticipation of claim 1, one must argue that completely siliciding a single-crystal Si nanowire inherently produces (i) a single-crystal metal semiconductor alloy (B) and (ii) a silicide column contiguous and interface-free with the contact-region silicide (D, unitary construction, "no material interface therebetween").

That inherency step is not sound as a matter of disclosure. Gutsche never states "single-crystal," and silicidation of a nanowire does not invariably yield a single-crystal (one-grain) product — the '093 patent itself treats single-crystallinity as an achieved, non-inevitable result ("in some cases the metal semiconductor alloy … formed with nanowires can be single-crystal (one long grain)"). Where a claim limitation is the point of novelty and the reference discloses at most a genus from which the limitation is a non-inevitable species, anticipation fails and the reference belongs to § 103. That is exactly the posture here — and it is precisely why the earlier § 103 combination (Gutsche + Decker, further in view of Basceri) was assembled: Decker supplies the missing single-crystal teaching and the express "contiguous growth … reduce contact resistance to a minimum value" motivation, neither of which Gutsche contains.

The same inherency problem defeats any attempt to read Basceri '473 (a filled contact opening) or Sharma/Kamins '971 (isolated electrode pairs) onto claim 1.

4. Practical takeaways on the § 102 record

1. No anticipation of any of claims 1–9. Because claim 1 is the sole independent claim and carries the single-crystal + unitary/no-interface + geometry limitations, and because no single reference discloses all of them, the § 102 case is empty. The citations' value is § 103, as set out in the prior section.
2. Two references are date-vulnerable and should be checked before anyone relies on them:
   • KR 2009/0016432 A (published 2009-02-13) — published after the critical date and a foreign publication, so it appears not citable at all on the present record.
   • US 2008/0303167 A1 (ASE) and US 2009/0108251 A1 (Kabir) — published after the critical date; citable only under § 102(e), and only if their U.S. filing dates (not merely the Google "priority" fields, which are assumptions) precede 2008-08-26. Verify each against its filing receipt.
3. One "reference" is not prior art — N3, the Nov. 26, 2012 Office Action in sibling 13/405,598. It has no § 102 or § 103 weight.
4. The single most dangerous reference for the patentee is Gutsche '333 paired with Decker (APL 2004) — Gutsche on architecture and complete silicidation, Decker on single-crystallinity and the express interface-elimination rationale. That pairing is a § 103 combination, not a § 102 anticipation.
5. The single most useful reference for the patentee's defense of validity is the same Gutsche '333 — because the only thing standing between Gutsche and clean anticipation of claim 1 is the express words "single-crystal" and "no material interface," and the patentee can argue those are neither taught nor inherent in Gutsche.

Confidence and sourcing

• High confidence: the citation list and its dates as recorded on the patent face (Google Patents/Justia) and in the authoritative full text here; the § 102 critical date (2008-08-26 via the 12/198,592 continuation); the § 102(b)/(a)/(e) classification of each reference from its published/granted date; the close reading of Gutsche, Basceri, and Decker content (verified above against primary sources — https://patents.google.com/patent/US20070105333 and https://patents.google.com/patent/US20060046473).
• Lower confidence / to verify from primary documents: the U.S. filing dates of Kabir '251 and ASE '167 for § 102(e) purposes (Google "priority date" is an assumption, not proof); the exact inventorship spelling on US 6,348,390 (Justia shows "Wu"; the abstract matches the Acer family) and on US 2004/0256662 (Justia shows "Black et al." for the application, while the same subject matter is associated with Guarini in the IEDM paper and the IEDM citation); and whether KR 2009/0016432 A has any qualifying earlier public-availability event.
• Not fabricated: I have not assigned an anticipatory disclosure to any reference that does not contain it, nor supplied proceeding/document numbers beyond those printed on the patent.

Not legal advice. The § 102(e) dates for Kabir '251 and ASE '167, and the citable status of KR '432, should be confirmed against USPTO Patent Center file wrappers and the actual foreign/U.S. filing receipts before this is relied on adversarially.

No contradiction with the earlier sections: the bibliographic, family, claim-tree, assignee, and § 103 material produced previously is consistent with everything found here. This section adds the per-reference § 102 date classification and resolves the "which reference, if any, anticipates?" question to none — consistent with the earlier § 103 conclusion that the closest reference (Gutsche) is defeated by the same single-crystal/no-interface language addressed there.

I'll ground this obviousness analysis by verifying the content of the examiner-cited and key prior-art references listed on the patent's face.

Obviousness Analysis — US 8,659,093 B2 under 35 U.S.C. § 103

Critical date: 2008-08-26 (the '093 application is a continuation of Ser. No. 12/198,592, filed 2008-08-26, and claims no earlier benefit). All prior-art dates below are assessed against that date. This builds directly on the bibliographic and claim-mapping work already produced; I don't repeat the family/assignment history here.

Framing caveat: This is an analytical exercise using the reference set printed on the patent's face ("Patent Citations (15)," "Non-Patent Citations (3)"). I do not have the '093 file wrapper, so I cannot say which references the examiner actually applied, or in what combination. The combinations below are constructed from the references' own disclosures as I verified them.

1. What must be shown

Claim 1 is the only independent claim; claims 2–9 depend from it. The limitations most likely to carry the patent's weight are:

The obviousness case reduces to whether D (interface-free, unitary, single-crystal) plus B, C, E, F, G were known or would have been obvious.

2. The reference set, and what it actually discloses

I verified content for the four most load-bearing references; the remainder I have only by title/abstract from the patent's face (flagging that explicitly).

2.1 The strongest reference: US 2007/0105333 A1 — Gutsche (Infineon/Qimonda)

patents.google.com/patent/US20070105333A1 · also patents-review.com summary · family member US 7,998,858 B2 (from Ser. No. 11/588,769); DE 10 2005 051 973 B3.

Gutsche is marked "cited by examiner" on the '093 face, and on verified content it maps onto claim 1 almost element-for-element:

• "by forming a catalyst on a contact region in a carrier substrate, subsequently forming a free-standing electrically conductive nanoelement between the catalyst and the contact region, and finally embedding the free-standing nanoelement in a dielectric layer, it is possible … to produce vertical interconnect structures with minimal dimensions in self-aligning fashion." → elements D-adjacent, F, G (catalyst-dot diameter sets the pillar width).
• "a metal-semiconductor compound, and particularly when using silicon as semiconductor material so-called silicides, may be formed at the surface of the contact region." → element C.
• "When using silicon nanoelements, a complete siliciding is preferably carried out, whereby the electrical properties of the interconnect structure can be improved further and, in particular, an interconnect resistance is significantly reduced." → the motivation for converting the entire column (element D), not just a bottom silicide layer.
• "As the dielectric layer, SiO₂ is preferably deposited over the whole area … and subsequently planarized as far as the surface of the nanoelement." → element H (exactly: dielectric planarized to expose the pillar top).
• "a bit line layer is furthermore formed at least in the dielectric layer, which is electrically connected to the further contact region"; memory element "formed at the surface of the dielectric layer and connected via the nanoelement." → element I.
• "semiconductor layers deposited epitaxially may additionally be formed on the source/drain regions" and "two selection transistors … a common diffusion region of the selection transistors." → element A/C context; epitaxial variant.
• "nanowires, nanotubes or nanofibers are preferably produced as nanoelements"; "the catalyst may be coagulated … self-aligned structure miniaturization … significantly reduces a cross-sectional area." → element E (uniform-diameter nanoelement) and G (pillar narrower than the contact region).

What Gutsche does not expressly say: that the silicide at the contact-region surface and the silicided nanoelement merge into one grain/interface-free body, and that the result is single-crystal. Those are the two carve-outs that map onto the "single-crystal" and "no material interface" language — i.e., the language that appears to have been drafted to distinguish this art.

2.2 The motivation linchpin: Decker et al. (non-patent literature)

"Directed growth of nickel silicide nanowires," Appl. Phys. Lett. 84(8), 1389–1391 (Feb. 23, 2004), DOI 10.1063/1.1650877 · AIP abstract.

This examiner-cited NPL is unusually on-point, and in two ways:

1. Single-crystal limitation (B): "These NWs were found to be single crystal … Depending on growth conditions, single-phase NiSi, Ni₂Si, and Ni₃Si₂ NWs were detected."
2. The "no material interface" motivation (D), stated as an express design goal: "A contiguous growth of Ni silicide and silicon NWs would reduce contact resistance to a minimum value and also potentially reduce dislocation generation due to the lattice misfit." And in the introduction: silicides are used for "electrical contacts, polycide gates, and local interconnects," with "Ni silicide, which offers lower contact resistance, stress, and process temperature, as well as less Si consumption."
3. BEOL compatibility: growth at 320–420 °C (best range 370–420 °C) — squarely inside the ~400 °C BEOL budget the '093 specification invokes to discredit carbon nanotubes.
4. Ohmic/low-resistance contact (claims 4–6): Decker measured the I–V of individual NWs and "estimated the upper limit of the contact resistivity between the SNW and metal contact to be about 10⁻⁴ Ω cm²."

2.3 US 2006/0046473 A1 — Basceri et al. (Micron)

patents.google.com/patent/US20060046473A1 — granted as US 7,241,705 B2 / US 8,084,142 / US 8,409,933. Examiner-cited.

Verified: a FET "comprising source/drain regions 18 and 20 … a transistor gate construction 24 … insulative sidewall spacers 34 and an insulative cap 36"; a "dielectric layer 38 … formed over transistor gate 16 and source/drain regions"; a "contact opening 40 … formed into dielectric layer 38"; transformation of gate dielectric material over the source/drain to "conductive metal silicides" in conductive contact with source/drain region 20; and "conductive material 46 … within contact opening 40 in electrical connection with source/drain region 20 through changed extending material 31." It also discloses the vertical-FET variant (FIG. 9) and local interconnects connecting source/drains.

This is the reference that supplies the otherwise-conventional elements A and H expressly and with a spacer, including the "contact through a dielectric opening over the gate and source/drain" architecture.

2.4 US 2008/0173971 A1 — Sharma & Kamins (HP)

patents.google.com/patent/US20080173971A1 — granted US 7,544,591 B2.

Verified: "selectively epitaxially growing a semiconductor feature from the semiconductor layer through the window" in an insulating film; the feature has "a vertical stem … and a ledge … a lateral epitaxial overgrowth (LEO) of the vertical stem on the insulating film"; "grown from a horizontal surface of one of the electrodes to a facing horizontal surface"; "a [111] oriented semiconductor crystal lattice … nanowires perpendicular to the (111) horizontal surfaces"; other orientations "including, but not limited to, a [110] orientation and a [100] orientation." It also expressly frames the problem the '093 solves: "efforts to integrate nanowires into device structures essentially have been limited to a research environment; these efforts are not conducive to … reproducible mass-fabrication."

This reference supports the epitaxial embodiment of the '093 (FIGS. 2A–2G) and the "unitary/seamless" and non-tapered vertical-stem concepts, plus claim 7's (100) orientation.

2.5 Remaining face references (title/abstract only in my check — treat with caution)

• US 2004/0256662 A1 (IBM, Guarini) and Guarini et al., IEDM 2003, p. 541 — templated self-assembly (diblock copolymer) for patterning catalyst dots. These are the exact references the '093 specification itself cites for forming catalyst dots, i.e., its own admitted technique for making the VLS pillar.
• US 2009/0108251 A1 (Kabir), priority 2005-04-25, "Controlled growth of a nanostructure on a substrate" — examiner-cited. I could not retrieve its disclosure; title indicates catalyst-positioned nanostructure growth (nanowire placement control), which is exactly the FIG. 1B–1C step.
• KR 2009/0016432 A (Yonsei University, priority 2007-08-10) — "Low Contact Resistance Silicon Nanowires and Manufacturing Method Thereof." I could not retrieve its disclosure. See §6 for a date problem with this reference.
• US 6,348,390 B1 (Acer) — recessed self-aligned silicide contact with extended source/drain junctions → salicide-to-source/drain with self-alignment past the spacer.
• US 2005/0156238 A1 (TSMC) — silicide gate transistors; US 2005/0151165 A1 (IBM) — self-aligned SiGe raised extrinsic base (selective epi through an opening in a dielectric); US 2004/0097047 A1 (IBM) — in-situ doped raised source/drain; US 6,939,751 B2 (IBM) — thin-SOI recessed channel; US 2007/0018205 A1 (IBM) — embedded SiGe source/drain; US 2008/0303167 A1 (ASE) — high-aspect-ratio via in low-k dielectric; US 2006/0186451 A1 (Düsberg) and US 2007/0045712 A1 (Haller) — memory cell/vertical structures. These are secondary; they fill in conventional elements.

One entry is not prior art at all: the third "Non-Patent Citation," "Office Action dated Nov. 26, 2012 received in … U.S. Appl. No. 13/405,598" — that is a co-pending sibling prosecution document (13/405,598 → US 8,530,293), not a printed publication. It cannot support a § 103 rejection; if it appears in any examiner's form as a basis, that is an error worth flagging.

3. The obviousness combinations

Combination 1 (primary — nanowire route): Gutsche '333 + Decker + Basceri '473 (+ Guarini/'662 or Kabir '251)

Combination 2 (alternative — epitaxial route): Sharma/Kamins '971 (US 7,544,591) + Basceri '473 + Decker (+ IBM '165)

Sharma supplies selective epitaxy through a window, the vertical stem of uniform cross-section, lateral overgrowth (the "lower portion" of claim 1's geometry, i.e., a wider base than stem), and the crystallographic teaching of (111)/(100)/(110); Basceri supplies the FET+spacer+dielectric-over-gate context and the silicide conversion of an epitaxial/material region in contact with the source/drain; Decker again supplies single-crystal silicide and the "contiguous = minimum contact resistance" motivation. This is the FIG. 2A–2G route.

Combination 3 (primary — conventional-contact-architecture route): Basceri '473 + Gutsche + Decker

Basceri is used as the base structure (FET + spacer + dielectric + contact opening + silicide in contact with S/D + metal in the opening); Gutsche supplies replacing the filled opening with a self-aligned grown nanoelement whose top is exposed by planarizing the dielectric; Decker supplies the single-crystal and interface-elimination teaching. This combination is attractive because Basceri is the reference for the "contact opening through a dielectric over the gate" environment that claim 1 assumes.

4. Motivation to combine (the § 103 "why")

The Federal Circuit/KSR rationales that apply here, in order of strength:

1. Express teaching, same purpose (the strongest). Decker literally states the goal the '093 claims as its advantage: "A contiguous growth of Ni silicide and silicon NWs would reduce contact resistance to a minimum value and also potentially reduce dislocation generation due to the lattice misfit." One of ordinary skill reading Decker in 2008 had a written invitation to merge the pillar and the underlying region into one silicide body — i.e., to eliminate the material interface recited in claim 1 element D.
2. Known technique improving a similar device in the same way. Gutsche seeks lower interconnect resistance by complete silicidation of a silicon nanoelement; Decker shows single-crystal NiSi NWs with ~10⁻⁴ Ω·cm² contact resistivity grown at 320–420 °C. Substituting Decker's Ni-silicide chemistry for Gutsche's generic "complete siliciding" is a simple substitution of one known silicide system for another with a predictable result (lower resistance), and Decker itself recommends Ni silicide over Ti/Co silicides for "lower contact resistance, stress, and process temperature."
3. Design incentive created by the scaling problem. Both the '093 and the references recognize the same problem: sub-30 nm vias, sidewall roughness, polycrystalline-metal grains, and the ~400 °C BEOL ceiling. Decker's 320–420 °C process and Gutsche's catalyst-defined, self-aligned, non-tapered nanoelement are direct answers to that problem; combining them is "the product not of innovation but of ordinary skill" (KSR Int'l v. Teleflex).
4. Reasonable expectation of success / predictable result. Everything is in the same field (MOL/BEOL contacts to FET source/drains), with overlapping materials (Si, NiSi, SiO₂ ILD), overlapping temperatures (Decker's range is within the BEOL budget), and predictable geometry (a catalyst- or window-defined column has a constant cross-section and is narrower than the contacted diffusion).
5. Result-effective-variable / self-alignment. Gutsche's own words — "self-aligning fashion," "self-aligning structure miniaturization" — supply the case for elements F and G (pillar narrower than the diffusion, and not contacting the gate spacer's outer surface), which are the natural geometric consequence of growing the pillar from a catalyst on the diffusion rather than etching a tapered via between the spacers.
6. No teaching away. The specification's discussion of carbon nanotubes (700 °C, O₂-plasma incompatibility) is a teaching against CNTs, not against silicide nanowire/expitaxial vias; it does not disqualify Gutsche+Decker.

5. Dependent-claim analysis

• Claim 2 (metal silicide): Decker (NiSi, Ni₂Si, Ni₃Si₂), Gutsche (silicides), Basceri (conductive metal silicides). Obvious.
• Claim 3 (metal germanide): Not expressly in the verified set; Germanide is the species counterpart from a Ge-containing substrate (a substrate alternative the '093's own spec and Basceri's substrate alternatives contemplate). Obvious as an alternative species absent evidence of unexpected results.
• Claims 4–6 (conductive path; ohmic; linear potential): Weakly supported as positive recitations, but Decker is close to dispositive on the underlying rationale — its stated goal of contiguous silicide/Si growth "to reduce contact resistance to a minimum" and the "no electrical junctions due to dissimilar materials" framing in the '093 spec are the same thought. Decker's measured I–V on single NWs supports linearity/ohmicity.
• Claim 7 (Si (100)): Sharma/Kamins expressly teaches [100]-oriented electrode surfaces; Basceri's substrate is monocrystalline silicon. Routine choice.
• Claim 8 (alloy also atop the gate electrode): Both Gutsche and the '093 spec treat catalyst placement on the gate as an option of the same process; IBM '047 (raised in-situ-doped S/D) and IBM '165 (selective epi on an exposed semiconductor surface) support epi from gate polysilicon. Obvious as an obvious aggregation for a known benefit.
• Claim 9 (alloy is a metal semiconductor alloy nanowire): Decker, verbatim — nickel silicide nanowires.

6. Where the record is thin, contradictory, or problematic (for the other side to exploit)

These are the points I would expect a patentee (or an examiner reconsidering) to press, and they are also the places where the record itself is unreliable:

1. The "no material interface / unitary construction" gap. Gutsche discloses a silicide at the contact-region surface and separately prefers complete siliciding of the nanoelement. Whether the two merge into one grain/one body is an inference, not an express disclosure. The obviousness case therefore leans heavily on Decker's "contiguous growth" sentence plus the inherency/natural-result argument — a combination argument, not anticipation.
2. "Single-crystal" is the clearest surviving differentiator. Gutsche says nothing about single-crystallinity; Decker does, but in a Ni-foil/Ni-film/SiO₂/Si-wafer, non-device, two-metal-pad context — not to a FET source/drain. The patentee will argue that nothing in the art teaches a single-crystal silicide contact column integrated to a transistor diffusion, and the '093 spec makes that its central technical effect ("one long grain," no grain-boundary scattering).
3. Date problem with KR 2009/0016432 A. Its publication date is 2009-02-13, after the '093 critical date of 2008-08-26. Under pre-AIA § 102, a Korean published application is § 102(a)/(b) art only as of its publication date, and § 102(e) reaches only U.S. filings (and PCT applications designating the U.S. that were published). On the face of the record supplied, KR20090016432A may not be citable unless a qualifying U.S. counterpart predates 2008-08-26. If an examiner relied on it as the primary contact-resistance-nanowire reference, that reliance is vulnerable.
4. Same problem, less severe, for US 2009/0108251 A1 (Kabir) (published 2009-04-30) and US 2008/0303167 A1 (ASE) (published 2008-12-11). Each can only be prior art via § 102(e) if its U.S. filing/priority predates the critical date. Kabir is listed with a 2005-04-25 priority, which is consistent with § 102(e) status; the ASE reference (filed 2007-06-08) similarly. But those statuses should be verified against the actual U.S. filing receipts — the Google "priority date" field is not proof of a § 102(e) date.
5. The "sibling Office Action" is not prior art (see §2.5) — a co-pending-application prosecution paper has no § 102/§ 103 weight.
6. My verified set is partial. I confirmed full disclosures for Gutsche '333, Decker, Basceri '473, and Sharma/Kamins '971. For US 6,348,390 B1, US 2005/0156238 A1, US 2005/0151165 A1, US 2004/0097047 A1, US 6,939,751 B2, US 2007/0018205 A1, US 2006/0186451 A1, US 2007/0045712 A1, US 2008/0303167 A1, US 2009/0108251 A1, and KR 2009/0016432 A, I have only the titles/abstracts printed on the '093 face. Those references should be pulled and read before this analysis is relied on for any adversarial purpose. I am not going to assert disclosures I did not read.

No contradiction with the earlier sections: the bibliographic, family, claim-tree, and assignee material generated previously is consistent with everything found here. The one addition I would make to that record is the §6(3)–(4) dating observation, which the earlier sections did not address.

7. Bottom line

On the verified record, claim 1 is, in my assessment, more likely than not to have been obvious over Gutsche US 2007/0105333 A1 in view of Decker et al. (APL 2004), further in view of Basceri US 2006/0046473 A1 — because Gutsche supplies the architecture (catalyst-defined, non-tapered nanoelement grown from a contact region, embedded in an SiO₂ ILD planarized to expose the element's top, with a bit line/metal above and a silicide at the contact region, plus "complete siliciding" for reduced resistance), Basceri supplies the express FET-with-spacer-through-dielectric contact environment, and Decker supplies both the missing single-crystal limitation and, in its own words, the express motivation to make the pillar and the underlying silicide contiguous so that contact resistance is reduced "to a minimum value." The Sharma/Kamins reference supplies an independent route to the same result via epitaxy for the FIG. 2A–2G embodiment.

The limitations that keep this from being a clean anticipation are the "single-crystal" and "unitary construction containing no material interface" language, and the two self-alignment geometries (F and G). Those are, however, exactly the limitations Decker's stated design goal and Gutsche's "complete siliciding"/"self-aligning" language were aimed at — so the strongest defense of the claim is likely to be that no single reference, and no articulated combination, quite closes the single-crystal-and-interface-free gap for an integrated transistor contact, rather than that the references are missing entirely.

Not legal advice. Verify the reference disclosures in §6(6) and the § 102 date status of the post-critical-date publications against primary documents (USPTO Patent Center for the '093 file wrapper, and the actual filing receipts for Kabir '251 / KR '432 / ASE '167) before relying on this.