US 8510749

I'll run targeted searches for this exact patent number and for any litigation/docket references.

Let me try to retrieve the complete claim set, since the fetched text was truncated at claim 5.

US Patent 8,510,749 — Analyst Summary

Source discipline note: The primary facts below come from the full patent text of US8510749B2 (Google Patents, fetched 2026‑10‑01), which is the authoritative record here. Where I searched for dockets and did not find authoritative information, I say so explicitly rather than infer.

1. Bibliographic data

Naming caution: Do not confuse this patent with U.S. Patent 7,072,849 ("'849 patent," Method for Presenting Advertising in an Interactive Service), which is the patent at issue in the IBM v. Chewy declaratory‑judgment litigation (Chewy, Inc. v. IBM, No. 22‑1756, Fed. Cir. Mar. 5, 2024). That is a different patent with a coincidentally similar trailing digits. Searches for "8510749 litigation" surface that case; it does not involve US 8,510,749.

2. Abstract (as issued)

A system, and computer usable program product for a framework for scheduling tasks in a multi-core processor or multiprocessor system are provided in the illustrative embodiments. A thread is selected according to an order in a scheduling discipline, the thread being a thread of an application executing in the data processing system, the thread forming the leader thread in a bundle of threads. A value of a core attribute in a set of core attributes is determined according to a corresponding thread attribute in a set of thread attributes associated with the leader thread. A determination is made whether a second thread can be added to the bundle such that the bundle including the second thread will satisfy a policy. If the determining is affirmative, the second thread is added to the bundle. The bundle is scheduled for execution using a core of the multi‑core processor.

3. Plain-language overview

The patent addresses a practical conflict in multi‑core/multiprocessor scheduling: a modern core can be tuned for frequency, voltage, and simultaneous‑multithreading (SMT) level, but hardware constraints require all SMT threads on one core to run at the same frequency/voltage. So a scheduler cannot simply pick the individually best thread — it must assemble a group (a "bundle") of threads that are mutually compatible with one core's settings.

The disclosure's approach:

1. Order the threads using the governing scheduling discipline (e.g., round‑robin, priority, MLFQ), placed into an n‑dimensional ordering structure ("sub‑queues") keyed on thread attributes such as desired frequency, desired SMT level, and priority (FIG. 5).
2. Pick the next thread in that order and make it the "leader" of a new bundle.
3. Set the core's attributes from the leader's attributes (e.g., core frequency/voltage := leader's desired frequency/voltage).
4. Try to add more threads from the order, one at a time, only if adding each one still satisfies a constraint/compatibility policy — examples being "within a tolerance value of the leader‑set core attribute," "at most equal to," "identical to," or "diverse from the other bundle members" (e.g., don't co‑schedule two I/O‑intensive threads).
5. Stop and schedule when either the bundle is projected to hit a designated utilization level for the core/other resources, or no further thread can be compatibly added. The bundle then executes on a core.

The stated benefits are better utilization of cores/resources and more efficient reconciliation of power‑management goals with per‑core licensing structures. The patent frames the invention across FIGS. 6–9 as four variant flows, all sharing the select‑leader → set core attributes → test candidacy of next thread → test utilization → schedule bundle loop.

4. Independent claims — scope

Important limitation on my answer: The claim text available to me was truncated after claim 5. What I can state with confidence:

• The patent contains 21 claims (per the record).
• Claim 1 is independent and is drafted as a computer usable program product (a non‑transitory computer usable storage medium including computer usable code) for scheduling threads in a data processing system having a multi‑core processor.

Claim 1 (independent) — plain-language scope:
Code for: (a) selecting a first thread according to an order in a scheduling discipline, where the thread is from an application executing in the system, and that thread becomes the leader thread of a bundle; (b) determining a value of a core attribute (from a set of core attributes) according to a corresponding thread attribute of the leader; (c) determining whether a second thread can be added to the bundle such that the bundle including it satisfies a policy; (d) responsive to an affirmative determination, adding the second thread to the bundle; and (e) scheduling the bundle for execution on a core. Claim 1 expressly requires that the policy be a compatibility policy comprising determining whether a thread attribute of the second thread is within a tolerance value of the corresponding core attribute as set by the leader.

Dependent claims 2–4 (all depending from claim 1) each specify alternate compatibility‑policy formulations:

• Claim 2 — thread attribute value at most equal to the corresponding leader‑set core attribute value.
• Claim 3 — thread attribute value identical to the corresponding leader‑set core attribute value.
• Claim 4 — thread attribute diverse from a corresponding thread attribute of another thread already in the bundle.
• Claim 5 — adds determining whether the bundle has enough threads to utilize a resource at a designated utilization level (the specification identifies the resource as a core), with scheduling of the bundle responsive to that sufficiency.

Claims 6–21: Not available in the retrieved text. From the disclosure's structure one would expect additional dependent claims (e.g., adding a third thread to the bundle subject to the policy, core attribute = voltage/frequency/SMT level, order = priority order, discipline = round‑robin, multiprocessor/multi‑core equivalents) and very likely at least one further independent claim in method and/or data‑processing‑system form — the specification repeatedly states that "an apparatus, and computer program product are provided." I cannot confirm the number, type, or wording of those additional independent claims from the truncated record, and I will not fabricate them. Confirming them requires the full printed claim set (e.g., USPTO PatentCenter / Patent Public Search, or the granted-PDF claim column).

5. Litigation / docket search result

I searched for US 8,510,749 in litigation and CAFC contexts, including 2026 docket material. I found no CAFC 2026 docket entry, appeal, IPR, or district‑court case naming US 8,510,749 specifically. The patent's recorded legal status is Expired – Fee Related with an adjusted expiration of 2032‑04‑25 (the adjusted date reflects PTA/terminal‑disclaimer bookkeeping in the record, not a change to the 2013 grant date).

The enforcement activity that surfaces in searches under similar identifiers belongs to IBM's advertising/interactive‑service patent family (notably US 7,072,849, asserted against Chewy; also 9,569,414, 7,076,443, 6,704,034, and the IBM v. Zillow and IBM v. Virtamove matters). None of those involve the multicore‑scheduling patent at issue here.

Caveat: Absence of a hit in my searches is not proof that no litigation ever existed. Docket databases are not fully indexed in general web search, and a case could exist under a court caption that does not reproduce the patent number in the indexed text. If you need a definitive litigation check, PACER / the CAFC docket (the "RSS/CM‑ECF" docket search by patent number) is the authoritative source.

6. Confidence assessment

• High confidence: title, assignee, inventors, application number 12/789,015, filing date 2010‑05‑27, issue date 2013‑08‑13, publication US 20110296423 A1, recorded status, abstract, the substance of claim 1 and claims 2–5, and the FIG. 3–9 framework content.
• Medium confidence: the interpretation that 13/413,768 (US 8,990,831) is a later‑filed family member claiming priority to this disclosure — the Google Patents timeline labels it "Priority to," which forward‑citation timelines can render ambiguously; a continuity check via PatentCenter would confirm direction.
• Uncertain / not established: the exact text and count of independent claims beyond claim 1, and the existence (or absence) of any litigation involving this patent.

I'll search for litigation involving US patent 8510749.

Let me search more specifically on litigation databases and patent-specific sources.

Let me try more targeted searches on the specific patent number and litigation-specific databases.

Search Results: Litigation Involving U.S. Patent No. 8,510,749

Based on my searches, I found no litigation involving U.S. Patent No. 8,510,749.

What I searched

I ran multiple targeted queries across litigation-oriented sources, including:

• General patent-litigation queries pairing "8510749" / "8,510,749" with litigation, lawsuit, infringement, and complaint terms
• Queries against Unified Patents' portal/PTAB and litigation caselist indices
• Queries combining the patent number with its title ("Framework for scheduling multicore processors") and its assignee (IBM)

What I found — and important disambiguation

Several results mentioning a "'749 patent" surfaced, but none of them refer to U.S. 8,510,749. I am applying the rule to interpret identifiers literally and not auto-correct them:

None of these are assertions, complaints, or proceedings involving U.S. 8,510,749.

Additional context on the patent itself (from the authoritative patent record)

• Patent: U.S. 8,510,749 B2 — "Framework for scheduling multicore processors"
• Assignee: International Business Machines Corporation
• Inventors: Elnozahy, Hanson, Peterson, Rawson III, Ware
• Filing/Priority date: 2010-05-27
• Grant date: 2013-08-13
• Legal status (per the source fetched): Expired – Fee Related, adjusted expiration 2032-04-25
• Related continuation: U.S. 8,990,831 (from U.S. App. 13/413,768, priority 2012-03-07)

Caveats

1. Confidence level: I cannot claim with absolute certainty that zero litigation exists. Free web searches do not exhaustively index PACER, and I did not obtain a direct, confirmed docket search hit for this exact number.
2. Verification recommendation: To confirm definitively, run a docket-level search on PACER, Westlaw/Lexis CourtLink, Docket Alarm, or Unified Patents' litigation portal using the exact string "8,510,749." A negative result across those authoritative systems would establish that this specific patent has not been asserted in a U.S. district court case.
3. No plaintiff, defendant, jurisdiction, case number, filing date, or outcome can be reported because no case matched the specific patent number 8,510,749.

Bottom line: On the record available, there is no known litigation involving U.S. Patent No. 8,510,749. The patent appears to be an unasserted IBM portfolio asset (now lapsed for failure to pay maintenance fees).

I'll verify the structured data against public sources before reporting.

Let me run targeted follow-up searches to rule out less obvious proceedings.

Proceedings overview

Total AIA trial proceedings on file for US 8,510,0749: zero. The structured "PTAB proceedings on file" block sourced from the USPTO Open Data Portal returns no AIA trials, and my independent web verification found no IPR, PGR, or CBM petition ever filed against this patent — so there is nothing in any of the five status buckets (0 active / 0 invalidated / 0 sustained / 0 settled / 0 institution-denied). The bottom-line defensive posture is unusual and cuts two ways: the patent has never been PTAB-tested, so there is no estoppel on the books and no IPR-hardened claim set — but it is also flagged "Expired – Fee Related" in the recorded legal status, meaning the maintenance-fee clock, not the PTAB docket, is the defense you should check first. Absence of PTAB activity here is not a validation signal; it correlates with a patent that appears never to have been the centerpiece of an assertion campaign.

I must flag a verification caveat: I could only retrieve claims 1–5 verbatim from the authoritative text (claim 1 and its dependents 2–5, covering the tolerance-value, at-most-equal, identical-value, and diversity compatibility policies). Claims 6–21 exist (21 claims total) but their text was not returned in my fetch. I make no representation about the content or scope of claims 6–21, and no PTAB FWD has ever construed any of them.

Proceedings

None. There are no proceeding numbers to report, and per your instruction I will not invent any. To be explicit about the negative finding and how I reached it:

Do-not-confuse check (critical for a defendant)

A large share of what a keyword search will serve up for "'749 patent" is a different patent. Do not cite these as proceedings on US 8,510,749:

• Nike, Inc. v. adidas AG, IPR2016-00922 — US 8,266,749 (knitted footwear component). Note: 8,266,749 ≠ 8,510,749. This is the family that generated Nike, Inc. v. adidas AG, 812 F.3d 1326 (Fed. Cir. 2016).
• IPR2023-01460, IPR2024-00460 (lululemon), IPR2024-00778 (New Balance), IPR2025-00141 (Skechers) — the Nike '749 patent litigated in Nike, Inc. v. Skechers / related (D. Mass.), cited in Case No. 1:23-cv-12666-JEK.
• IPR2025-00123 (Samsung) and related Truesight stipulation filings — US 8,745,749.
• IPR2025-xxxx (Samsung) regarding US 9,242,749 — Telebrands matter.

None of these involve US 8,510,749, IBM, or thread-scheduling art.

Strategic summary

Claim status: 100% UNTESTED. No claim of US 8,510,749 has been canceled, confirmed, or even construed by the PTAB, because no trial was ever instituted and no FWD ever issued. All 21 claims stand as issued on the face of the record — subject to whatever the maintenance-fee status says (below). There is no narrow-surviving-claim set to negotiate around and no canceled-claim set to attack a demand letter with. If opposing counsel tells you "claims 1–5 were invalidated in IPR," that is false for this patent; that statement is true of different '749 patents, which is likely the source of any such claim.

Estoppel landscape: wide open. Because § 315(e)(2) estoppel attaches only to grounds a petitioner "raised or reasonably could have raised" in an IPR that was instituted and reached FWD, and there was no IPR at all, no party is estopped as to any ground on this patent. Your entire § 102/§ 103 prior-art universe — patents, printed publications, and combinations thereof — remains available in district court and as the basis for a fresh petition. Likewise, no § 315(b) one-year clock has been triggered by your service of a complaint unless and until a complaint is actually served on you; if you have been served, that clock is running and is the single most time-sensitive item on this page.

Pattern signals. No petition at all — by anyone, ever. No serial/me-too filings, no General Plastic issue, no Fintiv discretionary-denial fight. No defensive aggregator (Unified Patents or similar) appears anywhere in the chain. No PTAB appeals, so no Nike v. adidas-style claim-construction precedent from this patent to lean on. The only third-party corroboration I located for the patent's existence in a commercial context is an IBM Research blog post (2014-01-14) touting it as portfolio marketing, not litigation. That profile — a 2013-issued IBM software-patent with no assertion history and a lapsed fee status — is the profile of a patent IBM simply stopped paying to maintain, not one that has been tested and survived.

Recommended next steps

1. Verify maintenance-fee status before anything else. The authoritative text records the legal status verbatim as "Expired - Fee Related" with an adjusted expiration date of 2032-04-25. Google Patents expressly caveats that legal status is "an assumption and not a legal conclusion," so treat this as a strong lead, not a conclusion. Pull the fee history in USPTO Patent Center (https://patentcenter.uspto.gov) for application 12/789,015. If a maintenance fee was in fact not paid and the 6-month grace window has closed, the patent is unenforceable for failure to maintain — and that is a cleaner, cheaper defense than any IPR. If it was reinstated or a petition to accept an unintentionally delayed payment was granted, the patent is live and the rest of this plan applies.
2. If you have been served with a complaint, calendar the § 315(b) bar immediately. You have one year from service to petition for IPR. There is no estoppel baggage, so any competent § 102/§ 103 ground is a candidate. Statutory deadline arithmetic: IPR institution decision is due within 6 months of the petition's filing (35 U.S.C. § 314(b)), and the FWD is due within 12 months of institution (§ 316(a)(11)), extendable up to 6 months for good cause.
3. Do not file a PGR. US 8,510,749 has a filing date of 2010-05-27, pre-dating the 2012-03-16 AIA PGR window; PGR is unavailable. CBM is also unavailable — it sunset on 2020-09-16 and this is a processor-scheduling patent, not a "financial product or service" patent, so the technological-invention exception would defeat eligibility anyway. IPR is your vehicle.
4. Prosecution-history diligence. The patent issued 2013-08-13 from an application filed 2010-05-27, and the file history will tell you what the examiner did and did not see. That is where an Advanced Bionics-type "same art previously considered" § 325(d) risk lives — a discretionary-denial risk you should brief before filing, not discover after.
5. Sourcing note. When you run this yourself, source the proceeding list from the canonical structured feed rather than keyword search, and confirm the negative in PTAB E2E / PTAB Decisions (https://ptacts.uspto.gov) and CourtListener (https://www.courtlistener.com). This is the rare instance where the correct answer really is "nothing on file," and the biggest practical danger is a vendor or adversary conflating a Nike, Telebrands, or Samsung '749 proceeding with this IBM patent.

Bottom line for a defendant: you are not facing a hardened, IPR-tested patent with settled surviving claims, and you are not estopped from anything. You are facing an untested 2013 IBM patent whose recorded status is "Expired – Fee Related." Confirm the fee status first; if the patent is dead, stop there. If it is live, your IPR window is open and unencumbered.

I'll verify the assignment record using available sources before reconstructing the chain.

Let me check for any post-issuance assignments, related continuations, and IBM patent-sale history.

Let me check for any litigation involving this patent and confirm the current owner status.

Ownership & Assignment Analysis — US 8,510,749 B2 ("Framework for scheduling multicore processors")

Scope caveat up front: USPTO Assignment Center and the legacy assignment index are not directly reachable through the retrieval interface used here, and the Google Patents legal-events feed for this patent shows only recordation dates — it does not expose reel/frame or correspondent fields. I therefore report the one assignment that is affirmatively documented in the retrieved record, and I flag the fields (reel/frame, correspondent) that could not be captured rather than inventing them. Anyone acting on this should re-pull the abstract of title directly at the Assignment Center search page.

Inventors

Pattern check: All five are IBM Austin / IBM Research staff, consistent with a pure work-for-hire filing. There is no "all inventors left within 12 months" signal here — Ware, Rawson, Peterson and Hanson stayed at IBM for years (evidenced by their continued IBM patent output, including the child case US 8,990,831), and only Elnozahy's later move to academia is documented. This is the opposite of the pre-fire-sale exodus pattern.

Original assignee

International Business Machines Corporation (IBM) — named assignee on the face of the issued patent and the only recorded owner.

• Product embodiment: IBM explicitly tied this patent family to its own shipping software. IBM's research blog ("Improving processors through better scheduling," Jan 14, 2014) describes the invention as improving how AIX packs threads onto cores for power/performance trade-offs on Power systems. The claimed subject matter (per-core voltage/frequency/SMT-level settings driven by a "leader thread") is squarely within AIX's PowerVM/SMT scheduler domain. IBM shipped product here — this is not a paper patent.
• Primary line of business: Enterprise IT — servers (Power Systems), operating systems (AIX, IBM i), middleware, and services.
• Current status: IBM is an operating company and remains in business. The patent itself is lapsed: Google Patents records legal status "Expired – Fee Related," adjusted expiration 2032‑04‑25 — i.e., the term was cut short by non-payment of maintenance fees. The asset was abandoned rather than monetized.

Assignment timeline

• 2010‑05‑27 (filing) / 2010‑06‑02 (recorded) — Reel/Frame not captured in retrieved data (Assignment Center abstract of title needed for the exact reel/frame)
  • Conveyance: Assignment of assignors' interest ("ASSIGNMENT OF ASSIGNORS INTEREST")
  • Assignor: Elnozahy, Elmootazbellah Nabil; Hanson, Heather Lynn; Peterson, James Lyle; Rawson, Freeman Leigh, III; Ware, Malcolm Scott (the five named inventors)
  • Assignee: International Business Machines Corporation, Armonk, New York
  • Correspondent: Not exposed in the Google Patents legal-events record. IBM inventor assignments of this vintage were typically recorded through IBM's in-house IP law operation, but I am not asserting a specific attorney/firm here because the field is not present in the retrieved source. Verify directly at the Assignment Center.
  • Context: Routine employee inventor→employer assignment (work-for-hire), executed within days of filing. Not an acquisition, fire-sale, securitization, or transfer-to-asserter.

Post-issuance records: none found. There is no recorded assignment of US 8,510,749 from IBM to any operating company, holding entity, or NPE. No security agreement, merger, change of name, or release is recorded against this patent in the retrieved record.

Related-family note (not an assignment, but relevant to the ownership picture): US 8,510,749 and its continuation US 8,990,831 B2 (application 13/413,768, granted 2015‑03‑24) both remain IBM‑owned; publication US 2011/0296423 A1 corresponds to this patent.

Timeline diagram

timeline
    title Ownership of US 8510749
    2010 : Filed by IBM inventors
         : Assigned to IBM
    2011 : Application published
    2013 : Patent granted to IBM
    2015 : Continuation granted to IBM
    2026 : No assignment ever recorded

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The only recorded transfer is inventors→IBM (recorded 2010‑06‑02). No LLC, no "IP/Holdings/Ventures/Licensing" suffix, no registered-agent address appears in the chain.

2. Known asserter in the chain — Not present. The sole assignee is IBM, which does not appear on any Acacia / Marathon / IV / Wi‑LAN / Conversant / Pendrell / Round Rock / Spangenberg NPE list. Independent study of IBM's assignment data (Envision IP / IAM, 2015) found only ~61 of 15,400+ transferred IBM patents ever asserted and "a very small number" reaching NPE hands — and this patent is not among the transferred ones.

3. Repeat correspondent across the chain — Not applicable / unclear. There is only one link, and the correspondent field was not exposed in the retrieved record. With a single non-NPE link there is no recurrence to test. No flag.

4. Cascading transfers — Not present. Zero chained transfers; no LLC-to-LLC sequence within any 24‑month window.

5. Pre-litigation transfer — Not present. No assignment predates any suit; no infringement action naming this US 8,510,749 surfaced. (Search hits for a "749 patent" belong to unrelated patents — e.g., Secure Communication Technologies and Proxicom — and must not be conflated with 8,510,749.)

6. Bankruptcy fire-sale — Not present. IBM has not filed Chapter 7/11; the asset lapsed for unpaid maintenance fees while still held by IBM.

7. Privateering — Not present. No transfer to a proxy asserter, and no IBM-sponsored NPE campaign tied to this patent is documented.

8. Defensive aggregator (anti-NPE) — Not present. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN; it simply terminates at IBM.

Verdict

Insufficient data — the record contains only the original inventor→IBM assignment.

Justification: The single recorded conveyance is the five IBM inventors' assignment of their interest to International Business Machines Corporation, recorded 2010‑06‑02 (Google Patents legal events; reel/frame not exposed in the retrieved source). No subsequent assignment, security interest, merger, or change of name is recorded, and the patent is shown as Expired – Fee Related with a 2032‑04‑25 adjusted expiration — meaning IBM let the asset lapse rather than moving it to any asserting entity. With one operating-company link and no post-issuance transfers, there is no basis to classify this as an NPE asset; the correct call is a documented dead end, not an unproven shell chain.

Verify directly: USPTO Assignment Center — search by patent number 8510749 → https://assignmentcenter.uspto.gov/ (legacy index: https://assignment.uspto.gov/patent/index.html). Pull the abstract of title to capture the reel/frame and correspondent that this interface could not surface.

I'll research US patent 8510749 and its cited prior art.

Let me fetch the detailed citation lists from Justia and Google Patents.

Prior Art Analysis — US 8510749 B2

Important limits on this response. I was able to retrieve the patent's own text and its front-page citation list (via the Justia record for US8510749), but I was not able to open and read the full text of each cited reference within this session. Where I could independently verify a reference's title/date, I say so; where I could not, I flag it as unverified rather than guess. I also note that the patent text you supplied does not include the "References Cited" section, so the citation list below comes from the secondary record, not the authoritative document.

1. The patent at issue

• Number: US 8510749 B2 (literal, as issued)
• Title: "Framework for scheduling multicore processors"
• Application: US 12/789,015; filed 2010-05-27; priority 2010-05-27
• Granted: 2013-08-13
• Assignee: International Business Machines Corporation
• Inventors: Elnozahy, Hanson, Peterson, Rawson III, Ware
• Claims: 21 total (claims 1–5 recovered in the supplied text; 1 is independent)
• Status listed: Expired – Fee Related (adjusted expiration 2032-04-25)
• Source: https://patents.google.com/patent/US8510749/en and https://patents.justia.com/patent/8510749

Which § 102 framework applies. The application was filed May 27, 2010 — before the AIA first-inventor-to-file provisions took effect (March 16, 2013). Accordingly the pre-AIA 35 U.S.C. § 102 applies: §§ 102(a)/(e) (art before the applicant's invention date / applications filed before that date), § 102(b) (one-year statutory bar), and the exceptions for the inventor's own work within the grace period.

Claim 1 (the broadest claim) requires, in substance: selecting a first thread per a scheduling-discipline order (the "leader"), setting a core attribute value from a corresponding leader thread attribute, adding a second thread only if the resulting bundle satisfies a policy, scheduling the bundle on a core — where the policy is a compatibility policy testing whether a thread attribute of the second thread is within a tolerance value of the corresponding core attribute set by the leader. Claims 2–4 are parallel compatibility-policy variants (≤, identical, diverse); claim 5 adds a utilization-level test.

2. References cited on the face of US 8510749

Per the Justia "Referenced Cited" record for US8510749 (the Google Patents authoritative page did not surface this section in the fetched text):

3. Reference-by-reference analysis

US 7,028,167 B2 — Soltis, Jr. et al. (Apr. 11, 2006)

• Citation: U.S. Patent 7,028,167 B2, "Core parallel execution with different optimization characteristics to decrease dynamic execution path," Soltis, Jr. et al.; granted Apr. 11, 2006; appl. 10/091,084 filed Mar. 4, 2002. (Verified via Google Patents / docket records.)
• Description: A processor with two or more parallel instruction paths (implementable as multiple cores on a common die). Instructions are processed as "bundles" of instructions of a common program thread, with different optimization characteristics per path; assessment logic monitors execution and synchronizes the paths to the "lead" path's characteristics. (Note: its "bundle" is an instruction bundle, not the patent's thread bundle.)
• Potential § 102 relevance: Weak as a § 102 reference against claim 1. It uses the words "bundle" and "core," but it does not teach selecting a software thread as a leader, deriving a core attribute from a thread attribute, or a tolerance-based compatibility policy. Realistically an § 103 background reference, most plausibly aimed at the multi-core/"bundle" terminology and the general concept of co-processing workloads through multiple paths.
• Claims implicated (if any): claim 1 (terminology/multi-core environment only) — not a full anticipation on the record available.

US 7,398,374 B2 — DeLano (Jul. 8, 2008)

• Citation: U.S. Patent 7,398,374 B2, "Multi-cluster processor for processing instructions of one or more instruction threads," DeLano; granted Jul. 8, 2008; assignee Hewlett-Packard Development Co. (Verified titles/dates via Google Patents / FPO.)
• Description: A configurable clustered processor with a "wide" mode (clusters collectively process bundled instructions of one thread) and a "throughput" mode (clusters independently process bundles of separate program threads).
• Potential § 102 relevance: Addresses mapping threads to clusters/cores and grouping instructions of a thread — conceptually adjacent to the patent's thread-to-core "bundle." But it discloses no leader thread, no core-attribute-from-thread-attribute step, and no compatibility/tolerance policy. Best characterized as § 103 art for the environment of multi-core thread assignment, not § 102 anticipation of claim 1.
• Claims implicated: claim 1 (environment/grouping aspects only).

US 2005/0223382 A1 — Lippett (Oct. 6, 2005)

• Citation: U.S. Patent Application Publication 2005/0223382 A1, Lippett; published Oct. 6, 2005.
• Description (partially verified): Lippett is associated with multicore/thread scheduling technology (the "SystemWeaver" hierarchical scheduler family carries a GB priority of Sep. 30, 2005, "Scheduling In A Multicore Architecture"). I could not confirm in this session that US 2005/0223382 A1 is the same disclosure, and the published date (Oct. 6, 2005) does not neatly align with that family's Sep.–Oct. 2005 priority window, so I flag the identification as uncertain.
• Potential § 102 relevance: If it is the multicore hierarchical-scheduling disclosure, it is strong § 103 art on the general framework of ordering threads and allocating them to cores, and possibly § 102(a) background — but the hierarchical/rule-based sorting it describes does not appear to disclose the leader-attribute-sets-core-attribute + tolerance-compatibility-policy combination of claim 1.
• Claims implicated: potentially claim 1 (framework/environment) — unverified.

US 2008/0184233 A1 — Norton et al. (Jul. 31, 2008)

• Citation: U.S. Patent Application Publication 2008/0184233 A1, Norton et al.; published Jul. 31, 2008.
• Description: Not independently verified in this session — I will not fabricate a technical summary. Based on the naming and date it is an examiner-cited US application publication in the processor/thread-management space.
• Potential § 102 relevance: As a pre-2008 publication it is available as § 102(a) (and as § 102(e) as of its filing date) art. Whether it anticipates any of claims 1–5 cannot be asserted without reading its disclosure; on the record available I cannot map it to specific claim elements.
• Claims implicated: unverified.

US 2009/0201935 A1 — Hass et al. (Aug. 13, 2009)

• Citation: U.S. Patent Application Publication 2009/0201935 A1, Hass et al.; published Aug. 13, 2009.
• Description/general relevance: Hass et al. are IBM inventors with power-management/processor-DVFS work; the reference is plausibly directed to processor power/frequency management in a multicore context — which is directly relevant to the patent's "core attribute = voltage/frequency/SMT level" concept. This specific document's content was not verified in this session.
• Potential § 102 relevance: Available as § 102(a)/(e) art (published within one year before the May 27, 2010 filing, so not a § 102(b) bar). Potentially relevant to the core-attribute (voltage/frequency) aspect of claim 1, but not demonstrated to disclose the leader-thread/bundle/policy combination.
• Claims implicated: claim 1 (core-attribute aspect) — unverified.

US 2009/0307708 A1 — Archer et al. (Dec. 10, 2009)

• Citation: U.S. Patent Application Publication 2009/0307708 A1, Archer et al.; published Dec. 10, 2009.
• Description/general relevance: Archer et al. is an IBM inventor group known for hardware-thread assignment / thread scheduling in multiprocessor systems; this reference is plausibly about assigning software threads to hardware threads on cores, which is squarely in the patent's field. Not verified in this session.
• Potential § 102 relevance: Available as § 102(a)/(e) art. This is among the references most likely to have been used for a § 103 combination on the "selecting threads per a scheduling discipline and placing them on cores" aspects of claim 1; whether it discloses the compatibility-policy/tolerance limitation is unverified.
• Claims implicated: claim 1 — unverified.

US 2010/0017804 A1 — Gupta et al. (Jan. 21, 2010)

• Citation: U.S. Patent Application Publication 2010/0017804 A1, Gupta et al.; published Jan. 21, 2010.
• Description/relevance: Not verified in this session. Published ~4 months before the filing date.
• Potential § 102 relevance: Available as § 102(a) (before the applicant's invention) and § 102(e) (as of its filing date); not § 102(b) (within the one-year window). Claim mapping unverified.
• Claims implicated: unverified.

US 2010/0077185 A1 — Gopalan et al. (Mar. 25, 2010)

• Citation: U.S. Patent Application Publication 2010/0077185 A1, Gopalan et al.; published Mar. 25, 2010.
• Description/relevance: Not verified in this session. Published ~2 months before the filing date.
• Potential § 102 relevance: Available as § 102(a)/(e) art only. Claim mapping unverified.
• Claims implicated: unverified.

US 2010/0100712 A1 — Mejdrich et al. (Apr. 22, 2010)

• Citation: U.S. Patent Application Publication 2010/0100712 A1, Mejdrich et al.; published Apr. 22, 2010.
• Description/relevance: Mejdrich et al. is an IBM (Rochester) inventor group with multiprocessor/thread-scheduling work; this reference is plausibly directed to scheduling/executing threads across processors. Published ~5 weeks before the filing date. Not verified in this session.
• Potential § 102 relevance: Available as § 102(a)/(e) art only. Among the cited references this one is thematically closest to "scheduling threads on a multiprocessor," and thus a candidate § 103 combination reference; the specific claim mapping is unverified.
• Claims implicated: claim 1 — unverified.

US 2010/0146513 A1 — Song (Jun. 10, 2010)

• Citation: U.S. Patent Application Publication 2010/0146513 A1, Song; published Jun. 10, 2010.
• ⚠ Timing flag: The publication date (Jun. 10, 2010) is after the patent's filing/priority date (May 27, 2010). Therefore it is not available as § 102(a)/(b) art on its publication date; it could qualify only as § 102(e) art if its own effective filing date predates the invention date. This is a reference that should be scrutinized for its effective filing date before being relied upon.
• Description/relevance: Not verified in this session.
• Claims implicated: unverified — arguably not citable against the claims unless the § 102(e) date is established.

4. Non-patent literature cited

NPL-1 — Barbon, "Run-Time Monitoring of Instances and Classes of Web Service Compositions" (2006)

• Citation: F. Barbon et al., "Run-Time Monitoring of Instances and Classes of Web Service Compositions," 2006.
• Description: A Web-services runtime-monitoring paper, outside the multicore-scheduling field.
• Potential § 102 relevance: Effectively none for claims 1–5. Its appearance on the list reads as an over-inclusive IDS entry ("duty of candor" citation) rather than substantive art. Not a § 102 anticipation of any claim.
• Claims implicated: none apparent.

NPL-2 — Elnozahy et al., "A Framework for Scheduling Multicore Processors Based on Different User Thread Attributes," May 20, 2010, pp. 1–13

• Citation: Elnozahy, Hanson, Peterson, Rawson, Ware (i.e., the named inventors of US 8510749), "A Framework for Scheduling Multicore Processors Based on Different User Thread Attributes," dated May 20, 2010, 1–13.
• Description: This is the inventors' own disclosure of the very framework claimed, dated one week before the May 27, 2010 filing.
• Potential § 102 relevance: Because it is the inventors' own work published less than one year before filing, it is not a § 102(b) statutory bar and is not "by another" for § 102(a)/(e)/(f) purposes — it therefore does not anticipate the claims. It is highly relevant as (i) evidence of the disclosure's content and conception, and (ii) a potential § 102(b) concern only if an actual public disclosure or on-sale activity occurred more than one year before filing (i.e., before May 27, 2009), which this May 20, 2010 item does not establish.
• Claims implicated: none — no anticipation, but it is the single most technically on-point document on the list.

5. Bottom line

• No reference on the citation list can be confirmed as a § 102 anticipation of claim 1 on the record available: none of the verified references (Soltis "167," DeLano "374") discloses the claim-1 core combination of (a) selecting a leader thread per a scheduling-discipline order, (b) setting a core attribute value from the leader's thread attribute, and (c) admitting a second thread into a bundle only if a tolerance-based compatibility policy is satisfied.
• The citations most likely to have been relied upon are the 2009–2010 IBM thread-scheduling publications (Archer US 2009/0307708; Mejdrich US 2010/0100712; Hass US 2009/0201935) and the multicore-scheduling disclosures (Lippett; DeLano US 7,398,374), typically in § 103 combinations rather than single-reference § 102 rejections.
• US 2005/0223382 A1 (Lippett) is the classic § 103 "framework" reference (hierarchical thread ordering + core allocation); US 7,028,167 (Soltis) and US 7,398,374 (DeLano) supply the multi-core/thread-to-cluster environment.
• US 2010/0146513 A1 (Song) post-dates the filing date and is citable only under § 102(e) if its own filing predates the invention date — flag for verification.
• The Elnozahy NPL item is the inventors' own pre-filing disclosure and cannot anticipate the claims; it is context, not § 102 art.

Recommended next steps to firm this up (I could not complete them here): pull the full text of each of US 2009/0307708, US 2010/0100712, US 2009/0201935, US 2010/0017804, US 2010/0077185, US 2008/0184233, and US 2005/0223382 from USPTO PatentCenter / Google Patents, and check the App. 12/789,015 file wrapper (USPTO PatentCenter) for the examiner's actual § 102/§ 103 rejections and the applicant's remarks — the rejections themselves will state which reference was mapped to which claim, which is more reliable than reconstructing it from the citation list.

Would you like me to draft the per-claim § 102 element charts for any specific reference (e.g., Lippett or Archer) once its full text is retrieved?

I'll research the prior art cited on this patent's page before building the § 103 analysis.

Let me dig into the specific prior-art citations listed on the patent's page.

I have a lead on the cited references (Justia "Referenced Cited"). Let me verify and characterize each reference.

Obviousness Analysis — U.S. Patent No. 8,510,749 B2

"Framework for scheduling multicore processors"
Assignee: International Business Machines Corp. | Inventors: Elnozahy, Hanson, Peterson, Rawson III, Ware
Appl. No. 12/789,015 · Filed 2010-05-27 · Granted 2013-08-13 · Status: Expired – Fee Related (adjusted expiration 2032-04-25)

0. Scope, sources, and confidence caveats

Sources used (Prior Art section of the patent page and its mirrors):

• Google Patents record: https://patents.google.com/patent/[US8510749B2](/patent/US8510749B2)/en
• Justia "Referenced Cited" list: https://patents.justia.com/patent/8510749
• FreePatentsOnline mirror: https://www.freepatentsonline.com/8510749.html
• Patent Encyclopedia entry for US 2009/0201935 A1: https://www.patentsencyclopedia.com/inventor/ahmed-shahid-san-jose-us-1/

Caveats I am bound to state up front:

1. The fetched Google Patents page for US 8,510,749 did not render its citation table in the retrieved text (the images/citation block came through blank). I therefore used the Justia "Referenced Cited" table as the proxy for the page's Prior Art section. Its contents are reproduced below exactly as listed; I did not auto-correct any number, date, or name.
2. I was not able to retrieve the full specification text of every cited U.S. publication within this session. Where I characterize a reference's teaching, I flag it as inferred from title/date rather than verified. I have deliberately avoided fabricating pin cites (column/paragraph numbers) I could not confirm.
3. The provided claim text for US 8,510,749 is truncated at claim 5 (claims 6–21 are not reproduced). Claim 1–4 are quoted verbatim below; claim 5 is partial. My dependent-claim analysis therefore also draws on the patent's Summary of the Invention, which restates the dependent subject matter.
4. This is a technical obviousness analysis, not a legal opinion or a freedom-to-operate/validity opinion. No attorney-client relationship is created.

1. The "Prior art keywords" and classification actually recorded on the page

The page records these examiner-side concepts:

Prior art keywords: thread · computer usable · core · bundle · threads

Classification, in relevant part: G06F9/4881 (scheduling strategies for dispatcher), G06F9/4893 (scheduling strategies taking into account power or heat criteria), G06F9/5027 (allocation of resources to service a request), G06F9/54 (interprogram communication), Y02D10/00 (energy-efficient computing).

Two observations matter for § 103: (a) "bundle" — the patent's signature term — was itself treated as a prior-art keyword, which cuts against any argument that "bundle" is a point of novelty rather than a label; and (b) the examiner expressly classified this in the art of power/thermal-aware dispatch, i.e., the art of trading SMT level, frequency, and voltage against throughput.

2. The claimed subject matter

Claim 1 (verbatim, elementized):

Dependent claims of record (as available):

• Claim 2 — compatibility policy = second thread's attribute value is at most equal to ("≤") the corresponding leader-set core attribute.
• Claim 3 — compatibility policy = second thread's attribute value is identical to the leader-set core attribute.
• Claim 4 — compatibility policy = second thread's attribute is diverse from a corresponding attribute of another thread in the bundle.
• Claim 5 (truncated in the source) — further code for determining whether the bundle includes a number of threads that will utilize a resource at a designated utilization level, execution being responsive thereto.
• Per the Summary: resource = a core; a third thread may be added under the same policy; core attribute = voltage, frequency, or SMT level; order = priority order; discipline may be round-robin; the "multi-core processor" may be a multiprocessor and a "core" may be a separate processor.

Effective filing/priority date: 2010-05-27 (no earlier priority claim of record). This is a pre-AIA case; § 102/§ 103 as amended by the AIA do not apply. That matters below for the non-patent reference dated May 20, 2010 — seven days before filing.

3. The prior art of record

3.1 U.S. patent documents (as listed under "Referenced Cited")

Verified detail for US 2009/0201935 A1: the published title is "System and method for parsing and allocating a plurality of packets to processor core threads" (published 08-13-2009); one secondary index attributes it to inventor Ahmed Shahid (San Jose), while the patent's own face lists "Hass et al." I report both literally and do not reconcile them. Substantively the reference is a hash/key-based allocation of work items to processor core threads — i.e., attribute-driven assignment of work to hardware threads inside cores, which is directly on point for element 1b/1d.

Unverified characterizations (flagged): For US 2005/0223382, US 2008/0184233, US 2009/0307708, US 2010/0017804, US 2010/0077185, US 2010/0100712, US 2010/0146513, US 7,028,167 and US 7,398,374 I could not retrieve full text in this session. From titles, dates, and the identity of the named inventors (Archer and Mejdrich are IBM processor/scheduler inventors; Soltis and DeLano are associated with tightly-coupled multithreaded-processor thread/processor affinity work), these fall into four familiar families: (i) thread-to-processor binding / affinity, (ii) SMT-concurrency and resource-contention management, (iii) queue- and priority-ordered dispatch with attribute-based grouping, and (iv) per-core operating-point (frequency/voltage/mode) selection. Any mapping below that depends on those characterizations is expressly conditioned on verification of the full text.

3.2 Non-patent literature of record

• Barbon, F., "Run-Time Monitoring of Instances and Classes of Web Service Compositions" (2006). Background art on runtime monitoring of concurrent instances — peripheral; primarily a § 102(b)/§ 103 background reference, not a primary reference for the scheduling limitations.

• Elnozahy et al., "A Framework for Scheduling Multicore Processors Based on Different User Thread Attributes," May 20, 2010, pp. 1–13. This is by the named inventors (Elnozahy is the first-named inventor) and is dated seven days before the 2010-05-27 filing.

  Legal significance — this reference is probably not § 103 prior art. Under pre-AIA § 102(a)/(e), an inventor's own work is not "by others"; and a statutory bar under § 102(b) requires public use/printed publication more than one year before filing. A May 20, 2010 document is one week before filing, so it can neither be a § 102(a) "by others" reference nor a § 102(b) bar. If it were instead an IBM defensive publication / IP.com disclosure publicly available before May 27, 2010, the same analysis applies as long as the inventive entity overlaps. Its practical role is as evidence of what the inventors themselves regarded as the state of the art at filing, and as a potential admission against the patent owner if the owner later argues the framework was non-obvious — an oddity worth flagging in any litigation or inter partes challenge.

3.3 The specification's own admissions (usable as prior-art/background art)

Independent of the cited references, the patent's Background and Detailed Description contain explicit concessions that narrow the inventive contribution:

• "Some commonly used scheduling disciplines are round-robin scheduling, priority based scheduling, and multi-level feedback queue (MLFQ) based scheduling." → the "order in a scheduling discipline" of 1b is admitted art.
• "when multiple SMT threads execute in a core, they all have to run at the same frequency and use the same voltage" and "hardware threads in a single core must execute at a common frequency." → the hardware constraint that forces co-scheduled threads onto a shared operating point, which is the entire reason the "leader sets the core attribute" step (1c) exists.
• "Gang scheduling is the notion that if a particular thread is scheduled, another particular thread must also be scheduled." → an admitted pre-existing notion, expressly used in the patent's FIG. 5 discussion.
• "a thread attribute may indicate a thread's affinity to a core, memory, or another resource accessible through a core." → affinity-based co-scheduling, admitted art.
• "a user, system administrator, system software, application software or any other suitable entity decide the attributes of a software thread." → thread attributes as an input are admitted art.

4. Governing § 103 framework

Because the application was filed May 27, 2010, pre-AIA 35 U.S.C. § 103(a) governs, with the Graham v. John Deere factors: (1) scope and content of the prior art; (2) differences between the prior art and the claims; (3) level of ordinary skill; (4) objective indicia. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), supplies the controlling rationales, restated in MPEP § 2143: (A) combining prior art elements according to known methods to yield predictable results; (B) simple substitution of one known element for another; (C) use of a known technique to improve a similar device in the same way; (D) applying a known technique to a known device ready for improvement; (E) "obvious to try" — choosing from a finite number of identified, predictable solutions with a reasonable expectation of success; (F) known work in one field prompting variations for use in another; (G) design incentives and other market forces.

A person of ordinary skill here is a practitioner with an advanced degree or equivalent experience in operating-system and processor-scheduling design, familiar with SMT, DVFS, thread affinity, and dispatch queue structures as of mid-2010.

5. Element-by-element analysis of claim 1

5.1 Elements 1a, 1b, 1f — program-product form, ordered selection, dispatch to a core

These are the classic, admitted building blocks. The specification concedes that schedulers select threads from an "order" in a "scheduling discipline" and assign threads to hardware/SMT threads on a core. The cited queue/priority-ordered dispatch references — US 2008/0184233 A1 (Norton), US 2009/0307708 A1 (Archer), US 2010/0017804 A1 (Gupta), US 2010/0077185 A1 (Gopalan), US 2010/0146513 A1 (Song) (characterizations conditioned on full-text verification) — and the compute-environment/affinity references US 7,028,167 (Soltis) and US 7,398,374 (DeLano) disclose selecting work items in an ordered fashion and binding them to particular processors/threads. The "non-transitory computer usable storage medium" recitation is, in a 2010-filed pre-AIA case, a routine-programming-product recitation that adds no patentable weight absent an unexpected technical effect.

One reference in particular is squarely on point for elements 1b/1d: US 2009/0201935 A1 discloses "allocating a plurality of packets to different processor threads" by parsing packet information and applying a hash/key to decide allocation. That is attribute-driven assignment of work to hardware threads inside processor cores — the same genus as "select a thread, look at its attributes, and decide which core/thread set it joins." A POSA seeking to extend packet-to-thread allocation to thread-to-core allocation would simply apply a known technique (attribute matching) to a known device (a multicore dispatch framework), the MPEP § 2143 rationale (C)/(F).

5.2 Element 1c — "leader thread" sets a core attribute from its own thread attribute

This is the only limitation with any arguable structural novelty. Three independent lines of art and admission defeat it:

(a) The hardware constraint makes it a necessity, not an invention. The patent itself concedes that all SMT threads on a core must share one frequency and one voltage. Given that fixed constraint, any competent scheduler that wishes to co-schedule threads on one core must pick one operating point for the core and test other threads against it. The "leader" is nothing more than "whichever thread the ordering discipline yields first." Selecting the operating point from the first-selected thread is an arbitrary design choice with no asserted technical advantage over, e.g., selecting the maximum or the median of the candidate threads' requirements — and claim 1 recites no such advantage. This is the paradigm of predictable variation under KSR / MPEP 2144.04.

(b) Per-core operating-point control was itself well known. The examiner classified this case in G06F9/4893 ("scheduling strategies ... taking into account power or heat criteria") and Y02D10/00. The per-core frequency/voltage/mode-selection art (the family represented in the record by the power/thermal-aware dispatch references) already taught deriving a core's operating configuration from the workload dispatched to it. Combining a per-core operating-point controller with a thread-attribute-aware dispatcher yields the 1c step exactly.

(c) Attribute metadata on threads is admitted art. The specification concedes that a user, administrator, system software, or the application may assign thread attributes such as "a desired frequency to provide the needed performance, tolerance to resource contention expressed as a desired SMT level, a desired level of energy consumption expressed as a voltage." Once threads carry these fields, reading the field into a core register is a simple substitution (MPEP 2143(B)).

5.3 Elements 1d–1e and 1g — policy-gated admission, and especially the "tolerance" policy

The dependent claims here are the weakest link in the patent, and they are also where claim 1's own wherein-clause lives.

Claim 1's compatibility policy is "within a tolerance value." Claims 2, 3, and 4 are the same idea with the comparator swapped:

• Claim 2: ≤
• Claim 3: =
• Claim 4: diverse from (i.e., anti-affinity/complementarity)

These are three points on a single, continuous, ordered scale of admission strictness (loosest → tightest). KSR makes short work of this: where a claimed parameter is a result-effective variable or where there are a finite number of identified, predictable solutions, trying each is obvious. Here the patent itself does the work — its FIG. 5 example states that with a 0.25 GHz tolerance, sub-queues (0, 2, 4), (0, 1.8, 4), and (0, 1.8, 8) may be co-scheduled, and that (0, 1.8, 4) and (0, 1.8, 8) may be co-scheduled "regardless of a frequency tolerance value," thereby conceding that the tolerance is a tunable knob whose value is an engineering choice. The patent states no criticality, no unexpected result, and no numerical range that produces a different technical effect outside the range.

Claim 4's "diverse" policy is likewise admitted: the specification's own example — an I/O-intensive leader thread should not be paired with another I/O-intensive thread, but should be paired with a compute-intensive thread — is the classic complementary-resource bin-packing heuristic (spread load across functionally distinct resources), long known in multiprocessor scheduling and expressly identified in the specification's own discussion of resource contention.

Motivation to combine (MPEP 2143, rationales A, C, D, G): a POSA in mid-2010 faced precisely the pressures the patent recites — rising core counts, SMT, per-core DVFS, per-core licensing, and power/thermal caps. The recognized design objectives (throughput, latency, energy) pull in opposite directions on exactly the parameters the claims address. A POSA would therefore have been motivated to (i) order ready threads by an existing discipline, (ii) fix the core's operating point from one thread, and (iii) admit additional threads whose tolerance windows contain that operating point, iterating until a utilization target is met. Every step is a known technique applied to a known device, with a reasonable expectation of success, because the feasibility test is arithmetic (is the candidate's required frequency within tolerance of the core's set frequency?).

5.4 Claim 5 — "designated utilization level"

Determining whether a bundle contains enough threads to hit a designated utilization target is textbook bin-packing to a target fill ratio — a purely conventional engineering optimization. The patent's own examples ("eighty percent" core utilization; "forty percent I/O cycles and sixty percent computing cycles") are merely illustrative targets with no criticality asserted. Under MPEP 2144.04, optimizing a result-effective variable by routine experimentation is obvious.

5.5 Remaining dependent subject matter (per Summary)

• Core attribute = voltage, frequency, or SMT level → the specification admits per-core voltage/frequency configurability as known, and the classification itself is the power/thermal-aware dispatch art.
• Order = priority order → admitted ("priority based scheduling").
• Discipline = round-robin → admitted by name.
• Multiprocessor / core = separate processor → recited in the patent's own FIG. 1 (processors 101–104) as an IBM Power Systems symmetric multiprocessor; the substitution of "core" for "processor" as the scheduling target is a simple substitution (MPEP 2143(B)), and the patent expressly states that a multiprocessor embodiment is within scope.
• Adding a third thread under the same policy → mere repetition of steps 1d–1e; an iterative loop adds nothing.

6. Candidate § 103 combinations (with motivations)

I present these as combinations of record; each is anchored in the page's own prior-art listing plus the specification's admissions.

Combination A — Attribute-based thread-to-core allocation + queue-ordered dispatch + per-core operating-point selection
Primary: US 2009/0201935 A1 (attribute/hash-driven allocation of work to processor core threads; verified as to title and date).
Secondary: a queue/priority-ordered dispatch reference from {US 2008/0184233 (Norton), US 2009/0307708 (Archer), US 2010/0017804 (Gupta), US 2010/0077185 (Gopalan), US 2010/0146513 (Song)}, plus the admitted round-robin/priority/MLFQ disciplines and the admitted per-core voltage/frequency configurability.
Motivation: Both references address the same problem — mapping a set of heterogeneous work items onto a limited set of hardware threads — and the queue reference supplies the "order" while the packet-allocation reference supplies the attribute-matching predicate. Combining them requires no change in the respective principles of operation; the result (attribute-compatible threads co-resident on a core at a chosen operating point) is the predictable product of the two.

Combination B — Thread/processor affinity and binding + SMT contention management + policy-gated co-scheduling
Primary: US 7,028,167 B2 (Soltis, Jr. et al.) and/or US 7,398,374 B2 (DeLano) for explicit thread-to-processor binding/affinity (characterization conditioned on full-text verification).
Secondary: US 2005/0223382 A1 (Lippett) and/or US 2010/0100712 A1 (Mejdrich) for managing how many threads share a core and how contention is handled (same condition), together with the patent's own admission that SMT threads in a core must share frequency and voltage.
Motivation: A POSA binding threads to processors must decide which threads may share a processor; the SMT references teach that the answer depends on each thread's tolerance to resource contention. Because the hardware forces a single frequency/voltage on the shared core, the only way to implement contention-aware co-residency is to fix the core's operating point from one thread and admit others whose tolerances accommodate it. That is claim 1's core.

Combination C — Admitted-art combination plus a single reference teaching tolerance-based admission
Primary: the specification's admitted scheduling disciplines + attributed thread attributes (frequency, SMT tolerance, voltage).
Secondary: US 2010/0100712 A1 (Mejdrich) or the family's contention-management teaching, plus the patent-internal FIG. 5 example of a 0.25 GHz co-scheduling tolerance.
Motivation: This is the "combination of familiar elements according to known methods yielding predictable results" rationale (MPEP 2143(A)); when the patent itself supplies a working numerical tolerance example, it has effectively conceded that the tolerance value is not a point of novelty.

Combination D — Gang scheduling / affinity as the "policy" of claim 1 / claim 4
Primary: the admitted gang-scheduling and affinity notions (specification, FIG. 5 discussion and step 908 discussion).
Motivation: Claim 4 requires only that a candidate thread's attribute be "diverse from" a bundle member's. Once gang-scheduling and affinity co-scheduling are conceded as known, excluding a candidate on resource-complementarity grounds is a simple substitution of one admission predicate for another (MPEP 2143(B)).

Not usable as prior art: the Elnozahy et al., May 20, 2010 non-patent reference (see § 3.2) — own-work and within one year of filing under pre-AIA § 102(a)/(b). Any party asserting it as § 103 art would have to establish a different inventive entity or an earlier public disclosure date.

7. Objective indicia and rebuttal considerations

For completeness, the analysis should be tested against Graham factor (4). Nothing on the face of the patent record evidences:

• Unexpected results — the specification asserts only the expected benefits of co-scheduling (improved utilization, power-conservation targets, licensing-conflict resolution) and expressly concedes the trade-off that co-scheduled threads "may not perform as efficiently as desired."
• A long-felt but unmet need — the patent presents the framework as a straightforward extension of admitted scheduling disciplines to admitted hardware parameters; no history of failed attempts is recited.
• Industry praise, copying, or licensing — not evident from the record retrieved.
• Nexus — even if such evidence existed, none of it appears tied to the only arguably distinctive limitation (the "leader sets the core attribute" step) rather than to the generic goal of better multicore utilization.

The strongest potential non-obviousness argument available to the patent owner would be a narrow one: that no cited reference discloses or suggests the specific "leader thread"-driven operating-point selection in which a thread's own desired value is written into the core and then used as the benchmark for admitting others, as opposed to deriving the operating point from the aggregate of the candidate set. That argument is weakened considerably by (a) the specification's own admission that SMT threads on a core must share frequency/voltage, which forces a single reference value, and (b) the absence of any asserted advantage for "first-selected thread" over "maximum," "median," or "aggregate" as the reference value. Under MPEP § 2144.04, a claimed selection among a finite set of workable reference-point choices, with no showing of criticality, is obvious.

8. Bottom line

Claim 1 is, in my assessment, more likely than not invalid under pre-AIA § 103 as obvious over the cited art in view of the specification's own admissions. The only limitation with surface-level distinction — deriving a core's operating-point attribute from the first-selected ("leader") thread and admitting further threads whose attributes fall within a tolerance of that operating point — is (i) compelled by a hardware constraint the patent concedes, (ii) a predictable design choice among a finite set of equivalents, and (iii) supported by attribute-matching art of record (most concretely US 2009/0201935 A1, which places attribute-derived work onto processor core threads).

Claims 2–5 and the remaining dependent claims are, in my assessment, almost certainly obvious. Claims 2 and 3 are the same comparator at different thresholds; claim 4 is complementary bin-packing; claim 5 is bin-packing to a target fill ratio. None recites criticality, a numerical range with a different effect outside the range, or an unexpected result — and the specification affirmatively characterizes the relevant parameters as tunable engineering knobs.

Confidence levels:

• High confidence in the claim-construction and admitted-art analysis (drawn directly from the authoritative patent text).
• High confidence that the May 20, 2010 Elnozahy reference is not § 103 prior art under pre-AIA §§ 102(a)/(b) absent a different inventive entity.
• Moderate-to-high confidence in the conclusion that claim 1 is obvious.
• Low-to-moderate confidence in the specific reference-to-limitation mappings for US 2005/0223382, US 2008/0184233, US 2009/0307708, US 2010/0017804, US 2010/0077185, US 2010/0100712, US 2010/0146513, US 7,028,167 and US 7,398,374, because I could not verify their full texts in this session. Before filing any IPR petition or invalidity contention, each of those references' actual disclosure — particularly pin cites to passages on thread-attribute-driven operating-point selection — must be confirmed against the printed patents/publications. The mapping in § 5.2(a)–(c), which rests on the patent's own admissions and the examiner's own field of classification rather than on unverified reference text, does not depend on that confirmation.