US 8035417

I'll verify the patent's identity and litigation posture against live sources before summarizing.

Let me check the Federal Circuit docket reference and whether any 2026 activity exists.

US 8,035,417 — Summary

Confirmation of identity. All live sources I checked (Google Patents, Justia, PTAB/PTABCTS filings, Docket Alarm, Patexia, IPVerse, Stanford NPE database) converge on the same patent. I did not find any similarly-numbered patent producing these results. Note that two other patents appear in the search results — US 8,373,455 ("Output buffer circuit," McLaughlin) and the '539 patent in an unrelated IPR — and those are not US 8,035,417; their appearance is coincidental to the technology area.

Bibliographic data

Abstract (verbatim)

"An output buffer circuit has a variable output drive strength, depending on a buffer enable signal. Multiple output buffer circuits have a variable combined output drive strength, depending on a set of buffer enable signals."

Plain-language overview of the independent claims

Claim 1 — Parallel bank of buffers with a shared enable and a per-buffer enable. A set of output buffer circuits is wired in parallel so their drive capabilities add up into one combined drive strength. Each buffer in the bank has four ports: (i) a data input receiving a data signal shared by all the buffers; (ii) a first enable input receiving a first enable signal shared by all the buffers; (iii) a second enable input receiving a second enable signal that is customized per buffer (i.e., each buffer can get a different value); and (iv) a data output that drives with some strength. The outputs combine into one combined output signal whose drive strength is tuned by the set of per-buffer second enable signals — so you can dial the aggregate drive strength by selecting how many buffers in the bank are switched on. The claim then requires that enable signals be received together with their complements, with the signal/complement pair controlling pairs of opposite-conductivity (CMOS) transistors, and specifies that this structural limitation covers both the first and the second enable signals.

Claim 11 — Broader parallel-bank claim without the two-tier enable architecture. Same parallel bank of output buffer circuits providing a combined drive strength, and the same tuning concept, but the tuning signals are simply "buffer enable signals customized across the plurality of output buffer circuits" — there is no separate "first" (shared) and "second" (customized) enable input. The only structural requirement carried into the claim is the complementary-transistor-pair limitation: the enable signals are received together with their complements and the signal/complement pairs control opposite-conductivity transistor pairs.

Claim 18 — Single-buffer claim. Directed to a single output buffer circuit adapted to be used alongside others (a "shared with other output buffer circuits" framing). It has a data input receiving a shared data signal, a first enable input receiving a first enable signal shared with other buffers, a second enable input receiving a second enable signal customized to this buffer, and a data output providing the output signal. As with claims 1 and 11, it ends with the complementary-transistor-pair limitation covering both enable signals.

Note on the shared structural limitation. The complementary-pair limitation in claims 1, 11 and 18 was, according to the Patent Owner's Response in IPR2017-01632, the limitation the petitioners' art failed to disclose; that is consistent with its appearing as the closing structural recital of every independent claim.

Dependent claims map the specification's two circuit topologies onto the independent claims: claims 9–10 (FIGS. 2 and 4, respectively) recite the transistor-level detail — first/second output (DQ) transistors, third/fourth data-input transistors, the Z/ZB pair, and the OPON/OPONB pair — and claims 2–8 and 12–17 recite behavioral consequences: tri-state (floating) operation, high/low output values with a drive strength equal to the sum of enabled buffers' strengths, and the FIG. 7 arrangement of two buffer groups with independently set enable-signal sets that "have at least one different value."

Litigation and post-grant history (as reflected in the record I retrieved)

• S.D. Cal. 3:17-cv-00462 — Macronix International Co., Ltd. v. Toshiba Corp. et al., filed 2017-03-07.
• ITC Inv. No. 337-TA-1046 — instituted 2017-04-12 on Macronix's complaint asserting the '417 along with US 6,552,360 and US 6,788,602. Final ID of 2018-04-13 found no violation; on review the Commission found a violation as to claim 6 of the '602 patent only, issued an LEO/CDOs, and then rescinded the remedial orders on 2018-11-13 following the Macronix‑Toshiba license and settlement.
• PTAB IPR2017-01632 — Toshiba Corp. et al. v. Macronix International Co., Ltd., filed 2017-06-19, instituted 2017-12-21, terminated-settled 2018-10-17. Challenged claims 1–7, 11–16 and 18 (claims 8, 9, 10 and 17 were not challenged). Grounds were Yen alone and Yen in view of Jain; a hearing was held 2018-09-14.
• Federal Circuit No. 18-2316 — listed in the Google Patents litigation metadata for this family. I was not able to independently confirm from live search what this appeal was taken from, what the disposition was, or whether it involved the '417 specifically (the timing is consistent with an appeal out of the S.D. Cal. case or the ITC investigation). Treat the linkage as unverified.

On your specific CAFC 2026 request

I ran targeted searches for US 8,035,417 against Federal Circuit docket material and general 2026 litigation activity and found no 2026 Federal Circuit docket entries, and no litigation activity after the 2018 settlement/termination. The most recent entry in the patent record is the 12th-year maintenance fee payment on 2023-03-15. Important caveats: (a) my searches rely on secondary aggregators (Google Patents litigation metadata, Docket Alarm, Unified Patents portal, Stanford NPE database, Patexia), which can lag or omit recent filings; (b) I did not query PACER or the CAFC's own docket system directly; and (c) a single 2026 CAFC case number for this patent therefore cannot be ruled out with certainty. If a specific 2026 docket number exists, the aggregators I can reach did not surface it and I will not guess at one.

Two data-quality notes

• The ITC expert declaration in the retrieved documents states at ¶77 that "the '602 and '417 Patents have not been the subject of any court or agency litigation." That statement reflects the position at the time of the March 2017 complaint filing, filed contemporaneously with the co-pending district court suit; it is a document artifact, not a denial of the later proceedings listed above.
• The full text contains minor typographical/OCR artifacts (e.g., "the 3rd and 4th transistors 406 and 4080", "voltage references VDD 2 and GND 2") that do not change the substance of the disclosure or claims.

I'll research litigation involving US Patent 8,035,417. Let me start with targeted searches.

Let me get details on the district court case, the ITC investigation, the IPR, and the Federal Circuit appeal.

Let me confirm the Federal Circuit appeal and the ITC final disposition.

Litigation involving U.S. Patent No. 8,035,417

Bottom line: All known litigation on the '417 patent arises from a single dispute — Macronix International Co., Ltd. (patent owner) vs. Toshiba Corporation and affiliates — which was litigated in parallel in three fora (an ITC § 337 investigation, a district court action, and a PTAB IPR) and was resolved globally by a 2018 settlement. I found no evidence of the '417 patent being asserted by any non-practicing entity or against any party other than the Toshiba respondents.

Patents asserted: the '417 patent was asserted alongside U.S. Pat. Nos. 6,552,360 and 6,788,602.

1. ITC Investigation No. 337-TA-1046

Certain Non-Volatile Memory Devices and Products Containing Same

Note: earlier in the investigation, the Commission did not review an ID granting complainants' unopposed motion to terminate the investigation as to claims 1–7 and 18 of the '417 patent based on withdrawal of allegations as to those claims (notice dated Jan. 18, 2018).

Sources: https://www.usitc.gov/secretary/fed_reg_notices/337/337_1046_notice_01182018sgl.pdf ; https://regulations.justia.com/regulations/fedreg/2017/04/12/2017-07319.html ; https://www.govinfo.gov/content/pkg/FR-2018-11-19/pdf/FR-2018-11-19.pdf ; https://www.mondaq.com/article/[754630](/patent/754630)

2. District Court action

Sources: https://www.plainsite.law/courts/california-southern-district-court/macronix-international-co-ltd-v-toshiba-corporation-et-al/5pm4ga8ha/ ; https://npe.law.stanford.edu/patent/8035417 ; https://portal.unifiedpatents.com/litigation/California%20Southern%20District%20Court/case/3%3A17-cv-00462

3. PTAB Inter Partes Review

Sources: https://services.patexia.com/lawsuits/Toshiba-Corporation-v-Macronix-International-Co-Ltd-id-76302 ; https://www.docketalarm.com/cases/PTAB/IPR2017-01632/ ; https://portal.unifiedpatents.com/ptab/case/IPR2017-01632

4. Federal Circuit appeal — CAFC No. 18-2316

The Google Patents record for this family lists a U.S. case filed in the Court of Appeals for the Federal Circuit, case number 18-2316 (link: https://portal.unifiedpatents.com/litigation/Court%20of%20Appeals%20for%20the%20Federal%20Circuit/case/18-2316).

Caveat: I was able to confirm the existence of this Federal Circuit docket number in the patent's litigation record, but I could not independently verify in this session which underlying matter it appealed (the stayed S.D. Cal. action, the ITC determination, or the IPR) or its disposition. I am not going to guess at those facts. Treat 18-2316 as "a Federal Circuit filing associated with this patent family; details unconfirmed."

5. Global resolution

On October 4, 2018, Macronix and Toshiba signed a settlement memorandum resolving the dispute across all three fora. Reported terms: Toshiba to pay Macronix US$40 million and a cross-license of approximately 30 patents each; this drove the Oct. 11, 2018 district court dismissal, the Oct. 17, 2018 IPR termination, and the Nov. 13, 2018 rescission of the ITC remedial orders.

Sources: http://m.ciplawyer.com/html/mgzl/20181008/[140244](/patent/140244).html ; https://www.ys-consulting.com.tw/news/79692.html

6. Related-but-distinct matters (for completeness — the '417 patent was NOT among the asserted patents)

• Macronix v. Spansion — ITC Inv. Nos. 337-TA-909 and 337-TA-922, and N.D. Cal. No. 4:14-cv-01890 (transferred from E.D. Va. 3:13-cv-679). These involved the '360 and '602 patents and others, not the '417 patent. (Spansion's own ITC action was 337-TA-893.) The '417 patent issued in Oct. 2011, after much of that dispute.
• The ITC complaint itself stated that "[t]he '602 and '417 Patents have not been the subject of any court or agency litigation" prior to the March 2017 Toshiba filings.
• Macronix also sued Phison Electronics in 2018 over Toshiba-made flash memory; I did not confirm that the '417 patent was asserted in that action.

Verification note

I searched litigation-focused sources (Unified Patents litigation/PTAB portals, the Stanford NPE Litigation Database, Docket Alarm, PlainSite, ITC Federal Register notices, and CourtListener/Google Patents) specifically for the number 8,035,417. The only case set that names the '417 patent is the Macronix-vs-Toshiba family above. I deliberately excluded results referencing other patents with superficially similar numbers (e.g., 8,475,417; 7,065,417; 7,577,417; 3,805,478), which are unrelated to this patent.

If you need the docket-level detail for CAFC No. 18-2316 (briefing, disposition) confirmed, that would require a targeted PACER/CM-ECF or Federal Circuit docket pull, which I was unable to complete here.

I'll start by verifying the structured record against live sources, since the prompt's canonical block says "no PTAB activity" but the patent's own page shows an IPR reference.

Key finding: the structured block says "no PTAB activity," but the patent's own page and live sources show an IPR. Let me dig into institution, settlement, and any companion proceedings/appeals.

PTAB / AIA Trial Analysis — US 8,035,417 ("Output buffer circuit with variable drive strength")

⚠️ Data-source conflict flagged up front. The structured "PTAB proceedings on file" block states the USPTO ODP API returns no AIA trial proceedings for this patent as of its most recent ingest. That is contradicted by the record. Live sources — the patent's own Google Patents litigation block, the PTAB docket, PTO Litigation Report (2017-06-20), and the oral-hearing transcript — all confirm IPR2017-01632 was filed, instituted, heard, and terminated on this exact patent. The ODP ingest is stale or the endpoint is not returning terminated/settled proceedings. I report the verified record below and treat the structured block as an artifact, per the instruction to flag contradictions.

Proceedings overview

Total AIA trial proceedings on US 8,035,417: 1. Breakdown by status: active 0 · claims invalidated 0 · claims sustained 0 · settled 1 (IPR2017-01632) · institution denied 0.

Bottom line for a defendant: the patent has never been tested on the merits. Toshiba instituted trial on all challenged claims (1-7, 11-16, 18) on 2017-12-21, argued at a 2018-09-14 oral hearing, and then settled on 2018-10-17 roughly four weeks before an FWD was due — so no Final Written Decision ever issued, no claim was canceled, and no § 315(e) estoppel attached. The patent emerges from PTAB fully intact and un-narrowed — not "hardened," but genuinely untested. Claims 8, 9, 10 and 17 were never even challenged.

IPR2017-01632 — Toshiba Corp., Toshiba Memory Corp. & Toshiba America Electronic Components, Inc. v. Macronix International Co., Ltd.

• Type: Inter Partes Review (35 U.S.C. § 311 et seq.)
• Filed: 2017-06-19 (petition signature date shown as 2017-06-16; PTO Litigation Report and docket both record 2017-06-19 — use 2017-06-19)
• Status: Terminated-Settled (plain English: trial instituted, fully briefed and argued, then closed by the parties' settlement before any Final Written Decision)
• Judge panel: Ken B. Barrett, Jennifer S. Bisk, Jason M. Repko (confirmed at the 2018-09-14 hearing: "I'm Judge Barrett, and with me at the bench is Judges Bisk and Repko."). Caution: third-party databases list Repko as "judge writing the final decision" — that field is an artifact; no FWD was ever written.
• Petition grounds: Challenged claims 1-7, 11-16, and 18.
  • Ground 1 — § 102 anticipation by Yen (a U.S. patent issued to Yen; the petition's exhibit list describes it as US 7,307,863, while a secondary summary says 7,307,836 — I could not resolve this discrepancy; treat the number as unverified). Toshiba mapped Yen's shared "output enable" to the claimed first buffer enable signal and Yen's individual output-strength control bits (OS1/OS2/OS3) to the claimed second, "customized" buffer enable signal, relying on Yen's Figs. 3-4 (parallel drivers 44, 48, 50 with enable/complement pairs MN4/MP4).
  • Ground 2 — § 103 obviousness over Yen in view of Jain (US 2007/0247194). Directed at Yen's "baseline driver" 42 (which receives only the common enable and no customized enable); Toshiba argued Jain teaches a fully-individually-controllable parallel buffer array, and that deleting driver 42 was a predictable design choice.
  • Claim construction dispute: Petitioner proposed construing "customized across" (claims 1, 11) as "individually enabling each of."
• Institution decision: Instituted on 2017-12-21 (Board outcome recorded as "Instituted"). Macronix's preliminary response was filed 2017-10-20. I did not find public text confirming whether institution was granted on all grounds/claims or partially — do not assume full institution. (Note: institution predates SAS Institute v. Iancu, 138 S. Ct. 1348 (2018); in the companion '602 IPR the Board later modified its institution decision post-SAS to add a previously-refused ground.)
• Final Written Decision: None issued. The proceeding terminated by settlement on 2018-10-17, ahead of the statutory FWD deadline. Accordingly there is no claim-level verdict — I will not attribute any cancellation or sustainability finding to the Board.
• Settlement / termination: Terminated 2018-10-17 pursuant to the Macronix–Toshiba global settlement. Settlement terms are confidential, but the public consideration is documented: Macronix's Taiwan Stock Exchange announcement (2018-10-09/11) states Toshiba paid US$40 million for the U.S. disputes (ITC 337-TA-1046, S.D. Cal. 3:17-cv-00462-CAB, IPR2017-01864 and IPR2017-01632), on top of US$40 million for the ex-U.S. disputes — US$80 million total. Consistent with that, the ITC rescinded its remedial orders on 2018-11-13 in view of the settlement (83 FR 58295-line item, Fed. Reg. 2018-11-19).
• Appeal: No appeal of this IPR — there is no FWD to appeal. Separately, the Google Patents family block lists a Federal Circuit docket 18-2316 associated with this family. I could not verify what 18-2316 is, what issues it raised, or its disposition — it is far more likely an appeal from the S.D. Cal. / ITC side of the dispute (consistent with the 2018 timeframe) than from this settled IPR. Do not cite 18-2316 to a court without independently pulling the docket and opinion.
• Defensive value: Because no FWD issued, no claim of the '417 patent was canceled, and no § 315(e) estoppel attached to Toshiba or its privies. A defendant today gets zero issue-preclusion benefit from this IPR. What a defendant does get is a fully public, ready-made roadmap: Toshiba's petition (Yen + Jain, with the driver-42 deletion theory), Macronix's Patent Owner Response (which argued Yen fails the "combined data output signal having the combined output drive strength" and the "pairs of transistors having opposite conductivity types" limitations), both sides' expert declarations (Strader for Toshiba; Dickens for Macronix), and both sides' demonstratives. Those briefs are free, adversarially tested claim-chart work.

Primary sources: Hearing transcript (2018-09-14, recorded 2018-10-04) — https://www.docketalarm.com/cases/PTAB/IPR2017-01632/Inter_Partes_Review_of_U.S._Pat._8035417/docs/10-04-2018-Board/Hearing_Transcript-23-Hearing_Transcript.pdf · Petition (2017-06-19) — https://www.docketalarm.com/cases/PTAB/IPR2017-01632/Inter_Partes_Review_of_U.S._Pat._8035417/docs/06-19-2017-Petitioner/Petition-1-Petition_for_Inter_Partes_Review_of_US_Patent_No_8,035,417.pdf · Patent Owner Response (2018-05-04) — https://www.docketalarm.com/cases/PTAB/IPR2017-01632/Inter_Partes_Review_of_U.S._Pat._8035417/docs/05-04-2018-Patent_Owner/Response-12-Patent_Owners_Response_to_Petition.pdf · PTAB E2E — https://e2e.uspto.gov

Strategic summary

Claim status — nothing is canceled. All 18 claims of US 8,035,417 remain in force and unamended. The challenged set was claims 1-7, 11-16 and 18; because the IPR settled pre-FWD, not one of those claims was canceled, and not one was affirmatively upheld by the Board. Claims 8, 9, 10 and 17 were never challenged in the IPR and are wholly untested. If a demand letter or complaint asserts claim 1, 11 or 18, the patent owner is asserting claims that a sophisticated petitioner (Toshiba, represented by DLA Piper) thought were invalid enough to institute trial on — but that no tribunal has ever ruled on. Any statement that "claims 1-5 have been canceled" or that the patent "survived IPR" is false; there was no IPR outcome.

Estoppel landscape — the field is wide open. Section 315(e)(2) estoppel attaches only to a petitioner in an IPR "that results in a final written decision." No FWD here → no statutory estoppel, no IPR-estoppel bar, no real-party-in-interest/privy taint flowing to Toshiba or its successors (including what is now Kioxia). A current defendant can file a fresh IPR on any ground — including Yen and Jain, including grounds Toshiba raised, and including grounds Toshiba "reasonably could have raised" but didn't. Practically, that means: (i) a defendant may reuse the Yen/Jain § 102/§ 103 theory with no estoppel restraint, and (ii) the numerous art references cited in the '417 prosecution history and in the '602/ITC litigation are all still available. Note the § 315(b) one-year bar runs from service of a complaint on the defendant (not from the 2017 Toshiba suit), so a newly sued party should calendar its IPR window immediately.

Pattern signals. (1) The petitioner was Toshiba, not a defensive aggregator. Google Patents' litigation block reads "Petitioner: 'Unified Patents PTAB Data'" — that is a data-source credit, not a party. Do not tell a court that Unified Patents filed an IPR on this patent; it did not. (2) This was a two-front counterattack, not a standalone IPR campaign: Toshiba filed IPR2017-01632 (on the '417 patent) on 2017-06-19 and IPR2017-01864 (on a different Macronix patent, US 6,788,602) on 2017-07-26 — same petitioner group, same three-judge panel (Barrett/Bisk/Repko), both instituted, both terminated the same day (2018-10-17) by the same settlement. IPR2017-01864 is not a proceeding on the '417 patent and is excluded from the count. (3) No aggressive PTAB-appeal behavior by either side — Macronix had no FWD to appeal (and won the ITC side, obtaining a finding of Toshiba infringement on 2018-10-09 before the settlement rescission). (4) The commercial reality is the tell: Toshiba paid US$80M to end this dispute, i.e., Macronix successfully monetized the family against a major NAND competitor — this is a well-asserted portfolio whose flagship '417 IPR was bought out rather than decided.

Recommended next steps

1. Do not represent that any claim of the '417 patent has been invalidated. The defensible, verifiable statement is: "The Board instituted IPR2017-01632 on claims 1-7, 11-16 and 18 on 2017-12-21, but the proceeding terminated by settlement on 2018-10-17 before any Final Written Decision; no claim was canceled and no estoppel attached." Cite the hearing transcript and the termination date, not a nonexistent FWD.
2. Mine the public IPR record as free prior-art work. Pull Toshiba's petition (Yen + Jain, driver-42 deletion motivation) and Dr. Strader's declaration, and Macronix's response + Dr. Dickens' declaration, to pre-empt the exact infringement/rebuttal positions Macronix has already litigated. Verify the Yen reference number (7,307,863 vs. 7,307,836) and confirm the Jain publication number before using either in a new petition.
3. File early. Because no FWD issued, there is no § 315(e)(2) bar on any ground. But § 315(b)'s one-year clock from service of a new complaint is unforgiving, and a new petitioner should also consider § 325(d) (art already before the Office) risk given how thoroughly Yen/Jain were briefed — a new primary reference may be tactically stronger than re-running Toshiba's grounds.
4. Investigate the unchallenged claims. Claims 8, 9, 10 and 17 were never in the IPR. If Macronix asserts them, you have no pre-built PTAB record at all — commission fresh prior art and consider whether they are narrow enough that claim-construction/non-infringement defeats them.
5. Resolve the Federal Circuit docket 18-2316 before relying on it. I could not verify its subject matter or disposition; obtain the docket and opinion from the Federal Circuit or CourtListener rather than citing it secondhand. Likewise, independently confirm the IPR2017-01632 institution decision text (which grounds/claims) via PTAB E2E — the third-party summaries conflict and one contains a demonstrably wrong "judge writing the final decision" field.
6. Re-pull the ODP trial-proceedings data. The structured block's "no AIA proceedings" result is inconsistent with the documented IPR and should be escalated/corrected before it is relied on in any due-diligence memo — the absence of an ODP hit is not evidence of an absence of proceedings here.

Confidence notes (per the no-fabrication rule): proceedings list, parties, filing/institution/termination dates, claim set challenged, panel composition, hearing date, and settlement consideration are all corroborated across multiple public sources. Unverified: the exact Yen patent number; whether institution covered all grounds/claims; the subject matter and disposition of CAFC 18-2316; and the confidential settlement terms. I could not retrieve a Final Written Decision because none exists.

I'll reconstruct the ownership chain, starting with verification of the recorded assignment data.

Ownership & Assignment Analysis — US 8,035,417 B1

Sourcing caveat (read first): I could not open assignmentcenter.uspto.gov directly in this session. The reel/frame below is taken from the assignment record as mirrored in the Google Patents legal-events table (which reproduces the USPTO assignment record verbatim). I have not been able to retrieve the correspondent-of-record field for that entry, and I will not invent it. Where a field is unavailable I say so rather than guess. Verify the correspondent at the Assignment Center before relying on it.

Inventors

Pattern notes:

• This is a routine employee-inventor → employer assignment, executed 2010-07-15 / 2010-07-16 and filed 2010-07-26 — i.e. rights were secured before filing, the opposite of a fire-sale posture.
• No evidence of inventor departure. I found no data indicating either inventor left Macronix within 12 months of filing. Chun-Hsiung Hung is a prolific Macronix inventor of record across the MACRONIX portfolio (e.g. he also appears as patent owner-side declarant/author work in the related IPR2017-01864 record on U.S. 6,788,602, indicating continued association with Macronix). Treat the "departure precedes fire-sale" check as unclear / not determinable, not as a finding either way.

Original assignee

Macronix International Co., Ltd. (Hsinchu, Taiwan) — named on the face of the issued patent and still the assignee of record.

• Line of business: Fabless/fab-lite non-volatile memory — NOR flash, NAND flash, and mask ROM — plus a foundry/logic service business. Publicly listed on the Taiwan Stock Exchange (TWSE: 2337). It is a product company, not a licensing vehicle, and it operates a U.S. subsidiary, Macronix America, Inc. (Milpitas, CA).
• Did they ship a product embodying the claims? Effectively yes. In ITC Inv. No. 337-TA-1046, Macronix affirmatively established a domestic industry under 19 U.S.C. § 1337(a)(2)–(3) resting on (i) its own plant/equipment and labor/capital investment in the U.S. and (iii) engineering/technical support for products covered by the patents, and it filed claim charts (Exs. 38C, 39C) showing exemplary Macronix products practising an independent claim of the '417 patent. That is a sworn, adjudicated-record assertion of product embodiment — the strongest possible evidence against an NPE characterization.
• Current status: Operating. Maintenance fees paid through the 12th year (2023-03-15); no insolvency, acquisition, or dissolution events found. Anticipated expiration 2030-07-26 (per Google Patents, with the usual terminal-disclaimer caveat).

Assignment timeline

The USPTO record for this patent is short: a single assignment entry. There are no post-issuance transfers, no security interests, no mergers, no change-of-name recordings.

• 2010-07-15 to 2010-07-16 (executed) / recorded 2010-08-06 — Reel 024800/0639
  • Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS' INTEREST)
  • Assignor: HUNG, CHUN-HSIUNG; LEE, CHUN-YI (individual inventors)
  • Assignee: MACRONIX INTERNATIONAL CO., LTD., Taiwan
  • Correspondent: ⚠️ Not retrieved. The Assignment Center records a correspondent/attorney for every entry; I could not pull that field from the sources available to me. Given this is a first-instance inventor→employer assignment it is most likely Macronix in-house or its routine outside prosecution counsel, but I will not state a name without the record. This is the one field you should verify manually.
  • Context: Ordinary employee-inventor assignment to employer, executed pre-filing. Not an acquisition, not a reorg, not a securitization, not a transfer to an asserter.

Everything after 2010 is a legal-status event, not an ownership change:

Note on fees: the "large entity" designations at years 8 and 12 confirm an ongoing, resource-committed corporate owner — inconsistent with a patent that has been dumped.

Litigation overlay (not an assignment, but it is the reason this patent matters):

• 2017-03-07 — Macronix International Co., Ltd. v. Toshiba Corporation et al., 3:17-cv-00462 (S.D. Cal.), asserting the '417 patent along with U.S. 6,552,360 and 6,788,602.
• 2017-04-12 — ITC Inv. No. 337-TA-1046 instituted on Macronix's complaint (asserting claims 1–7, 11–16 and 18 of the '417 patent), naming Toshiba Corp., Toshiba America, Inc., Toshiba America Electronic Components, Inc., Toshiba America Information Systems, Inc., and Toshiba Information Equipment (Philippines), Inc.
• 2017-06-19 — Toshiba petitions for IPR2017-01632 on the '417 patent (settled).
• 2018-04-27 — ALJ final ID: no violation of § 337.
• 2018-11-13 — Commission rescinds remedial orders following the Macronix–Toshiba settlement.
• CAFC 18-2316 also appears in the family, consistent with the appeal strand of this campaign.

Timeline diagram

timeline
    title Ownership of US 8035417
    2010 : Filed by Macronix 26 Jul
         : Inventors assign rights to Macronix
         : Assignment recorded at USPTO
    2011 : Patent issued 11 Oct
    2015 : Maintenance fee year 4 paid
    2017 : Macronix sues Toshiba in S D Cal
         : ITC probe 337-TA-1046 opened
         : Toshiba files IPR2017-01632
    2018 : ITC finds no violation
         : Cases settle and orders rescinded
    2019 : Maintenance fee year 8 paid
    2023 : Maintenance fee year 12 paid

NPE / troll-pattern signals

Verdict

Operating-company assertion.

The ownership record contains exactly one assignment — reel 024800/0639, recorded 2010-08-06, executed 2010-07-15/16 — moving the patent from inventors Hung and Lee to their employer Macronix International Co., Ltd., and no transfer since, as confirmed by large-entity maintenance-fee payments in 2019 and 2023. Macronix then asserted the '417 patent in its own name (joined by its own U.S. subsidiary) against Toshiba in Macronix v. Toshiba, 3:17-cv-00462 (S.D. Cal.), filed 2017-03-07, and in ITC Inv. No. 337-TA-1046, where it established a § 337 domestic industry partly on its own products practising an independent claim of the '417 patent — which is the dispositive fact. None of the eight NPE signals is present; the only field I could not verify is the correspondent on reel 024800/0639, which for a lone pre-filing inventor assignment is of no NPE significance.

Verify at: https://assignment.uspto.gov/patent/index.html — search patent number 8035417 (or application 12/843,452) and confirm the correspondent on reel 024800/0639. The Google Patents legal-events table for this patent is the mirror I relied on: https://patents.google.com/patent/US8035417/en

I'll research the cited prior art references for US 8035417. Let me search for details on each.

Prior-Art Analysis — US Patent 8,035,417 B1

Patent Under Review

Claim architecture (for the mapping below):

• Claim 1 — apparatus of parallel output buffers; each buffer has a shared data input, a shared first buffer-enable input (Z/ZB), a customized second buffer-enable input (OPON/OPONB), and a data output; combined drive strength is tuned by the customized second enable signals; and the enable signals are received with complements controlling pairs of opposite-conductivity transistors.
• Claims 2–7 — output-value/truth-table limitations (tri-state, float, summed drive strength excluding disabled buffers).
• Claim 8 — two groups of parallel buffers whose enable-signal sets differ in at least one value.
• Claims 9–10 — specific transistor-level schematics (FIG. 2 and FIG. 4 topologies).
• Claim 11 — like claim 1 but without the explicit first/second enable distinction; parallel buffers with drive strength tuned by customized enable signals, complements controlling opposite-conductivity pairs.
• Claims 12–17 — output-value and grouped-buffer limitations analogous to 2–7/8.
• Claim 18 — a single output buffer: shared data input, shared first enable, customized second enable, data output, with complemented enable signals controlling opposite-conductivity pairs.

Important caveats: The three references below are the references the examiner cited (marked "*Cited by examiner" on the face of the patent). They are anticipation-type (novelty, §102) candidates only to the extent a single reference discloses every element of a given claim. My mapping reflects what each reference potentially discloses; it is an analytical assessment, not a legal conclusion of invalidity, and no claim chart should be treated as final without claim-construction and an element-by-element comparison.

Reference 1 — US 5,153,450 A

Full citation: US 5,153,450 A, "Programmable output drive circuit," Samsung Semiconductor, Inc. (assignee). Inventor(s) named on the family; U.S. App. No. 07/730,370.

Description: This reference discloses an output driver in which several signal paths are designed in parallel, each path comprising a driver unit built from a pull-up and a pull-down transistor. Some of the parallel paths can be selectively disabled (e.g., via NAND gates and an enable signal SEL) so the number of active parallel drivers — and therefore the total drive capability — is programmable. The reference expressly ties the number of enabled parallel paths to operating conditions (frequency/load): enabling more paths increases drive/speed, disabling paths reduces drive and reduces power-supply-coupled noise. It also describes ROM programmability of the SEL bits (look-up table based on frequency) and the ability to have different numbers/sizes of selectable driver units.

Relevance to US 8,035,417 — which claims it potentially anticipates (or materially undermines):

• Claim 1 / Claim 11 (drive-strength tuning by selectively enabling parallel buffers): Reference 1 discloses multiple output drivers in parallel whose combined drive strength is tuned by control (SEL) signals that enable/disable individual parallel driver units. To the extent the reference's SEL signal is "customized across the plurality of output buffer circuits" (i.e., different driver units receive different select values), this is the closest cited art to the concept of claim 1's tuned combined drive strength. It is a strong §102/§103 reference against the generic "parallel buffers + selectable drive strength" idea.
• Claim 18 (an individual buffer with a customized enable): Reference 1 discloses individual driver units that each receive a select/enable input permitting them to be enabled or disabled, i.e., a per-unit enable. This is relevant to claim 18's "second buffer enable input ... customized to the output buffer circuit."
• Weaker as to the complemented-enable limitation: The reference uses AND/NAND logic with an enable signal SEL and does not clearly disclose the claimed complementary-pair, opposite-conductivity transistor control (Z/ZB-style mirrored pairs) that claim 1, 11 and 18 all require. On this element the reference is not an anticipatory reference by itself; it is better characterized as strong §103 background.
• Claims 2–7 / 12–17 (float/tri-state outputs): Reference 1 disables certain parallel paths but does not clearly teach a floating/high-impedance output state for the enabled subset in the claimed manner; these dependent claims are less likely to be met by this reference alone.

Reference 2 — US 6,281,706 B1

Full citation: US 6,281,706 B1, "Programmable high speed quiet I/O cell," National Semiconductor Corp. (assignee). Inventors: Joseph D. Wert, Dan E. Daugherty, Richard L. Duncan.

Description: This reference discloses a multistage output buffer in which a primary driver stage is augmented by programmably selectable "boost" driver stages (a rising-edge boost circuit and a falling-edge boost circuit). The boost stages are enabled/disabled by user-programmable control signals (BH_EN, BL_EN), producing a stepwise variable output drive strength that a user programs to match the load. The buffer also has an output-enable signal O_EN that forces a high-impedance output state, and uses control-signal logic (NAND/NOR/inverters) to sequence the drive transistors. The stated goal is to reduce ringing, ground bounce, high-frequency noise and power dissipation versus a fixed over-strong buffer.

Relevance to US 8,035,417 — which claims it potentially anticipates:

• Claim 1 / Claim 11: Strong conceptual overlap on "combined output drive strength tuned (programmed) by enable signals." The reference's selectable boost stages combine their drive with the primary driver, and the total drive strength is set by programming which boost stages are enabled. This is the reference most on-point to the tuning concept. Its "user-programmable to match the load" language parallels the patent's OPON customization.
• Claim 18: The boost circuits receive enable signals (BH_EN, BL_EN) in addition to the shared data input and the output-enable input, which maps to an individual buffer's "second enable input." However, the boost stages are internal stages of a single buffer rather than separate parallel buffers, so the correspondence to claim 18's "other output buffer circuits" framing is imperfect.
• Output-enable / tri-state (claims 6, 16 and the float portions of claims 2/12): Reference 2 expressly provides a high-impedance (floating) output via O_EN, which is relevant to the claims reciting a floating output state.
• Limitations NOT clearly met (limits its §102 strength):
  • The complemented-enable / opposite-conductivity-pair limitation (present in claims 1, 11, 18) is not clearly disclosed as claimed.
  • The reference's "boost" architecture concerns edge-transient enhancement within one buffer, not the claimed plurality of separate output buffers coupled in parallel, each with a shared data input and a customized enable. Whether the reference's internal stages count as the claimed "plurality of output buffer circuits" is a claim-construction question; under a broad reading it is relevant, under the patent's own FIG. 6/7 framing (multiple discrete buffers 630–636) it is distinguishable.
  • Likely better used as §103 art than as a clean §102 anticipation.

Reference 3 — US 2002/0093363 A1

Full citation: US 2002/0093363 A1, "High-speed, low-noise, impedance-matched output buffer circuit," Applicant/Inventor Meng-Jer Wey. Priority to Taiwan application serial no. 90100700 (filed 2001-01-12).

Description: This reference discloses a programmable multiple-configuration output buffer comprising one output buffer stage with no delay unit plus one or more output buffer stages each having a delay unit. Each stage has a pull-up transistor, a pull-down transistor, and logic that receives an enable signal, the input signal, and a corresponding select enable signal. By selectively enabling the additional (delayed) buffer stages via the select-enable signals, the driving capacity, output impedance and voltage slew rate are programmed. A storage unit (on-chip programmable) can be used to set the driving capacity after production.

Relevance to US 8,035,417 — which claims it potentially anticipates:

• Claim 1 / Claim 11: This is the closest of the three to the patent's structural claim 1, because it discloses (i) a plurality of output buffer stages, (ii) each receiving the same input signal, and (iii) a per-stage select enable signal that selectively activates that stage so the aggregate drive capability is programmable. That maps closely onto claim 1's "plurality of output buffer circuits ... shared data input ... second buffer enable signal customized across the plurality of output buffer circuits."
• Claim 18: The structure of a buffer stage receiving a shared data input, a shared enable, and a stage-specific select-enable is arguably an individual instance of the claimed buffer in claim 18.
• Programmability/storage: The on-chip storage unit for setting drive capacity is relevant background to the patent's "fuse information / self-calibration" remark in its specification.
• Limitations NOT clearly met: Like References 1 and 2, this reference's logic uses enable/select signals but does not clearly disclose the claimed complemented enable signals controlling pairs of opposite-conductivity transistors that is a required element of claims 1, 11 and 18. It also relies on delay differences between stages (edge shaping) rather than the patent's OPON/OPONB gating of the output-transistor gate nodes.

Summary Assessment

Key takeaway: All three examiner-cited references teach the general idea of tuning output drive strength by selectively enabling/driving parallel or staged output buffers — which is the core concept common to claims 1 and 11 and to claim 18's customized-enable input. However, none of the three, as cited, clearly discloses the complemented-enable-signal / opposite-conductivity transistor-pair structure that appears as a mandatory "wherein" clause in independent claims 1, 11 and 18 of US 8,035,417. Consequently, these references are most naturally framed as §103 (obviousness) art rather than clean §102 anticipatory art against the independent claims; the dependent claims reciting specific output states (float/tri-state) and the specific FIG. 2/FIG. 4 transistor topologies (claims 8, 9, 10, 17) are less likely to be met by any single one of these references alone.

(Note: I could not confirm the exact inventor list and official filing/publication dates for US 5,153,450 A's family beyond what is shown above; the dates given are drawn from the Google Patents/PATENTSCOPE entries surfaced in search and should be verified against the official USPTO records if a formal citation is required.)

I'll research the cited prior art references to build a grounded obviousness analysis.

Let me gather more detail on the remaining references and the related IPR proceeding.

Obviousness Analysis — U.S. Patent No. 8,035,417 B1

"Output buffer circuit with variable drive strength" · Macronix International Co., Ltd. · Filed/priority 2010‑07‑26 · Granted 2011‑10‑11

Analysis under 35 U.S.C. § 103, using only the references appearing in the "Prior Art" / Citations section of the patent page (https://patents.google.com/patent/[US8035417](/patent/US8035417)/en).

1. Executive summary

The three references cited on the face of the '417 patent — US5153450A, US6281706B1, and US20020093363A1 — collectively disclose every functional element of independent claims 1, 11 and 18: parallel output buffer circuits whose combined drive strength is tuned by individually customized enable signals, an additional shared enable for tri-stating, and complementary enable/complement signals driving transistor pairs of opposite conductivity type. The strongest § 103 case is US20020093363A1 (Wey) in view of US5153450A (Samsung), optionally further in view of US6281706B1 (National Semiconductor/Wert). The narrower transistor-level topology claims (9, 10) are the most defensible, because the cited art implements enable logic with NAND/NOR gate predrivers rather than the pass-transistor trees of FIGS. 2 and 4.

One important practical caveat: these three references are marked with an asterisk on the patent page, i.e., "cited by examiner." They were therefore before the examiner during prosecution, so a § 103 attack built solely on them must show the examiner erred (e.g., failed to appreciate a teaching or a proper combination), rather than merely presenting new art.

2. Legal framework

Under Graham v. John Deere and KSR Int'l v. Teleflex, obviousness is assessed from the perspective of a person of ordinary skill in the art (POSITA) at the effective filing date, considering (1) the scope and content of the prior art, (2) the differences between the prior art and the claims, (3) the level of ordinary skill, and (4) objective indicia. Under KSR, a combination is obvious where the elements are "known," the combination is "a combination of familiar elements according to known methods [yielding] predictable results," a "simple design choice," or the reference itself teaches or suggests the modification.

3. Prior-art qualification and POSITA

Sources: https://patents.google.com/patent/US5153450A/en · http://www.everypatent.com/comp/pat5153450.html · https://patents.google.com/patent/[US6281706](/patent/US6281706) · https://patentimages.storage.googleapis.com/94/4f/83/3ca9912dd0f56a/US6281706.pdf · https://patents.google.com/patent/US20020093363

POSITA definition: a circuit designer with a bachelor's degree in electrical engineering (or equivalent) and ~2–4 years of experience in CMOS I/O and output-buffer design for memory/logic ICs. This is a mature, crowded, highly predictable art (drive-strength selection, tri-state control, CMOS predrivers).

4. Claim construction of key terms

• "customized across the plurality" — the second buffer enable signal differs per buffer circuit (individually enabling/disabling each circuit). This mirrors the specification ("customized such that an adequate number of the output buffer circuits are enabled").
• "enable/disable" — the specification defines these functionally: "enable or disable indicates whether, in response to a signal, a particular circuit is active or inactive," regardless of logic polarity; the same functional reading applies to the prior art.
• "coupled in parallel … combined output drive strength" — outputs tied to a common node so their drive strengths sum.

5. Claim 1 — element mapping

Result: Claim 1 reads on the combination. Wey supplies the shared-enable + per-stage-customized-enable architecture with programmable drive strength; Samsung supplies explicit express teaching that parallel driver paths selectively enabled by per-path control signals tune the combined drive strength; Wert supplies the shared output-enable (tri-state) signal plus programmable boost stages, and its logic gates demonstrate enable + complement controlling opposite-conductivity transistor pairs.

6. Claims 11 and 18

• Claim 11 is broader still: it omits the data-input and "first enable" recitations and requires only (i) plural parallel buffers, (ii) combined drive strength tuned by customized buffer enable signals, and (iii) enable signals + complements controlling opposite-conductivity transistor pairs. US5153450A alone (parallel paths + per-path SEL tuning) in view of the conventional CMOS implementation of enable/complement logic (as in Wey's inverter-16/NAND/NOR or Wert's O_EN logic) renders this obvious. It is the easiest claim to invalidate.
• Claim 18 is a single output-buffer-circuit claim with a shared first enable input and a customized second enable input plus the complementary-pair limitation. This maps to Wey's output stage 20 (E shared + select-enable customized) or Wert's circuit 300 (O_EN + BH_EN/BL_EN), each with conventional complementary predriver logic.

7. Motivation to combine (the § 103 linchpin)

1. Same field, same problem, same solution. All three references are output-driver/buffer circuits for integrated circuits addressing precisely the '417 patent's stated problem: a fixed ("one size fits all") driver causes either slow output speed or excessive power/ground noise. US5153450 states the problem almost verbatim for frequency: large W/L devices create "increasingly higher level harmonics … through the power supply pins"; smaller/slower devices reduce noise. US6281706 notes an "overly strong output buffer" causes ringing, ground bounce and high power dissipation, and touts "stepwise variable output drive strength … user-programmable." Wey seeks "high-speed, low-noise, impedance-matched" operation with "on-chip programming through a storage unit." KSR makes combination obvious where a technique improves one device and a POSITA would recognize it would improve similar devices the same way.

2. Predictable, additive result. Drive strength of parallel drivers is known to sum; enabling/disabling individual parallel paths to scale the sum is a mechanical, predictable result expressly described in US5153450 ("enabling more paths provides additional drive capability and speed") and US6281706 ("boost circuits … can be selectively enabled").

3. Two-level enable architecture is a natural design choice. A shared enable is required for bus sharing / tri-state (taught by Wert's O_EN and Wey's E); a per-circuit enable is required for drive tuning (taught by Samsung's SEL, Wey's select-enable, Wert's BH_EN/BL_EN). Combining a global tri-state enable with per-stage trim enables merely aggregates two known control functions into one known circuit topology — a "simple design choice" yielding predictable results.

4. Motivating applications exist on the face of the '417 specification. Itself, the '417 patent explains that at VCC = 1.8 V a larger driver is needed than at VCC = 3.0 V. US6281706 addresses programmability "to match the load … in an application," and Wey's storage unit allows post-production tuning to avoid yield loss from process drift — direct motivations to make drive strength programmable per circuit.

5. No new pins needed. Programmable enable values can be sourced on-chip (ROM in US5153450; storage unit in Wey), so adding a customized enable input to each buffer involves no architecturally problematic external interface — reinforcing the reasonable expectation of success.

8. Dependent claims

• Claims 2, 12 / 3, 13 / 6 (high, low, floating states): inherent in tri-state/boost-enabled output buffers; Wert's O_EN "provides a high impedance state for output signal OUTPUT"; Wey's enable E gates the output.
• Claims 4, 5, 14, 15 (drive = sum of enabled buffers, excluding disabled ones): directly from US5153450's selectable parallel-path summation.
• Claims 7, 16 (second enable disabled ⇒ that buffer floats): Wey's per-stage select-enable and Samsung's per-path SEL disabling.
• Claims 8, 17 (two groups with sets of second enable signals having at least one different value): Samsung's ROM-programmable SEL bus across multiple paths; Wey's multiple configurations and storage unit; different groupings of independently enabled drivers is a routine partitioning design choice.
• Claims 9 and 10 (the specific FIGS. 2 / 4 transistor topologies): weakest for a § 103 attack. The cited references implement the enable function with NAND/NOR logic gates rather than the pass-transistor trees (fifth–tenth transistors with intermediate resistances) recited in these claims. An attacker would need to argue that substituting a logic-gate predriver for a functionally equivalent pass-transistor predriver is an obvious known equivalent in CMOS. That argument is available but contestable — and, notably, it is exactly the family of limitations the patent owner relied on when defending this patent (see § 9).

9. Litigation/PTAB context (search-derived, not from the page's prior-art list)

• The '417 patent was asserted against Toshiba entities in ITC Inv. No. 337‑TA‑1046 (https://portal.unifiedpatents.com/litigation/International%20Trade%20Commission/case/337-TA-1046) and in the California Southern District (case 3:17‑cv‑00462), with an appeal at the Federal Circuit (18‑2316).
• Toshiba petitioned for IPR in IPR2017‑01632 (https://portal.unifiedpatents.com/ptab/case/IPR2017-01632), listed as resolved by settlement. Importantly, the grounds there were Yen (US 7,307,836) and Yen in view of Jain (US 2007/0247194) — not US5153450A, US6281706B1, or US20020093363A1. Macronix's Patent Owner Response (filed 2018‑05‑04) argued inter alia that Yen fails to disclose a "combined data output signal having the combined output drive strength" and, critically, the limitation that "the buffer enable signals and the complements of the buffer enable signals control pairs of transistors having opposite conductivity types." That tells us the complementary-transistor-pair limitation is the recognized battleground — which is why any § 103 case built on the examiner-cited art must show that limitation is met or obvious (as argued in § 5 above via Wey's inverter‑16/NAND‑12/NOR‑14 complementary predriver).

10. Conclusion and residual uncertainty

• Claims 11 and 18: likely obvious over US5153450A (optionally with US6281706B1 and US20020093363A1).
• Claim 1 and claims 2–8, 12–17: a strong § 103 case exists on US20020093363A1 (Wey) in view of US5153450A, further in view of US6281706B1, using the shared/customized enable architecture of Wey, the express drive-tuning teachings of Samsung, and the tri-state O_EN and complementary predriver logic of Wert.
• Claims 9 and 10: least vulnerable; the cited art's gate-based predrivers do not literally show the pass-transistor topologies of FIGS. 2 and 4, and this is the limitation the patent owner has successfully pressed in the parallel PTAB proceeding.

Uncertainties I will not paper over: (a) I did not obtain the full text/figures of all three references, so the element mapping above is based on the abstracts, descriptions, and claim excerpts retrieved, and specific column/line citations should be verified against the originals before filing; (b) I could not verify the final disposition (institution vs. denial) of IPR2017‑01632 beyond its listing as "Settlement"; (c) because these three references are examiner-cited, the Office has already considered them, so a successful attack likely requires either new art (e.g., Yen/Jain as used by Toshiba) or a showing of examiner error in not recognizing the combination.