US 7870404

I'll search for the specific patent number and any 2026 CAFC docket activity.

US 7,870,404 — Verified Summary

Sourcing note: No 2026 CAFC docket entry, opinion, or oral-argument calendar item for patent 7,870,404 was found in my searches. The only Federal Circuit activity I located in the HD Silicon Solutions v. Microchip family (appeal No. 2023-1397) concerns U.S. 6,774,033 ("Metal Stack for Local Interconnect Layer"), a different patent — I am explicitly not attributing that appeal to the '404 patent. The most recent '404-specific records I found are the 2021–2022 PTAB and district-court matters listed below.

Bibliographic data (from the patent text and USPTO/Google Patents records)

Assignee chain (recorded reassignments): Transmeta Corporation → Transmeta LLC (merger, eff. 2009-01-27) → Intellectual Venture Funding LLC (eff. 2009-01-28) → Intellectual Ventures Holding 81 LLC (merger, eff. 2015-08-27) → Intellectual Ventures Assets 156 LLC (eff. 2019-12-16) → Innovative Silicon Solutions, LLC (nunc pro tunc, eff. 2020-01-10) → HD Silicon Solutions LLC (change of name, eff. 2020-11-10).

Flagged discrepancies:

• The Microchip IPR petition states the patent "issued on January 1, 2011"; the patent front page and Google Patents both say January 11, 2011. I treat 2011-01-11 as authoritative.
• One third-party site (Patentleaderboard) lists this patent under "Oracle" for inventor Sameer Halepete. That conflicts with every USPTO assignment record I found; I treat it as a data error, not a chain-of-title fact.
• A USPTO Certificate of Correction exists (request filed; corrections include "voltage:" → "voltage;" in claims 11 and 15, and "re responsive" → "responsive" in claim 19), so the claim text below reflects the as-corrected reading.
• The IPR petition itself contains a typo characterizing the '404 as issued from a "division" — the relationship is correctly a division of 09/694,433.

Abstract (verbatim)

"A method for reducing power utilized by a processor including determining that a processor is transitioning from a computer mode to a mode in which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled."

Plain-language overview of the independent claims

The claims as granted focus less on the broad "lower the voltage in sleep" idea of the specification and more on a timing problem: a regulator cannot always ramp all the way from a deep-sleep voltage to a high operating voltage within the system's allotted wake-up latency. The claims exploit a two-step wake-up — go to an intermediate operating voltage that is reachable in time, then continue to the higher voltage afterward.

• Claim 1 (system). A computer has a processor and circuitry that supplies three levels: a sleep voltage, a first operating voltage, and a second operating voltage lower than the first. The system's sleep→first-operating transition takes a first amount of time; sleep→second-operating takes a second. The twist: the second transition time fits inside the system's allowed sleep-to-operate window, while the first transition time is longer than that allowed window. (In other words, the system is arranged so the lower operating voltage is reachable from sleep in time to service an interrupt, but the higher one is not.)
• Claim 7 (method). Operate the processor by (i) transitioning from the sleep voltage to a first operating voltage within the allowed sleep-to-operate time, then (ii) transitioning from that first operating voltage up to a second operating voltage — where going directly from sleep to the second operating voltage would take longer than the allowed time. This is the "wake to an intermediate rail first, then finish ramping" concept.
• Claim 11 (system, adjustable supply). A processor plus an adjustable voltage supply that can output first and second sleep voltages, a first operating voltage responsive to a transition from the first sleep voltage, and a second operating voltage responsive to a transition from the second sleep voltage. The supply generates the transition from the second sleep voltage to the first operating voltage in a time greater than the allowed sleep-state-to-operating-state transition time. (Dep. claim 12 adds the complementary case: another operating voltage is reachable from sleep within the allowed time; claim 14 specifies the supply is a voltage regulator.)
• Claim 15 (system, paired rails). Circuitry supplies first and second sleep voltages and corresponding first and second operating voltages (first operating voltage when coming out of the first sleep voltage; second operating voltage when coming out of the second sleep voltage). The first operating voltage is greater than the second, and the first sleep voltage is greater than the second (i.e., a higher pair and a lower pair travel together). A transition from the second sleep voltage to the first operating voltage exceeds the allowed sleep-to-operate time. Claim 16 adds the reverse direction (each operating voltage maps back to its corresponding sleep voltage); claim 17 adds that the voltage difference between operating and sleep levels is approximately equal for both pairs.
• Claim 18 (system, means-plus-function). The same subject matter as claim 11 expressed as "means for processing" and "means for supplying a voltage," with the same "transition from the second sleep voltage to the first operating voltage takes longer than the allowed time" requirement. This is the only independent claim I'd flag as potentially governed by 35 U.S.C. § 112(f). Claims 19–21 are its dependents (bidirectional pairing; approximately equal operating-to-sleep voltage deltas; and the higher operating voltage paired with the higher sleep voltage).

Claim count: 21 total claims; independents are 1, 7, 11, 15, and 18.

Enforcement / validity history located (not 2026)

• District court: HD Silicon Solutions LLC v. Microchip Technology Inc., No. 6:20-cv-01092 (W.D. Tex., filed 2020-11-30), transferred 2021-10-25 to N.D. Cal. as No. 3:21-cv-08295.
• PTAB: Microchip Technology Inc. v. HD Silicon Solutions LLC, IPR2021-01265 (filed 2021-07-20, challenging claims 1–21 over NEC Databook + Stratakos). Institution denied under § 314(a) on 2022-01-26. Petitioner counsel: Sanjeet Dutta; Patent Owner counsel: Justin Oliver. Sibling Microchip IPRs covered related patents (7,154,299; 7,302,619; 6,774,033; 7,260,731, etc.).
• Federal Circuit: no '404-specific appeal identified. Appeal 2023-1397 (decided 2025) involved the '033 patent, not the '404.

Uncertainty statement

I could not confirm any 2026 CAFC docket, briefing, or argument date naming patent 7,870,404. My searches returned PTAB, district-court, and USPTO certificate-of-correction records only through the early-2020s plus unrelated 2026 Federal Circuit materials (e.g., the Oasis Tooling § 101 rehearing petition). If a 2026 appeal involving this number does exist, it was not surfaced by the sources available to me, and I will not infer its existence or outcome. Likewise, I have no authoritative basis for stating the current litigation status of the N.D. Cal. case beyond the transfer date.

I'll research litigation involving US 7870404. Let me start with several targeted searches.

Let me dig deeper into the specific cases and check for additional defendants.

Let me check the outcome of the district court case and the Federal Circuit appeals.

Litigation involving U.S. Patent No. 7,870,404

Bottom line: Search results show one district-court litigation naming U.S. 7,870,404, plus one PTAB proceeding (IPR) challenging it. I found no evidence of any other suit, ITC action, or CAFC appeal specifically involving the '404 patent. Details below, with sources.

1. HD Silicon Solutions LLC v. Microchip Technology Inc.

This is a single case that moved from Texas to California; the two case numbers that appear on the patent's Google Patents page are the same action, not two separate suits.

Sources: Google Patents litigation links (https://patents.google.com/patent/US7870404/en); W.D. Tex. Doc. 49 transfer order (https://law.justia.com/cases/federal/district-courts/texas/txwdce/6:2020cv01092/[1115676](/patent/1115676)/49/); N.D. Cal. stay order, 21-cv-08295-SK (https://www.docketalarm.com/cases/California_Northern_District_Court/3--21-cv-08295/HD_Silicon_Solutions_LLC_v._Microchip_Technology_Inc/docs/84.pdf); case-closure / basis-of-termination summary (https://www.patsnap.com/resources/blog/litigation/hd-silicon-solutions-v-microchip-technology-fpga-processor-ip-patsnap/); docket docket sheet (https://unicourt.com/case/pc-db5-hd-silicon-solutions-llc-v-microchip-technology-inc-[749749](/patent/749749)).

2. Related PTAB proceeding (not a district-court litigation, but directly on the '404)

Sources: https://ipverse.greyb.com/ptab-web/cases/case-details/IPR2021-01265; https://services.patexia.com/lawsuits/Microchip-Technology-Inc-v-HD-Silicon-Solutions-LLC-id-[153617](/patent/153617); institution decision (Docket Alarm copy of the Board's 1/26/2022 decision denying institution).

Important caveats and false positives

• Only one '404-specific case. The patent's Google Patents record lists exactly two "US case filed" entries — the W.D. Tex. case (6:20-cv-01092) and the N.D. Cal. case (3:21-cv-08295) — which are the same action after transfer. Darts-IP also flags a "[f]irst worldwide family litigation filed" (family ID 24788800), but that is a family-level flag covering the Transmeta/IV power-management family (which includes U.S. 7,260,731, 9,436,264 and 9,690,366), not proof of additional suits on the '404 itself.
• CAFC appeals in the HDSS/Microchip dispute concern other patents, not the '404. Appeals Nos. 23-1397 (the '033 patent, obviousness affirmed; precedential) and 23-1943 (arising from IPR2021-01567; Fed. Cir. judgment affirming, Jan. 15, 2025, nonprecedential) involve other HDSS patents in the same litigation family. Because institution of IPR2021-01265 was denied, there is no resulting merits appeal on the '404. I could not confirm, from the sources retrieved, any appeal or mandamus petition specifically directed to the '404 IPR denial.
• Ignore similarly numbered patents. Search results are heavily polluted with unrelated "'404" patents — e.g., U.S. 8,587,404 (Chamberlain Group garage-door opener litigation) and an Australian-origin '404 CPAP-mask headgear patent (Fisher & Paykel). Neither is U.S. 7,870,404.
• Procedural caution. I relied on secondary litigation databases and document aggregators; I did not directly query PACER or the full Darts-IP dataset, which sit behind logins. Case numbers, dates and outcomes above are quoted from those sources and the patent's own Google Patents record. Confirm against PACER dockets (W.D. Tex. 6:20-cv-01092; N.D. Cal. 3:21-cv-08295) before relying on any of this for a legal filing.
• Patent status note: U.S. 7,870,404 lapsed for failure to pay maintenance fees effective January 11/February 13, 2023, and is listed as "Expired – Fee Related."

If no other litigation exists beyond the Microchip matter, that is consistent with everything retrieved: HD Silicon Solutions/Innovative Silicon Solutions appears to have asserted this patent only against Microchip Technology.

I'll reconcile the structured "no proceedings" signal against the litigation block in the patent record (which does reference an IPR) and search for claim-level detail.

Found a live hit the structured block missed. Digging into the decision reasoning and whether there were companion petitions.

Need the institution-decision reasoning and to confirm no companion petition on this patent exists.

PTAB proceedings on US 7,870,404

Data-source discrepancy — flagging up front. The canonical "PTAB proceedings on file" block for this prompt reports no AIA trial proceedings. The patent record itself (Google Patents family/litigation block and USPTO legal events) shows one: a PTAB case entry reading "IPR2021-01265 filed (Not Instituted - Merits)", with the legal event "2021-08-24 — AIA trial proceeding filed before the Patent and Appeal Board: inter partes review, TRIAL NO: IPR2021-01265, Opponent name: MICROCHIP TECHNOLOGY, INC., Effective date: 20210720." Web sources independently confirm the case and its denial. I've therefore reported the proceeding rather than the empty structured list, and I've noted where the ODP gap is likely an indexing artifact.

Proceedings overview

One AIA trial proceeding on file for US 7,870,404 — 0 active, 0 with claims invalidated, 0 with claims sustained, 0 settled, 1 institution denied (IPR2021-01265).

That breakdown produces an unusual defensive posture, and it is important not to over-read it in either direction. No claim of '404 has ever been canceled, and no claim has ever been held patentable by the Board — the single IPR died at the institution stage on 2022-01-26, so the merits of claims 1–21 remain wholly untested at the PTAB. The patent owner has neither a patentability win nor a cancellation loss to point to. On top of that, the '404 patent's listed adjusted expiration is 2021-11-05 and USPTO legal events show it expired for failure to pay maintenance fees effective 2023-01-11 — so the practical question for a defendant today is not "how do I beat this IPR-proofed patent," but "what is left of an expired patent and what pre-expiration damages window can the owner still reach under the § 286 six-year lookback."

IPR2021-01265 — Microchip Technology Inc. v. HD Silicon Solutions LLC

• Type: Inter Partes Review (35 U.S.C. §§ 311–319)
• Filed: 2021-07-20
• Status: "Not Instituted - Merits" (verbatim from the Google Patents PTAB case entry). The docket indexes Paper 11 as "DECISION Denying Institution of Inter Partes Review 35 USC sec 314 (P.T.A.B. Jan. 26, 2022)." Plain-English gloss: the Board declined to institute — this was not a settlement or a withdrawal, and no final written decision ever issued.
• Judge panel: Frances L. Ippolito (writing), Nathan A. Engels, Arthur M. Peslak (Administrative Patent Judges).
• Petition grounds: Challenged all claims, 1–21. The petition presented § 102 anticipation and § 103 obviousness theories supported by the declaration of Donald Alpert, Ph.D. (Ex. 1002), which walks through both anticipation and obviousness frameworks. Petitioner's exhibit set included Intel486 SX/Low Power CPU documentation (Ex. 1036), i.e., prior-art processor power-management materials. I could not retrieve the full ground-by-ground prior-art listing from the indexed excerpts, and I will not reconstruct it — treat the specific reference pairings for each claim as unverified.
• Institution decision: DENIED — 2022-01-26 (Paper 11). Petitioner's brief also pre-emptively addressed Apple Inc. v. Fintiv, Inc., IPR2020-00019, arguing discretionary denial would be inappropriate because the parallel district court trial date (estimated 2022-12-05) post-dated the statutory FWD deadline, the petition was filed within roughly seven months of service, and the IPR covered all 21 claims while the district court case asserted only a subset. On the coding available to me, the Board's own outcome label for this case is "Merits," which indicates the denial rested on the substantive § 314(a) "reasonable likelihood of prevailing" threshold rather than a Fintiv discretionary denial. I was not able to obtain the text of Paper 11 and therefore cannot quote the panel's reasoning; do not assume it was a Fintiv denial without reading the paper.
• Final Written Decision: None. Trial was never instituted, so there is no claim-level verdict for any of claims 1–21. No claim was canceled; no claim was sustained.
• Settlement / termination: No settlement. The proceeding terminated on the institution denial, and the Board issued a Notice of Refund (Paper 15, mailed 2022-02-09) returning $23,250 in post-institution fees to Petitioner's deposit account — a procedural confirmation that no trial was instituted.
• Appeal: None on file, and effectively unavailable. A denial of institution is not appealable under 35 U.S.C. § 314(d). No Federal Circuit docket exists for this proceeding that I could locate. Separately, in the same window the Supreme Court/Federal Circuit line (Thryv, Inc. v. Click-to-Call Techs., 140 S. Ct. 1367 (2020); Mylan Labs. v. Janssen Pharmaceutica, 989 F.3d 1375 (Fed. Cir. 2021); Intel Corp. v. VLSI Tech. LLC) confirmed both the § 314(d) non-appealability rule and the unavailability of mandamus for non-institution decisions — so even a constitutional/APA-style challenge to the denial was realistically foreclosed.
• Defensive value: Mixed, and mostly procedural. Because the Board never instituted, the denial has no issue-preclusive effect and creates no estoppel — it does not immunize claims 1–21 from a later, better-constructed petition. But it also means the patent owner cannot claim any Board-endorsed claim construction or patentability holding. For a defendant today, the denial is a playbook item, not a shield: it tells you a full-scope challenge was tried and rejected at the threshold, and it hands you the panel's identity and the petitioner's expert framework — but nothing binding.

Strategic summary

Claim status — all 21 claims are UNTESTED at the PTAB. There are no canceled claims to point to and no sustained claims to avoid. Claims 1–21 are live on the face of the patent (subject to the certificate of correction of 2011-05-31, which deleted "voltage:" from claim 11 and corrected "re responsive" to "responsive" in claim 19 — quote the corrected text in any filing). Practically, though, the dominant fact is the expiration posture: the record lists an adjusted expiration of 2021-11-05, and the patent went "Expired – Fee Related" with a lapse for nonpayment of maintenance fees recorded 2023-02-13 (effective 2023-01-11). Any assertion today is necessarily a backward-looking damages claim, which sharpens the § 286 six-year lookback and the pre-2021-11-05 notice/marking questions far more than it sharpens the invalidity fight.

Estoppel landscape — there is none, in either direction. Section 315(e)(2) estoppel attaches only after a final written decision; IPR2021-01265 never instituted, so Microchip and its privies are not estopped from raising the same or better grounds. That cuts both ways for a current defendant: (a) every prior-art ground remains available, including the Alpert/Intel486-based theories Microchip asserted, refined versions of them, and entirely new references; but (b) you are not stuck with Microchip's framing, and you should treat the denied petition as a lower bound on quality — the better move is generally a re-engineered ground rather than a re-filing. The one hard constraint is statutory, not estoppel: § 315(b)'s one-year bar from service of an infringement complaint, which is why the 2020-11-30 W.D. Tex. complaint and the 2021 N.D. Cal. complaint matter so much to anyone served in that chain. Anyone who served Microchip in that action is long past the § 315(b) window.

Pattern signals — this was a coordinated campaign, and '404 was a single-shot target. Microchip filed a portfolio-scale set of IPRs against HD Silicon Solutions patents in 2021, all in the same litigation family: IPR2021-00752 (US 6,774,033, filed 2021-04-23), IPR2021-00872 and IPR2021-01042 (US 7,302,619, filed 2021-05-28 and 2021-06-15), IPR2021-01089 (US 7,154,299, filed 2021-06-25), and IPR2021-01420 / IPR2021-01421 (US 7,260,731 — the parent of '404 — both filed 2021-09-14). Against '404 itself, Microchip filed only IPR2021-01265. It did not file a second, corrected petition after the denial, which is itself a signal that the cost/benefit of re-challenging '404 was not attractive — consistent with a patent nearing expiration. There is no defensive-aggregator petition on '404. I want to be explicit about this because it is an easy mistake: the Google Patents litigation block links to a Unified Patents portal URL, but that is their data portal, not evidence of a Unified Patents-filed IPR. The only petitions here are Microchip's, filed defensively alongside litigation. Patent owner HD Silicon Solutions also did not pursue any PTAB appeal (none was available on a non-institution decision).

Recommended next steps

1. Pull Paper 11 before you rely on the reason for denial. The only decision that matters — the 2022-01-26 denial — is Paper 11 in IPR2021-01265. Retrieve it at PTAB E2E (https://ptabs.uspto.gov / PTAB case search for IPR2021-01265) or the mirrored docket at https://www.docketalarm.com/cases/PTAB/IPR2021-01265/Microchip_Technology_Inc._v._HD_Silicon_Solutions_LLC/, and the Unified Patents portal record at https://portal.unifiedpatents.com/ptab/case/IPR2021-01265. Confirm whether the denial was a § 314(a) merits failure or Fintiv-based; the coded label says "Merits," but the reason drives whether the petitioner's art is salvageable or fundamentally deficient. I have deliberately not quoted the panel's reasoning because I could not retrieve the text.

2. Lead with expiration, not invalidity. The listed adjusted expiration is 2021-11-05 and the fee lapse is recorded effective 2023-01-11. Establish the operative expiration date and PTA/terminal-disclaimer math from the file history before spending on prior art. If assertion is ongoing, the § 286 six-year lookback and pre-expiration notice/marking analysis will likely control exposure more than any IPR would.

3. No PTAB milestones to track. There is no active trial, no institution deadline, no oral hearing, and no statutory one-year FWD due date running against this patent — the single proceeding terminated on 2022-01-26 with fees refunded on 2022-02-09. Nothing is pending that would change the claim status of claims 1–21.

4. If you do prepare an invalidity position, do not rely on PTAB estoppel or PTAB rulings. Start from the campaign's shared art (the Intel486-class processor documentation and the Alpert analysis in the sibling petitions) but expect to rebuild the grounds independently, and check § 315(b) timeliness against whatever complaint you were served with before filing anything. Cite the corrected claim text (certificate of correction, 2011-05-31) rather than the printed columns.

5. Where to verify each fact I've stated: the case roster and status at https://ipverse.greyb.com/ptab-web/cases/case-details/IPR2021-01265; panel composition at https://services.patexia.com/lawsuits/Microchip-Technology-Inc-v-HD-Silicon-Solutions-LLC-id-[153617](/patent/153617); the full patent document and litigation/PTAB entries at https://patents.google.com/patent/US7870404/en. Note that the four "AIA trial proceedings" cited by third-party aggregators for this family (IPR2021-00752, -00872, -01042, -01089, -01420, -01421) are on different patents — do not attribute them to '404.

I'll research the assignment chain and correspondent/attorney records before drafting.

Let me dig into the original assignment record and the correspondent attorneys on the NPE-chain recordings.

Excellent leads on correspondents. Let me pin down the remaining recordings' reel/frame and correspondent details.

Ownership & Assignment Reconstruction — US 7,870,404 (14/… n/a; appl. 11/894,991)

Sourcing and limitations (read first). I was unable to open assignmentcenter.uspto.gov directly in this session (legacy mirror: https://assignment.uspto.gov/patent/index.html). The reel/frame values below are taken from the Google Patents "Legal Events" table for this patent, which mirrors the underlying USPTO assignment records, and the correspondent/party data is taken from reproductions of the actual USPTO assignment cover sheets filed as exhibits in Microchip's IPRs against this family (in particular Microchip Ex. 1003 in IPR2021-01265, the '404 IPR, and Exhibit 1004 in IPR2021-01420) and from the USPTO's own legacy assignment PDF mirror (legacy-assignments.uspto.gov). Where a reel exists but I could not source its cover sheet, I say so rather than guess the correspondent. I did not fabricate any assignment.

Also note a cross-reference: the prior summary already flagged the assignee chain; that chain is confirmed here at the reel/frame level. No contradiction found between the earlier section and this one.

Inventors

All three were Transmeta engineers. This is directly documented, not inferred: the Feb. 2001 transmittal in the parent application file wrapper (Exhibit 1004, IPR2021-01420) files an "assignment and cover sheet" and a small-entity declaration in which Transmeta Corporation is the named small business concern for "STATIC POWER CONTROL," app. 09/694,433, naming Read/Halepete/Klayman, attorney docket TRANS59 (TRANS‑P059).

Unusual-pattern check — inconclusive. The task asks whether inventors left within 12 months of filing. I could not confirm individual departure dates for any of the three, so I make no finding. The general context (not patent-specific evidence): Transmeta ceased x86 processor development in the mid-2000s and wound down its operating business, which is a portfolio-fire-sale precondition, not proof of individual departures. Flag the previously noted data error: PatentLeaderboard lists Halepete's portfolio under Oracle; that conflicts with every USPTO record located and remains a third-party data artifact.

Front-page ownership oddity worth knowing: US 7,870,404 issued with the inventors listed under "(76) Inventors" — i.e., as applicants — and with no "Assignee" (73) field, which is why Google Patents shows "Original Assignee: Individual." The divisional itself was apparently never the subject of a recorded assignment at issue; Transmeta's ownership flowed from the 2000 assignment recorded against the parent, and was only papered to the divisional later via the 2009 merger (below).

Original assignee

Transmeta Corporation (Santa Clara, CA) — not the entity on the issued face of this divisional, but the equitable original assignee via the parent-app assignment.

• Business: fabless x86-compatible microprocessor design (Crusoe / Efficeon). This is a genuine operating semiconductor company, and the patent's subject matter (dynamic core-voltage / deep-sleep power control) is consistent with Transmeta's LongRun power-management product line.
• Did it ship a product embodying the claims? The specification uses an "exemplary processor that utilizes the technique described in the above-mentioned patent application [Ser. No. 09/484,516, Adaptive Power Control]" — i.e., the claimed dual-rail sleep/wake behavior is described against a Transmeta-class processor. I cannot confirm that a shipped Transmeta part practiced these specific divisional claims, and I will not assert it.
• Current status: dissolved/defunct. Transmeta exited the processor business and became a licensing-only shell; it was merged into Transmeta LLC effective 2009‑01‑27 (Reel 022454/0522), which is the point at which its remaining IP was monetized.

Assignment timeline

All entries are records that exist or are mirrored in the USPTO assignment system. Entries marked "not located" are reels whose cover sheets I could not source in this session even though the reel event itself is recorded.

A. 2000‑10‑23 (execution date not confirmed) / recorded c. 2001‑02 — Reel not located (recorded against parent 09/694,433, not against 11/894,991)

• Conveyance: Assignment of assignors' interest (inventor → employer)
• Assignor: Andrew Read; Sameer Halepete; Keith Klayman
• Assignee: Transmeta Corporation, Santa Clara, CA
• Correspondent: not located; the transmittal references Transmeta deposit account 501497, attorney docket TRANS59 / TRANS‑P059
• Context: initial invention assignment, recorded with the parent application's missing-parts response. This is the only link where the inventors are the assignors.

B. 2009‑01‑27 (executed) / recorded 2009‑03‑26 — Reel 022454/0522

• Conveyance: Merger (Transmeta Corporation into Transmeta LLC)
• Assignor: Transmeta Corporation
• Assignee: Transmeta LLC (California)
• Correspondent: not located
• Context: internal corporate reorganization immediately preceding the portfolio sale.

C. 2009‑01‑28 (executed) / recorded 2009‑09‑22 — Reel 023268/0771

• Conveyance: Assignment of assignors' interest
• Assignor: Transmeta LLC (San Jose, CA)
• Assignee: Intellectual Venture Funding LLC (502 E. John St., Carson City, NV 89706)
• Correspondent: not confirmed for this reel. Contextual analogue only, not attributable here: a later 2022 re-recording of this same 2009 Transmeta→IV transaction (Reel 059360/0563, for a different application) used FisherBroyles LLP (ffbaralegal@maxval.com) submitted by Jonathan Lee.
• Context: transfer-to-asserter / portfolio acquisition — Transmeta's patent estate sold to the Intellectual Ventures complex as Transmeta wound down. Two-step structure (Merger B, then sale C) is the classic IV acquisition papering.

D. 2015‑08‑27 (executed) / recorded 2015‑09‑29 — Reel 036711/0160

• Conveyance: Merger
• Assignor: Intellectual Venture Funding LLC
• Assignee: Intellectual Ventures Holding 81 LLC
• Correspondent: not located
• Context: internal IV reorganization.

E. 2015‑08‑27 (executed) / recorded 2015‑10‑06 — Reel 036797/0356

• Conveyance: Corrective assignment (correct the assignor's name previously recorded at Reel 036711/0160)
• Assignor: Intellectual Venture Funding LLC
• Assignee: Intellectual Ventures Holding 81 LLC
• Correspondent: not located
• Context: correction only — no change in beneficial ownership; notable because it shows IV cleaning up its own chain title.

F. 2019‑12‑16 (executed) / recorded 2020‑01‑17 — Reel 051550/0711

• Conveyance: Assignment of assignors' interest
• Assignor: Intellectual Ventures Holding 81 LLC
• Assignee: Intellectual Ventures Assets 156 LLC, 251 Little Falls Drive, Wilmington, DE 19808 (Delaware LLC)
• Correspondent: not located
• Context: internal IV asset drop-down into a single-purpose Delaware holding LLC; 251 Little Falls Drive is a widely used commercial registered-agent address (Corporation Service Company's Wilmington address), not an operating facility. Same-day sibling drop-downs to "IV Assets 57 LLC" used IV's internal "Intellectual Ventures Management – IP Legal, Bellevue, WA" correspondent, which is the pattern for this class of IV recordings.

G. 2020‑01‑10 (executed) / recorded 2020‑03‑23 — Reel 052199/0838

• Conveyance: Nunc pro tunc assignment ("Assignment of Rights in Certain Assets")
• Assignor: Intellectual Ventures Assets 156 LLC (Wilmington, DE)
• Assignee: Innovative Silicon Solutions, LLC — described in the instrument as "a Texas limited liability company having an address at 5900 Balcones Drive, STE 100, Austin, TX 78731"
• Correspondent: FAHIM AFTAB — fahim@hongdungroup.com, phone 949‑791‑9366, attorney docket JG032320; service address 2382 Rockfield Blvd., Suite 170, Lake Forest, CA 92630, submitted /Fahim Aftab/
• Context: transfer-to-asserter. Bundled bulk assignment: the instrument lists this patent together with US 7,260,731, US 9,436,264, US 9,690,366 (the rest of the Read sleep-mode family) plus unrelated Transmeta-origin patents (e.g., 7,302,619 "Error Correction in a Cache Memory"; 7,600,166 "Trusted Access to a JTAG Scan Interface"). ► Flag for the recurring-correspondent signal: Aftab's service address is the same Lake Forest address carried as the assignee's address on the corrected cover sheet, i.e., the acquirer's own representative filed the recording.

H. 2020‑01‑10 (executed) / recorded 2020‑03‑28 — Reel 052253/0751

• Conveyance: Corrective assignment (correct the address of the receiving party previously recorded at Reel 052199/0838)
• Assignor / Assignee: same as entry G
• Correspondent: FAHIM AFTAB — fahim@hongdungroup.com, attorney docket JG032320‑2, address 2382 Rockfield Blvd., Suite 170, Lake Forest, CA 92630, signed 2020‑03‑23
• Context: correction only. The corrected cover sheet lists Innovative Silicon Solutions at 2382 Rockfield Blvd. Ste 170, Lake Forest, CA 92630 — creating a documented Texas-vs-California address discrepancy between the instrument body (Austin, TX) and the corrected record (Lake Forest, CA).

I. 2020‑11‑10 (executed, effective) / recorded 2021‑01‑14 — Reel 054993/0795

• Conveyance: Change of Name (no change in beneficial ownership)
• Assignor: Innovative Silicon Solutions LLC
• Assignee: HD Silicon Solutions LLC (Texas)
• Correspondent: not confirmed for this reel. A "Certificate of Filing of HD Silicon" appearing in the same IPR exhibit set as entries G/H was submitted by Fahim Aftab and signed 2020‑11‑12 — two days after the name-change effective date — which suggests but does not establish that Aftab was also the correspondent on 054993/0795.
• Context: change of name only — the litigation vehicle is renamed and, 18 days later, files suit (see signal 5).

Timeline diagram

timeline
    title Ownership of US 7870404
    2000 : Inventors assign to Transmeta Corp
    2007 : Divisional application filed
    2009 : Transmeta Corp merges into Transmeta LLC
         : Transmeta LLC sells rights to IV Funding
    2011 : Patent issues on Jan 11
    2015 : IV Funding merges into IV Holding 81
    2019 : IV Holding 81 drops to IV Assets 156
    2020 : IV Assets 156 sells to Innovative Silicon
         : Renamed HD Silicon Solutions
         : Suit filed against Microchip
    2021 : Microchip files IPR2021-01265
    2022 : IPR institution denied
    2023 : Patent lapses unpaid maintenance fee

NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT.
Reel 051550/0711 (exec. 2019‑12‑16) moves the patent from IV Holding 81 LLC into Intellectual Ventures Assets 156 LLC, 251 Little Falls Drive, Wilmington, DE 19808 — a single-purpose Delaware LLC at a commercial registered-agent address. Reel 052199/0838 then moves it to Innovative Silicon Solutions, LLC, which the corrected record (Reel 052253/0751) places at a Lake Forest, CA suite address. Both transferees are licensing/assertion vehicles with no products in commerce; the assignment itself recites only "the patents and patent applications listed in the table below," confirming a bare asset transfer. No products; registered-agent/office-suite addresses; single-purpose LLCs — the three tells are all documented, not inferred from naming.

2. Known asserter in the chain — PRESENT.
Intellectual Ventures is an NPE-list entity, and it is in the chain at Reels 023268/0771 → 036711/0160 → 051550/0711. The terminal assignee, HD Silicon Solutions LLC, is the named plaintiff in HD Silicon Solutions LLC v. Microchip Technology Inc., No. 6:20‑cv‑01092 (W.D. Tex., filed 2020‑11‑30), later transferred to N.D. Cal. as 3:21‑cv‑08295. Innovative Silicon Solutions LLC / HD Silicon Solutions LLC are tracked as assertion entities in Unified Patents' litigation directory for this family.

3. Repeat correspondent across the chain — PRESENT (limited to the assertion tail).
Fahim Aftab (fahim@hongdungroup.com; dockets JG032320 and JG032320‑2) is the correspondent of record on both Reel 052199/0838 and Reel 052253/0751, and appears as submitter of the HD Silicon filing dated 2020‑11‑12 associated with Reel 054993/0795 — i.e., a single repeat filer across three consecutive recordings, with a service address identical to the assignee's. Caveat stated plainly: I could not confirm correspondents on reels 022454/0522, 023268/0771, 036711/0160, 036797/0356, 051550/0711, or 054993/0795, so I do not claim Aftab ran the entire chain — only the 2020 transfers.

4. Cascading transfers — PRESENT.
Three transfers inside < 24 months, with the last two inside 11 months: 2019‑12‑16 (Reel 051550/0711) → 2020‑01‑10 (Reel 052199/0838) → 2020‑11‑10 (Reel 054993/0795). Entries G and H are two recordings of the same transaction nine days apart, sharing both a correspondent and the assignee's address.

5. Pre-litigation transfer — PRESENT.
The IV Assets 156 → Innovative Silicon transfer is effective 2020‑01‑10 (recorded 2020‑03‑23), roughly 10.5 months before the W.D. Tex. complaint; the HD Silicon Solutions name change is effective 2020‑11‑10 and the suit is filed 2020‑11‑30 — 20 days later. The chain was re-arranged into a plaintiff entity essentially contemporaneously with assertion.

6. Bankruptcy fire-sale — NOT PRESENT (as a bankruptcy).
No Chapter 7 or Chapter 11 docket for Transmeta Corporation was located. The 2009 disposition at Reels 022454/0522 and 023268/0771 was a wind-down/portfolio sale to IV, not a bankruptcy-court sale. Economically analogous, legally distinct.

7. Privateering — NOT PRESENT.
The classic privateering pattern requires an ongoing operating-company sponsor benefiting from the NPE's assertions. Here the original operating company (Transmeta) had ceased operating and was merged away in 2009, long before the 2020 Microchip suit. IV's transfer to Innovative Silicon/HD Silicon is monetization by a fund, not sponsorship by a live competitor.

8. Defensive aggregator (anti-NPE) — NOT PRESENT.
The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. It terminates at HD Silicon Solutions LLC, an active plaintiff. The inverse signal applies: the patent was not neutralized; it was asserted, defended in IPR (Microchip's IPR2021‑01265, institution denied 2022‑01‑26), and only lapsed for non‑payment of maintenance fees effective 2023‑01‑11 (recorded 2023‑02‑13).

Verdict

NPE — high confidence.

Driving records: (i) known asserter in the chain — Intellectual Ventures entities at Reels 023268/0771, 036711/0160 and 051550/0711; (ii) shell-entity transfer — Reel 051550/0711 into Intellectual Ventures Assets 156 LLC at a Wilmington registered-agent address, then Reel 052199/0838 to Innovative Silicon Solutions, LLC, corrected at Reel 052253/0751, with no products anywhere in the chain; (iii) cascading transfers — three assignments from 2019‑12‑16 to 2020‑11‑10, two of them nine days apart and sharing correspondent Fahim Aftab (dockets JG032320 / JG032320‑2); and (iv) pre-litigation transfer — HD Silicon Solutions renamed effective 2020‑11‑10 and sued 2020‑11‑30. Signals 6, 7, and 8 are affirmatively negatived, so this is not a defensive-aggregation ending.

Verify at: https://assignmentcenter.uspto.gov/ (search "7870404" or "11894991") — confirm against reels 022454/0522, 023268/0771, 036711/0160, 036797/0356, 051550/0711, 052199/0838, 052253/0751, 054993/0795. Patent text / assignee-chain cross-check: https://patents.google.com/patent/US7870404B2/en.

Open items I could not close (do not treat as findings): the reel/frame for the original inventor→Transmeta assignment (recorded against parent 09/694,433); correspondents for the six reels listed in signal 3; individual inventor departure dates; and whether Fahim Aftab was the correspondent of record on Reel 054993/0795 specifically.

I'll verify the patent record and key prior-art references before building the anticipation analysis.

Prior-Art Analysis — US 7,870,404 B2

Method note. I worked from the authoritative full text you supplied (Google Patents, fetched 2026-09-30) plus targeted verification searches. I did not substitute any near-neighbor patent number. Every reference below is reproduced literally as it appears in the '404 record (including quirky assignee spellings and the one clearly irrelevant citation). Where a date or an applied statutory basis is doubtful, I say so rather than resolve it.

1. The threshold fact that governs the whole analysis

The governing observation: every one of the 21 issued claims — independent claims 1, 7, 11, 15, 18 and therefore every dependent claim that incorporates them — requires one or more of these elements:

• E6 — an actual transition/ramp time from the sleep voltage to an operating voltage, and
• E7 — an "allowed time for transitioning from a sleep state to an operating state" of the computer system, with the claimed inequality between the two.

I searched all 110 patent citations and all 15 non-patent citations for any disclosure of a wake-up latency budget of the computer system compared against a regulator ramp time. None discloses E6+E7. The consequence is structural, not rhetorical:

In strict § 102 terms, no reference cited on the face of US 7,870,404 anticipates any of claims 1–21 — because no cited reference discloses the timing construct that is present in every claim. The cited art is overwhelmingly § 102(a)/(b)/(e) art of general relevance and § 103 material.

That is consistent with the enforcement history you already have: Microchip's IPR2021-01265 attacked the '404 as obvious over NEC Databook + Stratakos, not as anticipated by an examiner-cited reference; institution was denied.

Two further threshold flags before the citations:

1. Several cited references are dated after the critical date and so are not § 102(a)/(b)/(e) art at all against this family: US 2002/0073348 (filed 2000-12-13), US 2002/0087896 (filed 2000-12-29), US 2002/0138778 (filed 2001-03-22), US 2003/0065960 (filed 2001-09-28), US 2003/0074591 (filed 2001-10-17), and the Athlon-Processor Model 4 Data Sheet, Rev. K, Nov. 2001. If the examiner relied on these, the reliance is vulnerable on effective-date grounds. Flagging this explicitly rather than silently grading them as art.
2. US 7,260,731 B1 appears in the citation list — that is the '404's own parent (same inventors, same 2000-10-23 priority). It is not § 102 prior art to its own divisional.

Certificate of Correction: claims 11 and 15 read "voltage**;**" (not "voltage:") and claim 19 reads "responsive" (not "re responsive"). Claim text below is the as-corrected reading.

2. Element map used in the tables

3. The most relevant cited prior art — detailed

Tier 1-A — WO 2001/027728 A1 (Advanced Micro Devices, Inc.) — the closest citation on substance

• Full citation: WO 01/27728 A1, "Minimizing power consumption during sleep modes by using minimum core voltage necessary to maintain system state." Assignee: Advanced Micro Devices, Inc.
• Dates: international filing 1999-10-14; WO publication 2001-04-19.
• § 102 posture: the WO publication (2001-04-19) postdates the 2000-10-23 critical date, so it is not § 102(a) or § 102(b) art on its face. As a PCT designating the US with a pre-critical-date international filing date, it is a candidate § 102(e) reference under pre-AIA § 102(e) — subject to verification of the English-language PCT publication and the examiner's applied date. This is a real vulnerability/opportunity line and I will not state it more strongly than that.
• Disclosure (taken from the reference's own claim text as reproduced in the HD Silicon/Microchip record): a "power supply circuit responsive to control inputs to supply variable voltages"; a control circuit that supplies first voltage control information "indicating an operational voltage, while clocks are being supplied" and second voltage control information "indicating a second voltage, while the clocks are stopped," the second voltage lower than the operational voltage; a selector circuit, at least a first programmable register holding the two values, and control logic receiving "an indication of a wake-up event, an indication of a reset and an indication of the clock stop state" and generating the select signal. Dependent claim 7: the second voltage is "below the voltage level required to clock the circuit region at the predetermined frequency."
• Claim mapping: E1, E2, E3, E4, E5; and — element-for-element — the FIG. 3 architecture of the '404 (multiplexer 13, first input 14 from processor, second input 15 for deep sleep, control terminal 16 driven by stop-clock). Bears on D6/D10 (state-retention vs. computing-capability voltage), D9 (clocks stopped/enabled), and the structural elements of 1 / 11 / 15 / 18.
• § 102 verdict: Does not anticipate any of claims 1–21 — no E6/E7. Strong § 103 reference against the FIG. 3 subject matter and dependent claims 6/9/10.

Tier 1-B — US 5,852,737 A (National Semiconductor Corp.) — the strongest true § 102(b) art on the state-retention concept

• Full citation: US 5,852,737 A (Bikowsky), "Method and apparatus for operating digital static CMOS components in a very low voltage mode during power-down."
• Dates: filed 1995-04-24; issued 1998-12-22.
• § 102 posture: § 102(b) — patented well over one year before 1999-10-23.
• Disclosure (verified against the patent): system controller selectively programs a programmable power supply to generate "either an operating voltage, for example 5V, or a low voltage which is substantially lower than the operating voltage but which is sufficient to maintain register and internal state levels"; the programmable reference voltage ranges ≈1.5 V to 5.0 V; the controller drives the component via a component clock line and receives an idle status control signal; optionally several independent voltage-selecting circuits supply several components. Also: "no restoration or initialization of the system state is necessary upon powering the component following a power-down state."
• Claim mapping: E1, E2, E3, E4, E5, D9. It maps almost verbatim onto dependent claims 6 and 10 ("sleep voltage is sufficient to maintain state of said processing unit but is not sufficient to maintain processing activity") and onto claim 9's clock disable/enable.
• § 102 verdict: Does not anticipate (no E6/E7). Best single-reference § 102(b) art for the state-retention-voltage concept; the reference a challenger would want to pair with a transition-time teaching.

Tier 1-C — US 6,675,304 B1 (Intel Corp.)

• Full citation: US 6,675,304 B1 (Pole et al.), "System for transitioning a processor from a higher to a lower activity state by switching in and out of an impedance on the voltage regulator."
• Dates: filed 1999-11-29; issued 2004-01-06.
• § 102 posture: § 102(e) — US filing predates 2000-10-23.
• Disclosure: transitions the processor between activity states by switching an impedance in and out at the voltage regulator to change the voltage delivered to the processor for the lower-activity state.
• Claim mapping: E2, E3, E4, E5; claim 14 ("said adjustable voltage supply comprises a voltage regulator").
• § 102 verdict: No anticipation (no E6/E7). Solid § 103 art on claim 14 and on the two-level sleep/operate supply.

Tier 1-D — US 6,208,127 B1 (Maxim Integrated Products, Inc.) — closest cited art on the transition itself (E6)

• Full citation: US 6,208,127 B1, "Methods and apparatus to predictably change the output voltage of regulators."
• Dates: filed 1999-11-02; issued 2001-03-27.
• § 102 posture: § 102(e) (US filing 1999-11-02, before 2000-10-23). Not § 102(b) — it issued after 1999-10-23.
• Disclosure: methods/apparatus for controllably and predictably slewing the output voltage of a regulator from one level to another — i.e., control over the transition between output voltages (through the very Maxim regulator family the '404 specification calls out by name: "Prior art regulators such as the Maxim 1711 provide a feedback terminal…").
• Claim mapping: E2; and uniquely among the cited art it addresses E6 (the voltage transition/ramp itself).
• § 102 verdict: No anticipation — it does not tie a ramp time to a processor sleep-to-operate latency budget, nor to processor supply rails generally. This is the most valuable § 103 reference for the transition-time element when combined with Tier 1-A or 1-B.

Tier 1-E — US 5,917,262 A (Elonex I.P. Holdings, Ltd.)

• Full citation: "Variable-voltage CPU voltage regulator."
• Dates: filed 1994-10-07; issued 1999-07-06. § 102(b).
• Disclosure / mapping: a regulator whose CPU output voltage is variable under control → E2, E4, E5; claim 14.
• § 102 verdict: No anticipation. General-relevance § 102(b) art.

Tier 1-F — US 5,923,545 A (Intel Corp.)

• Full citation: "Method and apparatus for providing multiple output voltages from a voltage regulator."
• Dates: filed 1998-05-18; issued 1999-07-13. § 102(b).
• Mapping: E2, E4, E5 — "circuitry configured to provide … first operating voltage … and a second operating voltage." Bears on the structural core of claims 11, 15, 18.
• § 102 verdict: No anticipation.

Tier 1-G — US 6,021,500 A (Intel Corp.)

• Full citation: "Processor with sleep and deep sleep modes."
• Dates: filed 1997-05-07; issued 2000-02-01. § 102(b).
• Mapping: E1, E3; supplies the "sleep state / deep sleep" vocabulary found throughout the claims.
• § 102 verdict: No anticipation.

Tier 1-H — US 6,704,880 B2 (Intel Corp.) and US 2002/0026597 A1 (Dai)

• Full citations: US 6,704,880 B2, "Reducing sleep mode subthreshold leakage in a battery powered device by making low supply voltage less than twice the threshold voltage of one device transistor"; and its publication US 2002/0026597 A1, "Reducing leakage power consumption."
• Dates: both filed 1998-09-25; patent issued 2004-03-09; publication 2002-02-28.
• § 102 posture: § 102(e) (US filing before 2000-10-23). Not § 102(b) — issuance/publication postdate 1999-10-23.
• Disclosure: deliberately lowering the supply in sleep mode relative to threshold voltage to suppress subthreshold leakage — i.e., the motivation behind lowering the sleep rail.
• Mapping: E3.
• § 102 verdict: No anticipation. § 103 art on why one lowers the sleep rail.

Tier 1-I — US 6,510,525 B1 (Mediaq, Inc.)

• Full citation: "Method and apparatus to power up an integrated device from a low power state."
• Dates: filed 1999-04-26; issued 2003-01-21. § 102(b) (filing before 1999-10-23).
• Mapping: closest cited art on the wake-up / power-up side (E7's "operating state" half).
• § 102 verdict: No anticipation — no ramp-time-vs-allowed-time construct.

Tier 1-J — US 5,440,520 A (Intel Corp.)

• Full citation: "Integrated circuit device that selects its own supply voltage by controlling a power supply."
• Dates: filed 1994-09-16; issued 1995-08-08. § 102(b).
• Mapping: E1, E2, E4 — the processor commanding its own supply voltage.
• § 102 verdict: No anticipation. Background/§ 103.

Tier 1-K — US 5,712,731 A (Nokia Mobile Phones Ltd.)

• Full citation: "Method to reduce the power consumption of an electronic device comprising a voltage regulator."
• Dates: filed 1994-06-10; issued 1998-02-10. § 102(b).
• Mapping: E2, E4, E5.
• § 102 verdict: No anticipation.

Tier 1-L — US 6,094,367 A (Asustek Computer Inc.)

• Full citation: "Voltage regulating device for dynamically regulating voltage in a computer system."
• Dates: filed 1998-11-18; issued 2000-07-25. § 102(b).
• Mapping: E2; claim 14.
• § 102 verdict: No anticipation.

4. Complete citation-by-citation table (all remaining cited patent documents)

Legend for § 102: (b) = published/patented before 1999-10-23; (e) = US filing before 2000-10-23, publication later; ✗ = effective date after 2000-10-23 → not § 102 art; (fam) = same family. "Ant.?" = does it, on its face, anticipate any of the 21 claims?

* = third-party citation, per the Google Patents annotation.

5. Non-patent citations (all 15) and their bearing

6. Bottom line — anticipation matrix

Most likely § 103 combinations a challenger would assemble (not § 102):

1. WO 01/27728 + Maxim MAX1711/LTC1736 material — sleep voltage = minimum state-retaining voltage, selected on stop-clock, plus regulator-slew control.
2. US 5,852,737 + US 6,208,127 (or LTC1736) — programmable state-retaining low voltage, plus prediction/control of regulator output-voltage changes.
3. US 6,675,304 + US 6,208,127 — regulator-impedance switching into a lower-activity state, plus controlled output-voltage slew.
   The timing inequality of claims 1/7/11/15/18 remains the hardest element to reach, which is exactly where the refused IPR (NEC Databook + Stratakos) appears to have been aimed.

7. Flags and explicit uncertainty

• No reference anticipates. I want to be unambiguous: the answer to "which claims does reference X anticipate under § 102" is, for every reference cited on the '404, none of claims 1–21 — because the timing construct (E6/E7) appears in every independent claim and is inherited by every dependent claim. Anything stronger would not be defensible on this record.
• WO 01/27728's statutory status is genuinely uncertain. Its 2001-04-19 publication postdates the 2000-10-23 critical date; its 1999-10-14 international filing date makes it a candidate § 102(e) reference, but I have not verified the PCT publication language or the examiner's applied date. Do not treat the "§ 102(e)" tag above as settled.
• Six cited documents have effective dates after 2000-10-23 (listed in § 1) and are not § 102(a)/(b)/(e) art against this family. I flag this as a possible error in the citation set rather than silently grading them.
• Two citations appear facially irrelevant (US 5,701,783, a car-headlamp angle adjuster; US 5,687,114, a multi-bit nonvolatile memory) and one (US 5,204,863) concerns microprocessor-operation monitoring. These read as bulk-IDS artifacts.
• US 7,260,731 B1 in the citation list is the '404's own parent (same inventors, same 2000-10-23 priority) and is not § 102 art to its own divisional.
• I did not locate any 2026 CAFC docket activity naming 7,870,404, consistent with the earlier section. The appeal bearing number 2023-1397 concerns U.S. 6,774,033, a different patent.
• Prior-art content for the two AMD/Maxim/NSC references was verified against web sources (Google Patents for US 5,852,737; the HD Silicon/Microchip PTAB record for the WO 01/27728 claim text). For the remainder I relied on the titles/dates as printed in the '404 record itself and have not independently read every specification; treat the per-reference descriptions as title-level characterizations except where I cite quoted language.

I'll build the § 103 analysis on the prior-art section already produced. First, let me verify the identity of the two references Microchip actually relied on in the denied IPR (Stratakos and the NEC Databook), since those are the most probed combination and will anchor my analysis.

Obviousness Analysis — U.S. 7,870,404 B2 under 35 U.S.C. § 103

Scope note. This section builds on the element map (E1–E7, D6–D21) and the reference characterizations already established in the Prior-Art section; I do not re-derive them here. I have confirmed the actual grounds Microchip asserted in IPR2021-01265 against the primary documents (Petition, Patent Owner Preliminary Response, and the Board's institution decision), and I anchor the analysis on that combination before proposing alternatives.

1. Governing framework and the single point of novelty

The prior-art section reached a structural conclusion that governs everything below: every one of claims 1–21 requires E6+E7 — an actual voltage transition time compared against a system "allowed time for transitioning from a sleep state to an operating state," with a claimed inequality between them. That is the only point of novelty. E1–E5 (processor + sleep rail + two operating rails) are thoroughly anticipated in substance by the cited art; E6 (a controlled regulator slew) is disclosed by the Maxim and LTC1736 materials; E7 as a bare timing budget is disclosed in the ACPI / Southbridge / Athlon materials. The case therefore rises or falls on whether a PHOSITA would have been motivated to design a wake-up sequence oriented around the E6↔E7 relationship — i.e., to wake to a reachable intermediate rail before completing the ramp to the high rail.

That framing matters because it converts a facially "broad idea" patent into a narrow, single-concept patent. Narrow claims are not invulnerable, but they defeat lazy obviousness grounds — which is precisely what happened at the Board.

2. The combination that was actually tested — Ground 1 of IPR2021-01265

This is the only art combination ever adjudicated on this patent, and every future § 103 ground must be measured against it.

Ground 1: Claims 1–21 obvious over NEC-Databook (Ex. 1004, Single-Chip Microcomputer Databook, NEC Electronics Inc., May 1990) in view of Stratakos (Ex. 1005, Anthony J. Stratakos, High-Efficiency Low-Voltage DC-DC Conversion for Portable Applications, UC Berkeley Ph.D. dissertation, 1998), further in view of the knowledge of a POSITA; supporting exhibits included the ACPI Specification (Ex. 1006) and the Low Power Intel486 SX manual (Ex. 1036); expert declaration of Donald Alpert, Ph.D. (Ex. 1002).

The mapping, as the Petition actually presented it:

The numeric demonstration for claim 1: sleep 2.0 V → 3.3 V took ≈12.4 µs (≤ 15 µs allowed) and sleep 2.0 V → 3.78 V took ≈17.4 µs (> 15 µs allowed). On its face this squarely satisfies claim 1's inequality.

Why it failed — institution denied 2022-01-26 (Paper 11, panel Ippolito/Engels/Peslak). The Patent Owner's Preliminary Response and the Board's decision expose three defects, and they are the checklist for any improved ground:

1. The "allowed time" was unsupported by the references. Neither NEC-Databook nor Stratakos discloses any system-level allowed transition time, let alone one for the µPD751xx; the 15 µs figure came from the Petitioner's own expert reasoning. The Board found the Petition improperly used "the general knowledge of a POSITA to fill in the gaps."
2. No first and second sleep voltage. Both references disclose voltage ranges, not two discrete sleep rails. The Board: the Petition was "devoid of any explanation of why a voltage range would teach a POSITA a first and second sleep voltage." This kills independent claims 11, 15 and 18 on the stated ground.
3. No articulated motivation to combine. Powering a 1990 µPD751xx (a 4-bit microcomputer for VCRs/telephones) from a 1998 experimental doctoral-dissertation converter was not "plug-and-play"; the Petitioner's own expert conceded the Stratakos converter could not be used as-is. The Board asked the "crucial obviousness question": why, in 2000, would a POSITA recreate and then modify an experimental converter solely to power a decade-old specialized microcomputer? No persuasive answer was given.

Two cautions on weight. First, this was a § 314(a)/merits-threshold denial, not a final written decision — it is not a holding that claims 1–21 are non-obvious, and it creates no estoppel (see the PTAB section). Second, the denial partly reflects hindsight selection of exemplar voltages and an invented latency budget, which is a defect of that petition, not a property of the patent.

3. Stronger § 103 combinations

The litigated ground's weakness was its primary references — a 1990 4-bit microcomputer and a 1998 converter thesis that were never designed to work together. Better grounds pair references that are already addressed to the same problem in the same class of system.

Combination A — AMD's own sleep-voltage application + regulator-slew art + a documented exit latency

Why this is materially better than Ground 1. WO 01/27728 is the same architecture the '404 specification itself describes in FIG. 3 (multiplexer 13, processor-driven operating value at input 14, deep-sleep value at input 15, stop-clock as select at 16) — so the primary reference does the structural work the NEC-Databook could not, and the two references are in the same technical lane (both AMD, both processor power management). The ACPI/Athlon/Southbridge materials supply E7 from a documented, contemporaneous specification rather than from an expert's estmation — curing defect (1).

Motivation to combine: WO 01/27728 establishes the practice of programmatically dropping the core rail to a state-retention level on a clock-stop event; a PHOSITA implementing that practice against a known exit-latency budget (ACPI/real-time interrupt requirements) would immediately confront the finite slew rate of the regulator — a known, quantified constraint (Maxim/6,208,127; LTC1736; Stratakos). The predictable design response, once the full step cannot be completed within the budget, is to step to an achievable intermediate voltage first and complete the ramp afterward — the very two-step wake of claim 7.

Combination B — National Semiconductor's programmable state-retention supply + slew control + exit latency

Motivation: US 5,852,737 is the single best reference on the state-retention-at-low-voltage concept (it maps almost verbatim onto dependent claims 6 and 10). Its programmable-supply architecture makes the "second sleep voltage" a design input, not an accident — directly answering defect (2).

Combination C — Intel's regulator-impedance state transition + slew control + wake-up art

Motivation: same class of system (processor activity-state transitions via a regulator), same problem (what voltage/transition behavior to use on exit).

Combination D — Dynamic voltage-scaling art (multiple operating points) + a sleep-mode reference + slew control

Motivation (this is the combination aimed at the two-sleep-voltage claims 11, 15, 18): for each selected operating point, the corresponding state-retention rail must be chosen so that the wake ramp fits the exit-latency budget; because ramp time is a function of the voltage step (Stratakos; Maxim), a PHOSITA would necessarily pair a higher operating voltage with a higher sleep voltage and a lower operating voltage with a lower sleep voltage — claim 21 — and, by holding the step size roughly constant, arrive at approximately equal operating-to-sleep deltas (claim 17/20; see Combination E).

Combination E — For the deltas/pairing claims (15–17, 19–21): the self-admitted Maxim 1711 feedback network

The '404 specification names the Maxim 1711 by title and describes using its feedback terminal with a resistor–voltage divider — i.e., self-admitted prior art (see the Maxim non-patent citation). The specification's own FIG. 4 simply joins the divider to a higher source so the divider forces the output down rather than up. That inversion is a routine, predictable use of a known circuit:

• Claim 17 / 20 (deltas approximately equal for both pairs): the specification itself states the design goal and result — a 0.5–0.6 V drop "whether beginning at core voltages of 1.2 or 1.6 volts." Forcing a fixed ΔV with an offset-referenced divider is a known technique with a predictable result, the classic KSR "familiar elements according to known methods" case.
• Claim 14 (supply is a voltage regulator): US 6,675,304; US 5,917,262; US 6,208,127; US 6,094,367.

The independent-claim numeric patch (curing defect (1))

Any ground targeting claims 1 and 7 must supply E7 from a reference, not an expert. The proper move is to substitute a document that states an exit-latency figure — the ACPI Specification exit-latency parameter, the AMD Athlon C3/V_DD-retention timing, or the VIA Southbridge stop-clock/interrupt timing — as the source of the "allowed time," so that the inequality is demonstrated from the prior art rather than invented. This is exactly what the Board faulted Ground 1 for omitting.

4. Claim-by-claim § 103 matrix

Overall: the structural claims and the state-retention/clock dependents are readily obvious; the timing-inequality limitations of claims 1, 7, 11, 15 and 18 are where an obviousness case must be most carefully built.

5. Motivation-to-combine rationales, organized by KSR category

1. Combination of familiar elements according to known methods yielding predictable results. A dynamically adjustable regulator (WO 01/27728; US 6,675,304; Stratakos) + a state-retention low voltage (US 5,852,737; NEC-Databook) + known regulator slew behavior (Maxim; LTC1736). Ramps of different ΔV take correspondingly different times — a predictable physical result, not a discovery.
2. Design incentives and market forces. The entire field (Govil 1995; Weiser 1994; Intel DVS patents; Dai 6,704,880 on leakage) was driving toward lower idle rail, faster return. The ACPI/OnNow initiative contemporaneously imposed exit-latency requirements — the incentive to reconcile a slow rail against a fixed wake deadline.
3. "Obvious to try" — a finite number of identified, predictable solutions. Given (i) the budget and (ii) the ΔV∝time relationship, the solutions are few: don't sleep as deeply, speed up the regulator, or step up in stages. The two-step wake of claim 7 is one of a small set of predictable options. KSR expressly makes this sufficient motivation.
4. Design choice / obvious use of an old technique. The Maxim 1711 feedback divider used to lower an output (rather than raise it) is the known circuit applied with a predictable outcome; the "approximately equal deltas" of claims 17/20 is the natural consequence, which the specification itself reports.
5. Inherency of the timing inequality. For any given processor + regulator + load, the ramp times are physical consequences of the design. Where a challenger can show the configuration (three rails, a regulator whose full-range slew exceeds the system latency), the claimed inequality follows inherently — the patentee's own POPR concedes the relationship is "an integral part of the claims," which cuts toward inherency if the structure is shown.

6. Non-obviousness counterarguments a challenger must anticipate

• The Board's § 314(a) denial (2022-01-26). Not a merits holding and not binding (no estoppel; Thryv/Mylan foreclose appeal of the denial), but a court will notice that a full-scope challenge failed at the threshold. Any new petition/ground must cure the three defects (§ 2). Re-filing Ground 1 as-is would fail again.
• The "allowed time" cannot be a bare invocation of POSITA knowledge. POPR's central theme — that Petitioner "resorts to arguing that general knowledge of a POSITA would fill in the gaps" — is a durable criticism. Under KSR, POSITA knowledge is not an unbounded reservoir; there must be articulated reasoning with rational underpinning and a reasonable expectation of success. The allowed time must be sourced (ACPI/Athlon/VIA).
• Motivation to combine across system classes. The Board found "no POSITA would have been motivated" to adapt an experimental converter to a 1990 microcomputer. Combinations confined to like systems (AMD sleep-voltage app + AMD/ACPI exit-latency; NSC programmable-supply + known slew) remove that objection far better than the NEC/Stratakos pairing did.
• The "first and second sleep voltage" limitation (claims 11, 15, 18). No single cited reference discloses it; a challenger must affirmatively explain why selecting discrete paired rails out of disclosed ranges would have been obvious. This is the hardest element in the patent, and the Board already held the Petition failed to supply that explanation.
• No secondary considerations of record. The patent is expired (fee lapse effective 2023-01-11), and no commercial-success or licensing nexus evidence appears in the record; however, a patentee could attempt to tie Transmeta's LongRun/Adaptive Power Control to the claims — a nexus challenge would follow. I found no proof that a shipped Transmeta part practiced these divisional claims.

7. Bottom line

• No cited reference anticipates any of claims 1–21 (unchanged from the prior-art section) — the timing construct E6+E7 is in every claim. Every viable § 103 ground is a combination.
• The combination actually tested — NEC-Databook + Stratakos + POSITA knowledge — is the weakest plausible primary pairing and was correctly denied institution, principally for an unsupported "allowed time," no discrete sleep voltages, and a hindsight-flavored motivation across mismatched system classes.
• The strongest untested grounds center on WO 01/27728 (AMD) and US 5,852,737 (NSC) as primaries — because they disclose the '404's own FIG. 3 architecture and the state-retention low rail in the same class of system — combined with known regulator-slew art (US 6,208,127 / LTC1736) and a documented exit-latency reference (ACPI / AMD Athlon / VIA Southbridge / US 5,894,577) to supply E7.
• The two-step wake (claim 7) is the concept most amenable to a KSR "obvious to try" argument; the paired-rail claims (11, 15, 17, 18, 20, 21) are the most resistant and require an explicit, non-hindsight rationale for selecting discrete paired rails.
• Strength ranking: dependents 6, 9, 10, 14 (strong) > 17, 20 (moderate–strong) > 1, 7, 12 (moderate) > 11, 15, 16, 18, 19, 21 (weakest).

8. Explicit uncertainty and sourcing flags

• Claim-text caveat: cite the as-corrected text (certificate of correction, 2011-05-31) — claim 11/15 "voltage;" and claim 19 "responsive." Claim 18 is the one independent claim I flag as potentially governed by § 112(f) ("means for supplying a voltage"), so its prior-art mapping would run through the specification's corresponding structure (regulator 11 / mux 13) plus equivalents.
• WO 01/27728's statutory status is genuinely unsettled (2001-04-19 publication postdates the 2000-10-23 critical date; 1999-10-14 international filing makes it a candidate § 102(e) reference subject to verification). Do not treat its § 102(e) tag as settled — for a § 103 ground it can also serve as § 103(c)/background evidence of the state of the art.
• I relied on the IPR record, not PACER/PTAB E2E directly, for the Ground 1 mapping and the Board's reasoning. Verified sources: Petition (https://www.docketalarm.com/cases/PTAB/IPR2021-01265/Microchip_Technology_Inc/docs/07-20-2021-Petitioner/Petition-2-Petition_for_Inter_Partes_Review_of_US_Patent_No_7,870,404.pdf); Patent Owner Preliminary Response, Paper 6, 2021-10-28 (https://www.docketalarm.com/cases/PTAB/IPR2021-01265/Microchip_Technology_Inc._v._HD_Silicon_Solutions_LLC/docs/10-28-2021-Patent_Owner/Preliminary_Response-6-Patent_Owners_Preliminary_Response.pdf); institution decision excerpts (https://ptacts.uspto.gov/ptacts/public-informations/petitions/[1547797](/patent/1547797)/...); exhibit list (Ex. 1004 NEC-Databook; Ex. 1005 Stratakos; Ex. 1006 ACPI; https://www.docketalarm.com/cases/PTAB/IPR2021-01265/.../Exhibit_List-10-Petitioners_Updated_Exhibit_List.pdf). Stratakos verified at https://www2.eecs.berkeley.edu/Pubs/TechRpts/1998/8047.html (Ph.D. thesis, UC Berkeley, 1998).
• I could not retrieve the full text of Paper 11, so I have characterized the denial using the Board's own quoted reasoning as it appears in the reproduced response/document excerpts; do not attribute a Fintiv holding to the denial — the coded label and the text both point to § 314(a) merits failure.
• The specific numeric voltages and the 15 µs "allowed time" are Petitioner's selections in Ground 1, not admissions or disclosures of the references; I flag them as such because a similarly constructed ground would face the same criticism.
• No 2026 CAFC activity naming 7,870,404 was found, consistent with the earlier sections; the Federal Circuit appeal bearing 2023-1397 concerns U.S. 6,774,033, a different patent.