US 7260731

I'll search for authoritative information on this patent and any 2026 CAFC activity.

US Patent 7,260,731 — Analyst Summary

Source of record: Google Patents (authoritative full text supplied) — https://patents.google.com/patent/[US7260731](/patent/US7260731)/en; USPTO full-text PDF: https://patentimages.storage.googleapis.com/e9/3d/d8/780a2b887ae38a/[US7260731B1](/patent/US7260731B1).pdf

Bibliographic Data (verbatim from source)

Ownership chain: Transmeta Corporation → Transmeta LLC (2009 merger) → Intellectual Venture Funding LLC (2009) → Intellectual Ventures Holding 81 LLC (2015) → Intellectual Ventures Assets 156 LLC (2020) → Innovative Silicon Solutions, LLC (2020) → HD Silicon Solutions LLC (2021 name change).

Continuity/family (all sharing the 2000-10-23 priority):

• Division: US 11/894,991 → US 7,870,404 B2 ("Transitioning to and from a sleep state of a processor")
• Continuation: US 12/987,423 → US 9,436,264 B2
• Continuation: US 15/241,690 → US 9,690,366 B2 ("…by using feedback-configured voltage regulator")
• PCT: PCT/US2001/050801 → WO 2002035334 A1 ("Method and apparatus for reducing static power loss")

Abstract (as issued)

"A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled." (Note: the typographical error "is which" appears in the granted abstract and in the specification's Summary section; I have not corrected it.)

Technical Gist

The patent addresses static (sub-threshold leakage) power loss while a processor sits in "deep sleep" with its system clock stopped. Prior-art processors held the same core voltage in deep sleep as during computing (e.g., 1.8 V), wasting roughly 0.5 W to leakage. The invention lowers core voltage to a retention-only level — below the lowest voltage at which the processor is specified to compute — using one of three mechanisms:

1. FIG. 3: a multiplexer (13) selects between a normal VID input (14) and a deep-sleep input (15), controlled by the stop-clock signal (16), forcing the regulator to its lowest output (e.g., 0.925 V).
2. FIG. 4: a resistor divider (43 = 1 kΩ, 45 = 2.7 kΩ) is tied between the regulator output and a higher source (42 = 3.3 V) and fed back to the regulator's FB pin, forcing the output down (e.g., −0.5 to −0.6 V) rather than up — so the final sleep voltage depends on the voltage it started from.
3. FIG. 5: a control input (50, 51) switches the regulator between continuous/PWM "low noise" mode (which returns charge to the battery) and burst/skip "high efficiency" mode during the high-to-low transition, plus an optional bidirectional charge pump (53) or load-based charge drain.

Two disclosed constraints on how low the voltage may go: (a) state must be retained (tests showed <0.5 V retains memory state), and (b) the transition must complete within the ~50 µs wake/sleep window (only ~0.5–0.6 V of swing available in one exemplary configuration).

Plain-Language Overview of the Independent Claims

Claim 1 (method — mode-switching regulator). Detect that the processor is going from computing into a clock-disabled state; drop the core voltage to a level that is enough to hold state but not enough to keep processing; and — in response to that detection — switch the voltage regulator from a first regulation mode in which power is dissipated during the downward voltage transition to a second mode in which power is saved during that same transition.

Claim 4 (method — input + feedback reduction). Detect the transition to the clock-disabled state, then lower the core voltage by two cooperating actions: (i) supplying an input that commands the regulator to reduce its output, and (ii) supplying a feedback signal to the regulator that pulls its output below the regulator's specified/nominal output voltage.

Claim 6 (method — conserving during the transition; system level). Detect the processor's transition into the clock-disabled mode; reduce the regulator's core voltage to a state-retention level; and shift the regulator out of a mode that wastes power on downward voltage transitions into a mode that saves power on that transition — the shift being triggered by the detection of the entry into the clock-disabled mode. (Claim 7 adds returning the regulator to its original mode once the retention voltage is reached.)

Claim 8 (circuit — selectable voltage + mode change). A regulator with an output terminal for a selectable voltage and an input terminal for level-selecting signals; means for presenting both a computing-mode voltage and a lower, state-retaining voltage at that input; and means for moving the regulator from a power-dissipating downward-transition mode to a power-saving one. (Claim 9 = binary level-select signals; claims 10–11 = multiplexer with a clock-termination control terminal.)

Claim 12 (circuit — below spec minimum). Same regulator structure and means for selecting computing vs. lower voltage, plus means for reducing the selectable voltage below the lowest level the regulator is specified to output.

Claim 13 (circuit — above-rail divider feedback). Same regulator, now expressly including a regulator feedback circuit; means for selecting computing vs. lower voltage; and means for reducing the voltage comprising a voltage divider network connected between the output terminal and a voltage source higher than the selectable voltage, with the regulator's feedback circuit receiving a value from that divider. (This tracks FIG. 4.)

Claim 14 (circuit — charge conservation). Regulator with output/input terminals; means for selecting computing vs. lower voltage; circuitry for changing the regulator from a power-dissipating downward-transition mode to a power-saving one; and means for enabling that circuitry to conserve charge stored by the regulator when the voltage decreases (e.g., charge pump or battery return, per FIG. 5).

Claim 15 (circuit — feedback-network apparatus). A regulator with an output terminal, an input terminal, and a regulator feedback circuit; circuitry coupled to the input terminal that selects a first voltage for a first mode and a second voltage for a second mode; a voltage source furnishing a value higher than the selectable voltage; and a feedback circuit coupled to that source, the output terminal, and the regulator feedback circuit. (Claims 16–18 add that the first/second voltages are computing vs. lower, and that the feedback circuit is a voltage divider.)

Litigation and Post-Grant Status

• District court: HD Silicon Solutions LLC v. Microchip Technology Inc., No. 6:20-cv-01092 (W.D. Tex., filed Nov. 30, 2020; the '731 patent was Exhibit 1 to the complaint); transferred Oct. 25, 2021 to N.D. Cal., No. 3:21-cv-08295, and dismissed with prejudice on April 14, 2025 (per Patsnap litigation data).
• PTAB: Two Microchip IPRs against the '731 patent — IPR2021-01420 and IPR2021-01421, both filed Sept. 14, 2021 — were institution-denied on May 12, 2022 (Board decisions; see https://ipverse.greyb.com/ptab-web/cases/case-details/IPR2021-01420 and .../IPR2021-01421). The petition papers and the Alpert declaration are public at ptacts.uspto.gov (petitions 1548174 / 1548616). Because institution was denied, no final written decision on the '731 patent exists.
• A further W.D. Tex. case, No. 1:25-cv-01320, is listed against HD Silicon Solutions in the Google Patents litigation record (2025). I could not retrieve docket details or the asserted patents for that case from the searches performed.

CAFC 2026 Docket Check — Explicit Uncertainty

I found no Federal Circuit docket or opinion in 2026 involving U.S. Patent 7,260,731. Two cautions:

1. The Federal Circuit decision reported in Feary 2025 that involves HD Silicon Solutions — HD Silicon Solutions LLC v. Microchip Technology Inc., No. 2023-1397 (Fed. Cir. Feb. 6, 2025) (Lourie, Stoll, Cunningham) — concerns U.S. Patent No. 6,774,033 ("Metal stack for local interconnect layer"), not the '731 patent. Do not conflate them.
2. Search hits that superficially matched "726" in 2026 CAFC filings were unrelated: Collision Communications, Inc. v. Samsung Electronics Co., Ltd., No. 2026-1893, and De Sousa v. Smart726, No. 2026-1420 (Fed. Cir. order, Feb. 23, 2026, dismissing under Fed. R. App. P. 42(b)). "Smart726" there is a party name, not a patent reference.

Given that both IPRs against the '731 patent were denied institution and the sole district-court action asserting it was dismissed with prejudice in April 2025, there is no obvious posture from which a 2026 Federal Circuit appeal on this patent would arise — but I cannot fully exclude a 2026 appeal from the newer W.D. Tex. case (1:25-cv-01320) or an unnoticed docket, so this should be treated as not confirmed rather than affirmatively negative.

Confidence and Caveats

• High confidence: title, inventors, assignee-as-issued, application number, filing date (Oct. 23, 2000), issue date (Aug. 21, 2007), claim text and dependency structure, abstract, specification content, PTAB denial of institution, and the family members.
• Medium confidence: the precise disposition/date of the N.D. Cal. dismissal and the existence/details of the 2025 W.D. Tex. case — these come from third-party litigation aggregators, not the courts' own dockets.
• Low confidence / unverified: current ownership nuances after the 2021 HD Silicon Solutions name change, and any 2026 appellate activity on this patent. One aggregator lists the '731 priority date as 2000-10-22, which conflicts with the patent face (2000-10-23); I have not auto-corrected either value but treat the patent face as authoritative.

I'll search for litigation involving US Patent 7260731, focusing on litigation databases and court records.

Let me search for the specific district court cases identified in the patent record.

Let me search for the third district court case and additional details.

Litigation Involving U.S. Patent No. 7,260,731

Patent identification (literal, as recorded): U.S. Patent No. 7,260,731 (the "'731 patent"), "Saving power when in or transitioning to a static mode of a processor." Application No. 09/694,433; filed October 23, 2000; granted August 21, 2007; original assignee Transmeta Corporation (later Transmeta LLC → Intellectual Venture Funding LLC → Intellectual Ventures Holding 81 LLC → Intellectual Ventures Assets 156 LLC → Innovative Silicon Solutions, LLC → HD Silicon Solutions LLC, current assignee). The patent expired November 22, 2020 (adjusted expiration; status "Expired – Lifetime").

Based on the sources retrieved, the '731 patent has been asserted in two district court actions (the same underlying dispute, originally filed in Texas and transferred to California) and has been the subject of two IPR petitions. Details follow.

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1. HD Silicon Solutions LLC v. Microchip Technology Inc.

2. HD Silicon Solutions LLC v. Microchip Technology Inc. (transferred case)

3. HD Silicon Solutions LLC v. NXP Semiconductors NV

Note: This case appears in the litigation listing associated with U.S. 7,260,731. I could confirm the case caption, number, court, and filing date from the sources retrieved, but the retrieved records did not specify which of HD Silicon Solutions' patents (the '731 patent or other patents in the same family, e.g., 7,870,404 / 9,436,264 / 9,690,366) is asserted. I cannot confirm with high confidence that the '731 patent itself is among the patents asserted in HDSS v. NXP; treat that linkage as unconfirmed.

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PTAB (Inter Partes Review) Proceedings on the '731 Patent

These were part of a broader set of Microchip IPRs against HDSS's asserted patents (e.g., IPR2021-01089 on the '299 patent; IPR2021-00872/'01042 on the '619 patent; IPR2021-00752 on the '033 patent; IPR2021-01265 on the '404 patent).

The patent's Google Patents page also flags the family as having litigation (entries for the N.D. Cal. case 3:21-cv-08295, the W.D. Tex. case 6:20-cv-01092, and the W.D. Tex. case 1:25-cv-01320) and lists an IPR2021-01421 PTAB case, consistent with the above.

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Summary / Caveats

• Known district court litigation specifically identifying the '731 patent: HD Silicon Solutions LLC v. Microchip Technology Inc., filed as 6:20-cv-01092 (W.D. Tex.), transferred to N.D. Cal. as 3:21-cv-08295, ultimately dismissed with prejudice on April 14, 2025. The '731 patent was one of seven patents asserted, with claims 1, 4, 6, and 8 accused.
• Additional pending case on the family: HD Silicon Solutions LLC v. NXP Semiconductors NV, 1:25-cv-01320 (W.D. Tex.), filed August 19, 2025, currently open — but I could not confirm from the retrieved records that the '731 patent itself is asserted.
• PTAB: Two Microchip IPR petitions (IPR2021-01420 and IPR2021-01421) on the '731 patent; both denied institution on May 12, 2022.
• I did not find any CAFC appeal arising from the '731 patent, and no other defendants or jurisdictions in the search results. If an appeal of the N.D. Cal. dismissal (or of the IPR denial) exists, it was not surfaced in these results.

If you need PACER-level docket verification (e.g., full docket text for the 1:25-cv-01320 case to confirm which patents are asserted, or the final judgment in 3:21-cv-08295), I can run additional targeted searches on the specific case numbers.

I'll start by verifying the PTAB docket picture, since the structured ODP block says "none" but the patent's own Google Patents page surfaces two IPR case numbers.

Key correction found: the petitioner is Microchip Technology, Inc., not Unified Patents (the "Unified Patents" text on the patent page is a data-attribution string). Let me verify the denial reasoning and the parallel litigation.

Now let me pull the Federal Circuit appeal and the 2025 assertion activity, plus the exact claim scope of each petition.

Source reconciliation (read first)

Two things need correcting before the analysis:

1. The structured "PTAB proceedings on file" block is wrong/incomplete. It says the ODP API returns no AIA trial proceedings. That is contradicted by the patent's own Google Patents record, which lists two PTAB cases and links them, and by the Board's own public decisions. I am reporting the two proceedings that demonstrably exist on the public record rather than honoring an empty ODP response. (This is a known ODP ingest gap for older, non-instituted trials — never treat an empty ODP array as an affirmative "no challenges were filed.")
2. The petitioner is NOT Unified Patents. The Google Patents page shows Petitioner: "Unified Patents PTAB Data" — that is a data-attribution string for the PTAB dataset license, not the party. The real petitioner on both petitions is Microchip Technology Inc. The real party in interest, per Microchip's own 37 C.F.R. § 42.8 mandatory notices, is Microchip Technology Inc. alone.

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Proceedings overview

Two AIA trial proceedings on US 7,260,731 — both Inter Partes Review, both filed 2021-09-14 by Microchip Technology Inc., both institution DENIED on the merits on 2022-05-12, both terminated with no Final Written Decision ever issued. Breakdown: 0 active, 0 claims invalidated, 0 claims sustained (no FWD = no merits adjudication), 0 settled, 2 institution-denied.

Bottom line for a defendant: the patent is completely un-narrowed — all 18 claims are alive and none has ever been tested on the merits — but it has also never survived a merits trial, no estoppel attaches to anyone, and the patent is expired. This is a "paper-hardened, merits-untested" patent. There is no cancel-the-claims silver bullet, and no prior IPR estoppel blocking a fresh petition.

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IPR2021-01420 — Microchip Technology Inc. v. HD Silicon Solutions LLC (claims 1–7)

• Type: Inter Partes Review (post-AIA; patent filed 2000-10-23, so pre-AIA claims but AIA trial procedures apply)
• Filed: 2021-09-14 (Petition filed same day as its companion, IPR2021-01421)
• Status: Institution Denied (verbatim from structured data). Plain English: the Board never instituted; the trial never started; no claim was ever adjudicated.
• Judge panel: Administrative Patent Judges ENGELS (writing), PESLAK, and IPPOLITO. Same three-judge panel decided both petitions.
• Petition grounds: Obviousness under 35 U.S.C. § 103 over NEC-Databook in view of Burd (Ground 1), with limitation-by-limitation mapping to claims 1, 3, 6, and 7. Microchip's own § 42.8 notice states Petition 1 challenged claims 1–7. (Discrepancy flag: a secondary rendering of the decision's ORDER paragraph recites "claims 1–5"; I could not resolve that from the excerpt I retrieved. The Board's substantive analysis addressed claims 1, 3, 6, and 7, so I am using the petitioner's own stated scope of claims 1–7 rather than picking silently between the two.)
• Institution decision: DENIED, 2022-05-12 (Paper 13). Reasoning: the Board rejected Microchip's obviousness theory because the combination did not meet all limitations, and the motivation-to-combine showing failed — as one PTAB digest summarized, Microchip showed only a "theoretical" possibility of combining a 1990 data book with a 2000 conference presentation, and "ultimately failed to show why a skilled artisan would have in fact been motivated to do so." Critically, the Board denied on the merits and expressly did not reach the parties' 35 U.S.C. § 314(a) discretionary-denial arguments. Decision: IPR2021-01420 Paper 13 (May 12, 2022)
• Final Written Decision: None. No FWD was ever issued. Do not let anyone tell you a claim of the '731 patent was "held valid" here — the Board never reached the merits of patentability in a final decision.
• Settlement / termination: Not settled. Terminated on the institution denial. Board approved a refund of the post-institution fees on 2022-05-26 (Docket Alarm: Notice: refund approved, Refund Request of Post-Institution Fees filed by petitioner 2022-05-17).
• Appeal: None, and none was legally available on the denial. Precedent forecloses it. Microchip's appeal rights here were effectively nil, and the CAFC docket shows no appeal from either '731 IPR number.
• Defensive value: Claims 1–7 are completely intact and un-narrowed, but the denial hands you a free roadmap: the Board has already rejected the NEC-Databook + Burd theory, so recycling it verbatim is futile. Because there was no FWD, no § 315(e)(2) estoppel attaches — Microchip is not barred, and neither are you.

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IPR2021-01421 — Microchip Technology Inc. v. HD Silicon Solutions LLC (claims 8–18)

• Type: Inter Partes Review

• Filed: 2021-09-14

• Status: Institution Denied (verbatim). Plain English: same result as its companion — no trial, no adjudication.

• Judge panel: Before IPPOLITO, ENGELS, and PESLAK, Administrative Patent Judges; ENGELS authored.

• Petition grounds: Two three-way § 103 combinations against the circuit claims:

  • Ground 1 — Helms + Maxim-165X-Datasheet + MAX1711-Kit, against claims 8–11 and 14;
  • Ground 2 — Helms + TI-TPS5210-Datasheet + Nilsson, against the remaining challenged claims.

  The § 112 / written-description side was not the Battleground; this was purely an obviousness attack. Patent Owner's Preliminary Response (Paper 12, 2022-02-16) attacked both grounds as lacking reasonable expectation of success and motivation to combine.

• Institution decision: DENIED, 2022-05-12 (Paper 13). Reasoning: the information presented in the Petition "does not establish a reasonable likelihood that Petitioner would prevail with respect to at least one of the challenged claims," so under § 314(a) the Board did not institute. Patent Owner also argued all five Fintiv factors favored discretionary denial (no stay requested; FWD expected ~2023-05-16; petitioner delay; issue overlap; same petitioner and defendant) — the Board denied on the merits and did not need to reach Fintiv. Decision: IPR2021-01421 Paper 13 (May 12, 2022)

• Final Written Decision: None. Zero claims canceled, zero claims. Claims 8–18 (including independents 8, 12, 13, 14, and 15) were never adjudicated.

• Settlement / termination: Not settled; terminated on denial. Post-institution fees refunded (same 2022-05-26 refund entry).

• Appeal: None.

• Defensive value: The Board has now twice refused Microchip's maxim-specific art (MAX1711, TPS5210) on three-way-combination grounds. That is useful anti-obviousness ammunition for the circuit claims, but it is not claim preclusion and not issue preclusion — a different defendant with a cleaner two-reference combination is not bound by this reasoning at all.

Counsel of record (both proceedings): Petitioner — Sanjeet Dutta (Goodwin Procter LLP; pro hac vice Brett M. Schuman and Rachel M. Walsh per the 2022-02-07 order). Patent Owner — Justin J. Oliver and Sarah S. Brooks (Venable LLP).

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Related-family appeals (NOT on the '731 patent — do not conflate)

These are frequently confused with the '731 IPRs because the same parties and counsel appear:

HDSS lost both of these appeals. Neither arose from the two '731 denials (which, as institution denials under § 314(d)/Thryv v. Click-to-Call, were not appealable).

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Strategic summary

Claim status of US 7,260,731. The entire claim set is UNTESTED on the merits: no claim is canceled, none is judicially sustained. Claims 1–7 were challenged in IPR2021-01420 and claims 8–18 in IPR2021-01421 — a full-frontal attack on all 18 claims — and both petitions died at the § 314(a) threshold. The practical read: HDSS has 18 live claims, an un-narrowed claim 1 (which already recites the regulation-mode-transition limitation), and zero merits wins to show for five years of PTAB litigation. Note also that the patent's Google Patents legal-status field shows "Adjusted expiration 2020-11-22" — the '731 patent appears to have expired. If that is right (treat it as a legal conclusion to verify, not one I'm rendering), a 2025 assertion reaches only past infringement inside the 35 U.S.C. § 286 six-year lookback, i.e., a window that closes roughly a year after the priority-plus-20 date. The 2025 W.D. Tex. suit (1:25-cv-01320) would then be a past-damages play, not an injunction play.

Estoppel landscape. This is the most important defensive point: there is no IPR estoppel on this patent. Section 315(e)(2) estoppel is triggered only by a final written decision; an institution denial triggers nothing — not for Microchip, not for its privies, not for anyone. Accordingly: (a) Microchip itself is not estopped and could re-file; (b) you are free to file a fresh IPR on the '731 patent on any art and any theory, including art Microchip used and theories the Board rejected, because "could have raised" estoppel has no anchor without a FWD; (c) conversely, HDSS's own § 315(e)(1) patent-owner-side estoppel problem is nil, and the two denial decisions have no preclusive effect on claim construction or patentability — they are persuasive authority only. Watch the § 315(b) one-year clock: any new defendant served in the 2025 case gets its own 12-month window, and a Fintiv-based discretionary denial is now materially less likely given the Federal Circuit's 2024–2025 retreat from Fintiv (and note the Board never reached Fintiv here anyway).

Pattern signals. Yes — textbook repeat-player behavior. Microchip filed a coordinated six-patent, eight-petition campaign against the HDSS portfolio on 2021-04-23 through 2021-09-14 ('033 IPR2021-00752; '619 IPR2021-00872 and IPR2021-01042; '299 IPR2021-01089; '404 IPR2021-01265; '731 IPR2021-01420 and IPR2021-01421), taking a pincer approach on the '731 patent by splitting claims 1–7 and 8–18 across two petitions. No defensive aggregator is in the chain — the "Unified Patents" text on the Google Patents page is dataset attribution, not petitioner status. Patent Owner posture: HDSS litigates hard (it beat both '731 institution attempts and argued full Fintiv), but it lost both related-patent appeals, including a precedential affirmance on the '033 patent. HDSS itself is a monetization vehicle: the patents passed IV → Intellectual Ventures Assets 156 → Innovative Silicon Solutions (nunc pro tunc, 2020-03-23) → renamed HD Silicon Solutions (2021-01-14), and the complaint against Microchip was filed 2020-11-30, roughly eight months after the assignment — a classic arm's-length assertion setup. Litigation venue thread: 6:20-cv-01092 (W.D. Tex., filed 2020-11-30, Judge Albright) → transferred 2021-10-25 to 3:21-cv-08295-SK (N.D. Cal., Mag. J. Sallie Kim) → new 1:25-cv-01320 (W.D. Tex.).

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Recommended next steps

1. No claim of '731 is invalidated, so do not build a defense on "the PTAB killed it." That said, you have a full merits record to mine: both denial decisions are public and quote the Board's reasoning — IPR2021-01420 Paper 13 and IPR2021-01421 Paper 13. Use them to identify which limitation mappings and motivation-to-combine showings the Board found wanting, then build a different combination rather than re-running NEC-Databook + Burd or Helms + Maxim/TPS5210.
2. File a fresh IPR with new art. No § 315(e)(2) estoppel attaches from either denial, and Fintiv-style discretionary denial is on the wane. Verify your own § 315(b) bar date from the date you were served in the 2025 W.D. Tex. action before filing.
3. Run the expiration math immediately. If the '731 patent term ended 2020-11-22 as the Google Patents legal-status field indicates, then a 2025 complaint is limited to past damages for infringement inside the § 286 six-year window and to infringement before the expiration date. That is a case-narrowing, potentially case-ending motion — confirm against the front page (PTA/terminal disclaimer) and the USPTO Patent Center fee/expiration record rather than relying on the Google Patents field, and note that Google's own page disclaims that legal status as an assumption, not a legal conclusion.
4. Track 1:25-cv-01320 (W.D. Tex.) for the accused products and new defendants. Because the '731 claims are un-narrowed, HDSS can assert all 18 claims, and there is no prior-IPR estoppel protecting or constraining anyone on this patent.
5. Portfolio-level read. HDSS's related patents have fared worse than '731: the '033 claims were invalidated and affirmed (precedential, 2025-02-06), and the IPR2021-01567 appeal was affirmed under Rule 36 (2025-01-15). If a demand letter cites a portfolio, check each patent's own PTAB history — the '731 patent is the outlier that survived institution, not the rule.
6. Audit the ODP gap on your side. The "no PTAB activity on file" response was wrong for this patent. If your docket-monitoring pipeline trusts that array, it will silently miss non-instituted trials — precisely the population that old, expired patents fall into. Cross-check against PTAB E2E / Patent Center and the litigation data feeds.

Confidence and gaps: Panel composition, filing dates, denial dates, challenged claim sets, and petition grounds are sourced to the Board's own decisions and the parties' PTAB filings and are high-confidence. Two items I flag as unresolved: (a) whether IPR2021-01420's operative ORDER recited "claims 1–5" or "claims 1–7" — sources conflict and I did not resolve it; (b) the specific patent and claim outcome in IPR2021-01567 (the origin of CAFC 23-1943) — it is not the '731 patent, and I am not asserting what it held, only that the appeal was affirmed under Rule 36 on 2025-01-15.

I'll start by attempting to pull the Assignment Center records (correspondent of record is the key field Google Patents omits), and cross-check the litigation/asserter directories.

Strong hit — the IPR exhibit surfaced the actual assignment document and correspondent. Let me pull more of that chain and the litigation context.

Ownership Analysis — US 7,260,731 B1

"Saving power when in or transitioning to a static mode of a processor"
Application 09/694,433 · filed 2000-10-23 · issued 2007-08-21 · status: Expired – Lifetime (adjusted expiration 2020-11-22)

Source note / verification limit. I was not able to render the Assignment Center (assignmentcenter.uspto.gov) result pages directly in this session. The reel/frame numbers, execution dates, effective dates, and conveyance types below are taken from (a) the Google Patents "Legal Events" record for US 7,260,731, which reproduces the USPTO assignment data, and (b) the actual recorded assignment documents filed as exhibits in IPR2021-01420 / IPR2021-01421 (Ex. 1004 and related), which reproduce the USPTO assignment cover sheets including the CORRESPONDENCE DATA block. Correspondent-of-record names were recoverable only for the 2020 links; the remaining reels' correspondents are marked as gaps rather than guessed. Verify all entries at: https://assignmentcenter.uspto.gov/ (search patent 7260731) and https://assignment.uspto.gov/patent/index.html.

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Inventors

Pattern notes. Execution of the inventor assignment (2001-01-25) postdates the filing by ~3 months and postdates the 2000-10-26 California→Delaware corporate merger record (reel 011566/0681) — consistent with a standard pre-IPO housekeeping sweep rather than any inventor-driven transfer (Transmeta IPO'd in November 2000).

All three inventors assigned to Transmeta in a single instrument; I found no evidence any inventor individually retained or later re-acquired rights. I found no evidence of inventors departing Transmeta within 12 months of filing — mark that as not determinable from the assignment record alone; it would require employment/SEC data I could not verify here. Notably, the specification cites Transmeta's own copending application 09/484,516 ("Adaptive Power Control"), confirming this is an internal Transmeta R&D work product, not an acquired-in filing.

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Original assignee

Entity on the issued patent: Google Patents lists the original assignee as "Transmeta Inc." (current assignee listed as Hd Silicon Solutions LLC). ⚠️ Literal discrepancy: the recorded assignment names "Transmeta Corporation, a Delaware corporation," and the 2001 merger record names "Transmeta Corporation, a California corporation." I have not auto-corrected these — treat "Transmeta Inc." as a Google Patents label, not necessarily the recorded legal name.

Business. Transmeta Corporation was a fabless x86-compatible microprocessor company (founded 1995; Crusoe and Efficeon product lines; code-morphing software; LongRun power management). It shipped actual silicon and its power-management architecture is squarely the subject matter of the '731 claims (dynamic core-voltage/frequency control plus core-voltage reduction in clock-stopped "deep sleep").

Status. Transmeta exited the processor business (restructuring announced 2005) and by 2009 had ceased to operate as a product company. The chain shows Transmeta Corporation → Transmeta LLC (merger, effective 2009-01-27) and then, one day later, effective 2009-01-28, a sale of the portfolio to Intellectual Venture Funding LLC. The 2009 transfer is best characterized in the records as a distressed portfolio divestiture by a wound-down operating company. I could not independently verify via SEC filings whether a formal bankruptcy proceeding occurred, so I am not asserting Chapter 7/11.

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Assignment timeline

All entries below are recorded assignments; "effective" dates are as stated on the recorded instrument.

• 2001-01-25 (executed) / recorded 2001-02-05 — Reel 011536/0490

  • Conveyance: Assignment of assignors' interest
  • Assignor: Andrew Read; Sameer Halepete; Keith Klayman
  • Assignee: Transmeta Corporation, a Delaware corporation
  • Correspondent: not retrieved (see verification limit above)
  • Context: Ordinary employment/invention assignment to the operating company.

• 2000-10-26 (effective) / recorded 2001-02-13 — Reel 011566/0681

  • Conveyance: Merger
  • Assignor: Transmeta Corporation, a California corporation
  • Assignee: Transmeta Corporation (Delaware)
  • Correspondent: not retrieved
  • Context: Internal reorg / change of domicile (CA→DE), three days after the application was filed; classic pre-IPO restructuring.

• 2009-01-27 (effective) / recorded 2009-03-26 — Reel 022454/0522

  • Conveyance: Merger
  • Assignor: Transmeta Corporation
  • Assignee: Transmeta LLC (California)
  • Correspondent: not retrieved
  • Context: Internal reorg / entity conversion of the original assignee.

• 2009-01-28 (effective) / recorded 2009-09-22 — Reel 023268/0771

  • Conveyance: Assignment of assignors' interest
  • Assignor: Transmeta LLC
  • Assignee: Intellectual Venture Funding LLC (Nevada)
  • Correspondent: not retrieved
  • Context: Portfolio divestiture by a defunct operating company — the patent leaves the operating company one day after the entity conversion and ~8 months before the assignment is recorded. Recording lag of ~8 months is itself notable.

• 2015-08-27 (effective) / recorded 2015-09-29 — Reel 036711/0160

  • Conveyance: Merger
  • Assignor: Intellectual Venture Funding LLC
  • Assignee: Intellectual Ventures Holding 81 LLC (Nevada)
  • Correspondent: not retrieved
  • Context: Internal IV reorg (fund → holding entity).

• 2015-08-27 (effective) / recorded 2015-10-06 — Reel 036797/0356

  • Conveyance: Corrective assignment (correcting assignor's name in reel 036711/0160)
  • Assignor: Intellectual Ventures Funding LLC
  • Assignee: Intellectual Ventures Holding 81 LLC
  • Correspondent: not retrieved
  • Context: Correction only — evidence of template-driven bulk processing.

• 2019-12-16 (effective) / recorded 2020-01-17 — Reel 051550/0711

  • Conveyance: Assignment
  • Assignor: Intellectual Ventures Holding 81 LLC
  • Assignee: Intellectual Ventures Assets 156 LLC (Delaware)
  • Correspondent: not retrieved
  • Context: Transfer into a single-purpose IV asset shell — the carve-out vehicle for the Microchip assertion.

• 2020-01-10 (executed & effective) / recorded 2020-03-23 — Reel 052199/0838

  • Conveyance: Nunc pro tunc assignment
  • Assignor: Intellectual Ventures Assets 156 LLC, "a Delaware limited liability company, with an address at 251 Little Falls Drive, Wilmington, DE 19808" (signed by Jim Weisfield, "Authorized Person")
  • Assignee: Innovative Silicon Solutions, LLC — agreement recites "a Texas limited liability company" at 5900 Balcones Drive, STE 100, Austin, TX 78731; the USPTO record itself lists the receiving party at 2382 Rockfield Blvd., Suite 170, Lake Forest, California 92630
  • Correspondent: FAHIM AFTAB, 2382 Rockfield Blvd., Suite 170, Lake Forest, CA 92630 — phone 949-791-9366, email fahim@hongdungroup.com; attorney docket JG032320-2; signed 2020-03-23. ⚠️ FLAG — repeat correspondent: the identical correspondent (Fahim Aftab, same address, same 949-791-9366 number, same JG032320 docket prefix, same 2020-03-23 signature date) appears on the sibling IV carve-out assignment recorded the same day covering US 7,154,299 and US 6,748,577 (IV Assets entity → Innovative Silicon Solutions, LLC). One submitter, one docket family, multiple LLC counterparties.
  • Context: Transfer-to-asserter. The instrument conveys 10 patents in one batch: 7,260,731; 7,870,404; 9,436,264; 9,690,366; 7,302,619; 7,600,166; 7,334,173; 7,634,701; 7,810,002; 6,774,033 — i.e., the assertion package.

• 2020-01-10 (effective) / recorded 2020-03-28 — Reel 052253/0751

  • Conveyance: Corrective assignment (correcting the receiving party's address, previously recorded at reel 052199/0838)
  • Assignor: Intellectual Ventures Assets 156 LLC
  • Assignee: Innovative Silicon Solutions, LLC
  • Correspondent: not retrieved
  • Context: Correction only. Notably the correction is to the address — consistent with the Austin-TX recital in the agreement versus the Lake Forest-CA address in the record.

• 2020-11-10 (effective) / recorded 2021-01-14 — Reel 054993/0795

  • Conveyance: Change of name
  • Assignor: Innovative Silicon Solutions LLC
  • Assignee: HD Silicon Solutions LLC (Texas)
  • Correspondent: not retrieved
  • Context: Rebranding of the assertion vehicle — 20 days before the first infringement complaint.

Litigation context (from court docket and PTAB records, not the assignment record):

• 2020-11-30 — HD Silicon Solutions LLC v. Microchip Technology Inc., No. 6:20-cv-01092-ADA (W.D. Tex., Judge Albright), asserting 7 patents including 7,260,731 (claims 1, 4, 6, 8). Filed by Max L. Tribble, Jr. / Susman Godfrey (pro hac vice motion for Daniel Shih).
• 2021-10-25 — case transferred to N.D. Cal., becoming 3:21-cv-08295-SK (Judge Sallie Kim).
• 2021–2022 — Microchip filed a wave of IPRs against the HDSS portfolio: IPR2021-01420 and IPR2021-01421 (both on the '731 patent, both institution denied 2022-05-12, Paper 13), plus IPR2021-00752, -00872, -01042, -01089, -01265, -01567, -2022-00105.
• 2025-04-14 — 3:21-cv-08295 dismissed with prejudice (per Patsnap litigation data).
• 2025 — a further W.D. Tex. case, 1:25-cv-01320, is listed in the Google Patents litigation record.

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Timeline diagram

timeline
    title Ownership of US 7260731
    2000 : Filed by Transmeta Corporation
    2001 : Inventors assign rights to Transmeta
         : Transmeta reincorporates in Delaware
    2007 : Patent issued
    2009 : Transmeta Corp converts to Transmeta LLC
         : Transmeta LLC sells portfolio to IV Funding
    2015 : IV Funding merges into IV Holding 81 LLC
    2019 : IV Holding 81 carves out IV Assets 156 LLC
    2020 : IV Assets 156 sells to Innovative Silicon Solutions
         : Renamed HD Silicon Solutions LLC
         : Suit filed against Microchip in W D Tex
    2021 : Case transferred to N D Cal
    2025 : Suit dismissed with prejudice

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NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT (strong).
Reel 051550/0711 (effective 2019-12-16) moves the patent from IV Holding 81 into Intellectual Ventures Assets 156 LLC, recited in the recorded instrument as a Delaware LLC at 251 Little Falls Drive, Wilmington, DE 19808 — the Corporation Service Company registered-agent address, i.e. no operating presence. Reel 052199/0838 then conveys it out to Innovative Silicon Solutions, LLC, a Texas LLC at 5900 Balcones Drive, STE 100, Austin, TX 78731 (again a mass registered-agent address), with the USPTO record listing yet a third address in Lake Forest, CA. No products are associated with any of these entities; the assignor's signature block ("Jim Weisfield, Authorized Person") is the only human identified. The independent Stanford Technology Law Review study of IV's structure identified ~1,276 IV shell companies, of which ~1,201 were patent-holding vehicles — this patent's chain matches that template exactly.

2. Known asserter in the chain — PRESENT (strong).
Intellectual Ventures (via Intellectual Venture Funding LLC → IV Holding 81 LLC → IV Assets 156 LLC) is a named entity on the standard public NPE lists. The current owner, HD Silicon Solutions LLC, is a high-frequency plaintiff: it faced 9 PTAB proceedings (IPR2021-00752 through IPR2022-00105, all filed by Microchip) and filed at least two district-court actions (6:20-cv-01092 / 3:21-cv-08295; and 1:25-cv-01320). An entity that has never been identified as producing a product, yet has generated a nine-IPR defensive campaign, is by definition operating as an assertion vehicle.

3. Repeat correspondent across the chain — PRESENT, but scope-limited.
FAHIM AFTAB (fahim@hongdungroup.com, 949-791-9366, 2382 Rockfield Blvd. Suite 170, Lake Forest, CA 92630) is the named correspondent and submitter on reel 052199/0838, and the same individual, same contact block, same docket prefix JG032320, and same signature date (2020-03-23) recurs on the sibling IV Assets → Innovative Silicon Solutions assignment covering US 7,154,299 and US 6,748,577. That is recurrence across a related assignment family, not a one-off appearance. Caveat for precision: his correspondence address is the assignee's own address, not an outside law firm's, and I cannot confirm from the record whether he is a registered practitioner — so this is a "same submitter running a multi-assignment LLC carve-out" finding, not a "same outside counsel across the whole chain" finding. Gap: correspondents for reels 011536/0490, 011566/0681, 022454/0522, 023268/0771, 036711/0160, 036797/0356, 051550/0711, 052253/0751, and 054993/0795 were not retrievable from my sources — do not treat the absence as evidence of absence.

4. Cascading transfers — PRESENT (strong).
Three substantive transfers plus a change of name in under 12 months, all among affiliated or freshly minted LLCs:

• 2019-12-16 IV Holding 81 → IV Assets 156 LLC (reel 051550/0711)
• 2020-01-10 IV Assets 156 → Innovative Silicon Solutions, LLC (reel 052199/0838) — executed 25 days after the upstream transfer's effective date
• 2020-11-10 → HD Silicon Solutions LLC (change of name, reel 054993/0795)

Two corrective assignments (reels 036797/0356 and 052253/0751) sit alongside these, and the sibling IV Assets instrument even misidentifies the assignor as "Intellectual Ventures Assets 159 LLC" while the conveying-party table reads "156 LLC" — hallmark of bulk template conveyancing across dozens of near-identical shells.

5. Pre-litigation transfer — PRESENT (borderline; label with care).
On the strict 6-month test the acquisition (executed 2020-01-10, recorded 2020-03-23) predates the first complaint (2020-11-30) by ~10.7 months — outside the window. However, the operative event that put the plaintiff's name on the pleading — the change of name to HD Silicon Solutions LLC, effective 2020-11-10, recorded 2021-01-14 — occurred 20 days before the complaint. The chain was plainly arranged to enable assertion: a batch of 10 patents was carved into a Delaware shell, flipped to a Texas LLC, renamed, and then asserted against Microchip in Judge Albright's W.D. Tex. venue. I mark this present in substance, noting the dates do not satisfy the literal 6-month rule for the assignment itself.

6. Bankruptcy fire-sale — NOT PRESENT (as recorded).
No Chapter 7/11 filing appears in the chain. The 2009 exit (reel 023268/0771) is a distressed divestiture by a wound-down operating company, not a bankruptcy-court sale. I found no bankruptcy proceeding for Transmeta in my sources; I am not asserting one.

7. Privateering — NOT PRESENT (unclear on the classic definition).
Classic privateering requires a then-operating company to park patents with an NPE that asserts against its competitors. Here the original operating company (Transmeta) had already exited the processor business ~4 years before the 2009 transfer and ~11 years before the 2020 suit. The asserting party is IV and its assignee, acting on their own account — not visibly on a live operating company's behalf. No SEC filing or third-party report establishing a privateering arrangement was located.

8. Defensive aggregator — NOT PRESENT.
The chain terminates at an active plaintiff, not at RPX, AST, LOT, Unified Patents, or OIN. On the contrary: Unified Patents is the source of the tracked IPR2021-01421 data point on this patent — i.e., a defensive aggregator is on the opposing side, not in the chain. (Both IPR2021-01420 and -01421 were denied institution on 2022-05-12, so the patent was not neutralized by that route.)

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Verdict

NPE — high confidence.

Two or more strong signals are independently documented: (i) a known asserter in the chain — Intellectual Venture Funding LLC took the patent by assignment effective 2009-01-28 (reel 023268/0771) and pushed it down through IV Holding 81 LLC, then IV Assets 156 LLC (reel 051550/0711, effective 2019-12-16); (ii) a shell-entity transfer into a purpose-built vehicle — IV Assets 156 LLC (Delaware, at the CSC registered-agent address 251 Little Falls Drive) conveying a 10-patent batch to Innovative Silicon Solutions, LLC by nunc pro tunc assignment (reel 052199/0838, executed 2020-01-10), which was then renamed HD Silicon Solutions LLC (reel 054993/0795, effective 2020-11-10); and (iii) an actual assertion campaign — HD Silicon Solutions LLC v. Microchip Technology Inc., filed 2020-11-30 (6:20-cv-01092, later 3:21-cv-08295), asserting the '731 patent, which drew nine Microchip IPRs. The same correspondent (Fahim Aftab, docket JG032320) submitted the parallel IV carve-out assignments on the same day, and no entity in the chain has ever been associated with a product.

Verify at: https://assignmentcenter.uspto.gov/ (search patent number 7260731) — confirm reels 011536/0490, 011566/0681, 022454/0522, 023268/0771, 036711/0160, 036797/0356, 051550/0711, 052199/0838, 052253/0751, 054993/0795, and fill the nine missing correspondent-of-record fields, which are the one material gap in this reconstruction.

I'll research the prior art cited against US 7,260,731, prioritizing the most relevant references.

Prior-Art Analysis — U.S. Patent No. 7,260,731

Target patent: U.S. 7,260,731 B1 — "Saving power when in or transitioning to a static mode of a processor" (Transmeta; filed Oct. 23, 2000; granted Aug. 21, 2007). All §102 analysis below is under pre‑AIA 35 U.S.C. §102, since the application was filed in 2000. The critical date for §102(a)/(e) is Oct. 23, 2000; the §102(b) one‑year bar date is Oct. 23, 1999.

A threshold note on scope: this patent carries 109 cited references (patents + non‑patent literature). I cannot responsibly assert that every one of the 100+ citations is "the most relevant," nor did I retrieve the full text of each. Below I identify the references that are technically on point for the four independent method claims and five independent circuit claims, ranked by strength, and then note the remaining cited art by category. I also flag where a reference was actually used by a challenger at the PTAB, since that is probative evidence of what a skilled searcher considered the best art.

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A. Claim framework used for the §102 mapping

The four "pillars" of novelty are: (i) reducing core voltage below the operational level to a state‑retention level during stop‑clock; (ii) forcing the regulator below its specified minimum via a feedback divider referenced to a higher source; (iii) dynamically switching the regulator's regulation mode (continuous/PWM ↔ burst/skip/PFM) to save the transition energy; and (iv) charge conservation/recovery during the downward transition.

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B. Tier 1 — References most likely to raise §102 anticipation issues

1. WO 01/27728 A1 — Advanced Micro Devices, Inc.

"Minimizing power consumption during sleep modes by using minimum core voltage necessary to maintain system state"

• Cite: WO 01/27728 A1 (PCT/US00/11062); inventors Helms et al.
• Dates: Priority/filing Oct. 14, 1999; published Apr. 19, 2001 (after the '731 filing date, so its attack is under pre‑AIA §102(e) using the 1999‑10‑14 date).
• Disclosure: Explicitly teaches the core concept of claim 1: "Because the voltage required to maintain the integrated circuit context (e.g., processor state) intact may be significantly less than the voltage at which the processor can functionally operate at a particular frequency, significant power savings can be achieved by reducing processor voltage while the processor clocks are stopped." It discloses supplying a first voltage in operational mode, stopping clocks, then supplying a second, lower voltage sufficient to maintain context. The apparatus claims recite a control circuit that supplies first voltage control information during clocking and second (lower) voltage control information while clocks are stopped. It describes a south bridge multiplexer (MUX 201) selecting between VID jumper settings, a stop-clock VID register (202), and an operational VID register (203) under control of a stop-clock signal (208). Notably for claim 3, it discloses that the VID settings corresponding to Vcoremin "may be built into BIOS tables."
• Potential §102 mapping:
  • Claim 1 — the "determining … transitioning … reducing core voltage to a value sufficient to maintain state" elements are squarely met; the "value not sufficient to maintain processing activity" limitation is met by the express "voltage … may be significantly less than the voltage at which the processor can functionally operate." The regulator‑mode‑transition limitation is the weakest link and is normally supplied by the Maxim art (see ¶4–5 below).
  • Claim 3 — met by the VID multiplexer "furnishing an input to reduce an output voltage provided by a voltage regulator."
  • Claim 6 / Claim 8 — the "transfer the regulator from a mode in which power is dissipated … to a mode in which power is saved" element is the point of contention; Petitioner argued it through Maxim materials, not through Helms alone.
  • Claim 9 — binary VID signals.
  • Claim 10/11 — multiplexor with control terminal receiving a stop-clock indication (MUX 201, select line 204, stop-clock signal 208).
• Confidence: High that this is the single most material §102 reference; moderate as to whether it alone anticipates claim 1 (the regulator‑mode element is the gap).

2. U.S. Patent 6,748,545 B1 — Helms et al. (AMD)

Same family/subject matter as WO 01/27728 ("Helms"), the reference actually relied on as the primary reference in the IPRs (Exhibit 1010 in IPR2021‑01420).

• Dates: Filed Oct. 14, 1999 (US filing); granted 2004 (post‑dating the '731, so §102(e) applies).
• Disclosure: Petitioner asserted Helms teaches reducing the processor's core voltage in the stop‑clock/sleep state (ACPI C3) while retaining processor context, with a sleep voltage (e.g., 1.2 V) sufficient to retain the general‑purpose registers, and a VID multiplexer selecting between operational and sleep voltage settings.
• Potential §102 mapping: Claims 1, 3, 6, 8 (with the mode‑switch element supplied by the Maxim art per Petitioners' theory). Note: Helms/US 6,748,545 was NOT cited of record on the '731 face; only its PCT sibling (WO 01/27728) was. This matters — an examiner relying on the PCT publication would have missed any claim language unique to the US patent.

Important caveat on Tier 1 items 1–2: The PTAB denied institution on the merits in both IPR2021‑01420 and IPR2021‑01421 (Decision May 12, 2022; "Not Instituted – Merits"), and Patent Owner's Preliminary Response argued that Helms teaches away from a system in which the processor does not control its operating voltage, and that the proposed three‑way combinations (Helms + Maxim‑165X + MAX1711‑Kit; Helms + TI‑TPS5210 + Nilsson) would have been improper. A denial of institution is not a validity adjudication, but it is evidence that the PTAB did not view this combination as a likely winner against claims 8–11 and 14.

3. U.S. Patent 6,675,304 B1 — Intel Corporation

"System for transitioning a processor from a higher to a lower activity state by switching in and out of an impedance on the voltage regulator"

• Dates: Filed Nov. 29, 1999; granted Jan. 6, 2004 (pre‑AIA §102(e) date of Nov. 29, 1999 — before the '731 filing date).
• Disclosure: Control logic (host bridge / system bridge) drives a VRHI/LO# signal to the voltage regulator to raise or lower its output, and a GCPU_STP# / STPCLK# signal to place the processor in a low‑activity state (deep sleep or stop‑grant, i.e., ACPI C1/C2/C3), so that clock frequency and supply voltage may be varied. Explicitly addresses the timing of a STPCLK# assertion coincident with the regulator output changing from high to low, and the switching in and out of an impedance on the regulator.
• Potential §102 mapping:
  • Claim 1 — "determining that a processor is transitioning … to a mode in which a system clock … is disabled" (STPCLK#) + "reducing core voltage" (VRHI/LO#).
  • Claim 2 — monitoring a stop-clock signal (STPCLK#).
  • Claim 3 — furnishing an input to the regulator to reduce output.
  • Claim 8/9 — regulator with input terminal for selectable voltage + control signals.
  • The impedance‑switching teaching is also relevant to claim 13 (feedback network) and to the general concept of altering the regulator's output‑setting network.
• Confidence: High as a §102/§103 reference for the "detect stop‑clock → lower regulator voltage" method; weaker on the specific "state‑retention voltage below the operational minimum" and "regulator mode switch" elements.

4. U.S. Patent 6,208,127 B1 — Maxim Integrated Products (Doluca Tunc)

"Methods and apparatus to predictably change the output voltage of regulators"

• Dates: Filed Nov. 2, 1999 (app. 09/431,326); priority Nov. 1, 1999; granted Mar. 27, 2001 (§102(e) date Nov. 1999).
• Disclosure: Digitally programmable voltage regulator changing from a first set‑point to a second set‑point at a controlled rate; the MAX1638 digitally programmable controller is expressly identified. A counter/DAC generates a set‑point signal ramped at an oscillator‑controlled rate to limit inrush current during the transition.
• Potential §102 mapping: This is the reference the PTAB petitioner used to supply the "regulator changes set‑point in a controlled manner during the transition" teaching for claims 8–11 and 14. It is a regulator‑behavior reference, not a processor‑power reference — it does not by itself disclose detecting a processor clock‑stop transition. Best characterized as §103 fodder.

5. Non‑patent literature: Maxim MAX165X / MAX1711 datasheets ("High‑Speed Digitally Adjusted Step‑Down Controllers for Notebook CPUs")

• Dates: MAX1710/MAX1711 manual (undated in record; MAX165X datasheet, Maxim). The examiner's citation is dated to the MAXIM manual, pp. 11 and 21; the IPR refers to a July 2000 Maxim document (pp. 1–28).
• Disclosure: The MAX1711 is the specific regulator identified in the '731 specification as prior art: "Prior art regulators such as the Maxim 1711 provide a feedback terminal and describe how that terminal may be utilized with a resistor‑voltage‑divider network joined between the output terminal and ground to raise the output voltage level." The Maxim 165X datasheet discloses a controller that "automatically switch[es] between PWM operation at heavy loads and pulse‑frequency‑modulated (PFM) operation at light loads" — i.e., the two regulation modes recited in claims 1, 6, 8 and 14.
• Potential §102 mapping: This is the reference the petitioner used for the "means for changing the voltage regulator from a mode in which power is dissipated … to a mode in which power is saved" limitation of claim 8 (and the parallel method limitations of claims 1 and 6). Because the '731 itself characterizes the Maxim 1711 feedback technique as prior art, this datasheet is an admission‑backed §102(b) reference for the feedback/divider aspects of claims 4, 13 and 15.
• Confidence: High that the Maxim materials are the key §102(b)/§103 reference for the feedback‑divider and mode‑switching limitations. (The MAX1711 is also cited on the '731 face as a Non‑Patent Citation.)

6. U.S. Patent 6,704,880 B2 — Intel Corporation

"Reducing sleep mode subthreshold leakage in a battery powered device by making low supply voltage less than twice the threshold voltage of one device transistor"

• Dates: Earliest US priority Sept. 25, 1998; application 09/978,644 filed Oct. 18, 2001; granted Mar. 9, 2004. The 1998 priority date is well before the '731 filing date (§102(e)).
• Disclosure: Nearly a verbal match to the '731's problem statement. It teaches that clocks are off and a low supply voltage is provided to the processor, the voltage being "sufficiently low to prevent adverse consequences while dramatically reducing leakage current," with an architecture in which a voltage regulator 52 selectively provides one of two supply voltage levels (a higher conventional level and a lower "low power" level) and a Vcc detector in the clock control logic. The specification's leakage discussion (sub‑threshold leakage, exponential dependence on threshold voltage, doubling per 15 °C) tracks column 1–2 of the '731 almost line‑for‑line.
• Potential §102 mapping:
  • Claim 1 — cut clock + reduce supply to a level that maintains state but not processing; the "two reference voltages" regulator is directly on point.
  • Claim 12 — reducing the selectable voltage below the "lowest specified" operational level (the "less than twice the threshold voltage" teaching drives the voltage below ordinary operational minimums).
  • Claim 8 — regulator with selectable output + means for providing the two voltage levels.
• Confidence: High for the core "clock‑off + reduced supply" method; less strong on the regulator mode‑switch limitation.

7. U.S. Patent 5,919,262 A — Elonex I.P. Holdings, Ltd.

"Variable‑voltage CPU voltage regulator"

• Dates: Filed Oct. 7, 1994; granted July 6, 1999 — more than one year before the '731 filing date, so §102(b) applies squarely.
• Disclosure: Variable‑voltage CPU regulator enabling the processor core voltage to be changed (including reduced) in response to system control signals.
• Potential §102 mapping: §102(b) art against claims 8, 9, 12 (a CPU voltage regulator with selectable output voltage and control signaling). Weaker for the state‑retention and mode‑switching limitations.

8. U.S. Patent 5,852,737 A — National Semiconductor Corp.

"Method and apparatus for operating digital static CMOS components in a very low voltage mode during power‑down"

• Dates: Filed Apr. 24, 1995; granted Dec. 22, 1998 (§102(b)).
• Disclosure: Operating static CMOS logic in a very low voltage mode during power‑down while retaining logic state — the "voltage sufficient to maintain state but not to compute" concept in its purest prior form.
• Potential §102 mapping: §102(b) against the "value sufficient to maintain state … not sufficient to maintain processing activity" clause of claim 1 and the "voltage … sufficient to maintain state of the processor" clause of claims 8 and 12. It does not, however, address processor clock gating or regulator mode switching.

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C. Tier 2 — Strong secondary / §103 references

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D. Tier 3 — Cited art with low §102 relevance to the '731 claims

The following cited references are in adjacent fields and are unlikely to anticipate any claim individually; they appear in the record as general background:

• Thermal management: U.S. 5,422,806; 5,502,838; 5,712,xxx; 5,754,869; 5,832,284; 5,940,786; 5,940,785 / 6,047,248; 6,112,164; 6,510,400.
• Clock control / frequency switching: U.S. 2,xxx? no — specifically U.S. 5,572,719; 5,628,001; 5,914,996; 5,996,084; 6,111,806; 6,311,287; U.S. 5,204,863 (microprocessor monitoring); U.S. 5,201,059.
• GPS/portable standby: U.S. 5,592,173 (Trimble GPS low‑power standby); U.S. 5,682,093 (Nokia).
• Non‑processor memory/low‑power cell art: U.S. 4,987,xxx; JP 2752304; U.S. 5,463,585; U.S. 5,546,022.
• Communication/network power (Marvell) — post‑dating art: U.S. 7,454,634; U.S. 9,351,247.
• Family‑related (parent/child): U.S. 7,870,404; U.S. 9,436,264; U.S. 9,690,366 (all same‑family continuations/divisionals of the '731, sharing the Oct. 23, 2000 priority date — not prior art to the '731).
• Self‑citation: U.S. 5,832,205 (Transmeta).

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E. Non‑patent literature cited on the '731 face

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F. Art asserted by the challenger but not cited of record

Because these were chosen by a sophisticated petitioner (Microchip, with expert declarations), they are the strongest candidate §102/§103 references in practice:

Result: Both IPRs (IPR2021‑01420, IPR2021‑01421) were denied institution on the merits on May 12, 2022 (post‑institution fee refunds approved May 26, 2022). The Board's denial means it did not find the petitioner likely to prevail on the Helms‑based combinations against claims 8–11 and 14.

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G. Bottom line

Most relevant prior art for U.S. 7,260,731:

1. AMD's WO 01/27728 A1 / U.S. 6,748,545 (Helms) — the closest single reference; it expressly discloses reducing core voltage to a state‑retention level while clocks are stopped, via a multiplexer selecting between operational and stop‑clock VID values. This is the reference the challenger treated as the primary anticipation/obviousness reference, and it is the strongest §102(e) candidate for claims 1, 3, 6, 8, 9, 10, 11.
2. Intel's U.S. 6,675,304 B1 — closest art on the "detect STPCLK#/stop‑clock → change regulator output voltage" method (claims 1, 2, 3), and on impedance‑switching at the regulator (claim 13 concept).
3. Maxim's U.S. 6,208,127 B1 + MAX1711/MAX165X datasheets — the reference set for the feedback‑divider and dual‑mode (PWM/PFM) regulator limitations; because the '731 specification itself admits the Maxim 1711 feedback technique as prior art, these are §102(b)‑eligible for claims 4, 8, 13, 14, 15.
4. Intel's U.S. 6,704,880 B2 — with a Sept. 25, 1998 priority date, a close match to the core concept of claim 1 and the "below the lowest specified level" concept of claim 12 ("less than twice the threshold voltage").
5. National Semiconductor U.S. 5,852,737 A and Elonex U.S. 5,919,262 A — pure §102(b) art for the "very‑low‑voltage state retention" and "variable‑voltage CPU regulator" concepts (claims 1, 8, 9, 12).

Limitations I want to be explicit about:

• I did not retrieve or analyze the full text of all 109 citations; the Tier 2/Tier 3 groupings reflect my assessment of technical proximity, not a complete element‑by‑element chart.
• "Potentially anticipates" is used in the sense you requested (a §102 candidate) — I am not offering a legal conclusion of anticipation or invalidity for any claim.
• The two PTAB institution denials cut against treating the Helms + Maxim combination as a dispositive §102/§103 attack on the asserted claims (8–11, 14), even though Helms remains the most technically relevant single reference.
• Sources: Google Patents entry for US 7,260,731 (authoritative full text supplied in the prompt); PTAB filings for IPR2021‑01420/‑01421 (docketalarm.com, ipverse.greyb.com); Google Patents entries for WO 01/27728 A1, US 6,675,304 B1, US 6,208,127 B1, US 6,704,880 B2.

I'll ground the obviousness analysis by verifying the key references before charting combinations.

Now let me verify the remaining Tier-1 references and the regulator datasheets relied on in the IPRs.

Obviousness Analysis under 35 U.S.C. § 103 — U.S. Patent No. 7,260,731 B1

Target: U.S. 7,260,731 B1, "Saving power when in or transitioning to a static mode of a processor" (Transmeta; App. 09/694,433; filed Oct. 23, 2000; granted Aug. 21, 2007; 18 claims; expired 2020-11-22).

Governing law: Because the application was filed before March 16, 2013, pre‑AIA 35 U.S.C. § 103(a) applies, as construed in Graham v. John Deere, 383 U.S. 1 (1966) and KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007). The critical date is Oct. 23, 2000; the § 102(b) bar date is Oct. 23, 1999. Pre‑AIA § 103(a) does not require a "teaching, suggestion, or motivation" in the statute's text, but the Federal Circuit's pre‑KSR case law (and KSR's articulation of the same idea) supplies the operative framework I use below.

Why this analysis matters procedurally: Institution was denied on the merits in both Microchip Technology Inc. v. HD Silicon Solutions LLC, IPR2021-01420 and IPR2021-01421 (Paper 13, May 12, 2022). A § 314(a) denial is not a validity adjudication, creates no § 315(e)(2) estoppel, and has no preclusive effect — so nothing below is foreclosed by that outcome, and conversely nothing below should be read as contradicting it.

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1. Correction to the prior-art record before I begin

Two art-integrity issues that materially affect the § 103 dates, flagged per the cross-reference rule:

(a) "Helms" is two different documents, and the earlier Prior Art section conflated them. The petitioner's Exhibit 1010 in the '731 IPRs bears the text of U.S. 6,748,545 B1, "System and method for selecting between a voltage specified by a processor and an alternate voltage to be supplied to the processor" — App. 09/621,931, inventors Helms, Connolly, Lee, original assignee AMD, priority 2000‑07‑23, granted 2004‑06‑07. Its FIG. 1 text ("A multiplexer (VID MUX) selects between these two voltage settings in response to a mode control signal (CPUSTOP#) which may be provided from the south bridge… the OVID and SVID are hardwired") is quoted verbatim in the petition. (Exhibit 1010 PDF; US 6,748,545.)

WO 01/27728 A1 is a separate AMD/PCT document — "Minimizing power consumption during sleep modes by using minimum core voltage necessary to maintain system state," PCT/US00/11062. Its disclosure of multiplexer 201, VID stop-clock register 202, VID operational register 203, select line 204, stop-clock signal 208, and Vcoremin is quoted at petition download 1547797 — a different proceeding's exhibit set, not the '731 petitions. These are not the same document, and they carry different effective prior-art dates.

(b) The earlier Prior Art section's filing date for U.S. 6,748,545 — "Oct. 14, 1999" — conflicts with retrieved records (App. 09/621,931; priority 2000‑07‑23; grant 2004‑06‑07). App. 09/621,931 is a Series‑09/6xx,xxx filing consistent with a mid‑2000 date. Either date precedes the '731's Oct. 23, 2000 filing, so Helms qualifies as pre‑AIA § 102(e) art either way, but the margin matters if Transmeta was ever entitled to an earlier invention date, and it should be verified against the printed patent front page rather than a third-party aggregator. I am not auto-correcting; I am flagging.

(c) § 102(e) treatment of the PCT sibling. WO 01/27728 was published Apr. 19, 2001 — after the '731's filing date — so it is not § 102(a)/(b) art. Whether an international application gets § 102(e) effect as of its international filing date turns on the AIPA's § 102(e) amendment, which applies to applications filed on or after Nov. 29, 2000. The '731 was filed Oct. 23, 2000. On the pre-amendment text, WO 01/27728 does not carry a § 102(e) date against this patent. The § 102(e) burden therefore must be carried by the U.S. filings — U.S. 6,748,545 (2000) and, for the pre‑1999 AMD disclosure, whatever U.S. counterpart supports the WO's Oct. 14, 1999 priority. Practitioners should not assume the PCT publication is available art here.

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2. Level of ordinary skill in the art (POSITA)

Inferred from the field and the '731's own framing; the Board's Alpert declaration in IPR2021‑01420 is the best available proxy and I did not retrieve its full POSITA paragraph, so treat this as my construction:

A POSITA at October 2000 would hold a B.S. in Electrical Engineering or Computer Engineering (or equivalent) and 3–5 years of experience in microprocessor and mobile-computer power management, including familiarity with ACPI processor power states (C0–C3), x86 STPCLK#/CPUSTOP# clock-stop signalling, VID-programmable switching regulators, and sub-threshold leakage behavior.

This is a predictable, well-developed, single-field art — an important KSR consideration, because the more predictable the field and the more finite the set of solutions, the more the combination falls within § 103.

Identified problem at the critical date (undisputed on this record): sub-threshold leakage ("static power") burned ≈0.5 W in a typical x86 processor held in deep sleep at full core voltage, for ~90% of operating time. Both the '731's Background and Intel's U.S. 6,704,880 recite this same physics (exponential Vt dependence, doubling per ~15 °C, worsening with thinner gate oxides). A shared, expressly recognized problem across the references is the strongest possible motivation-to-combine evidence.

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3. Claim-construction predicates that shape the § 103 analysis

(a) Claims 8–15 are means-plus-function claims. They are drafted in pre‑AIA § 112 ¶ 6 form ("means for providing signals…," "means for changing the voltage regulator…," "means for reducing the selectable voltage…," "means for enabling the circuitry for conserving charge…"). Under pre‑AIA § 112 ¶ 6, these are limited to the corresponding structure disclosed in the '731 specification and equivalents thereof. The corresponding structures are:

This matters enormously: a § 103 combination must supply structure disclosed as performing the recited function, not merely a label. It also means the "means for changing the voltage regulator from a mode in which power is dissipated… to a mode in which power is saved…" limitation is narrow and specific — it is not met by any and every change in regulator behavior.

(b) "sufficient to maintain state … not sufficient to maintain processing activity" (claim 1). A relative, functional limitation. The '731's own tests put retention "significantly below one-half volt."

(c) "first regulation mode" / "second regulation mode" (claims 1, 6, 8, 14). The specification defines these as continuous/"low noise"/PWM mode (which "transfer[s] charge from the supply capacitors back into the power source," i.e., saves) versus burst/skip/"high efficiency" mode (which "drain[s] the charge on the supply capacitors … or allow[s] the load to drain the charge," i.e., dissipates). The limitation is not satisfied by an arbitrary operational change — it requires the power-dissipation/savings-from-the-transition character.

(d) The four pillars of novelty (from the prior-art section) map to claim groups as follows, and each combination below attacks one or more:

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4. Combination-by-combination analysis

Combination A — Helms (U.S. 6,748,545) + Maxim MAX165X / MAX1710 / MAX1711 datasheets

Targets claims 1, 2, 3, 6, 7, 8, 9, 10, 11

Motivation to combine — unusually strong, and it is express:

1. Helms itself names the MAX1711 as the regulator. "One example of a programmable voltage converter is a MAXIM MAX1711 High-Speed, Digitally Adjusted Step-Down Controller or its equivalent." This is a KSR express suggestion — the strongest form of motivation evidence.
2. Helms recites the identical latency constraint the '731 addresses: "The MAX1711 can transition between selected voltages in less than 100 µs." The '731's own 50 µs transition budget is the raison d'être of its mode-switching embodiment. The references are aimed at the same bottleneck.
3. Same field, same problem, same architecture (south-bridge-controlled notebook x86 CPU core voltage): KSR's "combination of familiar elements according to known methods … yields no more than predictable results."
4. The Maxim datasheets are not merely art — they are the '731's own admitted prior art. The specification states: "Prior art regulators such as the Maxim 1711 provide a feedback terminal and describe how that terminal may be utilized with a resistor‑voltage‑divider network…" and lists the MAX1710/MAX1711 manual as a cited non-patent reference. Applicant admissions are § 102(b)-quality evidence and, for § 103, are close to dispositive on the regulator-behavior elements.

Where this combination is weak (and why the Board likely denied institution):

• Maxim's PWM↔PFM handoff is automatic and load-based, not commanded "responsive to said determining" that the processor is entering a clock-disabled mode. The claim requires the detection to trigger the mode transition. Close, but a genuine gap.
• The '731's claimed benefit is that continuous mode returns charge to the battery, so the transition is net power-saving. Maxim's datasheet describes efficiency improvement, not charge recovery per se. The petition papered this with "Maxim-165X‑Datasheet and MAX1711‑Kit describe the function 'changing the voltage regulator from [one] mode to another'" — a function-only mapping that is vulnerable under § 112 ¶ 6's requirement of corresponding structure.

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Combination B — Helms + Doluca (U.S. 6,208,127, Maxim) [+ optionally Rushford]

Targets claims 1, 5, 6, 7, 8, 10, 14

Doluca (U.S. 6,208,127 B1, "Methods and apparatus to predictably change the output voltage of regulators," App. 09/431,326, priority Nov. 1, 1999, granted Mar. 27, 2001, assignee Maxim Integrated Products) discloses a digitally programmable regulator changing from a first set-point to a second set-point at a controlled rate — counter 100 / comparator 110 / oscillator 120 / DAC 130 — expressly to limit inrush current from a high-impedance battery source during the transition. (US 6,208,127.) Its FIG. 3 places the DAC in the feedback attenuation/amplification section — op amp 350 receives the feedback signal and the program signal to set the output.

Motivation: (i) Common assignee and common commercial product line (both Maxim; the '731's admitted-art regulator is a Maxim part); (ii) the same problem — the '731 states the transition must complete within ~50 µs or the voltage merely "may be lowered … to 0.6–0.7 volts," which is precisely the inrush/latency tradeoff Doluca addresses; (iii) KSR's "known technique to improve a similar device in the same way." A POSITA improving Helms' sleep-mode regulator would have looked to Maxim's own published method for changing a programmable regulator's set-point cleanly — and the MAX1711 that Helms names is in Doluca's own product family.

Strength: this is the best § 103 theory for the mode-switch pillar because it supplies structurally specific regulator-transition circuitry with a stated power rationale, rather than a bare functional label. Weakness: the reference addresses current inrush, not capacitor-charge recovery to the battery; a patent owner will argue the net energy accounting differs.

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Combination C — Helms + Rushford (U.S. 6,675,304, Intel)

Targets claims 1, 2, 3, 5, 8, 13

Rushford (U.S. 6,675,304 B1, "System for transitioning a processor from a higher to a lower activity state by switching in and out of an impedance on the voltage regulator," App. 09/450,321, filed Nov. 29, 1999, granted Jan. 6, 2004, Intel) is, on these claims, the most on-point § 102(e) reference in the record. It discloses:

• Control logic 100 that "controls a processor transition, detects a state change that calls for a reduction in the voltage regulator output voltage," asserts VRHI/LO# to the regulator and asserts GCPU_STP# to place the processor in "a low activity state (e.g., deep sleep or stop grant)" — expressly the ACPI C1/C2/C3 states;
• "In the deep sleep state … the external clock to the processor is disabled so that no activities are performed by the processor except maintenance of the stored data" — this is the state-retention clause, in substance;
• The key teaching for claim 1: "a separate signal to the voltage regulator is asserted, indicating that the change is a reduction in voltage and providing an additional load on the voltage regulator. When the voltage regulator settles, the control logic negates the separate signal, removing the extra load." That is a change in the regulator's downward-transition behavior, commanded by the detected processor state change — mapping directly onto "responsive to said determining… transitioning from a first regulation mode to a second regulation mode… power dissipated during a voltage transition… power saved."
• It also diagnoses and solves the '731's own problem statement: "When transitioning from a higher to a lower voltage, the bulk capacitors discharge to allow the supply to settle to the required voltage. Since the load is low, this transition can take a relatively long time, increasing the transition latency." (US 6,675,304; PDF.)

Motivation: both references are Intel/AMD-generation chipset power-management disclosures addressing the same ACPI C3 transition and the same low-load capacitor-discharge latency. Combining them is KSR's paradigm case: two references addressing the same problem in the same art, using a known technique (altering the regulator's transition dynamics) to improve a similar device.

Strength: strongest single reference for the "responsive-to-detection mode change" limitation. Weakness: Rushford's added impedance speeds settling — it does not obviously return charge to the battery — so it may be read as dissipating rather than saving. That cuts both ways: it is worst-case art if the claim is read narrowly, and best-case art if "power saved" is read as net system power.

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Combination D — Helms + Dai (U.S. 6,704,880, Intel)

Targets claims 1, 8, 10, 12

Dai (U.S. 6,704,880 B2, "Reducing sleep mode subthreshold leakage in a battery powered device by making low supply voltage less than twice the threshold voltage of one device transistor," Intel; earliest priority Sept. 25, 1998; application 09/978,644; granted Mar. 9, 2004; published as U.S. 2002/0026597 A1) is the closest art on the state-retention-below-operating-voltage concept. It discloses:

• "disabling the clock signal and reducing the leakage power consumption of the device";
• "a voltage regulator 52 selectively provides one of two supply voltage levels to the clock unit 30 and the rest of the processor 12" — the higher reference and "the lower reference voltage may be the low power supply voltage to reduce leakage power consumption";
• an exemplary ≈550 mV low supply voltage — "A low supply voltage is used that is sufficient to maintain all the internal registers of the device so that they retain their contents while avoiding floating nodes"; "the low supply voltage is less than twice a transistor threshold voltage";
• the same leakage physics narrative the '731 uses (exponential Vt dependence, doubling per 15 °C, worsening with scaling), and even a cache-flush step to address soft-error-rate increases at low voltage.
  (US 6,704,880; US 2002/0026597 A1 PDF.)

Claim 12 ("below the lowest level the voltage regulator is specified to output") is the target here: Dai's sub-2·Vt regime (~550 mV) is far below any voltage at which an Intel-architecture processor is specified to compute, while the only constraint recited is retention of internal registers. Helms supplies the programmable-regulator structure; Dai supplies the how-low teaching. Together they meet claim 12's "means for reducing the selectable voltage below a lowest level the voltage regulator is specified to output."

Motivation: (i) Identical problem statement, identical physics — two references independently reciting the same sub-threshold-leakage mechanism; (ii) Dai expressly identifies the same architectural lever (a two-level regulator under clock control) that Helms embodies; (iii) KSR's "predictable variation" — setting the sleep set-point below the operational minimum is a predictable, results-driven choice once the retention criterion is understood, and Dai quantifies it. Its 1998 priority removes any § 102(e) timing doubt.

Weakness: Dai is directed at designing the processor to operate at ultra-low voltage; it says less about the regulator's transition behavior. It therefore pairs with Helms/Rushford rather than standing alone against claim 1.

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Combination E — Helms + National Semiconductor (U.S. 5,852,737)

Targets claims 1, 3, 8, 12

U.S. 5,852,737 ("Method and apparatus for operating digital static CMOS components in a very low voltage mode during power-down," filed Apr. 24, 1995, granted Dec. 22, 1998 → clean § 102(b) art, more than a year before the '731 filing) is the purest § 102(b) disclosure of the retention-voltage concept. It claims:

"selectively supplying a reference voltage at two voltage levels including an operating voltage level and a low reference voltage level … detecting an idle state … and controlling the selectively supplying step to supply the low reference voltage in response to detection of the idle state. The low reference voltage level is substantially lower than the operating voltage level but is sufficient in voltage amplitude to maintain register and internal state levels of the static CMOS component."

And in dependents: "deactivating a timing signal to the static CMOS component in response to detecting an idle state"; and "controlling the selectively supplying step to gradually reduce the voltage from the operating voltage level to the low voltage level subsequent to the timing signal deactivating step" (its claim 3 — note how closely this tracks the '731's "after the clocks are stopped (or simultaneously therewith)" sequencing). Its Background expressly surveys and criticizes the three prior art options — clock deactivation alone (still leaks), power termination (loses state), and reduction only to a "minimum operating voltage" (minimal savings, and TTL-floor-limited to ~3 V) — thereby identifying precisely the gap the '731 fills.
(US 5,852,737; PDF; claims text.)

Motivation: § 102(b) art that (a) recites the retention criterion verbatim in substance, (b) recites the clock-deactivation-plus-gradual-voltage-reduction sequence, and (c) expressly frames the unmet need for voltage reduction below the minimum operating level. KSR: "the problem the patent addresses" being identified in the prior art is itself a strong suggestion. Any POSITA applying 5,852,737's teaching to a Helms-architecture programmable CPU regulator arrives at claims 1/3/8/12 directly.

Weakness: 5,852,737 uses a programmable power supply and a system controller, not a switching regulator with VID-style level inputs, and it does not touch regulator transition modes. It is a claim-1/12/8 reference, not a claim-1-full reference.

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Combination F — Helms (or Rushford) + Maxim MAX1711 datasheet + Doluca

Targets claims 4, 5, 10, 13, 15, 16, 17, 18 — the feedback-divider family

Claims 4 and 13 are the FIG. 4 embodiment: a resistor divider joined between the output terminal and a voltage source higher than the selectable voltage, feeding the regulator's feedback terminal, to force the output down (rather than up).

Mapping:

• Claim 4 — (a) "furnishing an input to reduce an output voltage provided by a voltage regulator": Helms' MVID / Rushford's VRHI/LO#; (b) "providing a feedback signal to the voltage regulator to reduce its output voltage below a specified output voltage": the MAX1711 feedback terminal driven by the divider network — and the '731 concedes that the Maxim 1711's feedback-terminal-plus-divider arrangement is prior art ("how that terminal may be utilized with a resistor-voltage-divider network joined between the output terminal and ground to raise the output voltage level"). The only delta is the direction of the bias.
• Claim 13 — voltage divider network between the output terminal and a higher source, with the regulator feedback circuit receiving a value from the divider.
• Claims 15, 16, 18 / 17 — same structure recited as apparatus; claim 15 adds "a voltage source furnishing a value higher than the selectable voltage."
• Claim 5 — final voltage depends on the pre-transition voltage (see Combination B).

Motivation: KSR's "predictable use of prior art elements according to their established functions." The '731 does not disclose a new circuit topology for the feedback network; it re-references an admitted-prior-art divider from ground to a rail above Vout. A POSITA who understood the Maxim 1711 feedback equation (Vout set by the FB pin's divider ratio) would recognize as a matter of routine circuit design that the same node can be biased from a supply above Vout to lower the regulated output. Doluca's FIG. 3 independently confirms that placing the programming element in the feedback attenuation/amplification section to set the output is a known, published technique from the same manufacturer. KSR — "if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious."

This is the combination to watch — and the weakest link in the whole § 103 case. I did not find, in the 109 cited references, in the four asserted IPR exhibit sets, or in the retrieved secondary literature, a reference that expressly teaches tying the regulator feedback divider to a source above the output rail in order to drive the output below the regulator's nominal/native set-point. The 6,748,545 / 6,208,127 / 6,675,304 trio all set a target through a control input; none over-drives the feedback node below the part's native minimum. Claim 12's "below the lowest level the voltage regulator is specified to output" is therefore most naturally met by Dai's voltage-selection teaching (Combination D) or by 5,852,737's sub-operational-voltage teaching (Combination E) rather than by the divider-direction argument. Expect a patent owner to press exactly here — and note that this is a § 103 argument that would benefit from expert testimony on the feedback loop, not from a bare reference citation.

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Combination G — Helms + Maxim datasheets (admitted art) + Rushford

Targets claims 6, 7, 8, 10, 11, 14 — and, in particular, the "conserve charge" limitation of claim 14

Claim 14 adds "means for enabling the circuitry for conserving charge stored by the voltage regulator when the selectable voltage decreases." The '731's corresponding structures are the charge pump 53 and/or the continuous-mode battery return.

Mapping and motivation:

• Helms supplies the dual-voltage programmable regulator and the stop-clock-controlled selection.
• Rushford supplies the detection → regulator-transition-behavior change linkage and the capacitor-discharge analysis.
• The Maxim datasheets supply the charge-conservation structure, because the '731's own cited NPL is titled "High-speed step-down controller with synchronous rectification for CPU power." Synchronous rectification — replacing the catch diode with a controlled synchronous switch — is the structural mechanism by which a buck regulator conducts current in both directions and returns inductor/output-capacitor charge to the source during a downward output transition. A POSITA would recognize that a synchronous-rectification controller inherently "conserv[es] charge stored by the voltage regulator when the selectable voltage decreases." That is inherent capability of the admitted prior-art part, which is the strongest form of § 103 evidence short of anticipation.
• The '731 specification itself admits that "It is common for regulators operating in the continuous mode to transfer charge from the supply capacitors back into the power source when the output voltage is changed from a higher voltage to a lower voltage" — and that "It is common for regulators operating in the high efficiency mode to drain the charge on the supply capacitors … or to allow the load to drain the charge." Both halves of claim 14's recited function are applicant-admitted prior art, leaving only the enabling ("means for enabling") selection logic — which is exactly what Helms' CPUSTOP#-driven VID MUX and Rushford's control logic 100 provide.

Weakness: I found no cited reference in the record that expressly discloses a bidirectional charge pump returning CPU-regulator output-capacitor charge to the battery. The charge-pump structure (item 53) is the '731's own contribution in FIG. 5. Claim 14's attack therefore runs through the admitted-art route (synchronous rectification + continuous-mode battery return) rather than through a single anticipating reference — defensible under § 103, but it is a rationale-based attack, not a documentary one.

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Combination H — Helms + Maxim datasheets (or Rushford) + AMD Athlon datasheets / ACPI

Targets claims 1, 2 (and the "state retention" premise of every independent claim)

Not a separate invalidity theory so much as the evidentiary backbone for "state sufficient to maintain state … not sufficient to maintain processing activity." The petition's Alpert declaration built this on the AMD Athlon Processor Module datasheet and the ACPI specification — "sleep state C3 in which the processor clock is disabled, as indicated by 'STPCLK# asserted,'" where "the processor complex context is maintained." (petition download 1548174.) A POSITA in the x86 space at October 2000 knew the retention boundary empirically from the platform datasheets; the '731's contribution was not discovering that state survives below the operational minimum, but exploiting it.

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5. Summary claim chart

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6. The KSR motivation synthesis (what a petitioner must actually argue)

Reduced to the rationales a tribunal will accept:

1. Express suggestion in the primary reference — Helms names the MAX1711 and its <100 µs transition; the '731 claims a ~50 µs transition budget. KSR treats this as near-conclusive. (Combination A)
2. Same field, same problem, same architecture — south-bridge-controlled notebook x86 with ACPI C3. Helms, Rushford, Dai, NS '737, Elonex, Maxim, Doluca, and the '731 all address sub-threshold leakage during clock-stopped operation; several recite the same physics and the same unmet need. (All combinations)
3. Known technique to improve a similar device — rate-controlled programmable set-point change (Doluca), impedance switching on the regulator output (Rushford), synchronous-rectification charge return (Maxim) are all known regulator techniques applied to the same class of device. (B, C, G)
4. Predictable variation / design choice — setting the sleep set-point below the part's native minimum (Dai; NS '737) and re-referencing the feedback divider (Maxim admitted art) are results-driven parameter choices with predictable outcomes. (D, E, F)
5. Obvious to try, finite predictable solutions — at October 2000 the identified approaches to the deep-sleep leakage problem were (a) stop clocks, (b) gate power, (c) drop the retention voltage, (d) recover the transition charge. That is a closed set with predictable results. KSR.
6. Economic/market pressure — the '731's own framing ("battery life of portable computers decreases"; the processor is in deep sleep ~90% of the time) documents a design incentive that KSR treats as a motivation.

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7. Where a § 103 attack will meet resistance

I want to be candid about the limits of the record as it stands:

1. No FWD, no merits adjudication. Both IPRs died at the § 314(a) threshold. The Board's reasoning — that Microchip showed only a "theoretical" possibility of combining a 1990 data book with a 2000 conference presentation and "ultimately failed to show why a skilled artisan would have in fact been motivated to do so" — is a warning about motivation-to-combine showings, not a finding of non-obviousness. Any new petition must do the motivation work that Microchip did not. (IPR2021-01420 Paper 13.)
2. The "power saved during the transition" clause is the crux of claims 1, 6, 8, 14. None of the cited references is aimed at net transition-energy accounting for a CPU regulator. Rushford explicitly adds a load (dissipating); Doluca limits inrush; Maxim's PFM/PFM handoff is load-driven. The combination is arguable, but a skilled patent owner will argue that the references teach away from the claim by adding dissipation or by being indifferent to it.
3. The above-rail feedback divider (claims 4, 13, 15) has the thinnest documentary support in the cited record. See § 4 / Combination F. This is where a § 103 case most needs expert testimony and, if available, art outside the 109 cited references — e.g., load-line/"voltage positioning" or remote-sense literature.
4. Means-plus-function limits cut against the petitioner on claims 8–15. A functional-mapping petition (as Microchip's appears to have been, at least for element 8[c.1]) invites the § 112 ¶ 6 corresponding-structure counter.
5. Teach-away argument already on the record. HDSS argued in its Preliminary Response that Helms teaches away from an architecture in which the processor does not dictate its own operating voltage. Claim 8's "means for providing signals at the input terminal" is not limited to the processor as the source, so the argument is weak — but it has been made once already and will be made again.
6. The patent is expired (2020‑11‑22). No injunction is available; the practical exposure is § 286 past damages. Note the Google Patents legal-status field carries its own disclaimer that the status is "an assumption and not a legal conclusion" — verify against the front page and Patent Center before relying on it.

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8. Bottom line

Yes — meaningful § 103 combinations exist, and the strongest ones do not require the art Microchip already lost with.

The most persuasive theory is Helms (U.S. 6,748,545) as the primary reference, because it supplies the detection, the retention voltage, and the multiplexed VID selection, paired with Rushford (U.S. 6,675,304) as the secondary reference, because it uniquely supplies the responsive-to-detection change in the regulator's downward-transition behavior — the single element that most distinguishes claims 1, 6 and 8 — and because it independently articulates the very problem (low-load capacitor-discharge latency) the '731 solves. Doluca (U.S. 6,208,127) then supplies structural, manufacturer-specific regulator-transition circuitry and the answer to claim 5. Dai (U.S. 6,704,880) and NS '737 (U.S. 5,852,737) supply the "below the specified minimum" and "sufficient to maintain state" elements of claims 1, 8 and 12 from clean § 102(b)/(e) positions. Claim 14 is best attacked through the applicant's own admissions about continuous-mode battery return plus the "synchronous rectification" character of the admitted-art Maxim controller.

The combinations that must be tested rather than assumed are those turning on (i) the net-energy character of the downward transition (claims 1, 6, 8, 14) and (ii) the above-rail feedback divider (claims 4, 5, 13, 15) — the second of which I could not source to any reference in the cited or asserted record. Everything else in the 18-claim set has a documented, structurally-mapped, motivation-supported § 103 path.

Verification still owed: (a) the printed front-page filing date of U.S. 6,748,545, which conflicts between sources as noted in § 1(b); (b) whether any U.S. counterpart (not the WO publication) supports the Oct. 14, 1999 AMD priority against the § 102(e) timing constraint discussed in § 1(c); (c) the Alpert declaration's POSITA definition, which I inferred rather than retrieved.