US 7532062

I'll verify this patent number against live sources before summarizing.

Let me check for any litigation or assignment records tied specifically to this number.

Let me verify the granted claim set (the full text provided truncates before the claims).

Verification note (read first)

I could not query USPTO PatentCenter, PACER, or the CAFC docket system directly — my tooling is a general web-search tool, not a docket database. What I can report is what public sources (Google Patents, Justia, FreePatentsOnline, USPTO.report) and open web results show for the literal number 7532062. I found no CAFC 2026 docket entry, no IPR/PGR, and no district-court case naming this patent. One apparent "litigation" hit (IPR2017‑01632, Toshiba v. Macronix) concerned a different patent, U.S. 8,035,417 — not 7,532,062 — so it is not responsive and I do not treat it as an activity record for this number. Treat the "no litigation found" statement as a negative search result, not a certified clearance.

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US 7,532,062 B2 — Bibliographic summary

Family members found: US 7,768,341 B2 (app. 12/424,290, filed 2009‑04‑15, priority 2005‑11‑08) and US 2009/0201076 A1, both bearing the same title/assignee family.

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Abstract (as published)

A semiconductor charge pump includes a plurality of P‑channel MOS transistors connected in series, a plurality of first pumping capacitors with one electrode connected to a connection point of each P‑channel MOS transistor, and a clock signal generating circuit generating first and second clock signals 180° out of phase, supplied alternately to the other electrodes of the first pumping capacitors. It further includes a plurality of dynamic level converter circuits each including a resistor element and a second pumping capacitor, connected to each gate of the P‑channel MOS transistors.

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Plain-language overview

Problem addressed. The patent targets an inexpensive, on‑chip high‑voltage source for an irreversible nonvolatile memory that programs by rupturing a MOS gate oxide (an "anti‑fuse"). Prior options were unattractive: a dual‑well diode rectifier is expensive; a parasitic diode rectifier leaks into the P‑substrate via a parasitic PNP; and diode‑connected N‑channel MOS rectifiers suffer the back‑gate effect, so drive current collapses as the pumped output rises. The inventors instead drive P‑channel MOS rectifiers whose gates are held at intermediate, dynamically self‑generated levels, so no high‑voltage transistor or special process is needed (source‑drain and source‑gate voltages stay within VDD).

Independent claim(s). Based on the patent's own "BRIEF SUMMARY" (aspects 1–4) and on claim text retrieved from the family publication, the independent claims cover:

1. Claim 1 (first aspect) — P‑channel version (verbatim basis): A charge pump with (a) plural P‑channel MOS transistors acting as current rectifier elements, gates present, series‑connected between an external supply (VDD) and a boosted output (VPP); (b) plural first pumping capacitors, one electrode tapped to each series node; (c) a clock generator producing two 180°‑offset clocks fed alternately to the other electrodes of the first pumping capacitors; (d) plural resistors connected between the MOS node and the corresponding gate; and (e) plural second ("auxiliary") pumping capacitors whose one electrode connects to the far end of each resistor and whose other electrode receives the alternating clocks — thereby generating the gate control signals. Plainly: a Dickson pump using P‑channel rectifiers whose gate bias is set on the fly by an RC/pumping network rather than by a fixed supply.

2. Second aspect — N‑channel version: Same architecture, with N‑channel MOS transistors as the rectifiers, the same resistor + second‑capacitor network generating the gate control signals.

3. Third aspect — two‑system P‑channel version: Two such P‑channel pumps, where the control signals generated by the second capacitors in one system control the gates of the P‑channel transistors in the other system (cross‑coupled gate drive).

4. Fourth aspect — two‑system N‑channel version: Same cross‑coupled two‑system arrangement with N‑channel rectifiers.

Dependent claims I could retrieve (from the same family text — see uncertainty note):

• Claim 2: the resistor elements are themselves MOS transistors (this is what the later figures 10–12 elaborate, including three‑transistor resistor units and single P‑channel resistor transistors).
• Claim 3: the first/second clocks are rectangular waves swinging between VSS (low) and VDD (high).
• Claim 4: the P‑channel transistors have back gates driven by bias circuits (the FIG. 7 back‑gate bias scheme that prevents parasitic bipolar/latch‑up and avoids over‑biasing the N‑well).

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Uncertainty and cautions

• Granted claim set not fully confirmed. The authoritative text supplied to me truncates before the claims. The claim‑1 wording above comes from a family publication (US 2007/0103224, the parent application) whose claim 1 is textually the same as the patent's "first aspect." I have not independently confirmed that the issued 7,532,062 claim set contains all four aspects as independent claims, nor the exact dependent‑claim numbering. The FIG. 1–12 embodiments and the four aspects are well documented; the mapping of aspects to issued claim numbers should be verified against the grant itself.
• Assignee string differs between sources ("Toshiba Corp." vs. "Kabusiki Kaisha Toshiba"); I have not normalized it.
• No docket/IPR/Court activity was found for this number, but as stated above this reflects only the sources I could reach.
• Numbers such as 7,768,341, 12/424,290, 2007/0103224, 2008/0246535, 2009/0201076, 2005‑323601, 2006‑266050, and 11/556,810 are reproduced as they appear in the sources; none were altered.

I'll research litigation involving US patent 7532062. Let me search multiple sources.

The initial searches returned unrelated patents. Let me search more targeted litigation databases.

Let me search a few more litigation-specific sources.

Findings: Litigation Involving U.S. Patent No. 7,532,062

Bottom line: I found no evidence of any litigation involving U.S. Patent No. 7,532,062. I could not identify any district court action, ITC investigation, PTAB proceeding, or Federal Circuit appeal in which this patent was asserted, challenged, or otherwise at issue.

What I did find (and why it does not qualify)

My searches for the exact numbers "7532062" and "7,532,062" returned only unrelated patents and cases — I am reporting these explicitly so you can see they are not matches and should not be confused with the target patent:

Several plausible-looking hits were false positives triggered by substring/identifier collisions (e.g., a Lithuanian business-registry notice numbered "7532062," and a Korean summary table listing a different patent, US 7,454,002). None of these are the patent at issue.

Negative (but non-conclusive) corroborating signal

The Google Patents page you supplied for US 7,532,062 B2 contains no "Litigation," "Federal Circuit," or "Related Litigation" section in its links block — it lists only USPTO, USPTO PatentCenter, USPTO Assignment, Espacenet, Global Dossier, and Discuss. Google Patents normally surfaces a litigation link when a patent has been litigated. Similarly, the patent's legal-status history shows only routine maintenance-fee events and an "Expired - Fee Related" status (anticipated expiration 2026-11-06) — no reexamination, no adverse proceedings.

Patent bibliographic details (for your reference)

• Patent: US 7,532,062 B2 — "Semiconductor charge pump using MOS (metal oxide semiconductor) transistor for current rectifier device"
• Inventors: Toshimasa Namekawa; Hiroshi Ito
• Assignee/Original Assignee: Toshiba Corp (Kabushiki Kaisha Toshiba)
• Application No.: 12/138,005 (divisional of 11/556,810)
• Priority date: 2005-11-08 (JP 2005-323601; 2006-266050)
• Filing date: 2008-06-12 | Grant date: 2009-05-12
• Status: Expired - Fee Related

Important caveats / recommended verification

I must be candid about the limits of this conclusion:

1. I could not run live queries against the specific databases you named. My access returned general web results rather than the Unified Patents litigation case list (portal.unifiedpatents.com/litigation/caselist), PAIR/PACER dockets, or RPX Insight directly for this patent number.
2. A grant of 2009 by Toshiba (a large operating company) makes large-scale assertion litigation unlikely, which is consistent with the absence of records — but "not found" is not proof of "none exists."
3. Patent numbers 7,532,062 must be searched literally, and I have done so; the absence of hits is meaningful, but you should independently confirm in:
   • PACER / CourtListener (courtlistener.com) — search "7,532,062" and "7532062"
   • Unified Patents Portal litigation case list
   • RPX Insight (insight.rpxcorp.com)
   • Docket Alarm and Justia Patents
   • USPTO Patent Trial and Appeal Board (for any IPR/PGR) and USPTO Assignment records (for any post-grant transfer to an NPE, which often precedes assertion)

If you require a definitive clearance-style opinion, I recommend a paid docket search (LexisNexis/Docket Navigator) before relying on this negative finding, as I cannot verify it with the live litigation databases as directly as you requested.

I'll verify the structured "no proceedings" default against the public record before writing.

Let me run a few more targeted checks before concluding.

Proceedings overview

Total AIA trial proceedings on US 7,532,062: 0 — no IPRs, no PGRs, no CBMs, whether active, decided, settled, or institution-denied. The structured USPTO ODP block states verbatim that the API "returns no AIA trial proceedings for this patent as of the most recent ingest," and four independent web searches (patent number alone, patent number + IPR/PGR/CBM, patent number + PTAB, assignee/title + litigation) surfaced nothing to contradict it. The defensive posture is therefore not "the patent has been narrowed" — it is "the patent has never been PTAB-tested at all," and, more importantly, its listed anticipated expiration is 2026-11-06, roughly five weeks from today.

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No proceedings to report

There is no {PROCEEDING_NUMBER} — {Petitioner} v. {Patent Owner} entry to write. I will not manufacture one. What I can tell you with confidence, and what I explicitly could not verify:

One trap worth flagging: several search hits refer to "the '062 patent" in IPR2020-00342, IPR2022-00029, and IPR2022-00030. Those are a different patent — the petitions argue Studor/Clem art and reach claims numbered up to 95. That is not US 7,532,062 (which has a handful of claims on Dickson charge-pump architecture). Do not let a vendor's patent-number substring match pull those into your invalidity narrative.

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Strategic summary

Claim status. No claim of 7,532,062 is canceled, and none is "sustained" in any adjudicated sense — the PTAB has simply never spoken. The claims you would be sued on are the four independent aspects recited in the specification: (1) series P-channel MOS rectifiers with resistor-plus-auxiliary-pumping-capacitor dynamic level converters generating the gate control signals; (2) the N-channel mirror image; (3) and (4) the two-system (cross-coupled) variants of each. Those claims are untested, which cuts both ways: there is no cancellation to hide behind, but there is also no adverse PTAB record, no Patent Owner disclaimer, and no estoppel-laden claim construction to fight.

Estoppel landscape — there isn't any. Because no petition was ever filed, § 315(e)(2) estoppel is empty. A defendant today has the entire prior-art universe available: the Dickson 1976 paper itself (cited on the face of the patent), Tanzawa & Tanaka (cited in the Background as the N-channel approach the inventor distinguished), and any dual-well/level-converter art. Nothing is foreclosed by a prior petitioner's record. Conversely, you also get no free ride — no institution decision describing the reference set, no FWD mapping elements to claims. You build the § 102/§ 103 case from scratch.

Pattern signals. No repeat petitioner exists to profile; no defensive aggregator (Unified Patents, RPX, etc.) appears anywhere in the chain; the current assignee of record is Toshiba Corp, and the patent carries "Expired - Fee Related" as its listed legal status. A patent this old, this narrow, and this close to expiry that was never IPR'd most likely simply was never asserted against a defendant with the incentive and budget to file. The absence of PTAB activity is a weak negative signal about defensive value — it tells you the patent was probably not a revenue driver, not that it is strong.

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Recommended next steps

1. Establish whether this patent is even enforceable against your client today. The Google Patents record lists Applied expiration / anticipated expiration 2026-11-06 and legal status "Expired - Fee Related." Verify the live status in USPTO Patent Center before doing anything else. Note the consequence: post-expiration, you cannot be enjoined, but you remain exposed for back damages going back six years if the patent was in force during the accused conduct. If a demand letter is in front of you, the first question is whether the accused product predates 2026-11-06.

2. If you are asserted against, attack the sibling, not just this patent. The '062 file is a divisional: US 12/138,005 (filed 2008-06-12) descends from abandoned Ser. No. 11/556,810 (filed 2006-11-06), and the family also produced US 7,768,341 via US 12/424,290. Same specification, different claims. Any freedom-to-operate or invalidity work that looks only at '062 on its own is incomplete — map the whole family's claims against your product.

3. If you do file, know the forum details that differ for expired patents. An IPR is still available against an expired patent, but the Board applies Phillips-style construction rather than its usual plain-and-ordinary-meaning approach (see Wasica v. Continental, Fed. Cir. 2015, on the expired-patent consequence in IPR), and the patent owner cannot amend claims to survive. Statutory estoppel under § 315(e)(2) attaches to the petitioner and its privies from the FWD, not from institution. Alternatively, an ex parte reexamination under 35 U.S.C. § 302 is available "at any time during the period of enforceability," which for an expired patent means during the damages tail — often cheaper and done under a lower threshold, though slower and without a claim-by-claim trial record.

4. If there is currently no proceeding, say so plainly in any opinion you write. There is no FWD to link to, no panel to name, and no disposition to quote. The honest line is: no PTAB activity on file as of 2026-09-29; the patent's anticipated expiration is 2026-11-06; any invalidity defense must be constructed de novo.

Sources checked:

• Structured ODP "PTAB proceedings on file" block (canonical — reports zero)
• Google Patents — US7532062B2
• USPTO PATS/ptacts (PTAB E2E and the petition-document repository, via indexed search hits)
• USPTO PTAB E2E endpoint — link for your own docket-confirming search
• CourtListener — link for your own CAFC/docket sweep

A limitation I want stated plainly: the district-court and reexamination columns in the table above are blank because I did not run a full PACER/Lex Machina docket sweep, and my web searches returned no litigation hits for this number. Treat "no litigation found" as unverified rather than as a finding. If your engagement depends on whether this patent has been asserted anywhere, that check should be run against a docket database before you rely on it.

I'll research the assignment record for US 7532062 before building the analysis.

Let me dig deeper into the specific assignment records.

Let me check the assignment abstract of title and legal events directly.

Ownership Analysis — US 7532062 B2

Patent: Semiconductor charge pump using MOS (metal oxide semiconductor) transistor for current rectifier device
App. No.: 12/138,005 (divisional of 11/556,810, filed 2006-11-06)
Priority: 2005-11-08 (JP 2005-323601); also JP 2006-266050, filed 2006-09-28
Granted: 2009-05-12
Assignee of record on the face of the patent: Kabushiki Kaisha Toshiba

Sourcing caveat up front: I could not open the USPTO Assignment Center UI directly from this session. Targeted searches of the assignment indexes (legacy-assignments.uspto.gov, uspto.report, Google Patents legal events) returned no recorded assignment for US 7532062 / application 12/138,005. Everything below is grounded in the patent front page, the Google Patents legal-events block, and related Toshiba filings. Where I am uncertain, I say so rather than fill the gap.

Inventors

Basis for employer attribution: not proof of employment directly, but strong circumstantial linkage. Namekawa is a long-running Toshiba circuit designer — he appears as an inventor on other Toshiba-assigned patents, e.g. US 6,529,399 B1 ("Semiconductor device realized by using partial SOI technology," assignee Kabushiki Kaisha Toshiba) and US 7,956,397 B2 (charge pumping circuit, assignee Kabushiki Kaisha Toshiba). Ito does not have a comparably documented trail in the material I retrieved.

Unusual patterns: none detected. Both inventors are Japanese-resident Toshiba circuit engineers on a Toshiba-assigned application with Japanese priority filings made by Toshiba. There is no evidence of inventors departing the assignee within 12 months of filing, and no evidence of inventor-held title. This does not look like a fire-sale precursor.

Original assignee

Kabushiki Kaisha Toshiba (Toshiba Corporation), 1-1 Shibaura 1-chome, Minato-ku, Tokyo 105-8001, Japan.

• Primary line of business: diversified electronics — NAND flash memory, discrete semiconductors, HDDs, power systems, infrastructure. In 2005–2009 (the relevant window) Toshiba was one of the world's largest NAND flash and CMOS logic suppliers.
• Did they ship a product embodying the claims? Unclear from the record I retrieved, and I will not assert it. The patent is directed at an internal circuit — a Dickson-type charge pump used to generate the ~6 V write voltage for gate-oxide-destruction anti-fuse elements on-chip (spec ¶ on "electrical characteristics required for an internal voltage increase power source"). Toshiba's own anti-fuse / OTP trim-memory products in 90 nm-generation CMOS would be the natural embodiment, but I found no product literature tying this specific circuit to a shipping part.
• Current status: Toshiba Corporation still exists. Its memory business was carved out into Toshiba Memory Corporation (2017) and later rebranded Kioxia — but I found no recorded assignment of this patent to Kioxia or Toshiba Memory, so I cannot say this patent moved with that divestiture. Google Patents currently flags the asset as "Expired – Fee Related," with an anticipated expiration date of 2026-11-06; if that label is accurate it means maintenance fees were not paid, which is itself a strong indicator of abandonment rather than assertion.

Assignment timeline

No recorded assignments were found for US 7532062.

The Google Patents legal-events block for this patent contains only: filing (2008-06-12), publication of US 2008/0246535 A1 (2008-10-09), grant (2009-05-12), a priority link to application 12/424,290 (US 7,768,341 B2), and the expiration entry (2026-11-06). There is no Assignment, Security Agreement, Merger, Change of Name, License, Release, or Correction entry. USPTO Assignment Center searches by patent number returned nothing either.

Per the source instructions: no Assignment Center records were retrievable for this patent. Taken at face value, that means title never left the original assignee — Toshiba retained it from filing through expiry, and no attorney or firm of record exists for this chain because no recording was ever made.

One adjacent observation, clearly labelled as not an assignment finding: the prosecution firm of record on Namekawa's Toshiba charge-pump/anti-fuse family was Oblon, Spivak, McClelland, Maier & Neustadt, P.C. (Alexandria, VA), which appears on US 6,529,399 and on the sibling application US 2008/0237673 A1. That is patent-prosecution counsel, not an assignment correspondent, and it is not evidence of any ownership transfer. I mention it only so it isn't mistaken for an NPE-side firm later; Oblon is a large general-practice IP firm that does substantial operating-company work.

Timeline diagram

timeline
    title Ownership of US 7532062
    2005 : JP priority filed by Toshiba
    2006 : US application 11/556810 filed
    2008 : Divisional 12/138005 filed
    2009 : Patent US 7532062 issued to Toshiba
    2026 : Anticipated expiration

NPE / troll-pattern signals

Verdict

Insufficient data (no records beyond the original inventor→Toshiba chain, which itself is not visible as a recorded assignment).

Justification: the retrievable record for US 7532062 contains no post-issuance assignment events of any kind — no reel/frame to cite, no assignee other than Kabushiki Kaisha Toshiba, and no correspondent of record because no recording exists. Google Patents carries the asset as "Expired – Fee Related" with an anticipated expiration of 2026-11-06, which points to lapse-by-non-payment rather than to any licensing or assertion campaign. There is therefore no NPE signal to evaluate: zero transfers, zero litigation I could locate, zero shell entities. I flag explicitly that I could not query the Assignment Center directly from this session, so this should be re-verified against the primary source before being relied on.

Verification links:

• USPTO Assignment Center (search patent 7532062): https://assignmentcenter.uspto.gov/
• Indexed mirror: https://assignment.uspto.gov/patent/index.html
• Google Patents legal events: https://patents.google.com/patent/US7532062/en
• Sibling patent US 7,768,341 B2 (same family, app 12/424,290): https://patents.google.com/patent/[US7768341B2](/patent/US7768341B2)/en

I'll research US patent 7532062 and its cited prior art references.

I found the cited references. Let me gather detailed bibliographic data on each cited patent.

Analyst Note on Scope and Sourcing

I attempted to pull US7532062's citation record and each cited reference directly. The citation list below is taken verbatim from the "Referenced Cited" section of the granted patent (as reproduced on Justia/Google Patents for US7532062). I was able to retrieve full descriptions for four references; for the remaining cited patents the retrieval budget was exhausted before I obtained their text, so I have flagged those explicitly rather than fabricating descriptions. Where I state a description, it is grounded in retrievable source text; where I do not, I say so.

Two additional caveats that matter for a § 102 analysis:

• The claims of US7532062 as granted are claims 1–5 only, all drawn to the two‑system P‑channel charge pump. (The specification's "second aspect" N‑channel pump and single‑system variants are in the specification/other family members, not in the granted claims of this patent.) Any anticipation analysis must therefore map against claims 1–5, not the broader disclosure.
• No single cited reference that I was able to review discloses every element of claim 1. The realistic posture of these references is § 103 (obviousness) art, or § 102 only against narrow dependent claims. I note this per reference below.

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1. The Patent at Issue

Granted claim 1 (independent) requires, combined:
(a) a two‑system charge pump of plural P‑channel MOS transistors as current‑rectifier elements in series between VDD and VPP;
(b) first pumping capacitors at the transistor connection points;
(c) a clock generator producing Φ1/Φ2 180° apart, alternately driving the first pumping capacitors;
(d) resistor elements from the connection points to the gates of the P‑channel transistors;
(e) second (auxiliary) pumping capacitors, clock‑driven, at the gate side, generating gate control signals (the "dynamic level converter"); and
(f) cross‑coupling: the control signals of one system drive the gates of the other system.

Dependent claims: 2 (resistors are MOS transistors), 3 (clock signals are rectangular, VSS/VDD), 4 (back‑gate bias circuits), 5 (clocks applied in reverse between the two systems).

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2. Patent Citations of US7532062 (face of the patent)

U.S. Patent Documents

Non‑Patent Literature (cited in the specification)

• N1 — J. F. Dickson, "On‑Chip High‑Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique," IEEE J. Solid‑State Circuits, vol. SC‑11, No. 3, June 1976, pp. 374–378.
• N2 — Toru Tanzawa & Tomoharu Tanaka, "A Dynamic Analysis of the Dickson Charge Pump Circuit," IEEE J. Solid‑State Circuits, vol. 32, No. 8, Aug. 1997, pp. 1231–1240.

(Note: the specification text in my authoritative copy of the patent also cites these two NPL references by name in the "Description of the Related Art.")

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3. Per‑Reference Analysis

N1 — Dickson (1976) — IEEE JSSC

• Citation: Dickson, IEEE JSSC, vol. SC‑11, No. 3, pp. 374–378, June 1976.
• Disclosure: The foundational "Dickson" voltage multiplier: cascaded rectifier elements (diodes) between supply and output, with pumping capacitors alternately driven by two non‑overlapping (180°‑offset) clocks. This is the basic topology recited in the preamble/organization of claim 1.
• § 102 relevance: Anticipates nothing in claims 1–5 as a whole — it uses diodes, not P‑channel MOS rectifiers with gate control, and has no resistor/auxiliary‑capacitor dynamic level converter and no two‑system cross‑coupling. It is background art establishing the "Dickson type" label used throughout US7532062.
• Best use: § 103 base reference.

N2 — Tanzawa & Tanaka (1997) — IEEE JSSC

• Citation: IEEE JSSC, vol. 32, No. 8, pp. 1231–1240, Aug. 1997.
• Disclosure: Dynamic (transient) analysis of the Dickson charge pump using diode‑connected N‑channel MOS transistors as rectifiers; explicitly treats the back‑gate (body) effect degrading current drive as the output rises.
• § 102 relevance: The specification itself distinguishes this reference (N‑channel MOS rectifiers, back‑gate effect problem). It does not disclose P‑channel rectifiers, the resistor+auxiliary‑capacitor gate driver, or two‑system cross‑coupling. No anticipation of claims 1–5.
• Best use: Context for the problem the invention solves; § 103 base reference.

US 4,922,402 — Olivo et al. (STMicroelectronics), 1990‑05‑01

• Full citation: US 4,922,402 A, "CMOS voltage multiplier," granted 1990‑05‑01; IT priority 1988‑06‑28.
• Disclosure (verified): A multistage CMOS voltage multiplier in which each stage's charge‑transfer device is an enhancement‑type P‑channel MOS transistor (T2a, T3a, …) used as a "diode equivalent structure." The gate of that P‑channel transistor is coupled via a coupling capacitor (Cc2, Cc3, …) to the same clock phase (φ1 or φ2) that drives that stage's output capacitor. A second like‑type MOS transistor is diode‑connected between drain and gate. The two clock phases φ1/φ2 are in phase opposition.
• § 102 relevance: This is the closest cited art to the "P‑channel MOS as current‑rectifier element with the gate driven by a capacitor coupled to a clock phase" idea — i.e., an ancestor of the "dynamic level converter." However, the gate‑control element is a diode‑connected MOS transistor, not a resistor element, and there is no two‑system cross‑coupling. It therefore does not anticipate claim 1. It could be argued against claim‑1‑type subject matter only in combination (§ 103), and its P‑channel‑MOS‑as‑rectifier disclosure is material to the pre‑characterization of the art.

US 5,066,870 — Kobatake (NEC), 1991‑11‑19

• Full citation: US 5,066,870 A, "Charge pump having pull‑up circuit operating with two clock pulse sequences," granted 1991‑11‑19; filed 1990‑06‑20 (US 07/541,808); JP priority 158587/89, 1989‑06‑20.
• Disclosure (verified): A charge pump with a charge‑up circuit and a pull‑up circuit formed by an enhancement‑mode MOSFET and a "time constant circuit" that has two capacitors and a resistor connected therebetween, responding to first and second clock pulse sequences to successively apply voltages to the drain and gate of the MOSFET. A clock generator produces first/second clock sequences of differing pulse durations; the charge‑up circuit is a depletion/enhancement MOSFET.
• § 102 relevance: Materially relevant to the "resistor element + capacitor(s), clock‑driven, controlling the gate of a MOS rectifier" concept that underpins claim 1(d)–(e) and claim 2. But it is an N‑channel MOSFET pull‑up/cascade pump, not a five‑stage P‑channel two‑system Dickson pump, and lacks the cross‑coupling of claim 1(f). No full anticipation of claim 1; strong § 103 reference for the resistor + clock‑driven capacitor gate‑control feature.

US 5,939,935 — Merritt (Micron), 1999‑08‑17

• Full citation: US 5,939,935 A, "Charge pump," granted 1999‑08‑17 (Micron Technology).
• Disclosure (verified): A charge pump / substrate‑bias generator in which MIS capacitor well regions and transistor well (body) regions are tied to a switched potential node to reduce body (back‑gate) effect and thereby lower threshold voltage; and in which the output phase circuits output pulses substantially 180° out of phase. Also describes MOS capacitors with source/drain shorted to the well.
• § 102 relevance: Directly material to claim 4 (back‑gate bias circuits) and to the two‑phase (180°) clocking of claim 1(c). It does not disclose the P‑channel Dickson rectifier stack, the resistor + auxiliary‑capacitor dynamic level converter, or the two‑system cross‑coupling, so it does not anticipate claim 1. It is a strong § 103 reference for the back‑gate‑bias concept of claim 4.

US 6,191,963 — McPartland et al., 2001‑02‑20

• § 102 relevance: Not assessed — I could not retrieve the document text, and I won't fabricate a description. Its 2001 grant date places it inside/around the relevant art window; it should be pulled and mapped to claims 1–5 before any final § 102 opinion is issued.

US 6,278,315 — Kim, 2001‑08‑21

• § 102 relevance: Not assessed — text not retrieved. (Listed on the face of the patent; a charge‑pump‑family reference by date.)

US 6,603,346 — Sawada et al., 2003‑08‑05 — and US 7,102,422 — Sawada et al., 2006‑09‑05

• § 102 relevance: Not assessed — text not retrieved. Note these are two Sawada et al. references cited on the face, suggesting a related charge‑pump family. Because the '422 reference is a September 2006 grant (after the 2005‑11‑08 priority and 2006‑09‑28 JP priority), it can only be § 102(a)/(e) art if it qualifies by its own effective filing date; treat with care. Flag for full retrieval.

US 6,690,227 — Lee et al., 2004‑02‑10

• § 102 relevance: Not assessed — text not retrieved.

US 6,864,739 — Shor et al., 2005‑03‑08

• § 102 relevance: Not assessed — text not retrieved.

US 6,952,129 — Lin et al., 2005‑10‑04

• § 102 relevance: Not assessed — text not retrieved. (Granted just before the Nov. 2005 priority; within window.)

US 6,992,522 — Ido, 2006‑01‑31

• § 102 relevance: Not assessed — text not retrieved.

US 7,190,211 — Nakagawa et al., 2007‑03‑13

• § 102 relevance: Not assessed — text not retrieved.

US 7,221,610 — Yamazoe et al., 2007‑05‑22

• § 102 relevance: Not assessed — text not retrieved. (2007 grant — only § 102(a)/(e)‑eligible if its effective filing predates the critical date.)

US 2008/0049485 A1 — Matsufuji et al., 2008‑02‑28

• Full citation: U.S. Patent Application Publication 2008/0049485 A1, published 2008‑02‑28.
• § 102 relevance: Not assessed — text not retrieved. Its 2008 publication date is later than the priority date, so it is only prior art (if at all) by its filing date/§ 102(e); verify effective filing date before relying on it.

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4. Most Relevant Prior Art (bottom line)

On the material I could verify, the references that most directly bear on the elements of claims 1–5 are:

1. US 4,922,402 (Olivo) — P‑channel MOS used as the charge‑transfer/rectifier device, with its gate AC‑coupled through a capacitor to a clock phase; two phase‑opposed clocks. Closest to the "P‑channel rectifier with dynamically driven gate" concept. But: diode‑connected MOS (not a resistor) controls the gate; no two‑system cross‑coupling.
2. US 5,066,870 (Kobatake) — Resistor + capacitors, clock‑driven, controlling the gate of a MOS device ("time‑constant circuit"); two clock sequences. Closest to the "resistor + auxiliary pumping capacitor dynamic level converter" of claims 1(d)–(e) and 2.
3. US 5,939,935 (Merritt) — Body/back‑gate biased to switched nodes to defeat body effect; 180°‑opposed phases. Closest to claim 4 (back‑gate bias circuits).
4. N1 Dickson (1976) and N2 Tanzawa (1997) — the base Dickson topology and its two‑phase clocking (N1) and the diode‑connected N‑channel/back‑gate‑effect analysis (N2); background for the preamble and the problem statement.

No single one of these anticipates claim 1. Claim 1 is a specific combination — P‑channel MOS rectifier stack + resistor/auxiliary‑capacitor clock‑driven gate control + two‑system cross‑coupling — that the verified references do not collectively, let alone individually, show. The realistic attack profile is a § 103 combination (e.g., Dickson/Olivo/Kobatake as to the rectifier/pump and gate‑drive, with Merritt as to back‑gate biasing for claim 4), plus a § 102(a)/(e) date check on the post‑2005‑11‑08 items (US 7,102,422; US 7,190,211; US 7,221,610; US 2008/0049485).

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5. Explicit Gaps / Recommended Next Steps

Because I could not retrieve the full text of ten of the fourteen cited U.S. documents, I have not opined on their § 102 effect and have not invented descriptions for them. To complete a defensible citation‑by‑citation § 102 chart, the following should be pulled from the USPTO PatentCenter/Google Patents and mapped to claims 1–5:

US 6,191,963 · US 6,278,315 · US 6,603,346 · US 6,690,227 · US 6,864,739 · US 6,952,129 · US 6,992,522 · US 7,102,422 · US 7,190,211 · US 7,221,610 · US 2008/0049485 A1.

Also worth noting for completeness: US7768341B2 (Appl. 12/424,290) and US20080246535A1 / US20090201076A1 are family members of US7532062 itself, not prior art, and should be excluded from any anticipation chart for this patent.

I'll ground this analysis in the references actually surfaced on the patent page, then check what else the record cites.

Let me pull the actual citation list for US 7,532,062 and check the two non-patent citations and the "bootstrapped clock" prior art it builds on.

Obviousness Analysis — US 7,532,062 B2

Patent: Semiconductor charge pump using MOS (metal oxide semiconductor) transistor for current rectifier device — Toshimasa Namekawa / Hiroshi Ito, assignee Kabushiki Kaisha Toshiba. App. 12/138,005 (divisional of 11/556,810, filed Nov. 6, 2006); JP priority 2005-323601 (Nov. 8, 2005) and 2006-266050 (Sep. 28, 2006). Granted May 12, 2009.
Source: https://patents.google.com/patent/US7532062/en

0. Verification caveats (read first)

• The Google Patents extraction I was given did not include the "Citations / References Cited" block. The "Prior Art" material actually present on the page is: (a) the Prior-art keywords (charge pump, MOS transistors, type MOS, type, pumping capacitors) and prior-art date 2005-11-08; (b) the classification entries including H02M 3/073 and H02M 3/075 ("…including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages"); and (c) the Background of the Invention, which cites Dickson 1976 and Tanzawa & Tanaka 1997. Those are the references I treat as "the Prior Art section of this page."
• Additional references below (Fujita US 5,943,271; US 2004/0246044 A1; Meng US 6,501,325; Park US 6,914,791; the pMOSFET/bootstrapped-clock EEPROM generator) were recovered by search and are flagged individually as to verification. One search hit (US 7,928,796 B2's page) showed a "Non-Patent Citations (2)" list — Matsukawa, High-Efficiency Charge Pump Circuits, Karuizawa Workshop 2004, and U.S. App. 11/670,605 (Wada, filed Feb. 2, 2007). Those appear to belong to US 7,928,796 B2, not to US 7,532,062, and the Wada application post-dates the Nov. 2005 priority date in any event. I do not rely on them.
• Claim numbering: the page reproduces only the four "BRIEF SUMMARY" aspects. I assume claims 1–4 = the four independent claims (P-channel; N-channel; P-channel two-system; N-channel two-system), with dependent claims not visible to me. I could not verify the granted dependent claim set or the prosecution history / reasons for allowance.

1. Legal framework

Because the application was filed Nov. 6, 2006 (divisional June 12, 2008) with a Nov. 8, 2005 foreign priority, pre-AIA 35 U.S.C. §§ 102/103 govern. Obviousness is judged under Graham v. John Deere (scope/content, differences, PHOSITA level, secondary considerations) and KSR Int'l v. Teleflex (predictable combinations of known elements; "a technique used to improve one device, and a person of ordinary skill would recognize it would improve similar devices in the same way"). Design choice and crowded-art considerations weigh heavily here because the classification itself (H02M 3/073–3/077) shows a highly developed art of multi-stage, two-clock charge pumps.

PHOSITA: a CMOS analog/mixed-signal circuit designer with ~3–5 years in on-chip high-voltage generation for nonvolatile memory, familiar with Dickson multipliers, MOS transfer transistors, level shifting, and N-well/back-gate biasing.

2. What the claims require (feature decomposition)

Claim 1 (P-channel version) requires:

Claims 2 and 4 substitute N-channel MOS transistors; claims 3 and 4 are the two-system variants in which the control signal generated in one pump controls the gates of the transistors of the other pump (cross-coupling). Notably, claim 1 as quoted does not recite that the gate signal is an "intermediate potential," nor any back-gate/well bias circuit — the intermediate-potential and N-well-bias features live in the specification (and in later embodiments). That breadth materially enlarges the § 103 exposure.

3. The prior art on the record

4. Ground 1 — Claims 1 and 2 obvious over Dickson + Tanzawa (+ bootstrapped/level-shifted gate drive)

Dickson alone does not anticipate claim 1 (no MOS rectifiers, no resistor/auxiliary-capacitor gate network); Tanzawa alone does not anticipate it either (MOS transfer transistors there are used as the rectifier element in the Dickson skeleton; the reference analyzes threshold/back-gate behavior of such devices and does not show a resistor-to-gate + auxiliary-capacitor dynamic level converter). The question is therefore combination obviousness, and the motivation is unusually well documented on the face of the patent itself:

1. Why replace the rectifier with a MOS transistor at all. The patent's own Background concedes the whole point of the invention: a Dickson pump conventionally needs a dual-well diode because a parasitic diode's forward-biased PN junction turns on a PNP parasitic bipolar and leaks into the P-substrate, but dual-well diodes are "high in [their] manufacturing cost." Avoiding special structures is the stated reason the anti-fuse memory can be made "inexpensively." Dickson provides the skeleton; Tanzawa confirms the industry already practiced MOS transfer transistors in Dickson pumps; Fujita and US 2004/0246044 confirm P-channel (and mixed N/P) MOS rectifier stacks with capacitors at the transfer nodes. Substitution of MOS transistors for diodes in a Dickson chain is thus a known, predictable substitution with an articulated cost/process motivation.

2. Why actively drive the gates. Tanzawa's own abstract/framing makes the MOS-rectifier pump's threshold-voltage/back-gate limitation the central design problem, and the pMOSFET/bootstrapped-clock EEPROM generator reference (above) expressly solves it by clocked (bootstrapped) gate drive "that does not suffer from the threshold voltage drop." The applicant's FIG. 5 comparative circuit confirms the same idea was in the art (clocks φ1′/φ2′ directly on the gates). A PHOSITA seeking to keep the P-MOS rectifier fully ON/OFF at each phase — rather than relying on diode-connection — would look to clock-derived gate drive.

3. Why the specific resistor + auxiliary-capacitor arrangement. The claimed dynamic level converter is, functionally, the textbook implementation of an AC-coupled level shifter / bias clamp: a resistor taps a DC operating point from the pump node, a capacitor couples the clock, and the resulting node settles at an intermediate potential that swings around it. Two independent motivations converge: (i) the patents' own problem statement is that a VSS↔VPP full-swing gate clock (FIG. 5) needs high-withstand-voltage transistors, defeating the "no special process" goal; a PHOSITA would therefore be led to reduce the gate swing — exactly what AC coupling through a capacitor with a resistive DC tap achieves; and (ii) the same AC-coupled bias network also drives the gate of a MOS rectifier whose source/drain swing with the pump, which is why the specification notes that source-drain and source-gate voltages of all devices stay ≤ VDD (allowing ordinary I/O-buffer transistors). The resistor value (~15 kΩ) and auxiliary-capacitor value (~1 pF) recited in the specification are merely routine design-parameter selection in view of the ~400 MHz clock.

4. KSR fit. Every element of 1a–1e is individually known: series MOS rectifiers with pumping capacitors and two anti-phase clocks (Dickson; Tanzawa; Fujita), and capacitively-coupled/resistor-clamped gate bias (level-shifter art; FIG. 5). The combination yields no more than the predictable aggregate of the known functions (faster/more complete charging of the transfer gates at low voltage without high-voltage devices). The classification H02M 3/075 shows the "two sets of clock signals … odd and even stages" architecture was a crowded, well-explored space.

5. Claim 2 (N-channel) is a fortiori obvious. Tanzawa's subject matter is diode-connected N-channel MOS transfer transistors; the claim 2 structure differs from claim 1 only in conductivity type. Adapting the same gate-drive network to N-channel devices is a mere substitution of a known equivalent, with the opposite-polarity gate signals an expected corollary.

5. Ground 2 — Claims 3 and 4 obvious over the above in view of cross-coupled / two-system charge-pump art (Meng; Park)

Claims 3 and 4 add only: the pump is provided in two systems, and the control signals generated in one system's auxiliary-capacitor network control the gates of the other system's transistors (cross-coupling).

• Two interleaved pumps in opposite phase is the standard way to reduce output ripple and increase effective pumping frequency, and is exactly what Meng US 6,501,325 ("Cross-Coupled High Voltage Charge Pumps") and Park US 6,914,791 (triple-well charge pump) address. The specification itself implements the interleaving by simply swapping the φ1/φ2 assignments in the second system.
• Cross-coupling a gate-control node from one half to the other half is the canonical cross-coupled latch structure; the motivation (each half is naturally in the complementary phase, so one half's gate signal is the correct drive for the other half) is immediate and requires no inventive insight.
• Because claim 3/4 recite the cross-coupling of a control signal that has already been found obvious in Ground 1, the added feature is a predictable use of a known technique on a known circuit — the classic KSR combination.

Claim 4 (N-channel two-system) follows from claim 2 by the same reasoning.

6. Secondary/objective considerations and the applicant's best counterarguments

Applicant-side (non-obviousness) arguments, and their strength:

1. "The art taught away." The specification disparages both known gate-drive routes: diode-connected N-channel is said to suffer fatal back-gate/threshold loss at high boost, and the FIG. 5 full-swing VPP gate clock is said to require high-withstand-voltage transistors — which defeats the entire cost premise. Assessment: weak-to-moderate. Disparagement of two alternatives is not a teaching away from the claimed third alternative; under KSR, identifying a drawback in an approach and seeking a lower-voltage variant of it is ordinary design iteration. However, if an accused infringer relies on the same references the applicant criticized, expect a genuine factual dispute over the level of skill required to arrive at the resistor/auxiliary-capacitor topology.
2. No express hint of the resistor + second-capacitor arrangement. The single best non-obviousness point is that the prior art (as characterized on this page) drives rectifier gates either by diode-connection or by full-swing clocks; if the pMOSFET/bootstrapped-clock reference likewise uses bootstrapped rather than resistor-clamped coupling, then the specific "resistor to the inter-transistor node, auxiliary capacitor to gate, driven by φ1/φ2" network is the point of novelty. Expect reliance on the intermediate-potential teaching in the specification. Caveat: claim 1 does not recite "intermediate potential," so this argument helps the specification more than the claim.
3. Objective indicia (weak so far). The specification asserts (i) usable with ordinary I/O transistors because all device voltages ≤ VDD, (ii) latch-up/parasitic-bipolar avoidance (embodiment 2), (iii) higher current drive by lowering the average gate potential with R0 to VSS (embodiment 3), and (iv) better current efficiency by taking the compensation charge from the drain-side nodes (embodiment 6). To be probative these need a nexus to the claimed structure and evidence (comparative data, long-felt need, failure of others, commercial success). The single-paragraph qualitative statements — and the specification's own note that embodiment 6's benefit is "particularly significant [when] the threshold voltage … is low" while embodiment 5's is significant when it is high — read as routine optimization along a known trade-off axis, which undercuts rather than supports non-obviousness.

7. Bottom line

Key verification gaps I did not close: (a) the actual "References Cited" list on US 7,532,062's face (not present in the extraction and not retrievable this session); (b) the bibliographic identity/date of the pMOSFET "bootstrapped clock generator" EEPROM HV-generator paper; (c) the granted dependent-claim set and the examiner's reasons for allowance. If a formal invalidity position is needed, the first step is to pull the patent's front-page citation list and file history, because the strongest art may be an examiner-cited reference I have not seen.