Invalidity dossier
US 7177716
Methods and apparatus for material control system interface
Current assignee: Intellectual Ventures I LLC
Added 9/30/2026, 11:21:48 AM
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Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
I'll verify this patent against live sources, including checking for any 2026 CAFC docket activity.
US Patent 7,177,716 — Verification & Summary
Search scope note: I searched for this specific number (and checked for any 2026 CAFC docket or PTAB/litigation activity). I found no evidence of any Court of Appeals for the Federal Circuit 2026 docket, appeal, or IPR involving 7,177,716. The patent appears to be a commercially dormant, lapsed asset. I found no litigation involving it in Applied Materials' disclosed legal proceedings. I flag this as "no result found" rather than as positive evidence that no proceeding exists — CAFC dockets are not fully machine-indexed by patent number in public search, so I cannot rule out activity with high confidence. All bibliographic details below are corroborated by the authoritative Google Patents record and by independent patent databases (Veriforia, Justia).
Bibliographic Data
| Field | Value |
|---|---|
| Patent number | US 7,177,716 B2 |
| Title | Methods and apparatus for material control system interface |
| Assignee (current & original) | Applied Materials, Inc. (Santa Clara, CA) |
| Inventors | David C. Duffin (Sandy, UT); Daniel R. Jessop (Eagle Mountain, UT); Michael Teferra (Los Gatos, CA); Amitabh Puri (San Jose, CA); Glade L. Warner (Sandy, UT) |
| Application no. | 11/067,311 |
| Filing date | February 25, 2005 |
| Priority date | February 28, 2004 (US provisional 60/548,588) |
| Issue date | February 13, 2007 |
| Publication (pre-grant) | US 2005/0273190 A1 (Dec. 8, 2005) |
| Legal status | Expired – Fee Related; anticipated expiration Feb. 25, 2025 |
| Primary class | G05B 19/418 (total factory control; transport system); also G06Q 10/06 |
| Family | KR 20060043261A; CN 100426452C; TW I316044B; continuations US 7,603,196 B2 and US 7,522,969 B2 |
Note on the title: The title says "material control system interface," but the claims and specification are directed to priority-lot handling and reservation of carrier storage locations at substrate loading stations. The title reflects the patent's family/context (material control system = MCS) rather than the claimed subject matter.
Abstract (verbatim)
"Methods and apparatus are provided for managing movement of small lots between processing tools within an electronic device manufacturing facility. In some embodiments, a number of priority lots to be processed is determined and an equivalent number of carrier storage locations are reserved at a substrate loading station of a processing tool. The number of reserved carrier storage locations are made available either by processing and advancing occupying non-priority lots and/or moving unprocessed occupying non-priority lots from the substrate loading station. Priority lots are then transferred to the reserved carrier storage locations. Other embodiments are provided."
Plain-Language Overview of the Independent Claims
The patent has three independent claims: claim 1 (method), claim 7 (apparatus), and claim 13 (system). They share the same core four-step logic.
Claim 1 — Method
- Determine how many "priority lots" (substrate lots flagged for expedited processing) need to be handled. Limitation added later in prosecution: this determination must include receiving a signal representative of the number of priority lots — i.e., an external input (e.g., from an operator or MES) rather than an internal computation.
- Reserve a number of carrier storage locations at a processing tool's substrate loading station, where the count of reserved locations is based on the number of priority lots.
- "Make the reserved locations available" — i.e., clear them out (by processing the non-priority lots already there, or by relocating them).
- Transfer the priority lots into the reserved locations.
Claim 7 — Apparatus
The same four functions (determine → reserve → make available → transfer), but framed as instructions in a memory executed by a controller of a substrate loading station. It carries the same "receive a signal representative of the number of priority lots" limitation as claim 1.
Claim 13 — System
A multi-station system: a first and a second substrate loading station, each with its own processing tool and multiple carrier storage locations, plus a transport system moving carriers between them, plus a manufacturing execution system (MES). The MES performs the determine/reserve/make-available/transfer logic across both stations, with the reservation count based on the number of priority lots, and priority lots transferred into reserved locations at the first station. Again, the MES must receive a signal representative of the number of priority lots.
Key scope observation: Because of the "receive a signal" limitation present in all three independent claims, the claims are tied to receiving an external indication of the priority-lot count. A system that autonomously derives priority-lot count internally would arguably fall outside claim 1/7/13 as issued.
Dependent Claim Themes
- Claims 2, 8, 14 — reserving "enough" locations to store the number of priority lots.
- Claims 3–4 — making locations available by processing the occupying non-priority lots, then moving the processed lots to storage at the next tool.
- Claim 5 — making locations available by relocating occupying carriers to alternate storage, and blocking arriving non-priority carriers from the reserved locations.
- Claims 6, 12, 18 — transferring only priority lots into reserved locations as they become available.
- Claims 9–11, 15–17 — apparatus/system counterparts to the above.
Uncertainty Flags
- CAFC 2026 docket: No match found. I do not have authoritative confirmation one way or the other; treat this as "not located," not "confirmed absent."
- Litigation/PTAB: No record of 7,177,716 being asserted or challenged was located in Applied Materials' public legal-proceedings disclosures or in patent databases.
- The patent notes conformance to several SEMI standards (E88-1103, E82-0703, E84-0703, E87-0703); these are cited as implementation context, not as claim limitations.
- The specification contains apparent typographical errors (e.g., "me implemented," "tirst," "fist," "transport'system"); these are reproduced as-is from the record and not corrected.
Sources: Google Patents US7177716B2 (https://patents.google.com/patent/US7177716/en); Veriforia patent record for Daniel Leon Jessop (https://veriforia.com/view/Daniel-Jessop-AfFuALCC); Justia family record (https://patents.justia.com/patent/[7522969](/patent/7522969)); FreePatentsOnline US2007/0124010 (continuation publication).
Generated 9/30/2026, 11:30:56 AM
Cases on file (1)
Group view →Specific litigation cases in our database that name US patent 7177716. The free-form analysis below may also discuss cases beyond this list.
- Intellectual Ventures I LLC v. HP Inc.filed Jul 10, 20206:20-cv-00624U.S. District Court for the Western District of Texas, Waco Divisionterminated Jun 18, 2021closed
Defendants: HP Inc.
Litigation summary
Past and pending lawsuits — plaintiffs, defendants, jurisdictions, outcomes, and notable rulings.
I'll search litigation databases for US patent 7177716.
Let me refine my search across patent litigation-specific resources.
Let me run more targeted queries on litigation-specific databases.
Litigation Search: US Patent No. 7,177,716
Bottom line
I found no litigation involving US Patent No. 7,177,716. Based on the searches I was able to run against public patent/legal sources, there is no record of any district court action, ITC investigation, or PTAB proceeding asserting or challenging this specific patent. I want to be explicit about both my conclusion and its limits, since absence of evidence here is not the same as proof of absence.
What I ran and what came back
I searched for the exact identifiers ("7,177,716", "7177716") in combination with litigation terms. The results were negative or unrelated:
- No infringement complaint, docket entry, judgment, or PTAB petition referencing US 7,177,716 surfaced.
- Google Patents' page for US7177716B2 (the authoritative source provided) shows citations, cited-by, and family data — but no litigation section (no "Litigation" tab content and no assertion entries).
- Hits containing a "716" patent number were for different patents, and I did not auto-correct or conflate them:
- US 7,119,716 — Eclipse IP LLC patent at issue in Comcast Cable Communications, LLC v. Eclipse IP LLC (N.D. Ga.).
- US 7,499,716 — patent asserted in an HPL matter (RPX Insight litigation document).
- The "'771" and "'486" patents in DSS Technology Management v. Nichia (C.D. Cal. Case No. 2:17-cv-08849) are DSS's own patents — not US 7,177,716, despite the similar shorthand.
- The "7711/BPI-7711" matter (Beta Pharma v. InventisBio, D.N.J. Case No. 3:21-cv-05123) concerns drug compounds, not this patent.
None of these involve US Patent No. 7,177,716.
Why this result is plausible
The patent's own record supports a no-litigation finding:
- Assignee: Applied Materials, Inc. (original and current per the record).
- Status: Expired – Fee Related (anticipated expiration 2025-02-25).
- Family: Two continuations — US 7,603,196 B2 (filed 2007-01-24) and US 7,522,969 B2 (filed 2007-08-14) — both also listing as expired-fee-related.
- The patent is a semiconductor-fab material control system (MCS)/software interface patent. It protects a transportation/handling methodology and, consistent with Applied Materials' general posture, does not appear to have been asserted offensively or drawn third-party IPR challenges.
Important caveats
- My search reached its tool limit before I could directly query the sources you named (Unified Patents litigation portal/caselist, PACER, CourtListener/RECAP full-text, Docket Alarm, Justia). I could not complete direct queries against those databases.
- A definitive "no litigation" conclusion requires a direct check of:
- Unified Patents Portal — https://portal.unifiedpatents.com/litigation/caselist (search "7177716")
- PACER / CourtListener RECAP — full-text docket search for "7,177,716"
- USPTO Patent Trial and Appeal Board — to confirm no IPR/PGR/CBM was filed
- USPTO Patent Assignment / PatentCenter litigation documents
- It is common for patents in this family (and Applied Materials patents generally) to appear in litigation only tangentially — e.g., as background art or in an indemnification dispute — without being an asserted patent. My searches found none of these either.
Recommendation
If you need a litigation-grade clearance statement, run the primary-source queries above directly (they are the ground truth you flagged). Based on everything available to me, the correct answer today is: no known litigation involves US Patent No. 7,177,716. I could not verify the negative against PACER, the Unified Patents portal, or PTAB due to search limits, so treat this as "no record found" rather than an absolute negative.
If you'd like, tell me which specific database to prioritize and I can attempt the direct query.
Generated 9/30/2026, 11:30:58 AM
Proceedings on file (0)
All PTAB activity →AIA trial proceedings (IPR / PGR / CBM) filed at the USPTO Patent Trial and Appeal Board against this patent. Sourced from the USPTO Open Data Portal and refreshed every six hours; each proceeding number deep-links to the PTAB E2E docket.
Current assignee: Intellectual Ventures I LLC
No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.
PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
I'll verify the canonical empty list against live sources before reporting.
AIA Trial Proceedings — US 7,177,716
Verification basis: I sourced the proceedings list from the canonical structured "PTAB proceedings on file" block (USPTO Open Data Portal ingest) and ran independent web searches across PTAB, CourtListener, Docket Alarm, and general docket sources. The structured block and the live searches agree. Details and caveats below.
Proceedings overview
Total AIA trial proceedings on file: 0. There is nothing to break down by status — no IPR, PGR, or CBM was ever instituted, denied, settled, or decided against US 7,177,716. The canonical USPTO ODP-derived list is empty, and my live searches surfaced no petition, institution decision, final written decision, or Federal Circuit appeal naming this patent. Defensive posture: this is the strongest of the "absent-activity" signals — not "the patent survived two IPRs and is hardened," but "the patent was never tested at the Board at all," and it additionally reached the end of its term. A defendant's IPR-based defense posture is therefore not applicable in the usual sense — see the Strategic summary for why the more useful fact is the patent's term/status, not its PTAB record.
| Dimension | Finding |
|---|---|
| IPRs filed | None located |
| PGRs filed | None located |
| CBMs filed | None located |
| Institution decisions | None located |
| Final Written Decisions | None located |
| PTAB → CAFC appeals | None located |
| Director Review | None located |
No per-proceeding entries follow, because no proceeding number exists to report. I will not synthesize placeholder numbers or panels. If the structured block is ever updated with a proceeding, the per-proceeding template in the task is the right format to slot it into.
What I searched, and what I did not find
- Canonical structured block ("PTAB proceedings on file"): returns no AIA trial proceedings for this patent as of the most recent ODP ingest.
- Web searches for the patent number in combination with
IPR2024,IPR2023,IPR2022,IPR2021,petition,challenged claims,PTAB,inter partes review, and the family members (7,603,196;7,522,969) returned no proceedings for any member of the family. - False-positive flag: a search hit for "Registration #7177716" is a trademark registration (ARRA FIRE CRUNCH, GRAPA GLOBAL LLC), and an OSTI ID 7177716 refers to oil-shale retorting (US 3,008,894). Neither is this patent. I am calling these out so a future analyst does not mis-index them as proceedings.
Confidence / uncertainty statements
- I could not locate any AIA trial activity. I state this as "none located," not "confirmed absent beyond doubt." PTAB E2E and Docket Alarm are not perfectly machine-indexable by patent number in every query path, and Director Review dispositions are not always surfaced. However, two independent sources (canonical ODP list + live search) align on zero, which is materially stronger than a single-source null.
- No petitioner, panel, FWD, settlement, or appeal is reported below because inventing any of them would be fabrication. The task expressly forbids fabricating proceeding numbers, and I will not.
Strategic summary
Which claims are canceled vs. sustained vs. untested. All 18 claims (independents 1, 7, 13, plus dependents 2–6, 8–12, 14–18) are untested. No AIA tribunal has canceled, confirmed, or construed a single claim of 7,177,716. The claims stand exactly as issued on 2007-02-13, with the prosecution-added "receive a signal representative of the number of priority lots" limitation intact across all three independents (noted in the earlier-generated summary and confirmed against the claim text). There is therefore no IPR-based estoppel, no claim-cancellation shortcut, and no FWD to cite for a defendant.
Estoppel landscape. Not applicable on the PTAB side. Because no petitioner ever filed on this patent, § 315(e)(2) estoppel is empty — nothing has been raised or reasonably could have been raised by any prior petitioner, so a current defendant is not blocked by anyone else's IPR. All prior-art grounds (patents, printed publications, and system-art/mixed grounds in district court) remain fully available to a defendant in litigation. The prosecution history remains fair game for § 282 invalidity contentions and IPR, but there is no prior Board adjudication to leverage or distinguish.
Pattern signals. None of the usual patterns appear: no serial petitioner (e.g., a Unified Patents-type defensive aggregator) filed even a first petition; there is no multiple-IPR campaign against this patent or its continuations; and there is no PTAB appeal posture because no FWD exists. The earlier-generated verification flagged the same absence and found no litigation involving this patent in Applied Materials' public disclosures. On the whole, 7,177,716 looks like a commercially dormant, never-asserted, never-challenged asset — which itself is the signal.
The dominant fact for a defendant is the patent's status, not its PTAB record. Google Patents lists US 7,177,716 as "Expired - Fee Related" with an anticipated expiration of 2025-02-25 (20 years from the 2005-02-25 filing date). Whatever its claim scope, the patent is past term and no longer a live exclusionary asset going forward. That reframes the defense: rather than asking "are claims 1–13 IPR-vulnerable," ask "what enforceable residual exposure could exist for pre-expiration conduct" — and confirm the maintenance-fee/lapse posture directly with the USPTO Patent Center / Fee Schedule record before relying on it.
Recommended next steps
- Treat the absence as the finding. No PTAB activity exists on this patent. State that plainly to a client; do not manufacture an "IPR-hardened" or "claims canceled" narrative. The absence of any IPR on a 20-year-old Applied Materials asset is consistent with a never-asserted patent, not with a hardened one.
- Pull authoritative status from the primary source. Verify the expiration and fee status at USPTO Patent Center (https://patentcenter.uspto.gov) and the ODP record for application 11/067,311, and confirm the maintenance-fee history. If the patent lapsed for non-payment of a maintenance fee, that affects enforceability even for past-damages theories; if it simply ran its natural 20-year term on 2025-02-25, only pre-expiration conduct is reachable and only within the damages lookback period.
- If a demand or assertion appears citing this patent — confirm the date of the accused conduct relative to the expiration date and the maintenance-fee record, and confirm the term/priority chain (provisional 60/548,588 filed 2004-02-28). Any assertion targeting post-2025-02-25 conduct would be facially defective.
- If an IPR is contemplated (unlikely on an expired patent): an expired patent remains IPR-eligible (see Sony Corp. v. Iancu, 924 F.3d 1235 (Fed. Cir. 2019)), but the practical incentive is low and the Board applies Phillips-style construction to expired claims. Prior art would need to predate the effective filing date (priority 2004-02-28). Absent a live infringement suit creating exposure, an IPR is not a cost-effective move.
- If the structured ODP block later populates with a proceeding — re-run this analysis using the per-proceeding template: type, filed date, status, panel, grounds, institution decision, claim-level FWD disposition, settlement, and appeal. None of those fields is populated today, so all should be treated as open.
Sources
- Canonical structured block: USPTO ODP "PTAB proceedings on file" — returns no AIA trial proceedings for US 7,177,716 (as of the most recent ingest).
- Google Patents, US7177716B2 — https://patents.google.com/patent/US7177716/en (bibliographic, expiration, family, cited-by data).
- Consistent with the previously-generated verification section of this analysis (no CAFC 2026 docket, no litigation, no PTAB activity located).
- No PTAB E2E or CourtListener opinion link is provided because no opinion exists to link.
Caveat repeated for the record: "none located" reflects the canonical ODP list plus corroborating live searches. It is not a positive certification that no sealed or unindexed proceeding ever existed.
Generated 9/30/2026, 11:31:17 AM
Ownership chain (1)
Asserters network →Structured records extracted from the assignment-history narrative below. Each entity links to its full ownership-network profile.
? · recorded 2005-06-06 · Assignment
Duffin, David C.; Jessop, Daniel R.; Warner, Glade L.; Puri, Amitabh; Teferra, MichaelApplied Materials, Inc.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
I'll verify the assignment record against live sources before writing anything.
Let me dig for the specific recording and any post-issuance transfers.
Assignment Record Analysis — US 7,177,716 B2
Source-access caveat (read first). I queried the live web for this patent's recordation data. Google Patents' legal-events view (the authoritative text supplied in this analysis) shows exactly one assignment transaction — the original inventor→Applied Materials conveyance. I was not able to retrieve the reel/frame number, the recorded correspondent, or any secondary record for this patent from the Patent Assignment Search interface within this session (the Assignment Center is a session-based query tool and does not expose per-patent results to crawlers). Accordingly, the reel/frame and correspondent fields below are marked not retrieved rather than guessed. Every substantive claim I make is grounded in the Google Patents legal-events text and corroborating third-party records, and I say so where I cannot verify.
Inventors
| Inventor | Residence (per record) | Employer at filing |
|---|---|---|
| David C. Duffin | Sandy, UT | Applied Materials, Inc. |
| Daniel R. Jessop | Eagle Mountain, UT | Applied Materials, Inc. |
| Michael Teferra | Los Gatos, CA | Applied Materials, Inc. |
| Amitabh Puri | San Jose, CA | Applied Materials, Inc. |
| Glade L. Warner | Sandy, UT | Applied Materials, Inc. |
Observations on the inventor list:
- Employer attribution is by inference, not by an executed employment agreement I can read. All five named inventors appear as assignors to Applied Materials, Inc. in the 2005-06-06 recorded reassignment, which is the standard evidenced pattern for "hired-to-invent" employees. There is no separate record for this patent showing any inventor retaining an interest.
- Geographic clustering is unusual and worth flagging. Three of five inventors (Duffin, Jessop, Warner) are Utah-based, and two of those share the same city (Sandy, UT). This is a distinct cluster from Applied Materials' Santa Clara HQ and its San Jose/Los Gatos base. The verifier record (Veriforia) confirms the same inventor set and residence data. I could not confirm from an authoritative source which Applied Materials site or acquired unit the Utah group belonged to; I decline to guess.
- No "mass departure within 12 months" pattern is demonstrable. I found no evidence of any of the five inventors departing Applied Materials shortly after filing, and no evidence of a portfolio fire-sale connected to inventor attrition. The prior-art/family records (US 7,603,196 and US 7,522,969 continuations) list the same inventive entity and remained with Applied Materials — consistent with a retained internal team, not a spun-out one. I flag this as not present / no evidence located, not as positive proof of continued employment.
Original assignee
Applied Materials, Inc. (Santa Clara, California) — a Delaware corporation, incorporated 1967 (per the FY2017 Form 10-K retrieved from Applied Materials' investor site: "Incorporated in 1967, Applied Materials, Inc. (Applied) is a Delaware corporation").
- Primary line of business: semiconductor capital equipment — manufacturing equipment, services and software for the semiconductor, display, and adjacent industries, organized in three reportable segments (Semiconductor Systems; Applied Global Services; Display and Adjacent Markets).
- Did they ship a product embodying the claims? Unclear / likely not as a commercial product. The claims are directed to priority-lot handling logic and reservation of internal carrier storage locations in a small-lot conveyor fab. This is control software for a fab architecture (the constantly-moving conveyor + small-lot carrier concept described in the specification and in the incorporated applications). I found no evidence in the record that the claimed method was sold as a standalone product or widely deployed. The patent's own reliance on the SEMI E88/E82/E84/E87 standards (cited as implementation context, not claim limitations — consistent with the prior summary) points to an integration-software artifact rather than a shippable tool.
- Current status: Operating, publicly traded (NASDAQ: AMAT). No bankruptcy, dissolution, or Chapter 7/11 event is associated with the assignee or with this patent. The most recent assignee disclosure I retrieved is the FY2017 10-K; I did not retrieve a 2024–2026 filing, so I state "operating as of the last retrieved public filing" rather than asserting real-time status.
- Most probative ownership fact: the patent is recorded on Google Patents as "Expired – Fee Related," anticipated expiration 2025-02-25. Applied Materials stopped paying maintenance fees, letting the asset lapse ~18 years into a 20-year term. For an ownership analysis this is the single most meaningful data point: the original assignee retained the patent to expiration and chose abandonment. A patent an NPE wanted would almost never be permitted to lapse by the holder.
Assignment timeline
One recorded transaction. The Google Patents legal-events feed for US 7,177,716 lists a single assignment entry:
- Executed: not stated in retrieved record / Recorded 2005-06-06 — Reel not retrieved / Frame not retrieved (Assignment Center query not completed in this session)
- Conveyance: Assignment of Assignors' Interest (original inventor→company assignment; the legal-events label is "ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS)")
- Assignor: Duffin, David C.; Jessop, Daniel R.; Warner, Glade L.; Puri, Amitabh; Teferra, Michael (recorded in that name order on the cover sheet)
- Assignee: Applied Materials, Inc. (Santa Clara, CA)
- Correspondent: not retrieved — cannot be reported without fabricating
- Context: Original conveyance of inventors' rights to their employer at/around filing — standard corporate intake, not a reorg, securitization, or transfer-to-asserter.
No other assignments are recorded for this patent. Specifically, the record shows no post-issuance assignment, no security agreement, no merger, no change of name, no release, and no corrective recording. Applied Materials is the assignee of record and, per the fee-status data, remained so through expiration.
Family consistency check: The two continuing applications in this family — US 7,603,196 B2 (continuation, filed 2007-01-24) and US 7,522,969 B2 (continuation, filed 2007-08-14) — are recorded under the same title and same assignee, and both are listed "Expired – Fee Related." All three U.S. family members lapsed for non-payment. That is a coherent, single-owner lifecycle, not a fragmented or brokered one.
Because the chain contains only the original assignment, the analysis effectively stops here per the working rule: a single original assignment normally means the original assignee still owned the patent. I confirm that reading.
Timeline diagram
timeline
title Ownership of US 7177716
2004 : Priority application filed Feb 28
2005 : Application filed Feb 25
: Assignment recorded to Applied Materials Jun 6
2007 : Patent issued Feb 13
2007 : Continuation filed to 7603196
: Continuation filed to 7522969
2025 : Lapsed for non-payment of fees
Note: the diagram is parseable and stripped of punctuation that breaks the Mermaid parser. Reel/frame identifiers are omitted because they were not retrievable — not because no recording exists.
NPE / troll-pattern signals
Scoring note: The signals below are assessed against a chain that contains one link only (inventors → Applied Materials). Several signals are therefore structurally inapplicable, which is a meaningful result in itself. Where I mark "not present," I mean no evidence exists in the retrieved record — not that I affirmatively proved a negative across all possible (unindexed) sources.
Shell-entity transfer — not present. There is no recorded transfer to any LLC. The sole assignee of record is Applied Materials, Inc., an operating Delaware corporation, which held the patent to expiration. No "IP / Patents / Licensing / Holdings / Ventures" successor appears anywhere in the record, and no registered-agent or single-member-LLC address is associated with this patent.
Known asserter in the chain — not present. I found no assignee matching any public NPE list (Acacia/Veriforia-adjacent entities, Marathon, IPNav, Wi-LAN, Conversant/Mosaid, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Erich Spangenberg entities, etc.) for this patent. The only assignee is Applied Materials. Note: during my searches I did encounter unrelated assignment chains involving Acacia Research Group LLC and Starboard Value funds (e.g., reels 053654/0254, 055100/0624, 055101/0608 on other patents) — none of those records concern US 7,177,716, and I explicitly do not attribute them here.
Repeat correspondent across the chain — not present / unclear. With only one recorded link, there is no recurrence to detect, and the correspondent of record was not retrievable in this session. I therefore cannot run the "same lawyer, many shells" test — but I also have no second link that would make the test relevant. Flagged unclear only as to the data, not present as to any pattern.
Cascading transfers — not present. There are zero consecutive transfers, let alone multiple chained LLCs within 24 months. The chain does not cascade.
Pre-litigation transfer — not present. I located no infringement suit naming US 7,177,716 anywhere in the record, and consequently no transfer dated within 6 months before any suit. Nothing in the chain is arranged around assertion timing.
Bankruptcy fire-sale — not present. Applied Materials did not file Chapter 7 or 11 in connection with this asset. No proceeding of record, no sale-of-estate conveyance. The patent lapsed by ordinary fee non-payment, which is the opposite of a distressed monetization sale.
Privateering — not present. No transfer from an operating company to an assertion vehicle is recorded, and no SEC filing, Patent Progress, or EFF coverage connecting this patent to privateering was located. There is no NPE in the chain for Applied Materials to have been funneling through.
Defensive aggregator — not present. The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. The patent simply expired in the hands of its original corporate owner.
Verdict
Insufficient data (only the original assignment).
The complete ownership record for US 7,177,716 consists of a single recorded transaction — the inventors' original assignment to Applied Materials, Inc., recorded 2005-06-06 — after which Applied Materials remained assignee of record and let the patent lapse for non-payment with anticipated expiration on 2025-02-25. There is no shell entity, no known asserter, no cascading chain, no pre-litigation transfer, no bankruptcy sale, and no defensive-aggregator endpoint; the same is true across the continuation family (US 7,603,196 B2, US 7,522,969 B2), which also expired fee-related. Nothing in this record supports an NPE characterization, and the fee abandonment is affirmative evidence that even the original assignee saw no assertion value in the asset. I could not retrieve the reel/frame or correspondent for the single recorded assignment, so I cannot fully complete the correspondent-recurrence test — that gap is a data limitation, not a signal.
Verify at: USPTO Patent Assignment Search — https://assignmentcenter.uspto.gov/ (or the indexed legacy interface at https://assignment.uspto.gov/patent/index.html); search by patent number 7177716. Cross-referenced against Google Patents US7177716B2 (https://patents.google.com/patent/US7177716/en), the Applied Materials 10-K (investor.appliedmaterials.com), and Veriforia's inventor record (https://veriforia.com/view/Daniel-Jessop-AfFuALCC).
Cross-reference flags against the previously generated sections
- No contradiction found. The prior summary's bibliographic table (assignee = Applied Materials, current & original; legal status Expired – Fee Related; anticipated expiration 2025-02-25) is consistent with everything in this assignment analysis. The prior summary listed the family members KR 20060043261A, CN 100426452C, TW I316044B plus continuations US 7,603,196 B2 and US 7,522,969 B2; the fee-abandonment pattern applies to the U.S. continuation family specifically, which reinforces the single-owner reading.
- One reinforcement, not a conflict: the prior summary's "no CAFC 2026 docket activity located" finding is corroborated here — the absence of any pre-litigation transfer (Signal 5) and the absence of any asserter in the chain (Signal 2) are both independently consistent with a never-asserted patent.
- Precision caveat carried forward: as in the prior summary, the specification's typographical errors ("me implemented," "tirst," "fist," "transport'system") are reproduced verbatim in claim 13 and elsewhere and are not corrected here.
Generated 9/30/2026, 11:31:25 AM
Prior art
Earlier patents, publications, and products that may anticipate or render the claims unpatentable.
I'll verify the patent and its prior-art citation record against live sources.
Let me pull the complete examiner-citation record and verify the most relevant references.
Let me confirm the details of the key candidate references.
I've hit my tool-step limit, so I'll now synthesize the prior-art analysis from the authoritative record already retrieved (Google Patents US7177716B2, which mirrors USPTO data, plus FreePatentsOnline US2007/0124010 and the Veriforia record). I'll flag clearly where a conclusion rests on the citation record rather than full-text reading.
Prior-Art Analysis — US Patent No. 7,177,716 B2
1. Identification / verification
- US 7,177,716 B2 — "Methods and apparatus for material control system interface"; Appl. No. 11/067,311; filed 2005‑02‑25; priority 2004‑02‑28 (provisional 60/548,588); granted 2007‑02‑13; assignee Applied Materials, Inc.; inventors Duffin, Jessop, Teferra, Puri, Warner. Legal status: Expired – Fee Related (anticipated expiration 2025‑02‑25).
- The USPTO-mirrored Google Patents record lists 66 cited references ("Citations (66)"), of which some are flagged with an asterisk = "cited by examiner" (as opposed to "cited by third party"). In the record retrieved, the examiner-flagged items are US 3,952,388 A, US 5,696,689 A, and US 6,839,603 B2.
- Note a classification discrepancy worth flagging: Veriforia's record gives International Classification G06F 19/00 / B65H 1/00 and USPC classes 700/112, 700/101, 700/115, 700/121, 700/228, 414/222.01, whereas Google Patents lists modern CPC G05B 19/418 and G06Q 10/06. Both are consistent with "total factory control / material transport."
Critical framing for § 102. Anticipation under 35 U.S.C. § 102 requires a single reference disclosing every limitation. The independent claims 1/7/13 share four steps: (a) determine a number of priority lots, including receiving a signal representative of that number; (b) reserve carrier storage locations at a substrate loading station, the count based on the number of priority lots; (c) make the reserved locations available; (d) transfer priority lots into the reserved locations. Because the patent issued over all 66 cited references, the examiner necessarily did not find any of them to anticipate the allowed independent claims. Therefore every § 102 "anticipation" below is a hypothesis to be tested against full text, not a conclusion — and the more realistic role of most of these references is § 103 obviousness, not § 102 anticipation. I have not read the full specification of each reference, so element-by-element anticipation cannot be confirmed here.
2. The 66 cited references (citation record)
2a. Pre‑1990 foundational / apparatus art (background)
| # | Citation | Date (pub) | Assignee | Title / substance |
|---|---|---|---|---|
| 1 | US 3,845,286 A | 1974‑10‑29 | IBM | Manufacturing control system for processing workpieces — early fab-wide control. |
| 2 | US 3,952,388 A * | 1976‑04‑27 | Toyoda Koki | Machine tool apparatus — examiner-cited; automated machine/part handling. |
| 3 | US 4,027,246 A | 1977‑05‑31 | IBM | Automated integrated circuit manufacturing system. |
| 4 | US 4,166,527 A | 1979‑09‑04 | Stelron Cam | Pick-and-place onto moving conveyors/assembly lines. |
| 5 | JP S55‑91839 A | 1980‑07‑11 | Seiko Epson | Production of electronic parts. |
| 6 | JP S58‑28860 A | 1983‑02‑19 | NEC | Semiconductor device/manufacture. |
| 7 | JP S60‑49623 A | 1985‑03‑18 | NEC Kansai | Manufacture of semiconductor device. |
| 8 | JP S63‑234511 A | 1988‑09‑29 | NEC Kyushu | Semiconductor substrate treatment device. |
| 9 | JP H01‑181156 A | 1989‑07‑19 | NEC | Parts control system. |
2b. 1988–1999 dispatch, wafer handling, carrier/store art
| # | Citation | Date (pub) | Assignee | Title / substance |
|---|---|---|---|---|
| 10 | JP H01‑257549 A | 1989‑10‑13 | Hitachi Seiki | Production line information managing method. |
| 11 | JP H02‑15647 A | 1990‑01‑19 | Mitsubishi Electric | Semiconductor manufacturing apparatus. |
| 12 | EP 0 365 589 B1 | 1992‑09‑23 | Hine Design | Aligning silicon wafers. |
| 13 | US 5,183,378 A | 1993‑02‑02 | Tokyo Electron Sagami | Wafer counter with aligning device. |
| 14 | JP H05‑128131 A | 1993‑05‑25 | NEC | Subcontractor control system. |
| 15 | US 5,256,204 A | 1993‑10‑26 | United Microelectronics | Single semiconductor wafer transfer method & manufacturing system. |
| 16 | JP H05‑290053 A | 1993‑11‑05 | Toshiba | Information-flow method in small-scale/many-kind production management. |
| 17 | JP H06‑132696 A | 1994‑05‑13 | Tokico | Substrate transfer device. |
| 18 | JP H06‑260545 A | 1994‑09‑16 | Mitsubishi Materials Silicon | Semiconductor wafer production management system. |
| 19 | US 5,382,127 A | 1995‑01‑17 | IBM | Pressurized interface for wafer transfer. |
| 20 | US 5,388,945 A | 1995‑02‑14 | IBM | Fully automated conveyor-based manufacturing line. |
| 21 | US 5,390,785 A | 1995‑02‑21 | IBM | Pressurized sealable transportable containers. |
| 22 | US 5,411,358 A | 1995‑05‑02 | IBM | Dispatching apparatus with gas-supply distribution for storing containers. |
| 23 | EP 0 663 686 A1 | 1995‑07‑19 | IBM | Automatic assembler/disassembler for pressurized containers. |
| 24 | US 5,544,350 A | 1996‑08‑06 | TSMC | Ratio of running work in progress (WIP management). |
| 25 | JP H08‑249044 A | 1996‑09‑27 | Nippondenso | Production controller. |
| 26 | US 5,612,886 A | 1997‑03‑18 | TSMC | Method and system for dynamic dispatching in semiconductor manufacturing plants. |
| 27 | JP H09‑115817 A | 1997‑05‑02 | Nikon | Exposure method/apparatus. |
| 28 | US 5,668,056 A | 1997‑09‑16 | United Microelectronics | Single wafer transfer method & manufacturing system. |
| 29 | US 5,696,689 A * | 1997‑12‑09 | Nippondenso | Dispatch and conveyer control system for a production control system of a semiconductor substrate — examiner-cited. |
| 30 | JP H10‑135096 A | 1998‑05‑22 | Nittetsu Semiconductor | Scheduling method in semiconductor manufacture. |
| 31 | EP 0 850 720 A1 | 1998‑07‑01 | Datalogic | Manufacturing process for an article. |
| 32 | US 5,811,211 A | 1998‑09‑22 | Nikon | Peripheral edge exposure method. |
| 33 | US 5,818,716 A | 1998‑10‑06 | TSMC | Dynamic lot dispatching / required turn-rate factory control. |
| 34 | US 5,825,650 A | 1998‑10‑20 | TSMC | Determining standard cycle time of a stage dynamically. |
| 35 | DE 197 15 974 A1 | 1998‑10‑22 | Merck Patent | Chemical supply system. |
| 36 | US 5,884,392 A | 1999‑03‑23 | IBM | Automatic assembler/disassembler for pressurized containers. |
| 37 | US 5,888,042 A | 1999‑03‑30 | Nidek | Semiconductor wafer transporter. |
| 38 | JP H11‑176717 A | 1999‑07‑02 | Sony | Semiconductor device production/management method. |
| 39 | US 5,957,648 A | 1999‑09‑28 | Applied Materials | Factory automation apparatus for handling/moving/storing wafer carriers. |
| 40 | US 5,971,585 A | 1999‑10‑26 | IBM | Best-can-do matching of assets with demand in microelectronics manufacturing. |
| 41 | JP H11‑296208 A | 1999‑10‑29 | Oki Electric | Production management information output device. |
2c. 2000–2005 MCS/MES, transport, stocker art (most relevant window)
| # | Citation | Date (pub) | Assignee | Title / substance |
|---|---|---|---|---|
| 42 | JP 2000‑012646 A | 2000‑01‑14 | Incam Solutions | Adapter for carrier pod. |
| 43 | US 6,048,259 A | 2000‑04‑11 | Speedfam | Wafer loading/unloading mechanism for load robot. |
| 44 | US 6,050,768 A | 2000‑04‑18 | Mitsubishi Denki | Automatic carrier control method in wafer cassette transport apparatus. |
| 45 | US 6,053,688 A | 2000‑04‑25 | Cheng, David | Loading/unloading wafers from a wafer carrier. |
| 46 | US 6,082,948 A | 2000‑07‑04 | Applied Materials | Controlled environment enclosure / mechanical interface. |
| 47 | US 6,128,588 A | 2000‑10‑03 | Sony | Integrated wafer-fab time-standard (machine tact) database. |
| 48 | US 6,196,001 B1 | 2001‑03‑06 | AlliedSignal | Environment-controlled WIP cart. |
| 49 | US 6,240,335 B1 | 2001‑05‑29 | Palo Alto Technologies | Distributed control-system architecture and method for a material transport system. |
| 50 | EP 1 128 246 A2 | 2001‑08‑29 | Canon | Push-type scheduling for semiconductor fabrication. |
| 51 | US 6,415,260 B1 | 2002‑07‑02 | TSMC | Dynamic capacity-demand forecast system. |
| 52 | US 2002/0094588 A1 | 2002‑07‑18 | United Microelectronics | Method of control management of a production line. |
| 53 | US 6,431,814 B1 | 2002‑08‑13 | Advanced Micro Devices | Integrated wafer stocker & sorter with integrity verification. |
| 54 | US 2002/0116086 A1 | 2002‑08‑22 | Ronald Huber | Installation for processing wafers. |
| 55 | US 2002/0144654 A1 | 2002‑10‑10 | Jürgen Elger | Installation for processing wafers. |
| 56 | JP 2003‑007584 A | 2003‑01‑10 | Hitachi | Semiconductor device manufacturing method and system. |
| 57 | US 6,540,466 B2 | 2003‑04‑01 | Applied Materials | Compact apparatus for storing/loading wafer carriers. |
| 58 | US 2003/0108407 A1 | 2003‑06‑12 | Mitsubishi Denki | Interbay transportation system and method. |
| 59 | US 6,587,744 B1 | 2003‑07‑01 | Brooks Automation | Run-to-run controller for microelectronic fabrication. |
| 60 | US 6,662,076 B1 | 2003‑12‑09 | Advanced Micro Devices | Management of move requests from a factory system to an automated material handling system. |
| 61 | US 6,673,638 B1 | 2004‑01‑06 | KLA-Tencor | Production of process-sensitive lithographic features. |
| 62 | US 6,684,124 B2 | 2004‑01‑27 | Infineon Technologies | Controlling a processing device for sequential processing of wafers. |
| 63 | US 2004/0049398 A1 | 2004‑03‑11 | IBM | Resolving transport errors in automated material handling system transactions. |
| 64 | US 2004/0062633 A1 | 2004‑04‑01 | Applied Materials | System for transporting substrate carriers (the '310 family — incorporated by reference). |
| 65 | US 2004/0187342 A1 | 2004‑09‑30 | Dainippon Screen | Substrate treating method and apparatus. |
| 66 | US 6,839,603 B2 * | 2005‑01‑04 | Tokyo Electron | Semiconductor manufacturing system and control method thereof — examiner-cited. |
Also relevant but appearing under "Family Cites Families (70)," not the direct 66-citation list (so they are prior art cited in sibling/family members rather than against '716's own claims): US 5,928,389 A (Applied Materials — "priority based scheduling of wafer processing within a multiple-chamber tool," filed 1996‑10‑21, pub 1999‑07‑27); US 5,442,561 A (Nippon Telegraph & Telephone — production management system; examiner-flagged in the family record); US 5,751,581 A (AMD — material movement server); US 5,570,990 A (Asyst — human-guided mobile loader stocker); US 6,009,890 A (Tokyo Electron — substrate transporting/processing system).
3. § 102 anticipation assessment — closest references
For each, "claims potentially anticipated" means a hypothesis requiring full-text confirmation; all are more safely characterized as § 103 references given that the claims issued.
| Reference | Full citation | Date | What it discloses (per record) | Claims asserted as potentially anticipated (§ 102) | Why / why not |
|---|---|---|---|---|---|
| US 5,696,689 A (examiner-cited) | Nippondenso Co., Ltd., "Dispatch and conveyer control system for a production control system of a semiconductor substrate" | filed 1994‑11‑25; pub 1997‑12‑09 | Integrated dispatch + conveyor control for a semiconductor production system — i.e., an automated material-handling control layer that decides where lots go and drives the conveyor. | 1, 7, 13 (best candidate) | Closest single-reference candidate because it combines lot dispatching with conveyor/transport control — the two pillars of claims 1/7/13. But anticipation requires the same reference to also disclose reserving storage locations at a loading station, count based on the priority-lot number, and the "receive a signal representative of the number of priority lots" limitation. Not confirmable from the record; likely fails the storage-reservation and signal-receiving limitations. |
| US 6,839,603 B2 (examiner-cited) | Tokyo Electron Ltd., "Semiconductor manufacturing system and control method thereof" | filed 2000‑05‑09; pub 2005‑01‑04 | Fab-level manufacturing system/control method (system architecture) — potentially the MES/controller-plus-transport architecture of claim 13. | 13 (and 1/7 if it recites station-level storage) | Candidate for the claim‑13 "manufacturing execution system + transport between loading stations" architecture. Unlikely to disclose priority-lot reservation specifically. |
| US 6,662,076 B1 | Advanced Micro Devices, "Management of move requests from a factory system to an automated material handling system" | filed 1999‑02‑10; pub 2003‑12‑09 | Handling/tracking move requests (MIR/MOR-type messaging) between the factory system and the AMHS/MCS. | 1, 13 (partial) | Directly addresses the MES→MCS command interface that underpins the claims, but appears to concern move-request management generally, not priority-lot storage reservation. Likely a § 103 reference, not anticipation. |
| US 5,612,886 A | TSMC, "Method and system for dynamic dispatching in semiconductor manufacturing plants" | filed 1995‑05‑12; pub 1997‑03‑18 | Dynamic dispatching of lots, including priority handling. | 1 (element (a) only) | Discloses determining/dispatching priority lots (element a), but a single-element disclosure cannot anticipate a full claim. § 103 candidate for the "priority" concept. |
| US 5,818,716 A | TSMC, "Dynamic lot dispatching required turn-rate factory control system" | filed 1996‑10‑18; pub 1998‑10‑06 | Dispatch keyed to required turn rate / priority. | 1 (element (a) only) | Same limitation as above. |
| US 6,240,335 B1 | Palo Alto Technologies (Asyst), "Distributed control system architecture and method for a material transport system" | filed 1998‑12‑14; pub 2001‑05‑29 | Multi-PLC distributed control for conveying pods between/within bays; scheduling/anti-collision. | 13 (architecture only) | The distributed transport-control architecture overlaps claim 13's "transport system … between loading stations," but no priority-lot storage reservation. |
| EP 1 128 246 A2 | Canon K.K., "Push-type scheduling for semiconductor fabrication" | filed 2000‑02‑28; pub 2001‑08‑29 | Push-mode scheduling of lots to tools. | 1 (elements a/b context) | Scheduling-oriented; may touch priority ordering but not storage reservation. § 103. |
| US 5,544,350 A | TSMC, "Ratio of running work in progress" | filed 1994‑07‑05; pub 1996‑08‑06 | WIP-level control — determine how much work (incl. priority) is in process. | — (background) | Supports only the "determine number of lots" context; no storage reservation. |
| US 6,128,588 A | Sony, "Integrated wafer-fab time-standard (machine tact) database" | filed 1997‑10‑01; pub 2000‑10‑03 | Fab scheduling database. | — (background) | Scheduling data model only. |
| US 5,971,585 A | IBM, "Best-can-do matching of assets with demand in microelectronics manufacturing" | filed 1997‑09‑09; pub 1999‑10‑26 | Matching fab assets to demand (capacity allocation). | — (background) | Planning-level, not station storage reservation. |
| US 6,415,260 B1 | TSMC, "Dynamic capacity demand forecast system" | filed 1999‑04‑21; pub 2002‑07‑02 | Capacity forecasting. | — (background) | Planning-level. |
| US 2004/0049398 A1 | IBM, "Resolving transport errors relating to automated material handling system transactions" | pub 2004‑03‑11 | AMHS transaction error handling. | — (background) | Error-recovery, not reservation. |
| US 6,050,768 A | Mitsubishi Denki, "Automatic carrier control method in wafer cassette transportation apparatus" | filed 1997‑08‑08; pub 2000‑04‑18 | Carrier transport control. | — (background) | Apparatus-level transport control. |
| US 2003/0108407 A1 | Mitsubishi Denki, "Interbay transportation system and method" | filed 2001‑10‑18; pub 2003‑06‑12 | Interbay transport. | — (background) | Transport routing. |
| US 6,431,814 B1 | AMD, "Integrated wafer stocker and sorter with integrity verification" | filed 2000‑02‑02; pub 2002‑08‑13 | Stocker + sorter integration. | — (background) | Storage hardware, not priority reservation. |
| US 6,196,001 B1 | AlliedSignal, "Environment-controlled WIP cart" | filed 1999‑10‑12; pub 2001‑03‑06 | WIP transport cart. | — (background) | Hardware only. |
| US 6,540,466 B2 / US 6,082,948 A | Applied Materials — compact wafer-carrier storer/loader ('466); controlled-environment enclosure ('948) | 2003‑04‑01 / 2000‑07‑04 | Carrier storage/loading hardware; enclosure interface. | — (background) | Structural/hardware antecedents (loading-station storage locations), not the claimed priority-reservation logic. |
| US 5,957,648 A | Applied Materials, "Factory automation apparatus…for handling, moving and storing wafer carriers" | filed 1996‑12‑11; pub 1999‑09‑28 | Fab automation for carrier handling/movement/storage. | — (background) | Same family as '466; hardware/automation antecedent. |
| US 2004/0062633 A1 | Applied Materials, "System for transporting substrate carriers" | pub 2004‑04‑01 | The conveyor/transport system incorporated by reference into '716 (app. 10/650,310). | — (anticipation of 1/7/13 ruled out) | This is prior art and incorporated by reference — i.e., it belongs to the same family. Being commonly assigned and incorporated, it cannot anticipate the claims that build on it; it supplies the conveyor environment. |
4. Which references are the "most relevant"
Ranked, on the record available:
- US 5,696,689 A (Nippondenso, examiner-cited) — the single best § 102 candidate for claims 1/7/13, because it couples lot dispatch with conveyor control in a semiconductor production system. The gap to close is whether it reserves station storage locations for priority lots based on a received count signal.
- US 6,839,603 B2 (Tokyo Electron, examiner-cited) — best candidate for the claim‑13 system (MES/control + stations + transport) and possibly claim‑1 method.
- US 6,662,076 B1 (AMD) — closest to the MES→AMHS move-request interface, which is the substrate for the "receive a signal" limitation; but generally a § 103 reference.
- US 5,612,886 A / US 5,818,716 A (TSMC) — strongest on the "priority lot" concept (element a), § 103.
- US 3,952,388 A (Toyoda Koki, examiner-cited) — examiner-cited but early machine-tool apparatus; likely cited for general automated material-handling context, weak on all four claim steps.
Everything else in the 66 (wafer alignment, pod adapters, enclosures, exposure, chemical supply, loaders, forecasters, error-handling, etc.) is background/field art with no plausible § 102 anticipation of claims 1/7/13 — consistent with the fact that the examiner allowed the claims over them.
5. Explicit uncertainty flags
- § 102 vs § 103: No reference in this record is identified as having anticipated the allowed independent claims; the patent issued. Treat the mappings above as hypotheses / § 103 candidates, not established anticipations.
- Title-level analysis: I could not read the full text of each of the 66 references within my tool budget. Anticipation cannot be established from titles/abstracts alone; the "potentially anticipates" columns state the element(s) each reference plausibly touches, not proven hits.
- Examiner-citation flags: The asterisks indicating "cited by examiner" (US 3,952,388 A, US 5,696,689 A, US 6,839,603 B2) are taken from the Google Patents rendering of the USPTO record; Google's asterisk conventions are not always consistent, so I present them as indicative, not authoritative.
- Do-not-conflate: A separate European search report (EP 1 803 839 A1, search completed 2007‑03‑12) surfaced with X‑category citations to US 5,915,194 A (Powell), US 6,488,771 B1 (Powell), US 4,144,116 A (Jacob) and US 6,086,673 A (Molnar) against its claims 1 and 3. I could not confirm that EP 1 803 839 A1 belongs to the '716 family (the '716 family members are KR 20060043261A, CN 100426452C, TW I316044B, plus US continuations 7,603,196 and 7,522,969). Its cited art is directed to wafer alignment/handling, not priority-lot storage reservation. I have not treated these as '716 prior art — flagging only to avoid a false match.
- Non-patent art: The patent incorporates by reference four SEMI standards — E88‑1103 (Stocker SEM), E82‑0703 (IBSEM), E84‑0703 (Enhanced Carrier Handoff Parallel I/O), E87‑0703 (Carrier Management). These are incorporated into the patent as implementation context; they are not in the 66-item citation list and are not asserted here as § 102 references.
- Litigation/CAFC: Per the previously generated sections, no litigation, IPR/PTAB, or 2026 CAFC docket involving 7,177,716 was located; this does not affect the prior-art analysis but means no third-party validity challenge record exists to mine for additional art.
Primary sources used: Google Patents US7177716B2 (citation record) — https://patents.google.com/patent/US7177716/en ; FreePatentsOnline US2007/0124010 — https://www.freepatentsonline.com/y2007/0124010.html ; Veriforia inventor/patent record — https://veriforia.com/view/Daniel-Jessop-AfFuALCC ; Google Patents US6240335B1 and US5928389 (for cross-checking two cited references) — https://patents.google.com/patent/US6240335B1/en and https://patents.google.com/patent/US5928389.
Generated 9/30/2026, 11:32:11 AM
Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
Obviousness Analysis — US 7,177,716 B2 under 35 U.S.C. § 103
Builds on the earlier summary and litigation sections; does not repeat bibliographic data. Note one framing point up front: the patent is Expired – Fee Related (anticipated expiration 2025‑02‑25). A § 103 analysis is therefore useful only retrospectively (e.g., validity counterclaims in actions filed before expiry, collateral estoppel, defensive publication, or a hypothetical reexam) — but the legal analysis below is the same either way.
I. Analytical framework applied
I apply the Graham v. John Deere factors as refined by KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007):
- A combination of familiar elements according to known methods is likely obvious when it yields only predictable results (KSR, slip op. at 12–13).
- "Any need or problem known in the field of endeavor at the time of invention and addressed by the patent can provide a reason for combining the elements in the manner claimed." (KSR, slip op. at 15; MPEP 2144.01).
- Design incentives and market forces (here: reducing WIP dwell time, meeting "move in request" deadlines for hot lots) can prompt the variation (KSR, slip op. at 15–17).
The examiner cited 66 references (from US 3,845,286 (1974) forward) — a 30‑year-deep record showing that essentially every sub‑element of the claims was known in semiconductor fab automation well before the 2004 priority date.
II. Element decomposition of the independent claims
Claims 1, 7 and 13 share a four‑step core. For § 103 purposes the limitations break down as:
| # | Limitation | Functional category |
|---|---|---|
| L1 | Determine number of priority lots to be processed, including receiving a signal representative of the number | Lot prioritization / host–equipment signaling |
| L2 | Reserve a number of carrier storage locations at a substrate loading station, count based on the priority‑lot number | Buffer-resource allocation at the load‑port |
| L3 | Make the reserved locations available | Eviction-by-processing or eviction-by-transfer |
| L4 | Transfer the priority lots into the reserved locations | AMHS routing / move execution |
| L5 (cl. 13 only) | First + second loading stations, each with a tool and multiple storage locations; transport system; MES orchestrating L1–L4 | Distributed MCS/MES architecture |
The applicant's own specification supplies admissions usable as prior art under MPEP 2129:
- Conventional Fab operation with stockers, MIR/MOR messaging, and MES lot selection (Background/Process Descriptions).
- "buffer stockers may be used by the MCS and/or substrate loading station as an alternate storage location" and "the MCS may include a list of alternate storage locations."
- Conformance to SEMI E88‑1103, E82‑0703, E84‑0703, E87‑0703 — i.e., standardized host/equipment interfaces and Carrier Management (CMS) were admitted to exist. Signaling a host with lot/carrier parameters is therefore admitted art.
Consequently, the only arguably novel concept is L2's reservation of a count of internal buffer locations tied to a priority‑lot count — and even that is a resource‑allocation step that scheduling/AMHS art had long approximated (capacity, priority, move‑request management).
III. Prior-art landscape from the cited record (by function)
| Function / element | Cited reference (from the page's Citations list) |
|---|---|
| Priority-based scheduling of lots | US 5,928,389 A (Applied Materials — Method and apparatus for priority based scheduling of wafer processing within a multiple chamber semiconductor wafer processing tool); US 5,612,886 A (TSMC — dynamic dispatching); US 5,818,716 A (TSMC — dynamic lot dispatching required turn rate); US 5,544,350 A (TSMC — Ratio of running work in progress); EP 1 128 246 A2 (Canon — Push-type scheduling for semiconductor fabrication) |
| Internal/buffer carrier storage at a tool load station | US 6,540,466 B2 (Applied Materials — Compact apparatus and method for storing and loading semiconductor wafer carriers); US 5,957,648 A (Applied Materials — Factory automation apparatus… handling, moving and storing semiconductor wafer carriers); US 6,431,814 B1 (AMD — Integrated wafer stocker and sorter) |
| MES→AMHS move-request / capacity handling, incl. redirecting to alternate storage | US 6,662,076 B1 (AMD — Management of move requests from a factory system to an automated material handling system); US 5,971,585 A (IBM — Best can do matching of assets with demand); US 2004/0049398 A1 (IBM — resolving transport errors relating to AMHS transactions) |
| Distributed control of material transport (MCS/MES architecture) | US 6,240,335 B1 (Palo Alto Technologies — Distributed control system architecture and method for a material transport system); US 5,751,581 A (AMD — Material movement server); US 6,839,603 B2 (Tokyo Electron — Semiconductor manufacturing system and control method) |
| Conveyor-based carrier transport / staged carriers | US 6,082,948 A (Applied Materials); US 2004/0062633 A1 (Applied Materials — System for transporting substrate carriers); US 6,050,768 A (Mitsubishi Denki — automatic carrier control) |
| Production-management signaling & push flows | JPH08249044 A (Nippondenso — production controller); US 5,696,689 A / US 5,569,689 A (Nippondenso — dispatch and conveyor control); US 2002/0094588 A1 (UMC — control management of production line); US 5,442,561 A (NTT — production management system) |
No single one of these appears to disclose all of L1–L5. That is the § 103 posture: the claims are a combination of known expedite-scheduling, known buffer storage, and known move-request handling.
(Reference URLs are constructible from the IDs: e.g., https://patents.google.com/patent/[US5928389A](/patent/US5928389A)/en ; https://patents.google.com/patent/[US6662076B1](/patent/US6662076B1)/en ; https://patents.google.com/patent/[US6540466B2](/patent/US6540466B2)/en ; https://patents.google.com/patent/[US6240335B1](/patent/US6240335B1)/en . See caveat in § VII.)
IV. Primary § 103 combinations
Combination A — "Priority scheduling + load-port buffer + move-request capacity management" (renders claims 1, 7, 13 obvious)
References: US 5,928,389 (Applied Materials) as primary + US 6,540,466 (Applied Materials) + US 6,662,076 (AMD); optionally US 6,240,335 (Palo Alto Technologies).
| Limitation | Disclosure / reasoning |
|---|---|
| L1 – determine priority-lot count; receive representative signal | US 5,928,389 discloses priority-based scheduling in which a priority designation for a lot is an input to the scheduler — i.e., a received signal. US 6,662,076 discloses the MES/MCS move-request message interface (a received signal) and US 5,818,716/US 5,612,886 disclose dispatching based on received priority/turn-rate data. The specification's own SEMI‑standard admissions confirm such signals were conventional. |
| L2 – reserve N load-port storage locations, N based on priority-lot count | US 6,540,466 teaches internal storage locations at a tool's carrier loading station and their allocation. Given L1, dedicating N of those locations to the N priority lots is a predictable allocation of a known resource to a known purpose (KSR). US 6,662,076's capacity logic (select an available storage destination, else redirect) is the mirror image of denying non-priority lots access to certain locations. |
| L3 – make reserved locations available | Two alternative mechanisms, both conventional: (i) process-and-advance — the normal, described operation of a processing tool (US 5,928,389; US 6,839,603); (ii) eviction to alternate storage — expressly admitted as known in the specification ("alternate storage locations," "buffer stockers," "list of alternate storage locations") and taught by US 6,662,076's fallback-destination handling. |
| L4 – transfer priority lots into reserved locations | Routine AMHS routing via move requests: US 6,662,076; US 6,240,335; US 6,082,948 / US 2004/0062633. |
| L5 (claim 13) – two stations + transport + MES | US 6,240,335 (distributed MCS/MES control of a material transport system) + US 5,957,648 / US 6,540,466 (multiple tool load stations) + US 2004/0062633 (transport system). |
Motivation to combine (articulated, KSR‑compliant):
The field's express objective was reducing WIP dwell time (stated in this patent's own Background, and the rationale behind the cited conveyor references). A hot lot that cannot be staged inside the load‑port buffer cannot be processed the moment the tool issues its MIR; it waits elsewhere. The known expedite tools (priority scheduling, US 5,928,389) and known staging tools (load‑port buffers, US 6,540,466) were each addressing that same problem. A POSITA, faced with a near‑capacity buffer, would predictably combine "expedite the lot" with "hold a slot for it" — the claimed result (priority lots are present when the tool is ready) is exactly the expected result of the combination, not a new function. That is the KSR paradigm.
Combination B — "Push scheduling + stocker/sorter + AMHS" (alternative rendering of claims 1 and 13)
References: EP 1 128 246 A2 (Canon, push‑type scheduling) + US 6,431,814 (AMD, integrated stocker/sorter) + US 6,240,335 + US 6,662,076.
Canon's push‑type scheduling supplies L1 (the fab pushes designated lots to tools rather than waiting for pull), AMD's stocker/sorter supplies the physical storage‑location inventory and integrity tracking for L2/L4, and Palo Alto Technologies/US 6,662,076 supply the distributed control and move‑request signaling. The combination yields the same four‑step method. Motivation: push scheduling exists precisely to get lots to the right tool ahead of the MIR; reserving buffer space to receive them is the necessary and obvious companion step.
Combination C — for the "evict / block non‑priority carriers" and "process‑then‑advance" dependent claims (5, 17 and 3–4, 15–16)
- Claim 5 / 17 (relocate occupying carriers to alternate storage; block arriving non‑priority carriers): US 6,662,076 (alternate‑destination selection when primary storage is unavailable) + US 6,431,814 (stocker as alternate store) + the specification's admitted "list of alternate storage locations." Blocking non‑priority carriers from specific locations follows directly from designating those locations reserved.
- Claims 3–4 / 15–16 (process the occupying non‑priority lots, then advance them to the next tool's storage): this is the ordinary processing flow of US 5,928,389 / US 6,839,603 plus routine AMHS advancement (US 6,662,076, US 6,240,335).
- Claims 2, 8, 14 (reserve "enough" locations): inherent in "based on the number of priority lots."
- Claims 6, 12, 18 (transfer only priority lots as locations free up): the logical consequence of reservation; nothing more is claimed.
V. Anticipated rebuttals and why they likely fail
- "Reservation is not taught." Reservation is a species of the capacity‑allocation and alternate‑destination logic in US 6,662,076 and the priority handling of US 5,928,389; § 103 reaches obvious species of a disclosed genus (In re Petering; MPEP 2144.04). Dedication of a subset of buffers is a predictable variation, especially where the specification concedes that buffer locations are already allocated by the MCS.
- "Non‑analogous art." All references are in semiconductor fab automation/AMHS/MES — the same field of endeavor, and reasonably pertinent to the problem (In re Bigio; KSR).
- "No motivation." The patent's own Background supplies it (reduce WIP/dwell time; expedite lots), as does the conventional MIR/MOR flow it describes.
- "Receiving a signal" is a limitation added later. Whatever its prosecution history, the limitation is met by any operator‑entered hot‑lot count or any MES/MCS message — the very interfaces the specification concedes via the SEMI standards. Under KSR, "a parameter input via a known interface" adds nothing patentable.
- Secondary considerations. None appear available: the patent lapsed for failure to pay maintenance fees, which undercuts any nexus‑based argument that the claimed reservation method drove commercial success. No unexpected results are disclosed, and the specification's result (priority lots available at MIR time) is precisely the predicted one (In re Soni).
VI. Honest uncertainty flags
- I am working from the reference titles and dates on the Google Patents "Citations" list, not their full texts. My element‑by‑element mapping is a well‑grounded hypothesis, not a confirmed disclosure-by-disclosure comparison. A formal § 103 chart requires pulling the specification of each primary reference (especially US 5,928,389, US 6,662,076, US 6,540,466, US 6,240,335) and confirming the specific passages.
- The page's "Family Cites Families (70)" list is truncated in the supplied text (cuts off at US 5,980,183 / Asyst). Additional references cited only in the continuations US 7,603,196 and US 7,522,969 may exist and could strengthen or alter the combinations.
- The examiner apparently did not reject these claims under § 103 over the cited art as issued — so this analysis is a post‑hoc invalidity theory, and the burden/standard (clear and convincing evidence, presumption of validity under § 282) would apply in litigation.
- Whether US 5,928,389's priority handling rises to a "signal representative of the number of priority lots" (as opposed to a per‑lot priority flag) is the pivotal factual question; if it does not, US 6,662,076's move‑request/capacity messages or the specification's admitted MES signaling would be used to fill that gap.
VII. Conclusion
The cited record strongly supports a § 103 conclusion that claims 1–18 would have been obvious. Every functional element was individually known in semiconductor fab automation before February 2004 — priority scheduling (US 5,928,389; US 5,612,886; US 5,818,716; EP 1 128 246), load‑port carrier buffering (US 6,540,466; US 5,957,648), MES/AMHS move‑request and alternate‑storage handling (US 6,662,076; US 5,971,585; US 2004/0049398), and distributed transport control (US 6,240,335; US 6,839,603). The claimed advance — reserving a number of internal buffer locations keyed to a priority‑lot count and filling them with priority lots as space frees up — is the predictable union of those known techniques, motivated by the field's admitted goal of reducing WIP dwell time. Absent evidence of unexpected results or a nexus‑bearing secondary consideration, the combination would likely be held obvious. I flag that full‑text verification of the four primary references (and the truncated family‑citation list) is required before this conclusion is treated as litigation‑grade.
Generated 9/30/2026, 11:31:53 AM
Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
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Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.
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