US 6100114

I'll search for authoritative information on US 6,100,114, including any CAFC docket activity.

Let me check for any litigation or CAFC activity involving this patent specifically.

US Patent 6,100,114 — Search Results and Summary

Search scope note: I ran targeted searches on the specific number 6100114 (Google Patents, Justia, FreePatentsOnline, patentimages PDF). Separate searches for a CAFC 2026 docket tied to this patent returned no results — no Federal Circuit appeal or docket entry for US 6,100,114 was found. The only "114 / CAFC" hit was Sensonics v. Aerosonic (Fed. Cir. 1996), which concerns an unrelated patent (DeMayo '114, a vibration sensor) — I am not treating that as this patent. I likewise could not retrieve a live USPTO PatentCenter status page in these results; status below is from the patent record (Google Patents legal events), which I flag as a secondary source.

Bibliographic data

Inventor-name caveat: the Google Patents bibliographic list reads "Mark V. Pierson," while the assignment record in the legal events reads "PIERSON, MARK S." I am reporting both literally rather than auto-correcting either.

Abstract (as issued)

"Solder bumps on electronic components are encapsulated before attachment to a substrate or component carrier. A film of sealing material is pressed against top portions of the solder bumps by pressing with a layer of low durometer flexible material. Encapsulant is positioned between the component and the film and in contact with the bumps, and partially cured. The film and layer of flexible material are removed to expose the top portions of the encapsulated solder bumps."

Key classification areas

H10W72/00 and H10W74/00 families (interconnections/encapsulations): e.g., H10W74/012 — manufacture of underfills on active surfaces of flip-chip devices; H10W72/012 — manufacture of bump connectors; H10W74/15 — underfill disposition.

Plain-language overview of the independent claims

Claim 1 — "Method of at least partially encapsulating a plurality of solder bumps on a semiconductor chip"

1. Provide a semiconductor chip with solder bumps, each having a top portion.
2. Position a film of sealing material next to the bumps.
3. Position a layer of low-durometer flexible material next to the film.
4. Press the flexible layer and film so the film contacts the tops of the bumps (the compliant layer conforms to bump-height/shape variation, sealing the bump tops).
5. Put encapsulant between the chip and the film, in contact with the bumps (but not the bump tops).
6. At least partially cure the encapsulant.
7. Remove the flexible layer and film to expose the bump tops.

Essence: a "pre-applied" or pre-bond underfill — the encapsulant is applied at the component level (potentially by the component supplier), using a sacrificial sealed film and a soft backing to keep the bump tips clean for later soldering.

Claim 11 — "Method of at least partially encapsulating a plurality of solder connections"
Carries over steps (1)–(7) of claim 1, and then adds:
8. Provide a circuitized substrate.
9. Bring the exposed bump tops into contact with the substrate and heat the bumps and encapsulant to form/encapsulate the solder connections between chip and substrate.

Essence: the same pre-applied encapsulation, plus the downstream assembly step — reflowing the chip onto a board to complete and encapsulate the joints.

Dependent claims (brief)

• 2: chip provided in wafer form (batch processing before dicing).
• 3: sealing film is Kapton or Teflon.
• 4: flexible layer is silicone.
• 5–7: encapsulant applied in liquid form, by injection, optionally under vacuum.
• 8: curing by heating.
• 9: after partial cure, slightly retract the film (keeping tip contact) and inject a thermoplastic adhesive between encapsulant and film.
• 10: film removed by peeling.
• 12: bumps are substantially spherical.
• 13: add an edge sealant around the chip perimeter.
• 14: add an overmold over the chip.

Cited prior art (examiner-cited, 6 references)

US 5,363,277 (Rohm — Tanaka); US 5,663,106 and US 5,776,796 (Tessera); US 5,714,252 (Minnesota Mining & Mfg. — Hogerton); US 5,661,088 (Motorola — Tessier); US 5,704,116 (Motorola). Non-patent literature: SMT Magazine, Feb. 1998; Gamota & Melton, IEEE Trans. CPMT Part C, Jan. 1998; McGovern et al., Electronic Packaging & Production, Feb. 1998.

Uncertainties / caveats

• No CAFC 2026 docket activity found for 6100114 — based on negative search results, not proof of absence from every docket system. Treat as "none found."
• I could not open a live USPTO PatentCenter page for application 09/132,127; the expiration/lapse details come from the Google Patents legal-events table.
• The full text supplied contains OCR artifacts (e.g., "there is provided an encapsulation method…" and "pressing the laser of flexible material"), which I have not corrected in substance; the claim text itself reads "pressing said layer of flexible material."
• Note also the spec's own inconsistency: "Son K. Tran" vs. the assignment record "TRAN, SON K." — consistent; only the Pierson middle initial differs as noted above.

I'll research litigation involving US patent 6100114. Let me run several searches.

Let me try several other searches.

Litigation Search — U.S. Patent No. 6,100,114

Bottom line: I found no evidence of any litigation involving U.S. Patent No. 6,100,114. As of the available information, this patent does not appear in any known patent infringement suit, declaratory judgment action, ITC Section 337 investigation, or Federal Circuit appeal.

What I searched

• Unified Patents litigation case list (https://portal.unifiedpatents.com/litigation/caselist), including the patent-filter URL pattern ?patents=<number>
• General web and CAFC/PACER-oriented queries for "6100114," "6,100,114," and the IBM encapsulation subject matter

None of these returned a case naming U.S. 6,100,114 as an asserted patent.

Important caveat on the hits that came back

Searches for the string "'114 patent" returned several documents that are not this patent. Per your instruction to interpret identifiers literally, I am flagging these explicitly rather than treating them as matches:

I did not find any case caption, docket number, or filing date that references the actual US 6,100,114.

Context from the patent record (relevant to enforceability)

• Patent: US 6,100,114 — "Encapsulation of solder bumps and solder connections"
• Inventors: Cynthia S. Milkovich, Mark S. Pierson (recorded as "Mark V. Pierson"/"Mark S. Pierson"), Son K. Tran
• Assignee: International Business Machines Corporation
• Filing / priority: August 10, 1998; granted: August 8, 2000
• Status: Expired – Fee Related. USPTO legal events show a maintenance-fee lapse notice (2008-08-08), "Lapse for failure to pay maintenance fees," and the 2008-09-30 entry: "PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362." Anticipated expiration would have been 2018-08-10, but the patent actually terminated in 2008 for non-payment.

This expiration history is consistent with the absence of litigation — an unenforceable, expired patent generates no damages exposure, and patent holders and NPEs have no incentive to assert it.

Conclusion

No known litigation involving US 6,100,114. The patent is IBM-owned, and it lapsed in 2008 for failure to pay maintenance fees. If you need a belt-and-suspenders confirmation, the definitive sources to check directly (I could not retrieve complete result pages for them in this session) would be:

• Unified Patents litigation portal — filter by patent number 6100114
• PACER / CourtListener RECAP docket search
• Lex Machina / Darts-ip (subscription patent-litigation databases)
• USPTO Patent Trial and Appeal Board and ITC EDIS for post-grant and Section 337 proceedings

I cannot, with high confidence, rule out a suit that exists only in a paywalled database I could not query — so I state this as "no litigation found in the sources searched" rather than an absolute negative.

I'll verify the canonical "no proceedings" signal against public sources before reporting.

Proceedings overview

Total AIA trial proceedings on file: 0 (zero). No IPRs, no PGRs, no CBMs — the USPTO ODP structured block for US 6,100,114 returns an empty proceedings list, and my independent searches (Google Patents full text, PTAB-related queries, and Federal Circuit / CourtListener queries keyed to the patent number) surfaced no PTAB proceeding and no appeal involving this patent. Because there are no proceedings, there is no breakdown by status, no institution decision, no Final Written Decision, and no claim-level outcome to report — and I will not manufacture proceeding numbers, panels, or dispositions to fill this template.

The bottom-line posture for a defendant is therefore unusual and strong, but for a different reason than the prompt's archetypes: this is not a "hardened patent that survived IPRs." It is a dead patent that nobody ever bothered to challenge at the PTAB. Two independent facts drive that:

1. The patent lapsed for nonpayment of maintenance fees in 2008 — roughly four years before the AIA trial regime even existed. Per the Google Patents legal events for US 6,100,114: the 4-year fee was paid 2003-09-25; a maintenance-fee reminder issued 2008-02-18; a "Lapse for failure to pay maintenance fees" entry is dated 2008-08-08; and a status entry dated 2008-09-30 reads "PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362," with an effective date of 2008-08-08. So the enforceable term ended in 2008, and the 20-year term from the 1998-08-10 filing date would have run out 2018-08-10 regardless.
2. AIA trials began 2012-09-16, after this patent was already lapsed. There is no commercially rational reason to file an IPR against a lapsed, non-asserted IBM packaging patent, which is the most likely explanation for the empty docket — not a merits victory by the patent owner.

I cannot render per-proceeding sections (filing dates, panels, institution decisions, FWDs, settlements, appeals) because none exist. Per the task constraint, I am not fabricating them.

Strategic summary

Claim status: all 14 claims are UNTESTED at the PTAB — but all 14 are also expired/unenforceable for failure to maintain. Claims 1–10 (the "at least partially encapsulating a plurality of solder bumps on a semiconductor chip" family) and claims 11–14 (the "encapsulating a plurality of solder connections" family, including the spherical-bump limitation of claim 12 and the edge-sealant and overmold additions of claims 13–14) were never challenged, never canceled, and never adjudicated. There is no narrowing, no surviving-claim list, and no claim-level FWD to quote — because no trial ever happened. The practical significance is that the claims died by operation of 37 CFR 1.362 in 2008, not by adjudication, so their validity was never tested; only their lifespan was.

Estoppel landscape: § 315(e)(2) estoppel attaches to no one. Because no IPR/PGR was ever instituted, no petitioner (or privy) is barred from any ground. If you are facing assertion of this patent today, the entire prior-art universe remains available to you — including the six references the examiner cited (US 5,363,277 to Tanaka; US 5,663,106 and US 5,776,796 to Tessera; US 5,714,252 to 3M; US 5,661,088 to Motorola; US 5,704,116 to Motorola) and the three non-patent citations the examiner relied on (SMT Magazine, Feb. 1998; Gamota & Melton, IEEE Trans. CPMT, Jan. 1998; McGovern et al., Electronic Packaging & Production, Feb. 1998). Any invalidity theory — § 102, § 103, or § 112 — is equally unfettered. The absence of any estoppel cuts entirely in the defendant's favor.

Pattern signals: none of the usual ones are present. There is no serial petitioner (no entity filed even once), no PTAB appeal activity by the patent owner, and no defensive-aggregator footprint (I found no Unified Patents, RPX, or similar involvement). The patent's assignee is International Business Machines Corp., the original assignee from the 1998-08-10 assignment, and the patent does not appear to have been trafficked into an NPE portfolio. This is consistent with a lapsed internal IBM packaging patent rather than a monetized asset — which is exactly why it never attracted an IPR. Note the competing signal: prolific, well-asserted patents almost always attract IPRs; a zero-IPR patent with a 2008 lapse date and no litigation footprint suggests it was never worth asserting.

Caveat on certainty. My conclusion is "no PTAB activity found," grounded in the ODP structured block plus negative search results. Two web searches on PTAB-specific queries returned empty result sets, and a CourtListener/Federal Circuit-oriented query returned only unrelated patents sharing the "'114" shorthand (e.g., US 6,772,114, US 8,386,114). I found no affirmative evidence of any district court action, ITC investigation, or ex parte reexamination either — but absence of a hit in a web search is not a negative assurance the way the ODP ingestion is. A docket check in Docket Navigator / PACER and a direct PAIR/Patent Center transaction-history pull would close that gap definitively.

Recommended next steps

• Lead with expiration, not invalidity. If a demand letter cites US 6,100,114, the dispositive response is that the patent expired for nonpayment of the 8-year maintenance fee under 37 CFR 1.362, effective 2008-08-08 (see the Google Patents legal-events table and the corresponding Patent Center transaction history). Confirm the lapse on USPTO Patent Center (https://patentcenter.uspto.gov/) and note that no petition to accept an unintentionally delayed maintenance fee payment appears to have been filed. Any accrued-damages theory is also time-barred under 35 U.S.C. § 286 (six-year lookback), which reaches back only to roughly 2020 — years after the patent's rights ended.
• There is no FWD to link, so link the sources that do exist. Rather than quoting a disposition that does not exist, cite (a) the patent's own text and claims at https://patents.google.com/patent/US6100114/en for the exact claim numbering (14 claims; independent claims 1 and 11), and (b) the PTAB E2E / ODP search at https://ptab.uspto.gov/ showing no proceeding for patent number 6100114. If you need a formal negative, a PTAB E2E "Patent Number" search export is the cleanest evidentiary artifact.
• If, notwithstanding all of the above, an assertion is live, the fallback defense is invalidity with no estoppel constraint: the six examiner-cited references plus the three NPL references are all fair game, and the file history shows the examiner never had to reach an institution-stage record. There is also no prosecution-history disclaimer or IPR-driven narrowing to limit claim construction.
• Monitor, but do not expect activity. No AIA trial can be filed against a patent that has been lapsed since 2008 in any practical sense, and the statutory term closed on 2018-08-10 in any event. The correct forecast is continued zero PTAB activity — the absence is permanent, not a gap awaiting an institution decision. There are consequently no trial-stage milestones (no institution deadline, no oral hearing, no statutory 1-year FWD deadline) to track for this patent.

One flag for the file: if your search universe includes the similarly-numbered US 6,772,114 (audio encoding — Google LLC v. Koninklijke Philips, IPR2017-xxxxx, Fed. Cir. No. 18-2213, affirmed 2019-10-23), US 8,386,114 (Valeo v. Magna, IPR2014-00222, claims held unpatentable), US 6,216,114 (Ariba v. Emptoris), or US 3,863,114 (Sensonics v. Aerosonic), those are different patents and must not be conflated with US 6,100,114. I flag this because the "'114" shorthand is a common source of misattribution in PTAB research.

I'll verify the assignment record with targeted searches before reconstructing the chain.

Inventors

Employer determination: The only hard evidence of employer is the recorded assignment itself — all three inventors are named as assignors conveying to INTERNATIONAL BUSINESS MACHINES CORPORATION (reel 009384/0330, signed 1998-08-04 through 1998-08-10). The patent is a C4/flip-chip packaging invention, and the specification cites IBM's own earlier application Ser. No. 08/939,302 (issued as US 5,888,850) as "assigned to the same assignee," which is consistent with an IBM Microelectronics packaging team. I cannot determine the specific IBM site at which these inventors worked from the record, and I will not guess it.

Flag — name discrepancy: The Google Patents inventor field renders the second inventor as "Mark V. Pierson," while both the assignment record (reel 009384/0330) and the Google Patents legal events entry read "PIERSON, MARK S." These are two different middle initials for the same person. This is most likely a rendering/transcription error in one of the two fields, but per the rule to interpret identifiers literally I am flagging it rather than silently normalizing it. The USPTO assignment cover sheet (reel 009384/0330) is the controlling record.

Unusual-pattern check: No evidence of inventors departing the assignee within 12 months of filing. Employment continuity for Milkovich, Pierson, and Tran after 1998 is not determinable from patent records, and I found no evidence of inventor-side re-assignment or inventor-retained rights. No individual inventor appears as an assignee in any record I could retrieve.

⚠️ Cross-reference note on the prior Litigation section: That section (from the earlier-generated analysis) lists the inventors as "Cynthia S. Milkovich, Mark S. Pierson (recorded as 'Mark V. Pierson'/'Mark S. Pierson'), Son K. Tran." That is not a contradiction with anything here — it correctly captured the same two-way discrepancy. Building on it rather than restating it.

Original assignee

International Business Machines Corporation ("IBM"), Armonk, New York — the assignee named on the face of the issued patent and the sole assignee in the assignment record.

• Primary line of business: Full-line information technology — hardware, software, services. In 1998 the relevant internal unit was IBM Microelectronics, which manufactured C4 flip-chip and organic chip-carrier products and was the natural home for this invention.
• Did IBM ship a product embodying the claims? Substantively yes, in the sense that matters for the NPE analysis — IBM was a volume manufacturer of C4 flip-chip packages and laminated chip carriers, and the specification's encapsulant suppliers (Loctite, Dexter/Hysol) and materials (Kapton, Teflon, GE/Dow silicones) are all commercial production materials, not laboratory curiosities. The method reads as a wafer-level/packaging-line process that IBM would practice internally or license to assembly houses. ⚠️ I could not retrieve a specific IBM product part number or datasheet tying the claim steps to a shipping SKU, so treat "shipped a product" as a substantiated-by-context inference, not a documented fact.
• Current status (as of 2026): IBM is an operating company and remains one of the largest US patent filers. It has not been in bankruptcy. It has, however, divested semiconductor manufacturing assets over time, most notably the 2015 transfer of its Microelectronics division to GlobalFoundries. That transaction is irrelevant to this patent's chain of title — see the bankruptcy/fire-sale and cascading-transfer signals below.
• Patent status: Expired – Fee Related. The 4-year maintenance fee was paid (2003-09-25); the next maintenance fee was not, producing a reminder (2008-02-18), lapse notice (2008-08-08), and the 2008-09-30 entry: "PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362." The statutory term would otherwise have run to 2018-08-10.

Assignment timeline

The Assignment Center / Google Patents legal-events record for this patent contains exactly one recorded conveyance, and it is the original inventor-to-IBM assignment. There are no post-issuance assignments, no security interests, no security-interest releases, no merger or change-of-name filings, no licenses, and no corrections.

• 1998-08-04 → 1998-08-10 (executed; signing dates 1998-08-04 to 1998-08-10) / recorded 1998-08-10 — Reel 009384/0330
  • Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS INTEREST)
  • Assignor: MILKOVICH, CYNTHIA S.; PIERSON, MARK S.; TRAN, SON K.
  • Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION (New York)
  • Correspondent: Not determinable from the sources I could retrieve. The legal-events entries exposed by Google Patents do not carry the correspondent/attorney-of-record field, and I could not pull the reel 009384/0330 cover-sheet image in this session. For context only — not verified for this reel — IBM-era recordings of this vintage were routinely filed through IBM's internal IP Law Department (Somers, New York), per a separate IBM assignment sample surfaced in search. I am explicitly declining to assert that as this patent's correspondent of record, because the one search hit containing the IBM IP Law Dept. address came back with OCR-garbled text ("IBM_2ORPORATION, IP LAW DEPT., 25A ROUTE 100") and belongs to a different patent. The recurrence signal in Section "NPE / troll-pattern signals" #3 therefore cannot be scored as present.
  • Context: Original employment/obligation-to-assign conveyance at filing — the first link in the chain of title, not a transaction. Executed within six days across the three inventors and recorded the same day the application was filed, which is IBM's standard practice of recordation contemporaneous with filing.

Post-issuance events in the record are maintenance-fee events, not transfers, and are listed here only for completeness since they bear on enforceability:

• 2003-09-25 — 4-year maintenance fee paid (FPAY, year of fee payment 4). No ownership effect.
• 2008-02-18 — Maintenance fee reminder mailed. No ownership effect.
• 2008-08-08 — Lapse for failure to pay maintenance fees. No ownership effect; rights begin to terminate.
• 2008-09-30 — Patent expired due to nonpayment of maintenance fees under 37 CFR 1.362. Recorded as "FP — Lapsed due to failure to pay maintenance fee," effective 2008-08-08. No ownership effect.

Finding: IBM is the sole owner of record from 1998-08-10 through expiration, and no third party ever appears in the chain of title. Per the instruction that this is itself a finding — it means the original assignee retained the patent, and the patent then lapsed rather than being sold.

Timeline diagram

timeline
    title Ownership of US 6100114
    1998 : Inventors assign to IBM
         : Recorded reel 009384 frame 0330
         : Application filed 1998-08-10
    2000 : Patent granted 2000-08-08
    2003 : 4 year maintenance fee paid
    2008 : 8 year fee not paid
         : Lapse notice 2008-08-08
         : Patent expired 2008-09-30

NPE / troll-pattern signals

Because the chain contains a single link — inventors → IBM — most signals are structurally impossible to trigger. I score them anyway, with the reel/frame and date citations driving each call.

1. Shell-entity transfer — NOT PRESENT. The only assignee in the record is International Business Machines Corporation (reel 009384/0330, 1998-08-10), an operating industrial company. No "IP / Holdings / Licensing / Ventures" entity ever appears. No registered-agent address, no single-purpose LLC.

2. Known asserter in the chain — NOT PRESENT. The chain is inventors → IBM → (expiration). None of Acacia, Marathon, Intellectual Ventures, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation Corp, or any Erich Spangenberg entity appears in any record associated with this patent. This is consistent with the earlier Litigation section's finding of no known suits — an asserter never acquired the patent.

3. Repeat correspondent across the chain — UNCLEAR (cannot be scored). There is only one recorded conveyance, so there is no "chain" across which a correspondent could recur. Beyond that, the correspondent field is not exposed in the legal-events data I could retrieve and I could not open the reel 009384/0330 cover sheet. I will not substitute the address of a different IBM assignment as if it were this one. Net effect: no recurrence signal, and no basis to allege one.

4. Cascading transfers — NOT PRESENT. Zero post-issuance assignments, let alone multiple chained LLC transfers in <24 months. The only date-clustered event is the original 1998-08-04 to 1998-08-10 inventor signing window, which is a single registration, not a cascade.

5. Pre-litigation transfer — NOT PRESENT. No assignment within 6 months before any suit, because (a) there are no assignments after 1998-08-10 and (b) no suit naming this patent was found in the earlier Litigation section's searches.

6. Bankruptcy fire-sale — NOT PRESENT. IBM never filed for bankruptcy, and no bankruptcy sale, trustee conveyance, or 363 sale appears in the record. Two adjacent facts are worth stating so they are not mistaken for fire-sale evidence: IBM did divest its Microelectronics division to GlobalFoundries in 2015, and IBM has been a net seller of patents generally. Neither can have carried this patent. The patent had already lapsed on 2008-08-08/2008-09-30 under 37 CFR 1.362 — roughly seven years before the GlobalFoundries transaction — so it was not an enforceable asset available for transfer, and no assignment of it to GlobalFoundries or anyone else was recorded.

7. Privateering — NOT PRESENT. No transfer to a licensing vehicle asserting on IBM's behalf, and no SEC 10-K/8-K disclosure or Patent Progress / EFF coverage linking this patent to such a program. The chain ends at IBM.

8. Defensive aggregator (anti-NPE) — NOT PRESENT. The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN; it terminates at IBM and then at expiration. It is worth noting that the patent is functionally neutralized regardless — an expired patent cannot be asserted — but that is a consequence of the 2008 fee lapse, not of any defensive-aggregation acquisition. I have no verified data on whether IBM is or was a LOT Network member, and I am not relying on any such claim here.

Composite: 0 signals present, 1 unclear (correspondent, only because the data field was unavailable and there is nothing to compare), 7 not present.

Verdict

Insufficient data — more precisely, the record contains only the original assignment, which the instructions call out as its own finding.

Justification: The sole recorded conveyance is the inventors' assignment to International Business Machines Corporation, executed 1998-08-04 to 1998-08-10 and recorded 1998-08-10 at reel 009384/0330. No post-issuance assignment, security interest, merger, or change-of-name filing exists in the record, so IBM retained ownership from filing until the patent lapsed on 2008-08-08 (notice) / 2008-09-30 (expiration entry) for non-payment of the maintenance fee due under 37 CFR 1.362. An operating company that never transferred the patent and then allowed it to expire is the opposite of the NPE pattern; there is no asserter, no shell entity, no cascading transfer, and no litigation (consistent with the earlier Litigation section). The only residual gap is the correspondent-of-record field for reel 009384/0330, which I could not retrieve — that gap changes nothing about the ownership conclusion, and I flag it rather than filling it with an inferred IBM IP Law Department address from a different patent's record.

Verify at: https://assignmentcenter.uspto.gov/ (search property number 6100114; the legacy interface at https://assignment.uspto.gov/patent/index.html surfaces the same underlying records). Reel/frame to pull directly: 009384/0330. Patent record: https://patents.google.com/patent/[US6100114](/patent/US6100114)/en

One caution on completeness, stated plainly: my searches did not return a live Assignment Center result page for this patent number in this session. The conclusion above rests on the Google Patents legal-events table bundled with the authoritative patent text, which lists the 1998 assignment and the 2008 lapse and no other conveyance. If a belt-and-suspenders confirmation is needed, the definitive check is the Assignment Center "Abstract of Title" for patent 6100114, plus the reel 009384/0330 cover sheet for the correspondent field.

I'll research each cited reference for US 6,100,114, prioritizing search results as ground truth.

Let me research the remaining citations and related references.

US 6,100,114 — Prior-Art Analysis of Cited References

Identification confirmed (no look-alike numbers): The record in the supplied authoritative text matches USPTO/Google Patents data exactly — US 6,100,114 (US6100114A), application 09/132,127, "Encapsulation of solder bumps and solder connections," IBM, filed 1998-08-10, granted 2000-08-08. I excluded look-alike identifiers, including the unrelated "'114" patents flagged in the prior litigation section (Atmel v. Authentec fingerprint-sensor '114; Smith Interface v. Apple mobile-device '114) and unrelated numbers such as 6,100,104/6,100,117.

Tool-budget note (disclosed per operating rules): I confirmed bibliographic and claim data for the references below via targeted searches (Google Patents, FreePatentsOnline, EveryPatent, PubChem, Unified Patents). For US 5,704,116, US 5,572,405, and US 5,888,850 the search budget was exhausted before I could retrieve full texts; their descriptions below are drawn from the patent's own citation/background passages and title records, and I flag them as not independently verified in this session.

Cross-reference to prior sections: The earlier summary and litigation sections are consistent with what follows. One discrepancy I flag, per your instruction to surface contradictions: the specification body (Google Patents OCR) cites "U.S. Pat. No. 5,714,352 by Hogerton et al.," whereas the front-page examiner citation list reads "US 5,714,252" (Minnesota Mining). The search results confirm US 5,714,252 is the Hogerton/Carlson 3M "Deformable substrate assembly" patent, so 5,714,352 appears to be an OCR/typesetting error in the specification text. I am not auto-correcting either number — I report both literally.

The six examiner-cited references (all pre-date the 1998-08-10 filing)

Reference-by-reference analysis

1. US 5,363,277 — Tanaka (Rohm)

• Full citation: US 5,363,277 A; "Structure and method for mounting semiconductor device"; inventor Osamu Tanaka; assignee Rohm Co., Ltd.; US app. 07/991,177 filed 1992-12-16; granted 1994-11-08.
• Description (verified): A flip-chip mounting structure in which an adhesive/hardenable thin film is applied over the wiring pattern of a circuit substrate; the IC's projecting electrodes are pressed through the film into contact with the pattern, and the film is then hardened (heat for epoxy; UV for photosetting resin) to hold the chip. No solder joint is formed — the electrical contact is a pressure/penetration contact held by the cured adhesive. (https://patents.google.com/patent/[US5363277A](/patent/US5363277A)/en; https://FreePatentsOnline.com/[5363277](/patent/5363277).html)
• Closest claims: Claim 11 (and by extension claims 12–14). Claim 11 requires "bringing said top portions of said solder bumps into contact with said circuitized substrate and heating said solder bumps and said encapsulant material to encapsulate solder connections." Tanaka discloses a circuit substrate with a chip bonded by hardened adhesive; the bump tips contact pads. It discloses the downstream assembly concept, but does not disclose solder bumps with a pre-applied encapsulant, the sacrificial sealing film, the low-durometer flexible layer, partial cure, or film removal. It forms no solder joints (adhesive bond only), whereas claim 11 expressly recites solder bumps and solder connections.
• §102 verdict: Does not anticipate any claim alone. Most plausibly a §103 secondary reference against the "adhesive/encapsulant + subsequent attach" aspects of claims 11–13. It supports the specification's own characterization (background section) of adhesive-only bonding limited to deformable substrates.

2. US 5,663,106 — Karavakis et al. (Tessera) — most relevant reference

• Full citation: US 5,663,106 A; "Method of encapsulating die and chip carrier"; Karavakis, Distefano, Smith, Jr., Mitchell; Tessera, Inc.; app. 08/246,113 filed 1994-05-19; granted 1997-09-02.
• Description (verified): Encapsulates a semiconductor chip assembly by (a) placing an encapsulant barrier (can/ring/mold) to define an encapsulation area, (b) providing a protective barrier so encapsulation material does not contact the exposed terminals, and (c) introducing liquid encapsulant (or a preform that is liquefied) which fills the area and is cured. Crucially, the protective barrier may be a solder mask with terminal holes, or a rubber shield that "rel[ies] upon the deformability of the rubber material to surround and protect the terminals," with pressure applied to make the rubber surround the terminals. It also discloses fill/vent holes and vacuum lamination. (https://patents.google.com/patent/US5663106; https://uspto.report/patent/grant/[5663106](/patent/5663106))
• Closest claims: Claim 1 and its dependents 5, 6, 7, 8, 10; and claim 11.
• §102 verdict — the strongest candidate, but still short of anticipation: The rubber shield under pressure ("some pressure must be applied in order to cause the rubber material to surround the terminals") is the clearest prior disclosure of a compliant layer protecting terminal/bump tops while encapsulant fills around them. However, claim 1 requires a two-layer stack — a "film of sealing material" plus a separate "layer of a low durometer flexible material" adjacent to it — pressed so the film contacts the bump tops, followed by partial cure, then removal of both the flexible layer and the film. The '106 rubber-shield embodiment is a single compliant member; the solder-mask embodiment is a film, but without the low-durometer backing layer and without removal-to-expose-bump-tops. Its encapsulation is around a chip-carrier assembly's terminals, not directly on a bare chip's solder bumps. Each claim-1 element is therefore not shown in a single reference → anticipation not established, but this is the reference most likely to have driven a §103 rejection of claims 1/5/6/8/10 and 11.

3. US 5,776,796 — DiStefano et al. (Tessera)

• Full citation: US 5,776,796 A; "Method of encapsulating a semiconductor package"; Tessera, Inc.; continuation-in-part of app. 08/246,113 (the '106 above) and app. 610,610 filed 1996-03-07; priority 1994-05-19; granted 1998-07-07.
• Description (verified): A spacer/compliant layer sits between a sheet-like substrate and the chip's contact-bearing surface; leads are bonded to chip contacts; a protective layer is attached over the substrate's bottom surface to cover/seal terminals; flowable curable encapsulant is deposited around the chip periphery to encapsulate the leads; the encapsulant is then cured or at least semi-cured; a dicing step (claims 3–6) singulates devices. (https://www.freepatentsonline.com/[5776796](/patent/5776796).html; https://uspto.report/patent/grant/5776796)
• Closest claims: Claim 1 (through its cure-step and protective-layer elements) and, notably, claim 2 — the wafer/batch concept. Claim 2 of the '114 patent recites "said semiconductor chip is provided as a semiconductor chip in wafer form"; the '796 patent expressly performs encapsulation "on a plurality of chip assemblies simultaneously" followed by dicing into singulated devices (claims 3–6).
• §102 verdict: Same structural gap as the '106 — a protective layer over terminals, not a sealing film pressed onto bump tops by a low-durometer layer, and no removal step to expose solder bump tops. Does not anticipate claim 1 or 11. Its multi-device/dicing teaching is relevant §103 art against claim 2 (wafer-form batch processing), which is one of the more vulnerable dependent claims.

4. US 5,714,252 — Hogerton/Carlson (Minnesota Mining & Manufacturing)

• Full citation: US 5,714,252 A; "Deformable substrate assembly for adhesively bonded electronic device"; Peter B. Hogerton and Kenneth E. Carlson; Minnesota Mining and Manufacturing Co.; priority 1995-08-29; granted 1998-02-03.
• Description (verified): A deformable substrate with ductile metal circuit traces; when a bumped component is adhesively bonded (flip-chip-direct-attach), the substrate material properties cause local plastic flow so the traces penetrate into the substrate surface, creating pressure-engaged (non-metallurgical) electrical connections. It discusses the C4 alternative and adhesive bonding with conductive particles. (https://patents.google.com/patent/[US5714252A](/patent/US5714252A)/en; http://www.everypatent.com/comp/pat5714252.html)
• Closest claims: Claim 11 (attach of bumped component to a substrate). This is the reference the specification's background discusses at length, noting the requirement that "the substrate be deformable" and that this approach "is limited to use on deformable substrates."
• §102 verdict: Does not anticipate any claim. It is an adhesive, non-solder bonding scheme; it lacks solder bumps with tops exposed by a removed sealing film, the low-durometer layer, and partial cure/encapsulation of the type claimed. Best treated as §103 background art and as evidence of the general "pre-applied material + attach" state of the art.

5. US 5,661,088 — Tessier et al. (Motorola)

• Full citation: US 5,661,088 A; "Electronic component and method of packaging"; Tessier, Kaskoun, Jandzinski; Motorola, Inc.; app. 08/583,835 filed 1996-01-11; granted 1997-08-26.
• Description (verified): Forms a hole through a substrate, disposes a malleable conductive layer over the hole, deforms it into the hole to form a dimple, couples a flip-chip die to the malleable layer, and disposes an underencapsulant (preferably a silica-filled epoxy-acrylate) under the die and over/in the hole. (https://portal.unifiedpatents.com/patents/patent/US-[5661088](/patent/5661088)-A; http://www.everypatent.com/comp/pat5661088.html)
• Closest claims: Claim 1 insofar as it discloses "positioning an encapsulant material substantially between the [component] and … in contact with the solder bumps" and curing an underencapsulant for a flip chip.
• §102 verdict: Does not anticipate any claim. It contains none of the distinguishing claim-1 elements: no sealing film over bump tops, no low-durometer flexible layer, no pressing-to-contact-tops step, no partial-cure-then-remove sequence. Underfill is applied conventionally after die attach. Pure §103/background art. (Note the specification separately cites US 5,661,088 by "Tessier et al." as an example of dispensed-and-cured encapsulant — consistent.)

6. US 5,704,116 — Motorola

• Full citation: US 5,704,116 A; "Method of holding a component using an anhydride fluxing agent"; Motorola, Inc.; priority 1996-05-03; granted 1998-01-06.
• Description (not independently re-verified this session; from title/record): A method in which an anhydride fluxing agent is used to hold/tack a component in position relative to bonding sites so it stays in place through the joining operation. Referenced in the '114 background discussion of flux/underfill-related arts.
• Closest claims: At most, tangential support for the general "material applied before/around the joint" concept of claims 1/11.
• §102 verdict: Does not anticipate any claim. It concerns fluxing/holding chemistry, not bump encapsulation, sealing-film capping, or compliant-layer pressing. §103/background art only.

Most relevant prior art — ranking

1. US 5,663,106 (Tessera, Karavakis et al.) — the closest art. Discloses (i) a protective barrier keeping encapsulant off terminals, (ii) introduction of liquid encapsulant into a defined area, and (iii) — importantly — a rubber shield relied upon for its deformability, pressed to surround and protect the terminals. This is the reference that most nearly reads on the "low-durometer flexible material" + "capped terminals" concept of claim 1. It still fails anticipation of claim 1 because it does not show the claimed two-layer film-plus-low-durometer stack, the partial-cure, and the removal of both layers to expose the bump tops.
2. US 5,776,796 (Tessera, DiStefano et al.) — the CIP sibling of the '106; closest on batch/wafer-form processing (relevant to claim 2) and on protective-layer-over-terminals.
3. US 5,714,252 (3M, Hogerton/Carlson) and US 5,363,277 (Rohm, Tanaka) — the two adhesive/"no-flow" attach approaches; relevant to claim 11's downstream attach step, but both lack solder-joint formation and the pre-applied encapsulated-bump structure.
4. US 5,661,088 (Motorola, Tessier et al.) and US 5,704,116 (Motorola) — peripheral background/§103 art only.

Overall §102 conclusion: On the face of the cited disclosures, none of the six examiner-cited references appears to anticipate (i.e., disclose every element of) independent claim 1 or claim 11, or any dependent claim read against those independents. The likely posture during prosecution was a § 103 combination (Tessera '106/'796 + a Motorola or 3M reference), with the '114 patent's novelty resting on the specific combination of: (a) a sealing film pressed onto bump tops by (b) a low-durometer flexible backing layer, (c) an encapsulant applied in contact with the bump sides but not the tops, (d) partial cure, and (e) peeling away both the flexible layer and film to expose the bump tops for later reflow. This is the same "essence" identified in the earlier plain-language claim overview.

Non-patent literature cited by the examiner (all 1998, on-sale/publication §102(a)/(b) candidates)

(Also cited in the specification background but not in the front-page citation list: US 5,572,405 (Wilson et al.) re: ball grid array packages, and US 5,888,850 — the '114 inventors' own assignment, "U.S. application Ser. No. 08/939,302 filed Sep. 19, 1997," describing an immersion encapsulation process. I did not retrieve full texts for these two in this session.)

Caveats and open items (stated rather than fabricated)

• Unverified in this session: full texts of US 5,704,116, US 5,572,405, and US 5,888,850; my descriptions of the first rest on the title/record, so the claim-mapping for it is provisional.
• Anticipation vs. obviousness: My §102 findings are based on the disclosed subject matter of each reference, not on the examiner's actual rejection record. The prosecution history (Office actions) would confirm whether these were applied under §102 or §103 — I did not retrieve it. The patent's "Expired – Fee Related" status (lapsed effective 2008-08-08) is unaffected by prior-art strength.
• Date discrepancy: the task states the current date as April 26, 2026, while the environment header gives 2026-09-11; both are after all cited references and neither affects the analysis.
• Identifier discipline: I did not auto-correct the "5,714,352 vs. 5,714,252" discrepancy between the specification body and the citation list; I flag it and leave both as written.

I'll verify the disclosures of the examiner-cited references before building the obviousness grounds, since the page gives me the reference titles but not their full texts.

Now let me verify the remaining two cited patents and the non-patent literature.

I ran targeted verification searches on the examiner-cited references before constructing the grounds, because the patent page supplies only reference titles. The searches substantially strengthen the obviousness case — particularly Tessera '106. Note one discrepancy I am flagging rather than auto-correcting: the '114 specification's Background cites "U.S. Pat. No. 5,714,352 by Hogerton et al.," while the Google Patents "Citations (6)" table lists US 5,714,252 (3M, "Deformable substrate assembly for adhesively bonded electronic device"). These are two different numbers for the same described subject matter. I treat the examiner-cited 5,714,252 as the reference of record and the spec's "5,714,352" as an apparent typo in the patent itself — but per the ID-rule, I do not silently correct either.

Obviousness Analysis — US 6,100,114 under 35 U.S.C. § 103

1. Governing framework

• Pre-AIA § 103 applies (filed 1998-08-10; never reexamined, lapsed 2008-08-08). The inquiry is Graham v. John Deere: scope/content of the prior art, differences from the claims, PHOSITA level, and secondary considerations.
• KSR Int'l v. Teleflex (2007) governs the combination analysis. The TSM test is not the sole test; a combination of known elements with predictable results is obvious where there was a known problem, a finite number of identified solutions, and a reasonable expectation of success. Where the patent's own Background articulates the commercial motivation, that is an admission usable against it.
• PHOSITA (proposed): a B.S. in materials science, mechanical or electrical engineering, plus ~2–5 years in semiconductor packaging/flip-chip assembly, familiar with C4, capillary underfill, BGA, and the trade literature (the NPL cited is addressed to exactly this person).
• Prior-art status of the cited art (pre-AIA): all six patents issued well before the 1998 filing (or are § 102(e) art as of their earlier filing dates — notably US 5,776,796 issued 1998-07-07, only 34 days pre-filing, but is § 102(e) art as of its 1996-10-07 CIP filing / 1994-05-19 parent). The NPL (SMT, Feb. 1998; Gamota & Melton, IEEE CPMT Part C, Jan. 1998) predate filing by only ~6–7 months, so they are § 102(a)-type art (before applicant's invention), not § 102(b) art. This matters only marginally; a Rule 131 swear-behind across a 6-month gap is unlikely, but counsel should note it.

2. Verified disclosures of the references of record

3. Element-by-element mapping — Claim 1

Every step of claim 1 has a factual counterpart in the cited art. The remaining question is only motivation and expectation of success.

4. Element mapping — Claim 11 (adds steps 8–9)

5. Grounds of rejection

Ground 1 — Claims 1–8, 10, 12 over Tessera '106 in view of Motorola '088 (and '277 / '252)

'106 teaches the entire architecture: a barrier protecting terminals from encapsulant, an embodiment in which that barrier is a flexible covering member that deforms into engagement with the top layer under pressure, introduction of a liquid curable encapsulant into the encapsulation area, curing (including by heating), and removal of the barrier/mold after partial cure while leaving terminals exposed. '088 supplies the flip-chip-with-underencapsulant context and the dispensing/curing of an underfill between die and substrate. '252 supplies the express recognition that bump-height variability must be accommodated by a compliant/deformable member, motivating the low-durometer backing layer. '277 supplies UV/heat curing of a pressed-through adhesive film (supporting claim 8 and the curing concept).

• Motivation: identical field (flip-chip/area-array packaging); '106's own stated objective — protecting terminals from encapsulant — is precisely the '114 objective; and '114's Background admits the desirability of applying encapsulant at the component level rather than only at the substrate, for wafer-form batch economics and supplier-level processing. KSR: a known problem (contaminating bumps with encapsulant destroys solderability), a small number of known solutions (mask, barrier, mold, sacrificial film), predictable results.
• Claims 3 and 4 (Kapton/Teflon film; silicone layer): '106's mold/barrier and the routine selection of heat-resistant release films and silicone sheet are conventional; the '114 specification itself merely lists commercially available materials (DuPont Kapton™/Teflon™, GE 3281 and Dow 1-4731 silicones). In re Kemps/routine-optimization reasoning, and the reference's list of known barrier materials, dispose of these.
• Claims 5–7 (liquid, injected, under vacuum): '106 expressly discloses liquid encapsulant, fill and vent holes, and preform/injection alternatives; vacuum-assisted underfill is standard (and '106 uses vacuum lamination). Routine optimization under In re Huang.
• Claim 10 (peel removal): a peelable release film is the ordinary way to remove '106's mold/mask.
• Claim 12 (spherical bumps): C4 bumps are the acknowledged norm in the '114 Background itself.

Ground 2 — Claim 11 over Tessera '106 in view of McGovern and Tanaka '277 (optionally with '088 and Gamota & Melton)

Claim 11's only added subject matter is (i) providing a circuitized substrate and (ii) contacting and heating to reflow the bumps to encapsulate the connections. McGovern discloses exactly the chip-on-board sequence with pre-applied encapsulant and simultaneous reflow + cure; Gamota & Melton and the SMT article establish that integrating reflow and encapsulation was a recognized, high-priority objective in the art (so-called high-speed/no-flow underfill). Tanaka '277 discloses pressing projections through a film to a circuitized substrate and hardening by heat. The combination is a predictable sequence of known steps with an expected result.

• Motivation: the '114 Background itself states the goal of applying encapsulant to the component before attachment, and notes that substrates "frequently have components of many differing sizes and shapes, often requiring a variety of encapsulation quantities and procedures." McGovern supplies the throughput/cost driver; KSR permits combining known steps in the known order (encapsulate → assemble → reflow) where the improvement is predictable.

Ground 3 — Claims 13 and 14 (edge sealant, overmold)

Applying an edge sealant at the chip perimeter and an overmold is the routine packaging practice; the '114 specification presents both as optional add-ons using off-the-shelf materials (Hysol FP4450, Dexter Corp.), and Tessera '796 discusses cured encapsulant bumpers at the periphery and dicing-induced perimeter encapsulation. These are the very definition of a predictable, art-recognized expedient.

Claim 9 — the strongest candidate for non-obviousness

Claim 9 (after partial cure, slightly retract the film while maintaining tip contact, then inject a thermoplastic adhesive between encapsulant and film) is the one claim I cannot clearly map onto the art of record. It amounts to a two-layer (thermoset + thermoplastic) pre-applied underfill. A reasonable examiner could reach it by combining multi-layer/multi-material underfill teachings with '106, but on the cited record alone this claim is the hardest to invalidate. Flag it as the claim to attack with additional art (e.g., multi-layer underfill or B-stage/adhesive-skin references), not with the six references of record.

6. Anticipated patentee counter-arguments and their strength

1. "Hogerton '252 teaches away from solder reflow" (its whole premise is adhesive, non-metallurgical bonding). Partially valid but easily avoided: grounding claim 11 in McGovern, not '252, sidesteps the teaching-away. '252 is needed only for the height-variation motivation, which is a separate, non-conflicting teaching.
2. "McGovern applies encapsulant to the substrate and pierces it; the claims apply it to the component behind a sacrificial film." This is the best argument — but it is an argument about a difference in where/which side, not about a missing element. Both '106 and '796 already teach protecting terminals with a barrier/mold and removing it after cure, so the "component-side, film-protected" variant is a predictable re-arrangement of known process steps.
3. "No reference teaches a low-durometer backing to press a sealing film onto bump tips." The closest is '106's disclosure of a flexible covering member that deforms into engagement with the top layer under pressure combined with '252's express accommodation of bump-height variation. That is a strong factual foundation, but the patentee can argue the specific numeric durometer (40–50) and the film/backing sandwich are not taught. Note: the claims recite "low durometer" generically (not the 40–50 figure, which appears only in the specification), which weakens this argument for claim scope purposes.
4. Unexpected results / secondary considerations: none in the record. The patent lapsed in 2008 for non-payment of maintenance fees (per the legal-events table reported in the earlier sections), there is no known litigation, and no evidence of commercial success attributable to the claimed method was adduced. Absent nexus evidence, this factor is neutral-to-negative.

7. Bottom line

• Claims 1–8, 10–14 are, on the examiner-cited record, vulnerable to a § 103 rejection. The most economical ground is Tessera '106 as the primary reference (barrier/flexible member/mold protecting terminals; liquid encapsulant; cure; mold removal) in view of Motorola '088 and Tanaka '277, with 3M '252 supplying the height-variation/accommodation rationale and McGovern / Gamota & Melton / SMT supplying the pre-applied-underfill-and-reflow motivation for claim 11. The specification's own Background supplies much of the motivation, which makes the KSR analysis unusually one-sided.
• Claim 9 is the exception: I cannot, with the references on this page, construct a clean prima facie case for the retract-film-then-inject-thermoplastic-adhesive step. That step should be treated as the residual point of novelty.
• Caveats: I could not retrieve the full text of US 5,704,116, the Gamota & Melton paper, or the McGovern article in this session — my characterizations of those three rely on their titles and on the '114 specification's own descriptions of them, and are flagged accordingly. I also could not verify the internal inconsistency between the spec's "US 5,714,352" and the cited US 5,714,252; the analysis uses 5,714,252 as the reference of record. Finally, this is a retrospective analysis of an expired patent (lapsed 2008-08-08; no litigation found), so the conclusion has no live-validity consequence.