US 5974500

US Patent 5,974,500 — Summary

Identification (as literally printed on the document)

• Patent number: US 5,974,500 (US5974500A / US 5974500)
• Application number: 08/971,117
• Title: "Memory device having programmable access protection and method of operating the same"

Bibliographic data

Family / foreign counterparts (titled "Programmable access protection in a flash memory device"): WO1999026253A1, EP1029326B1, JP2003532962A, KR100489757B1, CN1129916C, CA2310080A1, DE69814138T2, MY114492A, NO20002265L, TW417060B, HK1031456B.

Abstract (verbatim)

"A memory device comprises a memory array having corresponding first access control bits to control access thereto. A second set of access control bits is provided to control write access to the first access control bits. The memory array is divided into memory blocks, each block having a corresponding access control bit. At least one such block is further subdivided into pages, each page having a corresponding control bit."

Plain-language overview of the independent claims

Claim 1 — Memory device with two-tier protection (apparatus).
A memory array plus control logic that governs access to it. A first bit store holds access-control information that determines what access the array gets. A second control mechanism governs whether the first bit store can be written. A second bit store (a "sticky"-style bit store with one bit per first-store bit) holds modification-control information; write access to any bit in the first store is permitted only if the corresponding bit in the second store is at a defined ("second") logic state. Two external pins: one (WP2) sets the second bit store to a first logic state; the other (WP1) inhibits all write access to the array.

Claim 9 — Block-organized memory with access-enable bits and dual write-protect pins.
The array is organized into multiple memory blocks. Access-control logic enables/disables read and write to a selected block based on the logic levels of that block's access-enable bits. Write-control logic loads externally supplied access-enable information into those bits. A second bit store has one bit per access-enable bit, and writing to the first store is enabled only when the corresponding second-store bit equals a first logic state. A first write-protect pin prohibits write access to the array when asserted; a second write-protect pin sets the second bit store to a first logic level when asserted LO.

Claim 13 — Method of operating a memory device.
On a read request, check the permission bits for the addressed location and perform the read only if permitted; likewise for a write request. The array is divided into blocks with associated non-volatile permission bits, and requests are carried out per block. Updating the permission bits requires checking access information and is done only if that access information is at a first logic state. Updating the access information itself allows only changes from the first logic state to a second logic state (i.e., one-way/sticky). The access information is set back to the first logic state on power-on-reset or on asserting an access-protection pin. One block is further subdivided into pages, with per-page non-volatile page permission bits checked on each read/write to that page.

Claim 16 — Apparatus claim reciting the block/sticky-bit architecture.
Substantially claim 1's elements, additionally reciting that the memory array comprises a plurality of blocks each with corresponding access-control information, that the access-control information comprises a plurality of protection bits each associated with a block, and that the second storage means comprises a plurality of sticky bits, each sticky bit corresponding to a protection bit.

Claim 17 — Block-and-page apparatus with dual write-protect pins.
An array organized into blocks, at least one subdivided into N pages. Access-control logic enables/disables read and write to a selected block per that block's access-enable bits; write-control logic loads externally supplied enable information; a second bit store has one bit per access-enable bit and gates writing to the first store. A first write-protect pin prohibits write access to the array when asserted. A third bit store has N page-enable bits, and the access-control logic enables/disables read and write to a selected page based on the page-enable bit. A second write-protect pin, when asserted LO, sets the second bit store to a first logic level.

Notable implementation details (from the specification)

• Preferred embodiment is a serial EEPROM with pin SDA, plus two write-protect pins WP1 and WP2.
• WP1 is a conventional hard write-protect (disables the EEPROM high-voltage pump; also blocks writes to the sticky bits).
• Sticky bits can only be written to logic 0 via SDA; they reset to logic 1 only on WP2 asserted LO or on power-on-reset (POR).
• Protection bits are two-bit fields: (0,0)/(0,1) = no access; (1,0) = read-only; (1,1) = full read/write.
• Protection bits reside in an "access protection page" (APP) mapped as 16 bytes (byte0–byte15); sticky bits share that address space but physically live in separate registers (e.g., D-type flip-flops) so they can be initialized on power-up.
• FIG. 5 shows an RFID application (interrogator + tag with tank circuit, bridge rectifier, load modulation).
• Cited prior art (9 references) includes US 4,498,151; US 4,796,235; US 4,905,140; US 5,047,982; US 5,210,854; US 5,386,539; US 5,540,741; US 5,430,447; US 5,862,075.

On the "USPTO / CAFC 2026 docket" search — uncertainty noted

I could not find any authoritative record of CAFC 2026 docket activity involving US 5,974,500. Searches surfaced only patent-family, citation, and prosecution-history records (Google Patents, EPO, uspto.report). Points I can state with confidence:

• No appellate or PTAB proceeding specifically tied to this patent number appeared in the search results. (One PTAB/P-TACTS document that surfaced concerned an unrelated patent, "the '850 Patent," and different parties — it is not about 5,974,500, so I flag it as a false hit.)
• The patent's own legal-status record shows it expired for failure to pay maintenance fees / at end of term (anticipated expiration 2017-11-14), with the last recorded assignment being a release by JPMorgan Chase as secured party (2022-02-28). An expired patent is an unlikely candidate for live 2026 infringement litigation, though it could still be cited as prior art in other proceedings (it is, for example, cited as examination prior art in EP1538556A1 and EP1672566A1).
• I do not have authoritative information confirming any 2026 CAFC docket number, appeal, or IPR/CBM associated with this patent. Treat that absence as "not found," not as proof of none.

If you need a definitive docket check, the authoritative sources would be the CAFC docket (PACER/CM/ECF) and USPTO Patent Public Search / Patent Trial and Appeal Board (PTAB) APIs, which I cannot query directly here.

Primary source: https://patents.google.com/patent/US5974500/en

I'll search litigation-focused sources for this specific patent number.

Initial searches returned unrelated patents. Let me target litigation databases and the specific number more precisely.

Let me check litigation databases directly for this patent number and for the patent owner.

Litigation Check — U.S. Patent No. 5,974,500

Bottom line

I found no litigation involving U.S. Patent No. 5,974,500 — no U.S. district court action, no ITC Section 337 investigation, no CAFC appeal, and no PTAB proceeding (IPR/PGR/CBM). The only third-party proceedings that reference this patent at all are examination-stage prior-art citations in other people's patents, not adversarial cases against it.

I want to be explicit about the limits of that answer: the searches I could run (targeted web/database queries) are not a substitute for a PACER/CM-ECF docket query or the Unified Patents portal.unifiedpatents.com/litigation/caselist and PTAB APIs, which I could not query directly. Treat this as "not found," not "proven to be none."

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What I searched, and what came back

I searched literally on 5974500 / 5,974,500 and on the patent's identifying text, deliberately not broadening to similar numbers:

Near-miss hits I ruled out (checked the numbers literally, per instruction)

These surfaced in search and are not this patent — flagging so you can see they were considered and excluded:

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The only proceedings that touch this patent: prior-art citations

The patent does appear in the examination record of other applications/patents as cited art — which is not litigation but is the closest thing to a "proceeding" involving it:

• EP1538556A1 ("Radio frequency identification tags," filed 2004-11-30) lists US 5974500 A — Maletsky Kerry D [US], et al under "Citation (examination)."
• EP1672566A1 also cites US 5,974,500 as examination prior art (per the Google Patents citation data).
• Its own family members carry the title "Programmable access protection in a flash memory device": WO1999026253A1, EP1029326B1, JP2003532962A, KR100489757B1, CN1129916C, CA2310080A1, DE69814138T2, MY114492A, NO20002265L, TW417060B, HK1031456B.

The nine references cited in the patent (i.e., the examiner's prior art against it) are: US 4,498,151; US 4,796,235; US 4,905,140; US 5,047,982; US 5,210,854; US 5,386,539; US 5,540,741; US 5,430,447; US 5,862,075.

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Why no litigation is the expected result

• Expired status. The patent's legal-status record shows "Expired – Lifetime," with anticipated expiration 2017-11-14 (20 years from filing). Under 35 U.S.C. § 271, infringement liability ends with the patent term; damages cannot be recovered for post-expiration conduct. So the window for a damages suit on this patent closed in 2017.
• Last recorded legal events are financing/lien releases, not enforcement: Atmel → Morgan Stanley Senior Funding (security agreement, 2014), release (2016); Atmel → JPMorgan Chase (security interest, 2017), release by secured party (2022-02-28). None of those are infringement suits.
• The technology (EEPROM block/page read-write protection bits + "sticky bits" gating write access to those protection bits) is now ubiquitous in flash/EEPROM and smart-card/RFID controllers, but modern litigation in that space has been fought over later patents, not this 1997 Atmel filing.

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Two data caveats you should know about before relying on any of the above

1. Assignment-record anomaly (flagged, not "corrected"). The Google Patents reassignment history lists, verbatim, a 2005-08-04 assignment of "ASSIGNOR'S INTEREST" from International Business Machines Corporation to Lenovo (Singapore) Pte. Ltd., then a 2015-11-25 nunc-pro-tunc assignment to Lenovo PC International, which is why "Current Assignee" shows Lenovo PC International Ltd alongside Atmel Corp. That chain does not fit an Atmel-originated patent whose own assignment record shows Atmel→Atmel (1999) and Atmel as the security-agreement grantor in 2014 and 2017. This looks like a mis-linked reel/frame in the aggregate assignment data, but per the instruction to interpret identifiers literally I am reporting it as printed rather than silently correcting it. Practical consequence: do not assume Lenovo owns this patent, and do not assume Lenovo has any litigation history on it — I found none.

2. Date discrepancy. Your task header states the current date is April 26, 2026, while the operating environment and the patent fetch are timestamped 2026-09-30, and the search results include news dated September 2026. This only matters for framing "current status"; the substantive finding (no litigation) is unaffected. Flagging it because you asked me to surface contradictions rather than paper over them.

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How to get a definitive answer

Because "no litigation found" via web search is weak evidence, I'd confirm via:

1. PACER / CM-ECF — party-name search for "Atmel" and "Atmel Corporation," plus a "patent number" query where available (D. Del., E.D. Tex., N.D. Cal., C.D. Cal., and S.D. Cal. are the likely fora).
2. Unified Patents Litigation Portal — https://portal.unifiedpatents.com/litigation/caselist, search the patent number directly.
3. PTAB / P-TACTS API — search for IPR/PGR/CBM with patent number 5974500.
4. USPTO Patent Public Search — "Patent Litigation" and "Assignment" tabs for the patent number; the assignment reel/frame records will let you verify or refute caveat #1 above.
5. CAFC docket — no 2026 appeal tied to this number surfaced in any search; confirm via the Federal Circuit's CM/ECF.

If you want, I can draft a short litigation-history declaration suitable for an invalidity/§ 282 notice or a damages analysis, with the above search strings and dates recorded as the basis.

Proceedings overview

Total AIA trial proceedings on US 5,974,500: zero. The canonical source — the structured "PTAB proceedings on file" block, which the ODP API (USPTO Open Data Portal) populates from PTAB's trial records — returns no IPR, no PGR, and no CBM for this patent, and four independent web-search passes surfaced nothing that contradicts it. There is therefore no proceeding-level breakdown to report (0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution denied), and no Federal Circuit appeal of an FWD exists because no FWD exists.

Bottom line for a defendant: the patent is not "hardened" — it is simply unchallenged. Every one of claims 1, 9, 13, 16 and 17 (and all 12 dependents) stands exactly as issued on 1999-10-26, untouched by any AIA trial. At the same time, no petitioner has ever had a reason to spend $100k+ attacking it, and the reason is visible on the face of the record: US 5,974,500 expired for failure to pay maintenance fees / end of term on 2017-11-14 (Google Patents legal-status: "Expired – Lifetime"; anticipated expiration 1997-11-14 + 20 years). If a demand letter today cites this patent, the practical question is not "did PTAB kill it?" but "what enforceable term can it possibly still have?"

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No proceedings to list

There is no {PROCEEDING_NUMBER} — {Petitioner} v. {Patent Owner} entry to populate. Per the source block: "The USPTO ODP API returns no AIA trial proceedings for this patent as of the most recent ingest… the default should be 'no PTAB activity on file.'" — and my searches did not surface any older or un-indexed proceeding, so no flag is raised.

How hard I looked, and what I found instead:

False positives I explicitly reject (both concern different patents and are not about 5,974,500):

• IPR2020-00717 / IPR2020-00718 — Samsung Electronics v. Bell Northern Research, on U.S. Patent 7,957,450 and U.S. 8,416,862. The shared last three digits ("450") are coincidental. (Petition, IPR2020-00717)
• Hyundai v. Autoliv (Inoue/Narin airbag art) — also an unrelated "'450 patent."
• Ex parte Malitski (Appeal 2012-001096, Appl. 11/213,149) — a name-similarity hit (Malitski ≠ Maletsky) in a completely different art unit (shipping/transportation planning). Not this patent.

The only third-party USPTO/EPO-type appearance of this patent I could confirm is as examination-cited prior art in other people's cases: EP1538556A1 and EP1672566A1 both list "US 5974500 A (19991026) — MALETSKY KERRY D [US], et al." as a Citation (examination). That is a citation, not a challenge to this patent.

Confidence caveat, stated plainly: I could not directly query PTAB E2E or the ODP API in this session. My conclusion rests on (a) the ODP-derived block furnished in this prompt, which is authoritative, and (b) web corroboration. If you need a court-grade negative, run the manual check at PTAB E2E / Patent Trial and Appeal Board End-to-End and USPTO Patent Public Search, and check CourtListener under "Patent 5,974,500" for any § 319 appeal.

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Strategic summary

Claim status — everything is UNTESTED; nothing is CANCELED and nothing is SUSTAINED-by-PTAB. Because no AIA trial was ever instituted, claims 1–17 remain exactly as issued. There is no narrowing, no certificate cancelling claims, and no PTAB-sanctioned claim construction. Do not let anyone tell you an IPR "confirmed" or "hardened" these claims — an unchallenged patent has zero adversarial validity testing behind it. That cuts both ways: there is no favorable PTAB record to lean on, but there is also no in rem estoppel or statutory cancellation working against you.

Estoppel landscape — empty. § 315(e)(2) estoppel requires a petitioner that instituted a trial; there is no such petitioner, so no party (privity chains included) is estopped from raising any prior-art ground against these claims, in the PTAB or in district court. Everything is on the table, including the nine references already in the file — US 4,498,151; US 4,796,235; US 4,905,140; US 5,047,982; US 5,210,854; US 5,386,539; US 5,430,447; US 5,540,741; US 5,862,075 — plus anything else a search turns up. Note the flip side of § 325(d): art already before the Examiner may invite discretionary denial if you do file, so the highest-value targets are references the 1999 Examiner never saw.

Pattern signals — the strongest signal is the silence itself. No repeat petitioner, no defensive aggregator (no Unified Patents trace), no patent-owner appeal aggressiveness to measure. Nothing else in the chain points to a campaign patent: the recorded assignments are a corporate drift (Atmel → Lenovo (Singapore) → Lenovo PC International, plus Morgan Stanley and JPMorgan security interests, released 2016-04-04 and 2022-02-28) — i.e., portfolio housekeeping, not litigation financing. Patent families that are actually being asserted tend to attract at least one IPR; this one went twenty years without a single petition.

The decisive fact is not the absence of PTAB, it's the expiration date. With the statutory term ending 2017-11-14, the patent can support neither injunctive relief nor ongoing royalties. Any residual exposure is pre-2017-11-14 damages and the six-year § 286 look-back. And if you nevertheless want a PTAB ruling — e.g., to eliminate a stale demand or a prior-art cloud — be aware the Board construes expired claims under the Phillips framework rather than the broadest reasonable interpretation, which changes the claim-construction battlefield. Budget for that before filing.

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Recommended next steps

1. Confirm the negative yourself before you rely on it. Pull the patent in PTAB E2E and USPTO Patent Public Search ("Application/Control Number" and "Patent Number" = 5974500), and search CourtListener for "5,974,500" to catch any § 319 appeal. The absence of PTAB activity is only useful as a defense if you've verified it on the Office's own systems.
2. Lead with expiration, not invalidity. Assert, with the Google Patents legal-status record as support (patent US5974500A), that the patent expired 2017-11-14 and is unenforceable for post-expiration conduct; demand that any assertion be limited to acts before that date and within § 286.
3. If the demand letter survives that, there is no PTAB shortcut. Invalidation means district court (jury, clear-and-convincing) or an IPR petition you would have to file — no estoppel blocks it, but with an expired patent the cost/benefit rarely pencils out. Prefer a well-supported § 102/§ 103 invalidity contention built on art outside the nine references the Examiner already of-record, to sidestep § 325(d).
4. Watch your § 315(b) clock if you are in litigation. One year from service of the complaint is the deadline to petition; since nothing has been filed, that clock — not any existing proceeding — is your constraint.
5. Check the family before you assume anything global. The foreign counterparts (EP1029326B1, JP2003532962A, KR100489757B1, CN1129916C, CA2310080A1, DE69814138T2, TW417060B, WO1999026253A1, MY114492A, HK1031456B, NO20002265L) may have their own national-office revocations, oppositions, or lapses that matter for non-US exposure. I found no PTAB equivalent for these, and I did not verify their individual national statuses — treat that as "unchecked," not "clear."

Sources: Provided ODP-derived "PTAB proceedings on file" block (canonical); Google Patents US5974500A (bibliographic, legal status, family, citations); PTAB E2E; CourtListener. No proceeding-specific opinion exists to link for this patent because no proceeding was ever instituted.

I'll reconstruct the assignment record. Let me first verify the chain against live sources, since the Google Patents legal-events data I was given contains a puzzling IBM→Lenovo link for what is nominally an Atmel patent.

Let me pull the specific assignment records and correspondents.

Assignment & Ownership Reconstruction — US 5,974,500

Scope note (read first). I could not open the USPTO Assignment Center (assignmentcenter.uspto.gov) directly from this session. The reel/frame data below is taken from the Google Patents "Legal Events" block embedded in the authoritative patent text supplied above, which mirrors the USPTO assignment database's reel/frame and free-format text fields, cross-checked against a mirrored copy of the record on plainsite.org. Correspondents of record are only exposed where a mirror surfaced them; for five of the eight recordings I have no correspondent name and I say so rather than guess. Verify every entry at the Assignment Center by searching patent number 5,974,500: https://assignmentcenter.uspto.gov/ (legacy mirror: https://assignment.uspto.gov/patent/index.html).

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Inventors

Pattern notes:

• All five inventors assigned to Atmel Corporation on a single instrument (reel 009014/0844), signing dates 1998-01-23 through 1998-02-03 — i.e., ~2–3 months after the 1997-11-14 filing date. That is the ordinary corporate-invention sequence (file first, paper the assignment afterward), not a pre-filing departure pattern.
• No evidence of inventor departure within 12 months of filing. I cannot verify employment histories for these individuals from the sources available, and I will not infer it.
• ⚠️ Unverified lead, flagged not relied upon: a "Daryl Cromer" is publicly associated with IBM/Lenovo. Whether this is the same individual as inventor Daryl C. Cromer is not established by anything in the record, and inventor mobility would not in any event transfer patent ownership. I raise it only because of the anomalous Lenovo recording discussed below. Do not treat it as a finding.

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Original assignee

Atmel Corporation (California corporation; address of record on the 2016 release paperwork: 2095 Ringwood Avenue, San Jose, CA 95131).

• Line of business: semiconductor design/manufacture — microcontrollers, non-volatile memory (EEPROM/flash), touch controllers, RF/RFID and secure-memory ICs. This patent sits squarely in that portfolio: serial-EEPROM access protection, block/page protection bits, and an RFID (tag/interrogator) embodiment are all described in the specification.
• Did they ship a product embodying the claims? Atmel's serial EEPROM, secure-memory, and RFID tag lines operate in exactly this space, and the specification's "sticky bits + access protection page + WP1/WP2" scheme reads as a description of production silicon rather than a paper design. I have not verified a specific datasheet/part number in this session, so I state the product link as likely-but-uncited rather than proven.
• Current status: operating, but no longer independent — Atmel was acquired by Microchip Technology Inc. (announced January 2016; deal closed April 4, 2016). Atmel continues as a Microchip subsidiary/brand. It was not a Chapter 7/11 debtor and did not sell this patent in bankruptcy. The April 4, 2016 release of the Morgan Stanley security interest (reel 038376/0001) coincides exactly with the Microchip closing date — a useful corroboration that the 2013 lien was Atmel's pre-acquisition term-loan collateral.

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Assignment timeline

Listed chronologically by execution date (recording dates and reels in the headings).

1998-01-23 → 1998-02-03 (executed) / recorded 1998-03-02 — Reel 009014/0844

• Conveyance: Assignment ("ASSIGNMENT OF ASSIGNORS' INTEREST")
• Assignor: Maletsky, Kerry D.; Ward, James P.; Steinmetz, Michael J.; Cromer, Daryl C.; Pruett, Gregory
• Assignee: Atmel Corporation (California)
• Correspondent: not obtained from available sources
• Context: original inventor-to-employer assignment; establishes Atmel as first owner.

1999-09-13 (executed) / recorded 1999-09-22 — Reel 010231/0283

• Conveyance: Assignment of Assignor's Interest
• Assignor: Atmel Corporation
• Assignee: Atmel Corporation (California)
• Correspondent: not obtained
• Context: Atmel-to-Atmel confirmatory/internal assignment — beneficial ownership does not change. The same instrument appears across many Atmel patents of this vintage, consistent with an intra-corporate reorganization/merger of Atmel entities in September 1999. Not a sale.

2005-05-20 (executed) / recorded 2005-08-04 — Reel 016891/0507 ⚠️ ANOMALOUS — CONTRADICTS THE REST OF THE CHAIN

• Conveyance: Assignment ("ASSIGNMENT OF ASSIGNOR'S INTEREST")
• Assignor: International Business Machines Corporation
• Assignee: Lenovo (Singapore) Pte Ltd.
• Correspondent: not obtained
• Context: This is the IBM PC-division divestiture to Lenovo (a massive portfolio transfer that closed in 2005). It does not belong in an Atmel-originated patent chain. There is no recorded IBM assignment into this patent and no recorded Atmel assignment to IBM. I flag this as an unresolved data-attribution problem, not as a genuine ownership event. Two readings are possible — (a) a false attribution merged into this patent's legal-events stream, or (b) the patent number genuinely appeared on that reel's cover sheet. I cannot resolve it with the sources available, and the operating rule "prefer the record" cuts against silently deleting it. It should be resolved directly at the Assignment Center by pulling reel 016891/0507 and confirming whether application 08/971,117 is on its property list.

2013-12-06 (executed) / recorded 2014-01-03 — Reel 031912/0173

• Conveyance: Patent Security Agreement (grant of security interest — not a title transfer)
• Assignor: Atmel Corporation
• Assignee: Morgan Stanley Senior Funding, Inc., as Administrative Agent
• Correspondent: not captured on this reel (see note under reel 038376/0001 — the same lender-side filing agent is the likely correspondent on the companion Morgan Stanley records)
• Context: securitization — Atmel pledged its patent portfolio as collateral for its December 2013 term loan.

2013-04-01 (executed) / recorded 2015-11-25 — Reel 037160/0001

• Conveyance: Nunc Pro Tunc Assignment
• Assignor: Lenovo (Singapore) Pte Ltd.
• Assignee: Lenovo PC International (Hong Kong)
• Correspondent: not obtained
• Context: internal Lenovo group restructuring (Singapore → Hong Kong entity, back-dated to 2013-04-01). Same caveat as reel 016891/0507: this only makes sense if the anomalous 2005 IBM→Lenovo recording is real; if that recording is a misattribution, this one is carried along with it.

2016-04-04 (executed) / recorded 2016-04-07 — Reel 038376/0001

• Conveyance: Termination and Release of Security Interest in Patent Collateral
• Assignor: Morgan Stanley Senior Funding, Inc.
• Assignee: Atmel Corporation
• Correspondent: Joanna McCall, National Corporate Research, Ltd., 1025 Vermont Avenue, N.W., Suite 1130, Washington, DC 20005
• Context: release of collateral — collapses the 2013 lien, timed to the Microchip/Atmel closing (2016-04-04). The correspondent is a corporate-services/lien-filing agent used by secured lenders, i.e., a lender artifact, not an NPE tell.

2017-08-29 (executed) / recorded 2017-08-29 — Reel 043440/0467

• Conveyance: Security Interest
• Assignor: Atmel Corporation
• Assignee: JPMorgan Chase Bank, N.A., as Administrative Agent
• Correspondent: not obtained (expect the same lender-side filing agent as above)
• Context: securitization — Atmel collateral pledged under the post-Microchip credit facility. A portfolio-level blanket filing, so it would sweep in patents of any remaining term.

2022-02-18 (executed) / recorded 2022-02-28 — Reel 059114/0333

• Conveyance: Release by Secured Party
• Assignor: JPMorgan Chase Bank, N.A., as Administrative Agent
• Assignee: Atmel Corporation
• Correspondent: not obtained
• Context: release of collateral — chain ends with the operating company (Atmel/Microchip) holding title, unencumbered.

Expiry (not an assignment): Google's legal events record "Anticipated expiration 2017-11-14" (20 years from filing), with maintenance fees paid in 2003, 2006 and 2011. Status: Expired – Lifetime. There are no recorded assignments after 2022-02-28, and no recorded litigation or IPR.

Correspondent caveat: The only correspondent I could positively tie to this chain is Joanna McCall / National Corporate Research, Ltd. on reel 038376/0001 (mirrored as "38376/1" — the leading-zero difference is a mirror formatting artifact, same record). I did not retrieve correspondents for reels 009014/0844, 010231/0283, 016891/0507, 037160/0001, 043440/0467 or 059114/0333. Do not read a "repeat correspondent" signal into this — I simply don't have the data. Any conclusion on signal #3 below requires a direct pull from the Assignment Center.

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Timeline diagram

timeline
    title Ownership of US 5974500
    1997 : Filed 14 Nov by Atmel Corporation
    1998 : Five inventors assign to Atmel
    1999 : Atmel to Atmel confirmatory deed
         : Patent issues 26 Oct
    2005 : IBM to Lenovo Singapore recorded
    2013 : Morgan Stanley security interest
    2015 : Lenovo Singapore to Lenovo PC
    2016 : Morgan Stanley releases interest
    2017 : JPMorgan security interest
         : Patent reaches end of term
    2022 : JPMorgan releases interest

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NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT.
No "IP / Patents / Licensing / Holdings / Ventures" entity anywhere in the chain. The complete list of assignees is: Atmel Corporation (operating), Lenovo (Singapore) Pte Ltd. and Lenovo PC International (operating subsidiaries of a public OEM — and see the anomaly flag), Morgan Stanley Senior Funding, Inc. and JPMorgan Chase Bank, N.A. (lenders taking security interests, not title, reels 031912/0173 and 043440/0467). No single-purpose LLC, no registered-agent address as a principal place of business.

2. Known asserter in the chain — NOT PRESENT.
No assignee matches Acacia, Marathon, Intellectual Ventures, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation Corp, or any Spangenberg entity. (I could not query the RPX/Unified Patents asserter directories from this session; the call rests on the absence of any matching name in the recorded chain, which is a name-based check only.)

3. Repeat correspondent across the chain — UNCLEAR / NOT ESTABLISHED.
Only one correspondent surfaced: Joanna McCall, National Corporate Research, Ltd., reel 038376/0001 (2016-04-07). NCR is a lien/assignment filing service retained by secured lenders — a single appearance in a security-interest release is not a finding under the stated rule, and its appearance is better explained as lender paperwork than as NPE coordination. The other six recordings' correspondents are unknown to me. Net: unclear, no evidence of an NPE-connective attorney.

4. Cascading transfers (chained LLCs in <24 months) — NOT PRESENT.
The chain spans 1998 → 2022. The only sub-24-month pairings are the grant/release pairs on the same collateral (2013-12-06 grant → 2016-04-04 release ≈ 28 months; 2017-08-29 grant → 2022-02-18 release ≈ 54 months) and the Lenovo nunc-pro-tunc recording (executed 2013-04-01, recorded 2015-11-25, i.e., a recording lag, not a rapid ownership cascade). No shared-correspondent or common-principal shell chain exists on this record.

5. Pre-litigation transfer — NOT PRESENT.
I found no infringement suit naming US 5,974,500. The last recorded transfer is a 2022-02-18 collateral release; there is no assignment within six months preceding any suit because no suit appears.

6. Bankruptcy fire-sale — NOT PRESENT.
Atmel never filed Chapter 7/11. The controlling 2013–2016 events are a term-loan pledge (reel 031912/0173) and an M&A acquisition by Microchip Technology that closed on the same day the lien was released (reel 038376/0001, 2016-04-04). That is a solvent change of control, not a fire sale.

7. Privateering — NOT PRESENT.
No operating company transferred this patent to an NPE to assert against competitors. A security interest to Morgan Stanley/JPMorgan is not privateering; those are credit-support instruments and both were released back to the grantor.

8. Defensive aggregator (anti-NPE) — NOT PRESENT.
The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. It terminates at Atmel Corporation (now a Microchip subsidiary), holding title free of all recorded liens as of 2022-02-28.

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Verdict

Defensive / non-asserting.

Justification: Every recorded transfer is either a corporate-internal event (reel 010231/0283, Atmel→Atmel, executed 1999-09-13), a collateral grant/release (reels 031912/0173 and 043440/0467 granting to Morgan Stanley/JPMorgan; reels 038376/0001 and 059114/0333 releasing back to Atmel), or the original inventor assignment (reel 009014/0844, executed 1998-01-23/1998-02-03). There is not a single shell-entity, asserter, aggregator, bankruptcy or pre-suit transfer on the record, no litigation naming the patent surfaced, and the patent reached its full term on 2017-11-14 with title sitting with an operating company. Caveat on category fit: the enumerated definition of "Defensive / non-asserting" contemplates termination at a defensive aggregator; here non-assertion arises from the chain never having left operating companies and the patent having expired, not from RPX/AST/LOT. This case does not map cleanly onto the taxonomy — if the aggregator criterion is read strictly, the next-best label would be "Insufficient data," because of the unresolved reel 016891/0507 problem below.

One open item that does not change the verdict but must be resolved: the 2005-05-20 / recorded 2005-08-04 IBM → Lenovo (Singapore) Pte Ltd. recording at reel 016891/0507, and its downstream nunc pro tunc recording at reel 037160/0001 (2015-11-25, effective 2013-04-01), are structurally impossible for an Atmel-originated patent and are the reason Google Patents lists "Lenovo PC International Ltd" as a current assignee alongside Atmel. Either the patent number was mis-attributed into that reel, or a genuine unrecorded upstream transfer is missing. Pull reels 016891/0507 and 037160/0001 at the Assignment Center and confirm whether application 08/971,117 appears on their property lists before relying on the Lenovo branch of this chain.

Verify at: https://assignmentcenter.uspto.gov/ — search patent number 5,974,500; also https://assignment.uspto.gov/patent/index.html and the Google Patents legal-events block at https://patents.google.com/patent/US5974500/en.

I'll research the cited prior art for US 5,974,500, verifying each reference against the record and building out the § 102 analysis.

Let me pull the remaining cited references.

Prior Art Analysis — U.S. Patent No. 5,974,500

Patent: US 5,974,500 B1 — "Memory device having programmable access protection and method of operating the same"
Appl. No.: 08/971,117 · Filed/Priority: 1997-11-14 · Issued: 1999-10-26 · Assignee: Atmel Corp.
Legal status: Expired – Lifetime (anticipated expiration 2017-11-14)

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1. Scope, method, and a necessary caveat

What I searched. I searched on the literal number 5974500 / 5,974,500 and on the title/inventor/assignee text, deliberately refusing to auto-correct or broaden to near numbers. The results returned this patent's own record plus its citation and family data. I excluded the near-miss numbers that surfaced (e.g., US 7,957,450 / IPR2020-00717, US 7,608,597, US 10,659,885) — they are different patents and are not reported here.

Source of the citation list. I could not reach USPTO Patent Public Search / PatentCenter directly in this session. The nine-reference list below is taken from the "References Cited" / "Patent Citations (9)" block of the patent's own record (USPTO-derived front-page data, as exposed via Google Patents and mirrored in the EPO family data). That is the authoritative set of citations on the face of this patent — there are no foreign patent documents and no non-patent literature in the U.S. citation list; all nine are U.S. patents.

Legal framework — pre-AIA. Because the application was filed 1997-11-14, the pre-AIA version of 35 U.S.C. § 102 governs. The three subsections that matter here:

Honest bottom line up front. None of the nine references, alone, anticipates any independent claim (1, 9, 13, 16, 17) of US 5,974,500 on the record available. Each cited reference is missing at least one element of the two-tier architecture — most commonly the second bit store with a bit-per-bit correspondence to the first bit store, the dual write-protect pins (WP1/WP2), or the read-access gating via the protection bits. These are best characterized as § 103 (obviousness) references, with a few individually strong against dependent claims or against individual method steps of claim 13. I flag that explicitly rather than manufacture anticipations.

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2. The nine cited references at a glance

(Two further references appear in the family/EP-citation stream — US 5,491,827, Bull HN Information Systems, "Secure application card…" (1994-01-14 / 1996-02-13), and JP 4148990 B2, Macronix, "Non-volatile memory device for error tolerant data." These are not on the U.S. face of the patent but are worth a look given the secure-memory-card subject matter of claim 9; I note them as supplemental, not as the "citations for 5974500.")

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3. Reference-by-reference analysis

(1) US 4,498,151 A — "On board non-volatile memory programming"

• Full citation: U.S. Patent 4,498,151, Texas Instruments Inc., filed/priority 1980-04-17, published 1985-02-05.
• Description: On-board (in-system) programming of a non-volatile memory — i.e., the charge-pump / programming-voltage and program-enable control that lets the array be written without removing it from the host. (I was not able to pull full text this session; the description is title/assignee-derived and should be treated as low-confidence.)
• § 102 analysis: Relevant only to the high-voltage-pump / program-enable aspect of claim 6 and to the general "EEPROM that is programmed in-system" background. It does not disclose a first bit store, a second (sticky) bit store, bit-for-bit correspondence, or the two write-protect pins. No independent claim is anticipated. Best case: a secondary reference in a § 103 combination for claim 6.

(2) US 4,796,235 A — "Write protect mechanism for non-volatile memory" ★ high relevance

• Full citation: U.S. Patent 4,796,235, Motorola, Inc., filed 1987-07-22, published 1989-01-03 (inventors incl. Brian F. Wilkie).
• Description (verified from the document): A write-protect apparatus for a PROM/EEPROM in a single-chip microcomputer. It comprises:
  • "protect register means for storing data" — writes to the PROM are allowed "if and only if said protect register means contains particular, predetermined data";
  • timer means allowing that data to be written into the protect register only within a predetermined time after a predetermined event (reset);
  • an express object of providing "independent write protection for a plurality of independently write-protectable blocks of PROM";
  • it also notes the on-chip charge pump generating the higher programming voltages (contrast with the '500 patent's WP1 disabling of the pump).
• § 102 analysis:
  • Claim 1 / 16 — Conceptually the closest prior art to the "two-tier" idea: the protect register (≈ first bit store) gates writes to the array, and writes to the protect register itself are separately gated. But it is not an anticipation, because (i) the gating of the protect register is by a timer, not by a second bit store having a bit corresponding to each bit of the first store; (ii) there is no first pin that sets a second store to a first logic state, and no second pin that inhibits all writes; (iii) it concerns write protection only — no read-access control. These missing elements are the heart of claim 1, so the reference supports § 103, not § 102.
  • Claim 2 / 3 / 9 / 16 (blocks with independent protection, protection bits per block) — this is the reference's strongest point; it expressly claims independent write protection of multiple blocks. Strong § 103 art, again not a clean anticipation because claim 9 additionally requires the second bit store, the write-control logic, and two write-protect pins.

(3) US 4,905,140 A — "Semiconductor integrated circuit device"

• Full citation: U.S. Patent 4,905,140, Hitachi, Ltd., filed/priority 1984-08-22, published 1990-02-27.
• Description: Generic-titled integrated-circuit device; on the title and assignee alone it is plausibly directed to a semiconductor memory with a protection/control function. (Full text not verified this session — description is inferred and low-confidence.)
• § 102 analysis: Treat as background/general-purpose art for claims 1–2. On the record available I cannot map it to any limitation with confidence. I am not asserting it anticipates any claim; a full-text pull would be required before relying on it. This is an explicit "insufficient information," not a conclusion of irrelevance.

(4) US 5,047,982 A — "Write protection method and apparatus for an EEPROM" ★ relevant to the "gating" concept

• Full citation: U.S. Patent 5,047,982, Caterpillar, Inc., filed 1990-04-12, published 1991-09-10 (inventors incl. Alan L. Stahl).
• Description (verified): A microprocessor/EEPROM system in which an EEPROM write normally requires pulling a write-enable pin (WEN) low. To defeat inadvertent writes, an intermediate means 20 plus a write subroutine require the microprocessor to issue a "pseudo address signal" (an unused address code) a preselected number of times; a decoder feeds an R-C integrator whose output crosses a threshold to finally deliver the write-enable signal. A counter-based software loop controls how many pseudo-address writes occur.
• § 102 analysis:
  • Claim 1's "second control means" (the idea of making the write-enable path depend on a gate other than the ordinary write enable) and claim 6 (enabling/disabling programming) — thematically on point.
  • Not an anticipation: the write-enable gating is by a decode/counter/R-C analog sequence, not by a bit store per bit of a first bit store, and there are no two write-protect pins in the '500 sense. § 103 only; useful as a "it was known to require an unlocking sequence to write an EEPROM" reference.

(5) US 5,210,854 A — "System for updating program stored in EEPROM…" ★ relevant to partitions/blocks

• Full citation: U.S. Patent 5,210,854, Digital Equipment Corporation, filed 1989-06-14, published 1993-05-11.
• Description (verified): An all-EEPROM firmware system with hardware partitioning of the firmware into "protected" and "unprotected" partitions. A control logic device between the CPU and EEPROM decodes address and control signals to prevent writing to protected partitions, while permitting updates to unprotected areas; transfer vectors/jump tables provide failure recovery during update.
• § 102 analysis:
  • Claim 2 / 9 (memory organized into blocks, with logic enabling/disabling writes to a selected block based on its control information) and claim 10 (control-bit address space being a subset of the array address space) — good § 103 material: it teaches address-decoded, per-partition write gating by control logic.
  • Claim 1 — its control logic arguably reads on "first control means"; but there is no second bit store and no dual pins. No anticipation. Also note it is write-only protection (no read-access control), which is a core feature of claims 1/9.

(6) US 5,386,539 A — "IC memory card comprising an EEPROM with data and address buffering…"

• Full citation: U.S. Patent 5,386,539, Fuji Photo Film Co., Ltd., filed/priority 1990-09-28, published 1995-01-31.
• Description: An IC memory card with an EEPROM and buffering for controlling data/address transfer to the EEPROM. (Title-derived; full text not verified this session.)
• § 102 analysis: Relevant at most to the interface/buffering environment of claim 7 (serial or parallel interface) and as background for the memory-card application. It does not disclose the access-control bit architecture. No anticipation.

(7) US 5,430,447 A — "Protection against manipulation of batteryless read/write transponders" ★★ most relevant overall

• Full citation: U.S. Patent 5,430,447, Texas Instruments Deutschland GmbH, filed 1993-08-23, published 1995-07-04 (inventor Herbert Meier; EP counterpart EP 0 640 939 A2).
• Description (verified): A batteryless RF transponder whose EEPROM is organized in blocks/pages, where:
  • each block/page can be read, programmed, or locked, and only the addressed page is accessed at a time;
  • a "lock" bit can be set but there is no function to unlock it ("no function is provided for unlocking the EEPROM cell") — i.e., a one-way, non-resettable protection state;
  • Control Logic circuit 22 controls access to the Segment Code, and a Segment Code / Selective Address acts as a password gating read and program functions; a mismatch causes the transponder to refuse to respond;
  • the Segment Code is stored in EEPROM "which can be locked (fixed) using another EEPROM cell" — a first store whose write-access is governed by a separate control store.
• § 102 analysis:
  • Claim 13 is the claim most exposed. Its steps — check permission bits on read and on write (detecting … the logic state of permission bits … and carrying out … only if permitted), block/page organization with non-volatile permission bits, and specifically "allowing only updates wherein the access information is changed from the first logic state to a second logic state" (one-way/sticky behavior) and "subdividing one of the memory blocks into a plurality of pages … non-volatile page permission bits" — map closely onto the transponder's lock bit that can only be set, never cleared, and its per-page read/program/lock gating by Control Logic. This is the single best § 102 argument on claim 13 in the cited set, but claim 13 as a whole also requires the permission-bit check architecture and the "set back to the first logic state on POR or on asserting an access-protection pin" reset behavior, which the transponder (which is intentionally non-resettable) does not disclose. So: near-miss / strong § 103; anticipation is arguable only for individual sub-steps, not the claim as a whole.
  • Claims 1, 9, 12, 15, 17 — it is highly relevant art for RF-interface claims (12, 15) and for the page concept (17), and its "lock an EEPROM cell using another EEPROM cell" is close to the first-store/second-store relationship. However, it does not disclose the bit-for-bit correspondence of the second store to the first store, nor the two write-protect pins (WP1/WP2), nor read/write access bits encoded as a two-bit (MSB,LSB) field per block. No anticipation of the independent claims.

(8) US 5,548,741 A — "IC memory card system having a host processor selectively operable with an IC memory card including either an SRAM or an EEPROM"

• Full citation: U.S. Patent 5,548,741, Fuji Photo Film Co., Ltd., filed/priority 1991-02-07, published 1996-08-20.
• Description: An IC memory card system in which the host processor can operate with a card carrying either SRAM or EEPROM. (Title-derived.)
• § 102 analysis: Because it published 1996-08-20 — less than one year before the 1997-11-14 filing — it is not § 102(b) art; it is § 102(a) art only to the extent it predates the invention date. It maps, at most, to the interface environment of claim 7 and as background for memory-card systems. No anticipation of any claim.

(9) US 5,862,075 A — "Device for protection after a page-write operation in an electrically programmable memory" ★ relevant; § 102(e) only

• Full citation: U.S. Patent 5,862,075, SGS-Thomson Microelectronics S.A., filed 1996-11-28, published 1999-01-19.
• Description: Protection circuitry that acts after a page-write operation in an electrically programmable (EEPROM/Flash-type) memory — i.e., page-level write protection logic. (Title-derived; full text not verified this session.)
• § 102 analysis — important date nuance: This reference published 1999-01-19, after this patent's 1997-11-14 filing, so it is NOT § 102(a) or § 102(b) art. It qualifies only under § 102(e), because its application was filed 1996-11-28, before the '500 applicant's filing/invention date. Any § 102(e) assertion against the '500 claims is therefore available but is limited to what the reference discloses as of its filing date. It is the most relevant cited art to the "page" features — claim 11 (N pages, third bit store with page-enable bits) and claim 17 (block subdivided into N pages, page-enable bits) — and to the page-level checking steps of claim 13. It does not disclose the second (sticky) bit store, the bit-for-bit gating, or the dual write-protect pins. No anticipation of the independent claims; good § 103 art on the page limitations.

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4. Synthesis — the § 102 picture by claim

Independent claims (the real targets):

Dependent claims where a single reference is more directly on point:

• Claim 2/3 (blocks, protection bit per block): US 4,796,235 — strongest single-reference relevance.
• Claim 6 (high-voltage pump enabled/disabled by the second pin): US 4,498,151 + the pump discussion in US 4,796,235.
• Claim 10 (first bit store address space ⊂ array address space): US 5,210,854 (partitioned controller).
• Claim 11 (subdivided block, third bit store): US 5,862,075 (§ 102(e)) and US 5,430,447.
• Claim 12/15 (RF interface): US 5,430,447 — a genuine RF transponder, the best on-point art in the set for the RFID claims.

Ranking of the nine references by relevance to the '500 claims:

1. US 5,430,447 (RF transponder, per-page lock bits, one-way locking) — closest overall.
2. US 4,796,235 (protect register gating writes + independent block protection) — closest on the two-tier/block structure.
3. US 5,862,075 (page-write protection; § 102(e)) — closest on the page features.
4. US 5,210,854 (hardware-partitioned, address-decoded write gating).
5. US 5,047,982 (unlocking sequence required to write an EEPROM).
6. US 5,548,741 (memory card, SRAM/EEPROM) — interface/background.
7. US 5,386,539 (EEPROM card with buffering) — interface/background.
8. US 4,498,151 (on-board programming/high-voltage) — claim 6 background.
9. US 4,905,140 (generic IC device) — lowest-confidence mapping.

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5. What this means practically, and the caveats you must carry forward

1. No clean § 102 anticipation is visible in the cited set. If the object is invalidity, the cited references support an obviousness (§ 103) theory — combining, e.g., US 4,796,235 (protect-register-gated block protection) with US 5,430,447 (per-page, one-way lock bits and RF transponder) to reach the '500's sticky-bit/second-store and page architecture. That is the argument to develop — not a § 102 knockdown.

2. Watch the reference dates in any § 102 chart. Eight of the nine are § 102(b) art (published before 1996-11-14); US 5,548,741 is § 102(a) only (published 1996-08-20); and US 5,862,075 is § 102(e) only (published 1999-01-19, but filed 1996-11-28). Mislabeling US 5,862,075 as "prior art under 102(a)/(b)" would be an error.

3. Intervening-rights / § 102(e) nuance: because US 5,862,075 was copending with the '500 application and published afterward, if it were the primary reference you would also need to address § 102(e) provisos (e.g., common-ownership/§ 103(c) considerations are generally inapplicable here — different assignees — but confirm).

4. Verification limit — stated plainly. I verified the full text/teaching of US 4,796,235, US 5,047,982, US 5,210,854, and US 5,430,447 in this session. For US 4,498,151, US 4,905,140, US 5,386,539, US 5,548,741, and US 5,862,075 I have only the front-page metadata (number, assignee, dates, title), so the descriptions above for those five are title/assignee-derived and low-confidence; the § 102 mappings for them should be re-checked against full text before being relied upon in any filing.

5. The patent is expired (2017-11-14). Any invalidity analysis is defensive/preservation-of-rights only — it cannot support (and does not need to defeat) a live infringement claim for post-2017 conduct. See the litigation and PTAB sections of this analysis: no litigation and no AIA trial ever touched this patent.

6. False positives filtered. Searches surfaced unrelated hits I checked and excluded by literal number — US 7,957,450 (IPR2020-00717, Samsung v. Bell Northern Research), US 7,608,597 (Idenix v. Gilead), US 10,659,885 (Taction v. Apple), and a numeric coincidence in a Korean sequence listing — none of which relate to US 5,974,500.

Primary sources: US 5,974,500 (Google Patents, incl. the cited-reference list); US 4,796,235; US 5,047,982; US 5,210,854; US 5,430,447; EP 0 640 939 A3 (EP counterpart of US 5,430,447). For a court-grade § 102 chart, pull each reference's full text from USPTO Patent Public Search / PatentCenter and confirm the filing-date and § 102 sub-section for US 5,862,075 and US 5,548,741 in particular.

I'll ground this § 103 analysis in the actual prior-art references listed in the patent's Prior Art section. Let me pull details on the key references.

Now let me pull the two references most directly on point for the RFID read-protection and page-write aspects.

Let me check two more references — the Hitachi device and the TI on-board programming patent — to complete the mapping.

Obviousness Analysis — U.S. Patent No. 5,974,500 under 35 U.S.C. § 103

Scope note / cross-reference. This section builds on the previously generated Summary, Litigation, PTAB, and Strategic sections and does not repeat them. Two of their findings frame everything below: (1) the patent is expired (2017‑11‑14) and never challenged in any AIA trial, so all 17 claims stand exactly as issued and there is no estoppel against anyone raising § 103 grounds; and (2) the only "proceedings" in which it appears at all are examination-stage prior-art citations in other people's patents. Because there is no adversarial record, this § 103 analysis is necessarily a de novo construction-and-mapping exercise, not a critique of anyone's earlier brief.

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1. Framework and evidentiary limits

• Governing law. Application 08/971,117 was filed 1997‑11‑14, before the AIA's 2013‑03‑16 effective date. This is a pre‑AIA § 103 case; §§ 102/103 as amended do not apply. The controlling test is Graham v. John Deere, 383 U.S. 1 (1966): scope/content of the prior art, differences from the claims, PHOSITA level, and secondary considerations — with KSR Int'l v. Teleflex, 550 U.S. 398 (2007), supplying the explicit "combination of familiar elements according to known methods," "obvious to try," and "design incentive / predictable variation" rationales.
• What counts as "the Prior Art section." On the Google Patents page for US5974500A the printed prior-art content is the "Citations (9)" block, i.e., the references the Examiner applied against this patent. That is the universe the task directs me to use. Three cautions on the page's other "prior-art-looking" material:
  1. "Cited By" is not prior art. The 52–126 forward citations (US6154819, US6446179, US7275128, etc.) all post-date 1997 and are irrelevant to § 103.
  2. "Similar Documents" is not prior art. US5991197, US5826007, US6229731, US6034889, US5890191 are all later filings.
  3. The family members are not prior art against the patent. WO1999026253A1, EP1029326B1, JP2003532962A, etc. share the 1997‑11‑14 priority and are the same invention in other jurisdictions.
• One gap I must flag honestly. A final verification search for US 4,498,151 returned nothing usable before my search budget was exhausted. I therefore describe it only at the level of its printed title/assignee/date and mark its specific disclosure "not independently verified" rather than invent content for it. Everything else below is grounded in retrieved text.

The nine references, with § 102 status as of 1997‑11‑14

That last line matters: US 5,862,075 is § 102(e) art, available only as of its 1996‑11‑28 filing date, and it cannot be § 102(a) or (b) art. Any § 103 ground that needs it as the primary reference is correspondingly more fragile than one built on the eight § 102(b) references.

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2. Level of ordinary skill (PHOSITA)

A bachelor's degree in electrical engineering (or equivalent) plus 2–3 years designing non‑volatile memory and memory controllers, including familiarity with: EEPROM/FLASH cell programming and the high-voltage pump that programs them; the then-standard software data protection (SDP) instruction protocol; write-enable gating; power-transition data-corruption failure modes; and the memory requirements of smart cards and RFID transponders. This is a mature, crowded, incremental art — the KSR posture is unfavorable to the patent, because essentially every element is a known building block being rearranged.

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3. What each reference actually teaches (retrieved text)

US 4,796,235 (Motorola) — the closest single reference. Retrieved text establishes it discloses:

• a protect register holding "particular, predetermined data," plus "write protect means for allowing writes to the PROM if and only if said protect register means contains" that data — i.e., a first store whose content gates write access to the array;
• timer means allowing that data to be written into the protect register "only within a predetermined time of the occurrence of a predetermined event" — i.e., a second control that gates writes to the first store, reset by an event;
• an express object: "independent write protection for a plurality of independently write protectable blocks of PROM" — i.e., one protection bit per block;
• and an express discussion of the prior art it improves on, including U.S. 4,580,246 ("writes to the control registers are allowed only once, and only within a short, predetermined time after the system is reset. After that period, no writes are allowed until the system is reset again").
  Source: patents.google.com/patent/US4796235

US 5,047,982 (Caterpillar) — EEPROM write-enable gating; teaches that the simple write-enable signal "dramatically reduces the likelihood of an inadvertent EEPROM write; but… it is still possible for the stored data to be accidentally overwritten," motivating extra protection. Source: patents.google.com/patent/US5047982A/en

US 4,905,140 (Hitachi) — a voltage-level detector on an external terminal Vpp that discriminates write/read modes and gates the high voltage to the EPROM, plus an address discriminator that inhibits the write operation and returns a blank for addresses outside the protected area. Source: patents.google.com/patent/US4905140

US 5,430,447 (TI Deutschland) — a batteryless RF transponder with:

• EEPROM "organized in blocks" with a Page Address and per-page Read/Selective-Read/Program/Lock commands;
• a "Selective Addressing" comparator whose failure to match causes the transponder to discharge and refuse to respond — i.e., denial of read to unauthorized users;
• and, critically, a Segment Code "protected by storing [it] in an EEPROM 26 which can be locked (fixed) using another EEPROM cell. Programming or locking functions are provided for the EEPROM cell, but no function is provided for unlocking the EEPROM cell."
  Sources: patentimages…US5430447.pdf; zhuozou.cn.uspto.report/patent/grant/5430447

US 5,862,075 (SGS‑Thomson) — a page-write plus write-protection instruction for EEPROM-compatible FLASH; after all page registers are loaded, a protection cell 8 containing "the SDP write protection bit" is programmed, and "this cell is identical to a storage cell of the matrix 5," the SDP bit thereafter "indicat[ing] that the memory is protected and prohibit[ing] writing in the memory." Source: patents.google.com/patent/US5862075A/en

US 4,498,151 / US 5,210,854 / US 5,386,539 / US 5,540,741 — secondary; supply the microcontroller-EEPROM programming context (TI), fail-safe EEPROM program updating via a new location and updated transfer vector (DEC — the closest analogue to the patent's "access protection page" that is itself rewritten), and memory-card data/address buffering and host-interface context with SRAM-or-EEPROM selectability (Fuji). These are support references for the interface claims (7) and the "portion of the array stores the access information" claim (14), not primary references.

Supplemental art I located but which is outside the nine and therefore flagged separately. The Hitachi family around US 4,920,518 (and its EP counterpart EP0283238) discloses "a **protecting data memory element for storing at least one-bit protection data … disposed in the matrix. Whether operations such as programming (i.e., writing), erasing or reading … will be allowed or inhibited is determined in accordance with the contents of the protecting data memory element," expressly for "each of the plurality of divided relatively small areas." That is direct teaching of per-area read-and-write protection from a protection bit. It is not in the patent's cited set, so § 325(d) does not shield the patent against it. Source: patentimages…US4920518.pdf

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4. Claim element → prior art mapping

The load-bearing elements of the independent claims are (a) a first store of access-control info that gates array access; (b) a second control gating writes to that first store; (c) a one-bit-per-bit correspondence between the two stores; (d) two distinct external pins, one soft/resettable and one that kills all writes; and (e) a third store at the page level.

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5. The § 103 grounds

Ground 1 — Claims 1, 2, 3, 4, 5, 6, 16: US 4,796,235 in view of US 4,905,140 (and optionally US 5,862,075)

Why combinable. Both are non-volatile-memory write-protection references in the same field, and US 4,796,235's own background section frames the problem — inadvertent writes during power transitions and loss-of-control program execution — that US 4,905,140 addresses by hardware gating.

The mapping. US 4,796,235 supplies the entire two-tier structure: a protect register whose contents gate writes to the array (first store + first control means), a timer means gating writes into that protect register (second control means + second store), and an express object of independent per-block protection (claims 2, 3). Its protect register is therefore already "a bit store" with one protection bit per block. US 4,796,235 even expressly describes the prior-art U.S. 4,580,246 approach — writes to a control register allowed once, only within a window after reset, and not again until the next reset — which is the "sticky-bit" behavior of claims 1/4/5 in everything but name, and which US 4,796,235 identifies as the starting point for its own improvement. US 4,905,140 adds the second pin: an external terminal (Vpp) whose level is detected and used to disable the write mode and gate the programming high voltage (claims 1, 6).

Motivation / KSR rationale. (i) Both references address the identical problem of unauthorized or inadvertent writes to reprogrammable non-volatile memory. (ii) US 4,796,235 explicitly states the reason for the extra tier — the simple write-enable is insufficient (a point echoed verbatim in US 5,047,982). (iii) Combining a windowed/timed software lock with a hardware pin-level lock is the paradigmatic "arrangement of old elements, each performing the same function it was known to perform, yielding no more than predictable results" — the KSR "familiar elements according to known methods" rationale. (iv) Where the claims require per-block bits, US 4,796,235's own stated object supplies them, so no cross-art leap is even needed for claims 2–4.

Ground 2 — Claims 7, 8, 12, 15: Ground 1 further in view of US 5,430,447

Why combinable and what it supplies. US 5,430,447 is an RFID transponder — the exact application the patent's FIG. 5 describes — and it discloses a block/page-organized EEPROM with a Page Address, per-page Read/Selective-Read/Program/Lock commands, and read denial (discharge) to unauthorized interrogators. It thus supplies the RF interface (claims 8, 12, 15) and, for claim 7, the serial/contactless interface. US 5,386,539 / US 5,540,741 supply the alternative card-based host interface and the data/address buffering that the patent's data store 108 implements.

Motivation. The patent's own background states that RFID tags "usually have some sort of write protection capability and read access control," and that prior password-gated read control "result[s] in a bulky device." US 5,430,447 is literally that prior art, and its stated motivation is to achieve access control "while still obtaining a low cost, manufacturable device" — i.e., the same design objective (compactness) the patent asserts. That is an express, articulated reason to combine. A PHOSITA implementing the US 4,796,235 protection scheme in a transponder would place the protection register bits in the transponder's EEPROM and expose the gate through the existing RF front end — a predictable use of a known technique in the field the technique was designed for.

Ground 3 — Claims 9, 10, 11, 17: US 4,796,235 + US 5,862,075 + US 5,430,447, and, for the read-protection element, supplemental US 4,920,518

Claim 9 adds three things over claim 1: (a) read and write control per block; (b) an addressable first store whose address space is a subset of the array (claim 10); (c) page-level subdivision with a third store (claim 11).

• (a) Read and write from the same bits is taught squarely by US 4,920,518 ("whether a programming (writing), erasing or reading … is allowed or inhibited is determined in accordance with the contents of the protecting data memory element"), and in weaker form by US 4,905,140's address discriminator (blanks reads) and US 5,430,447's Selective Read discharge. Note the § 325(d) implication: US 4,920,518 is not among the nine references of record, so it is not merely cumulative and is not exposed to discretionary denial.
• (b) The protection store being addressable and inside the array's address map is taught by US 5,862,075: the SDP cell "is of same type as the memory cells providing the memory array" and "can be located anywhere in the memory," and by US 4,796,235's register mapping.
• (c) Page-level protection with a separate enable bit is taught by US 5,862,075's page-write-then-protect instruction and by US 5,430,447's Page Address architecture. The patent's claim 11 ("at least one of the memory blocks is subdivided into N pages … third bit store having N page enable bits") is a straightforward application of US 5,862,075's page concept to US 4,796,235's independently-protectable blocks.

Motivation. The combination is a two-dimensional refinement (block × page) of a known one-dimensional protection scheme, each dimension independently known in the art, producing the expected benefit (finer-grained protection) with no surprising result. Claim 17 is claim 9+11 with the dual-pin limitation, which Ground 1 already supplies.

Ground 4 — Claims 13, 14: Method claim over US 4,796,235 + US 4,920,518 + US 5,862,075 (+ US 5,430,447)

Each step of claim 13 maps to a reference teaching:

1. Detect permission-bit state on read request and perform if permitted → US 4,920,518 (read inhibited per area based on the protection element); US 5,430,447 (Selective Read denial).
2. Detect permission bits on write request → US 4,796,235 ("if and only if"); US 5,862,075 (SDP prohibits writing).
3. Divide into blocks with non-volatile permission bits; operate per block → US 4,796,235 (independent blocks) + US 5,862,075 (SDP cell is a non-volatile cell of the array).
4. Update permission bits only if the associated access information is at a first logic state → US 4,796,235 timer means (protect register writable only within its window).
5. Access information may only change from first to second logic state (one-way) → US 5,430,447 ("no function is provided for unlocking the EEPROM cell"); and the volatile, reset-restorable variant in US 4,796,235's discussion of US 4,580,246.
6. Reset access information to first state on POR or on asserting a protection pin → US 5,430,447 (power-on-reset initializes the CRC/segment logic); POR and reset-pin initialization are ubiquitous.
7. Subdivide a block into pages with non-volatile page permission bits checked per request → US 5,862,075 page-write protection.
8. Claim 14 (allocate array space to the access information) → US 4,796,235/US 5,862,075 (cell inside the array).

Motivation. Steps 5–7 read like a straightforward restatement of the references' own instruction protocols; a PHOSITA would combine them to obtain the very benefit the patent's background recites (protection against inadvertent and unauthorized read/write in EEPROM/smart-card/RFID contexts).

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6. The real battleground — and the strongest non-obviousness arguments

A candid § 103 opinion must identify what the Examiner presumably relied on for allowance, because that is where the patent is hardest to kill with these nine references:

1. The strict one-bit-per-bit correspondence between the two stores. While US 4,796,235 gives per-block protection bits and a separately-gated protect register, and US 5,430,447 gives a lock cell locking a data cell, no single one of the nine references clearly shows a second, one-bit-per-block store whose individual bits gate the writing of the corresponding individual first-store bits. This is almost certainly the feature that distinguished the claims. A challenger must therefore run a true combination argument (US 4,796,235's per-block register bits + its windowed-reset control register of US 4,580,246 + US 5,862,075's self-protecting cell) and must articulate why a PHOSITA would map the two stores one-to-one — the mapping is a natural, in fact compelled, way to preserve the per-block independence US 4,796,235 already claims as its object, but it is not literally spelled out.
2. Volatile / reset-to-enable vs. irreversible lock. US 5,430,447's lock cell is expressly irreversible; the patent's sticky bits reset to the enabling state on POR or WP2 LOW. A patent owner could argue US 5,430,447 teaches away from a resettable store. This is blunted — decisively, in my view — by US 4,796,235's own description of US 4,580,246's reset-restorable, once-per-cycle writable control register, which is the sticky-bit behavior and is described as known and desirable for exactly this purpose. But the counter-argument is real and a petitioner must address it head-on.
3. The dual-pin division of labor (a resettable soft pin WP2 that enables the second store, versus a hard WP1 that kills all writes including to the second store). US 4,796,235's single timer event and US 4,790,982/US 4,905,140's single write-enable style each cover only part. This is a classic "arrange two known locking mechanisms at two levels" argument that will be won on the KSR "predictable results" rationale, but it is not slam-dunk literal anticipation.
4. Claim-drafting ambiguity (a genuine construction problem for any § 103 attack). Independent claim 1 recites that the first pin sets the second store to a first logic state, yet permits writes only when the corresponding bit is at a second logic state. Independent claim 9 uses the opposite, and internally coherent, convention: writes enabled when the second-store bit is at the first logic state; the WP2 pin sets it to that first level on assertion LOW; the WP1 pin drives it to a second state. Read against the specification — WP2/POR set the sticky bits to logic 1, and "a protection bit can be written only if its corresponding sticky bit is set to logic '1'" — claim 1's "second logic state" appears inverted relative to claim 9 and the spec. Per the operating rule I will not auto-correct it; I flag it, because § 103 mapping is impossible without first construing these terms, and this inconsistency materially affects how (or whether) claim 1 can be met by art in which the enabling state is fixed. Expect the claim-construction fight before the obviousness fight.
5. Claim 16 and 17 are effectively re-issues of claims 1–4 and 9+11. Claim 16 = claim 1 + claims 2, 3, 4. Claim 17 = claim 9's elements + claim 11's third bit store + the second WP pin. They inherit the same weaknesses and the same attacks; a challenger should not treat them as independent redoubts.

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7. Bottom line

• Using only the nine references in the patent's printed Prior Art section, a legally sufficient § 103 case can be assembled for all five independent claims and most dependents, with US 4,796,235 as the structural primary reference, US 4,905,140 / US 5,047,982 supplying the hard write-protect pin and high-voltage gating, US 5,862,075 supplying page-level protection with a self-protecting non-volatile cell inside the array, and US 5,430,447 supplying the RFID/RF-interface and read-denial elements.
• The weakest link in any ground built on that set is the strict one-bit-per-bit second store, which is very likely why the claims issued. Adding US 4,920,518 (Hitachi) — not of record, therefore free of § 325(d) risk — substantially closes that gap, because it expressly discloses per-area, non-volatile protection data controlling read as well as write/erase.
• Nothing in the record helps the patent owner beyond the claims themselves. There is no PTAB construction, no litigation, no secondary-considerations evidence (no commercial-success or licensing nexus appears anywhere in the file), and the patent expired 2017‑11‑14. Absent objective indicia, this is a pure Graham/KSR exercise, and the art is old, crowded, and squarely on point.
• Two caveats I will not paper over. (a) US 5,862,075 is § 102(e)-only art, so any ground that leans on it as the primary reference is weaker than a US 4,796,235-anchored ground. (b) US 4,498,151's disclosure is not independently verified in this session — do not rely on it without pulling the document. (c) As flagged in earlier sections, the task header date (2026‑04‑26) and the environment/fetch timestamps (2026‑09‑30) disagree; this does not affect the analysis.

Primary sources: US5974500A (claim text, spec, and the nine-reference Citations block); US4796235; US4905140; US5047982A; US5430447 and uspto.report copy; US5862075A; supplemental US4920518.