US 5619123

I'll search for this specific patent number across USPTO and court docket sources.

Let me run a couple more targeted searches to confirm whether any litigation or 2026 CAFC docket activity exists for this specific patent.

Searches performed

I ran targeted queries against public patent databases (Google Patents, Justia, EveryPatent, Google Patents sitemap) and against the CAFC scheduled-cases listing and 2026 PTAB/CAFC activity summaries for the literal string "5619123" / "5,619,123", restricted to US patent 5,619,123. No litigation, IPR/PGR, or CAFC docket activity involving US 5,619,123 was found. I have no direct authenticated USPTO PatentCenter/PAIR API access in this session, so treat the "no litigation" finding as a well-supported negative rather than an exhaustive court-records check. Below is my summary, grounded primarily in the authoritative patent text you supplied.

US 5,619,123 — Summary

Abstract (as published): A power supply circuit for an NTL circuit includes a monitoring circuit, a reference circuit, and a comparing and regulating circuit. The monitoring circuit outputs a monitor voltage substantially proportional with a first factor to a voltage variation between an NTL lower voltage and an NTL higher voltage. The reference circuit outputs a reference voltage substantially proportional with a second factor to the voltage variation. The comparing and regulating circuit compares the monitor and reference voltages and regulates the NTL lower voltage so it equals a predetermined voltage.

Prior art cited: JPS59115618A; US5126597; US5160857; JPH0439806; JPH0439805; US5187391; US5089724; EP0584471A2; US5341042.

Plain-language overview of the independent claims

Claim 1 — the circuit (apparatus)
A power supply circuit for an NTL chip containing many NTL gates. It has three blocks:

1. Monitoring circuit — produces a "monitor" voltage that scales with (a first factor ×) the change in the chip's internal lower supply voltage (V_EE on line 6) relative to the external higher supply (V_CC, line 2) and external lower supply (GND, line 4). In the embodiment, this is a replica ("dummy") NTL inverter built from transistors T1–T3 and resistors R1–R5, whose emitter-follower output equals an NTL gate's logic-low output.
2. Reference circuit — produces a reference voltage that scales with (a second factor ×) the same variation. Embodiment: constant-current source 12, diode D1, transistor T4 (emitter to V_EE), and a resistor divider R6/R7 tapping V_BE.
3. Comparing and regulating means — compares the two voltages and drives the internal lower rail (V_EE) to a fixed target value (negative feedback).

Key point: because the monitor is a replica of an actual NTL gate and the reference tracks the base-emitter voltage V_BE, the regulated internal rail stays correct across temperature and supply drift, keeping the NTL logic-low level inside the window demanded by equations (2)–(4).

Claim 12 — the method
A method of regulating the NTL higher/lower supply voltages, comprising: (i) monitoring the logic-low voltage of a dummy NTL gate circuit to generate a monitor voltage that tracks the variation between the NTL lower and higher voltages; (ii) generating a reference voltage; and (iii) regulating the NTL lower voltage to a predetermined value based on the difference between them.

Claim 16 — the semiconductor integrated circuit
An IC that includes an NTL circuit plus its own on-chip regulator, comprising: (a) a dummy NTL gate circuit that always outputs a logic low; (b) output means producing a monitor voltage derived from that logic-low output and representing the variation between the NTL lower and higher supply voltages; (c) a reference circuit generating a reference voltage; and (d) regulating means that forces the NTL lower voltage to a predetermined value based on the monitor-vs-reference difference.

Notable dependent claims: claim 5 (specific T1/T2/T3 + R1–R5 topology; monitor scales as r1/r2); claim 6 (specific reference topology: current source, diode D1, transistor T4, divider R6/R7); claims 7–8 (T4's V_BE and the constant current matched to the NTL gates' transistors for higher precision); claim 9 (diff-amp + N-channel MOS pass device — better when V_EE-to-GND headroom is small); claim 10 (diff-amp + NPN bipolar pass transistor with base resistor R10 — smaller area, per the second embodiment); claim 11 (regulator and NTL circuit on the same chip).

Uncertainties and caveats

• No CAFC 2026 docket entry or litigation found for US 5,619,123. Absence of a hit in my searches is not proof of no litigation; a PACER/docket-level search would be needed to be certain.
• Number-collision caution: searches for "5619123" also surface an unrelated Japanese patent JP 5619123 B2 (Yagi Seisakusho K.K.; wind turbine / wind-power generator; filed 2012, registered 2014). This is a different patent office and a completely different invention — it must not be conflated with US 5,619,123. I have interpreted numbers literally and made no correction or merging.
• Details of the German counterpart (DE19536829C2) and Japanese counterpart (JP2679644B2) are from the Google Patents family listing; I did not independently verify their full texts.
• The patent's own text contains apparent typographical errors (e.g., "tt is desirable," and inconsistency in the r1/r2 vs. r2/r1 ratio between equations (5)/(6) and claim 5). I have quoted the identifiers literally and not "fixed" them.

I'll search for litigation involving US patent 5619123 across patent litigation databases.

Initial searches returned mostly irrelevant results. Let me search the specific litigation databases.

Litigation Search Results: U.S. Patent No. 5,619,123

Bottom line: I found no evidence of any litigation (district court, ITC, CAFC, or PTAB) involving U.S. Patent No. 5,619,123.

What the patent is

• Patent: U.S. 5,619,123 — "Power supply circuit for non-threshold logic circuit"
• Inventor: Hitoshi Okamura
• Assignee: NEC Corporation
• Application: US 08/533,835; filed 1995-09-25; priority 1994-10-03 (JP 6-238801)
• Granted: 1997-04-08
• Status: Expired – Fee Related (lapsed 2005-04-08 for nonpayment of maintenance fees under 37 CFR 1.362)
• Family: JP 2679644B2 (JP 6-238801), DE 19536829A1/C2

Searches performed and what they returned

Identifiers I deliberately did not merge (per instructions, IDs are read literally):

• JP 5619123 B2 — a 2014 Japanese patent on wind turbines (Yagi Seisakusho). This is not the same document as U.S. 5,619,123 and is not a patent-in-suit in any U.S. matter I could locate.
• The "5619123" appearing in a Lithuanian company registry extract is a coincidental data string, not a patent.

NEC litigation context (for completeness — none involve '123)

NEC has been active in patent litigation (e.g., Lone Star Technological Innovations, LLC v. NEC Corp., 6:17-cv-00687 (E.D. Tex.), dismissed with prejudice Jan. 2019; NEC Corp. v. Peloton Interactive, Inc., 1:22-cv-00987 (D. Del.); NEC Corp. v. YI Technologies, 2:24-cv-00722 (E.D. Tex.); NEC Corp. v. Anker, 2:26-cv-00847 (E.D. Tex.)), but none of these assert U.S. 5,619,123, and the '123 patent expired in 2005 — well before any current NEC campaign. As an expired patent, it could not support an infringement action for post-expiration activity beyond the 6-year damages lookback window.

Caveats

• I could not directly query PACER, Docket Navigator, or the Unified Patents litigation portal (they require subscription/authentication), so this is a search-engine-level finding rather than a full commercial-database check.
• Coverage of 1990s-era litigation in public web sources is generally incomplete. The patent's short enforcement life (1997–2005) and its expiration without reported assertion make litigation unlikely, but I cannot state with certainty that no suit was ever filed. I did not find one, and I am not aware of one.

Recommendation for a definitive answer: run the patent number in Docket Navigator or Lex Machina, or the USPTO Patent Center "Litigation" tab, which index complaints and CAFC records directly.

Proceedings overview

Total AIA trial proceedings on file for US 5,619,123: zero — no Inter Partes Review, no Post-Grant Review, and no Covered Business Method review has ever been filed against this patent (0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution denials), which leaves every one of claims 1–19 fully intact and completely untested at the Board — meaning a defendant gets no PTAB-based shortcut whatsoever and must litigate or license on the merits (or attack the patent some other way), while the patent owner faces no § 315(e)(2) estoppel and no cancelled claims to worry about.

The canonical list from the structured "PTAB proceedings on file" block (USPTO Open Data Portal) is empty, and my independent web searches — Google Patents, USPTO PTACTS/PTAB E2E indexed petition documents, PTAB litigation-center reports, CourtListener/CAFC RECAP, and docketalarm derivatives — surfaced no proceeding number referencing this patent. I did not invent any proceeding numbers to fill the gap.

Proceeding-by-proceeding detail

None. There are no proceeding numbers, panels, institution decisions, Final Written Decisions, settlements, or appeals to report for US 5,619,123. The instructions require me not to fabricate proceeding numbers, and the structured source list is empty, so this section is deliberately blank rather than populated with speculation.

Strategic summary

Claim status: nothing is canceled. Every claim is UNTESTED. Claims 1, 12, and 16 (the independents) and dependent claims 2–11 (including the T1/T2/T3 replica-inverter topology of claim 5, the constant-current/diode/T4 divider reference of claim 6, the NMOS pass-device claim 9, the NPN pass-device claim 10, and the same-chip claim 11) and 13–15 and 17–19 have never been construed by the Board, never been the subject of an institution decision, and never been held unpatentable. There is no "claims 1–5 are dead" argument available to a defendant here — that fact pattern does not exist for this patent.

Estoppel landscape: empty, in both directions. Because no IPR/PGR ever reached a Final Written Decision, § 315(e)(2) and § 325(e)(2) estoppel never attached to anyone. A current defendant is not carrying any petitioner-side estoppel, and, symmetrically, the patent owner has not obtained any confirmatory Board rulings that would pre-empt or narrow a district-court invalidity case. Any prior-art challenge — including the art already listed on the face of the patent (JPS59115618A; US 5,126,597; US 5,160,857; JPH0439806; JPH0439805; US 5,187,391; US 5,089,724; EP 0 584 471 A2; US 5,341,042) — remains fully available in litigation, unconstrained by any Board ruling or estoppel. Note the 1997 grant date means the AIA § 102/§ 103 framework does not apply; validity would be judged under pre-AIA §§ 102/103.

Pattern signals: the absence of any PTAB activity is itself the signal, and here it has a structural explanation rather than a litigation-driven one. Three structural facts explain why a zero count is unsurprising: (1) the patent lapsed on 2005-04-08 for failure to pay maintenance fees, roughly seven years before the first AIA petitions were even filed (AIA trials became available 2012-09-16); (2) PGR under §§ 321–329 is unavailable for a patent with a 1994 priority date, because PGR requires a first-inventor-to-file effective filing date on or after 2013-03-16; and (3) CBM review (available only for "covered business method" patents, and subject to an eight-year sunset under § 18 of the AIA that ended 2020-09-16 for new petitions) has no application to a 1990s bipolar NTL power-supply regulator. In other words, this is not a "hardened patent that survived attacks" — it is a dead patent that was never worth attacking. There is no serial-petitioner pattern, no defensive-aggregator (e.g., Unified Patents) involvement in the chain, and no patent-owner appeal activity, because there was never a proceeding to appeal.

Recommended next steps

1. If you are a defendant facing an assertion of US 5,619,123: there is no PTAB record to exploit, and you cannot get one now. No FWD exists to cite and no claim has been canceled. Do not represent to a court or counterparty that any claim has been invalidated by the Board — that would be a misstatement of the public record.

2. Lead with the expiration and lapse facts. The patent's legal-status record shows expiration due to nonpayment of maintenance fees, effective 2005-04-08, under 37 CFR 1.362 (noted at 2005-05-12 and 2005-06-07 in the ODP legal events; anticipated expiration 2015-09-25). An expired/lapsed patent cannot support infringement liability for post-lapse activity, and damages are in any event limited by the six-year lookback of 35 U.S.C. § 286 measured from the complaint. Verify the precise lapse/expiration position against the current Patent Center maintenance-fee record at https://patentcenter.uspto.gov before relying on it in a filing.

3. Verify the negative PTAB finding directly before you commit to it. Confirm on PTAB E2E (https://ptacts.uspto.gov/ptacts/) and via the USPTO Open Data Portal proceedings endpoint for application 08/533,835, and check CourtListener (https://www.courtlistener.com) for any CAFC appeal with this patent number. My searches were search-engine and public-document level; the ODP ingest can lag, and I could not authenticate into PACER/Docket Navigator/Lex Machina this session. Note also that the structured ODP block covers AIA trials only — it does not by itself rule out a pre-AIA ex parte or inter partes reexamination. If you need absolute certainty on that point, pull the file history (CRU/Patent Center "Reexamination" and "Litigation" tabs).

4. If the file history is clean, the merits attack is a district-court-only fight. Without an IPR, your invalidity case under pre-AIA §§ 102/103 must be built on the patent's own cited art plus whatever you can find from the 1994–1995 era, and you carry the clear-and-convincing burden. Commission a focused prior-art search on bipolar NTL replica-bias / V_EE regulator circuits as of 1994-10-03, the JP 6-238801 priority date, since the monitoring-circuit-plus-reference-comparator architecture in claim 5/claim 6 will be the natural target.

5. No estoppel math to do. Since no petitioner ever reached an FWD, there is no § 315(e)(2) bar to work around for any party. Conversely, if you are advising the patent owner, understand that the complete absence of Board validation means there is no "the PTAB upheld claim X" talking point for licensing negotiations, and there is no stay leverage to argue from.

Caveats, stated plainly: (a) The proceeding count of zero is taken from the structured USPTO ODP block supplied as canonical; my web searches are corroborative but not a substitute for a docket-grade query; (b) I found no pre-AIA reexamination either, but I cannot certify that none exists without a CRU/file-history pull; (c) ignore any hit for "JP 5619123 B2" (Yagi Seisakusho, wind turbine, registered 2014) — that is a different patent office and a different invention, and must not be conflated with US 5,619,123.

I'll verify the assignment chain for US 5,619,123 against public sources before reconstructing the record.

Assignment & Ownership Reconstruction — US 5,619,123

Sources actually consulted: Google Patents legal-events table for US5619123 (which mirrors USPTO assignment metadata), PlainSite's mirror of USPTO assignment records (plainsite.org/profiles/okamura-hitoshi/), Justia Patents, and the patent front page (US5619123 PDF). I do not have authenticated API access to the USPTO Assignment Center in this session, so reel/frame below is taken from the recorded event string published in those mirrors rather than re-queried live. Verify at the Assignment Center search page linked in the Verdict.

Headline finding: there is exactly one recorded assignment in this chain — the original inventor→employer assignment. No post-issuance transfer of any kind appears in the record.

Inventors

Pattern check — departures/fire-sale precursor: No evidence in the record of the "all inventors out the door within 12 months" pattern. A single inventor assigning to his employer as a condition of employment is the ordinary case, and no subsequent chain exists to be explained by inventor attrition. Not present.

Cross-reference observation (flagged, not merged): A second recorded assignment exists under the name "Okamura, Hitoshi" — Okamura, Hitoshi → NEC Corporation, Patent Assignment 10570/953, paperwork executed 2000-01-28, recorded 2000-02-14, correspondent Norman P. Soloway, Hayes Soloway, PC, 175 Canal St., Manchester NH 03101, covering application 09/503,933 / US 6,510,549 ("Method Of Designing A Semiconductor Integrated Circuit Device In A Short Time"). That instrument does not name US 5,619,123. I cannot confirm from the record whether it is the same individual (a serial NEC inventor) or a namesake; I am treating it as a different matter and not folding it into this patent's chain. Per the operating rule on literal identifiers, no correction or merging has been applied.

Original assignee

NEC Corporation — named as assignee on the issued patent and on the only recorded assignment; the front page (US5619123 PDF) and Google Patents "Current Assignee" both list NEC Corp, original assignee NEC Corp.

• Primary line of business: Diversified electronics/IT — semiconductors (bipolar, BiCMOS, and CMOS ASICs), computers/mainframes, telecommunications and network equipment. The NTL (non-threshold logic) family at issue is a bipolar/BiCMOS logic style that NEC used in high-speed LSI of the mid-1990s.
• Did they ship a product embodying the claims? Not determinable from the assignment record. The specification is written as an on-chip regulator for an NTL LSI, and the claims recite "said power supply circuit and said NTL circuit are formed on the same chip" (claim 11, and the claim-16 "semiconductor integrated circuit" genus). NEC was a merchant supplier of bipolar/BiCMOS ASICs in this era, so a commercial embodiment is plausible, but I have no verified product-level evidence tying a shipped NEC part to these claims, and I am not going to infer it from the patent text alone.
• Current status: Operating. NEC Corporation remains a listed, active company (Tokyo Stock Exchange, securities code 6701); it did not undergo a Chapter 7/11 liquidation and did not sell this patent in any recorded proceeding. Its semiconductor business was subsequently reorganized (spun off as NEC Electronics in 2003, merged into Renesas in 2010), but no assignment of this patent to NEC Electronics or Renesas was ever recorded, and no such transfer appears in the legal-events table.

Assignment timeline

One entry. The record is otherwise empty of conveyances.

• 1995-09-08 (executed) / recorded 1995-09-25 — Reel 007704 / Frame 0179
  • Conveyance: Assignment — of assignor's interest ("ASSIGNMENT OF ASSIGNORS INTEREST")
  • Assignor: Hitoshi Okamura (sole)
  • Assignee: NEC Corporation (Japan)
  • Correspondent: Not exposed in the sources available to me. The Google Patents legal-event string and the PlainSite mirror both publish only "ASSIGNMENT OF ASSIGNORS INTEREST; ASSIGNOR: OKAMURA, HITOSHI; REEL/FRAME: 007704/0179; Effective 19950908" — no attorney/agent of record field. A live Assignment Center pull would be needed to capture the correspondent name for this recording. I will not guess it.
  • Context: Ordinary inventor-to-employer assignment of a patent application, executed ~2 weeks before the 1995-09-25 US filing and ~4 weeks before the 1994-10-03 JP priority date's aftermath. Not a fire-sale, reorg, securitization, or transfer-to-asserter.

No other conveyances are recorded on this patent. Fee/maintenance events are not assignments and are listed below only to show the chain was never touched again:

Because the only recorded instrument is the original inventor→employer assignment, I am stating plainly: there are no post-issuance records. That is itself the finding — it means the patent was held by NEC from filing until it lapsed in 2005, and was never sold, securitized, or moved into a licensing vehicle.

Timeline diagram

timeline
    title Ownership of US 5619123
    1994 : Japan priority application filed
    1995 : US application filed by NEC
         : Assignment executed by Okamura
         : Recorded reel 007704 frame 0179
    1997 : Patent issued to NEC
    2000 : Fourth year maintenance fee paid
    2004 : Maintenance fee reminder mailed
    2005 : Lapsed for nonpayment
         : Patent expired with no further transfer

NPE / troll-pattern signals

Verdict

Insufficient data — strictly because the recorded chain contains only the original assignment, which is the factual definition of this category in the task framing; there is no second link to evaluate. The sole instrument is Hitoshi Okamura → NEC Corporation, executed 1995-09-08, recorded 1995-09-25 at reel 007704 / frame 0179, with no post-issuance conveyance and no correspondent field published. This is the profile of a captive captive-employer patent, not a monetization asset: NEC held US 5,619,123 from filing until it lapsed for non-payment effective 2005-04-08 (37 CFR 1.362), never sold it, never securitized it, and never transferred it into a licensing vehicle — so every one of the eight NPE signals above resolves to not present. If the correspondent of record on reel 007704/0179 is material to another tracked matter, it must be pulled live; I have not fabricated it.

Verification link: https://assignmentcenter.uspto.gov/ (search application 08/533,835 or patent 5619123; the corresponding legacy Assignments-on-the-Web page is https://assignment.uspto.gov/patent/index.html).

Caveats: (a) The reel/frame and correspondent data here come from Google Patents' legal-events table and PlainSite's mirror of USPTO assignment data, not from a direct authenticated Assignment Center query — a live pull is the only way to confirm the correspondent and to rule out any 1995-era recording that never propagated to the mirrors. (b) The 10570/953 Okamura→NEC assignment for US 6,510,549 is a different matter and has not been merged into this chain; identity of the individual is unconfirmed. (c) The unrelated Japanese registration JP 5619123 B2 (Yagi Seisakusho; wind turbine) shares a number-only resemblance and is a different office and invention — deliberately not conflated.

I'll research the cited prior art references for US 5,619,123. Let me run targeted searches.

Let me search for the remaining cited references.

Prior-Art Analysis — US 5,619,123

Confirmation of the searched document

The USPTO record (as mirrored in the authoritative Google Patents text you supplied, sourced from USPTO) confirms the document:

I searched the specific number 5619123 only. I did not merge it with the unrelated JP 5619123 B2 (Yagi Seisakusho; wind turbine, 2014) that appears in generic web results — that is a different office and a different invention.

I could not run an authenticated USPTO PatentCenter/PAIR or Docket Navigator query in this session; the citation set below is taken from the patent's own "Patent Citations (9)" listing, corroborated against USPTO-hosted reference PDFs and Google Patents.

The nine cited references

The patent cites nine prior-art documents (all pre-date the 1994-10-03 priority date):

Statutory note: References 1–7 published more than one year before the 1994-10-03 priority date (eligible under pre-AIA §102(b)). References 8 and 9 published less than a year before the priority date; 9 (a US patent with a 1992 US filing) is also §102(e) art. All are at minimum §102(a)/§103 background.

Per-reference analysis

1. JPS 59115618A — "Power supply circuit in bipolar LSI" (Hitachi)

• Full citation: Japanese unexamined publication JPS59115618A; filed/priority 1982-12-22; published 1984-07-04; applicant Hitachi Ltd.
• Description: Titled a power supply circuit for a bipolar LSI. This is the only cited reference whose subject matter is topically a power supply circuit for a bipolar LSI, placing it squarely in the field of internal supply generation for bipolar logic.
• Claims potentially implicated: Independent claims 1 and 16 (the "power supply circuit" / "regulating means" concept), and claim 11 (on-chip integration).
• Caveat: I could not retrieve the full Japanese text; the title alone does not establish that it discloses (a) a monitor voltage from a dummy NTL gate that is proportional to a supply-volt variation, (b) a reference circuit, and (c) a comparator driving the internal lower rail. Based on title-level evidence it does not appear to anticipate any claim under §102; a full-text review would be required before excluding it.

2. US 5,126,597 A — "High speed IC device employing non-threshold logic circuits…" (Hitachi; Shiozawa et al.)

• Full citation: US 5,126,597 A; priority 1989-07-13; issued 1992-06-30; Hitachi, Ltd.
• Description (from the document): An IC in which NTL, emitter-follower-equipped NTL (EF/NTL), and SPL gates with different drive/load requirements are combined on one chip. Critically, it discloses a "supply voltage producing circuit which includes means for producing said first and second negative supply voltages on the basis of a third negative supply voltage" and its FIG. 11 is a power supply voltage generator providing internal supply voltages for the on-chip blocks.
• Why it's the most relevant cited item: This is the closest citation to the '123 concept of generating internal NTL supply rails on-chip.
• Claims potentially implicated: Claims 1 and 16 (internal NTL supply generation/regulating means), claim 11 (same chip).
• §102 assessment: No anticipation. Even reading FIG. 11 generously, the reference generates/shifts multiple negative rails and matches signal levels between gate types; it does not disclose a monitoring circuit that outputs a monitor voltage proportional (by a first factor) to a variation in the NTL lower voltage, nor a reference circuit outputting a reference voltage proportional (by a second factor) to that same variation, nor a feedback comparator that forces the lower rail to a predetermined value from the monitor-vs-reference difference. Its disclosure is nonetheless the strongest §103 ("suggested the internal-rail-generation" element) art of the set.

3. US 5,160,857 A — "Integratable transistor switch unit of the NTL logic family" (Siemens)

• Full citation: US 5,160,857 A (EP 0 436 876 A3 counterpart); priority 1990-01-11; issued 1992-11-03; Siemens AG.
• Description: An NTL NOT/NOR gate in which MOS transistors are inserted into the emitter current path to reshape the NTL transfer characteristic so it can interface with ECL and other families. Discusses collector resistor RC, emitter resistor RE, MOS devices, and a "variable but constant supply voltage."
• Claims potentially implicated: Claims 2/4 (form of the NTL gate used in the monitor) and 5 (specific transistor/resistor topology) to the extent the monitor is a standard NTL inverter — but the reference is directed at linearizing the gate, not at supply regulation.
• §102 assessment: No anticipation of any independent claim; no monitoring/reference/feedback-regulator structure. Relevant only as NTL-gate-art background and as §103 context for a "replica gate" monitoring arrangement.

4 & 5. JPH 0439806A and JPH 0439805A

• Full citation (as listed): JPH0439806A and JPH0439805A; priority 1990-06-04; published 1992-02-10; Tokyo Electric Co Ltd; Google Patents lists the title as "Elevating device."
• Description — DISCREPANCY FLAGGED: The '123 specification itself states these are the Japanese examined disclosures "JP-B2-Hei4-39805 and JP-B2-Hei4-39806" and describes them as disclosing "conventional methods for setting a reference voltage in a logic LSI including a non-threshold logic (NTL) circuit and an emitter coupled logic (ECL) circuit." That characterization (reference-voltage setting for NTL/ECL LSIs) does not match the "Elevating device / Tokyo Electric Co Ltd" bibliographic listing returned by the databases. I am reporting both literally and not auto-correcting either; this inconsistency should be resolved against the actual JP texts before any reliance.
• Claims potentially implicated (if the specification's characterization is correct): Claims 1, 6, 12, 13, 16, 17 — specifically the reference circuit / reference-voltage generation element.
• §102 assessment: Given the conflict, I cannot make a definitive §102 finding. Even taking the specification's own description at face value, a "method of setting a reference voltage for NTL/ECL logic" would disclose at most the reference circuit element, not the dummy-gate monitoring circuit or the comparing/regulating feedback — so it would appear to be §103 rather than §102 art. I flag this explicitly because I do not have the JP full texts.

6. US 5,187,391 A — "Modified non-threshold logic circuit" (NEC)

• Full citation: US 5,187,391 A (EP 0 465 167 A2 / DE 691 221 84 counterpart); priority 1990-06-29; issued 1993-02-16; NEC Corporation.
• Description: An MNTL basic gate plus an emitter-follower output stage; the pull-down transistor's base is clamped by a clamping transistor and a high-resistance bias resistor and AC-coupled to the OR output, shortening pull-down delay. Operates between a first power-supply line V_CC and a second power-supply line V_EE.
• Claims potentially implicated: It is same-assignee NTL-gate art most relevant to the "NTL gate/output-stage" background and to the emitter-follower T3/R5 monitor stage of claim 5. It uses the V_CC/V_EE rail naming later adopted in the '123 patent.
• §102 assessment: No anticipation of any claim — it is a gate-level circuit, not a supply regulator, and contains no monitor/reference/comparator regulation loop.

7. US 5,089,724 A — "High-speed low-power ECL/NTL circuits with AC-coupled complementary push-pull output stage" (IBM)

• Full citation: US 5,089,724 A (EP 0 487 917 A2 counterpart); priority 1990-11-30; issued 1992-02-18; IBM Corp. (Chuang et al.).
• Description: ECL/NTL circuits using an AC-coupled complementary PNP-NPN push-pull output stage with capacitors coupling an AC pulse to the output transistors. Notably, its dependent claims recite a diode having an anode connected to the base of a first complementary transistor, with series resistors in the biasing network (claim 3), and a current-source means (claims 5–6). This diode-plus-resistor-divider and current-source motif is structurally reminiscent of the '123 reference circuit (diode D1 + R6/R7 divider + constant-current source, claim 6).
• Claims potentially implicated: Claim 6 (reference circuit topology — diode/divider/current source, on a §103 combination theory) and claims 2/4 (NTL gate output stage).
• §102 assessment: No anticipation. US 5,089,724 uses its diode/resistor network to bias an output stage at "cut-in" (nearly-on), not to generate a reference voltage that is compared against a monitor voltage to regulate a supply rail. It lacks the monitoring circuit and comparing/regulating means entirely. Best characterized as §103 art for the reference-divider sub-feature.

8. EP 0 584 471 A2 and 9. US 5,341,042 A — "Low voltage, cascoded NTL based BiCMOS circuit" (IBM)

• Full citation: EP 0 584 471 A2, published 1994-03-02; US 5,341,042 A, issued 1994-08-23; both priority 1992-08-10; IBM Corp. These two are the EP and US members of the same family, so they are one disclosure for prior-art purposes.
• Description: A low-voltage, cascoded NTL-based BiCMOS logic circuit architecture operating at low supply voltage.
• Claims potentially implicated: Background only — claims 1/16 (low-voltage NTL environment motivating internal-rail control) and claim 9 (BiCMOS/MOS-device context).
• §102 assessment: No anticipation of any claim. It addresses low-voltage circuit topology, not internal supply regulation, and discloses neither the dummy-gate monitor nor the reference/comparator loop.

Overall §102 conclusion

No cited reference, on the evidence I could obtain, anticipates any claim of US 5,619,123 under 35 U.S.C. §102. This is consistent with the patent having issued over all nine references. The cited art clusters into two groups that each cover only part of the claimed combination:

1. NTL/ECL gate-design references (US 5,160,857; US 5,187,391; US 5,089,724; EP 0 584 471 / US 5,341,042) — these supply the environment and the replica-gate structure (claim 5's emitter-follower topology; claim 6's diode/divider motif) but nothing about a feedback supply regulator.
2. Internal/power-supply references (JPS 59115618; US 5,126,597) and the reference-voltage-setting references (JPH 0439805/06) — these approach the output-side of the invention (generating an internal rail or a logic-LSI reference voltage) but do not disclose the monitoring circuit that measures a dummy NTL gate's logic-low voltage and produces a monitor voltage proportional to the NTL lower-rail variation, nor the comparing-and-regulating means that closes the loop.

The claimed novelty of US 5,619,123 — a replica ("dummy") NTL gate monitored against a V_BE-based reference and fed back to regulate the internal NTL lower rail — is not disclosed by any single cited document.

Most relevant citations, ranked: (1) US 5,126,597 — internal NTL supply-voltage generation on-chip; (2) JPS 59115618A — power supply circuit for a bipolar LSI; (3) US 5,089,724 — diode/resistor/current-source reference-like biasing network; (4) JPH 0439805/06 — reference-voltage setting for NTL/ECL logic LSIs (subject to the discrepancy note); the remainder are background NTL-gate art.

Caveats and limitations

• Language/full-text limits. I could not retrieve the full texts of the three Japanese references (JPS 59115618A, JPH 0439805A, JPH 0439806A). My §102 characterizations of those three are provisional and, for 0439805/06, rest partly on the '123 specification's own description of them.
• Bibliographic discrepancy (flagged, not corrected). The '123 specification describes JP-B2-Hei4-39805/39806 as reference-voltage-setting methods for NTL/ECL LSIs, whereas the databases return "Elevating device / Tokyo Electric Co Ltd" for the corresponding publication numbers. I have reported both literally.
• No authenticated USPTO API. Citations are read from the authoritative patent text you supplied (sourced from USPTO via Google Patents) plus USPTO-hosted reference PDFs; I did not run a live PatentCenter query.
• Statutory-basis detail. The §102(a)/(b)/(e) categorization above assumes the 1994-10-03 priority date; a different effective filing date would shift which references are §102(b) versus §102(a)/§103 art but would not change the "no complete anticipation" conclusion.
• Not legal advice / not a validity opinion. The §102 mapping is a technical analyst's assessment of the cited record, not a Freedom-to-Operate, validity, or infringement opinion.

I'll ground this obviousness analysis in the actual prior-art references listed on the patent, so let me pull details on the key ones.

Good detail. Let me pin down two more cited references before writing the analysis.

Obviousness Analysis — U.S. Patent No. 5,619,123

"Power supply circuit for non-threshold logic circuit" — Okamura / NEC, priority 1994‑10‑03, filed 1995‑09‑25.

Scope note: This section builds on the prior-generated summary/overview. It uses the references from the "Patent Citations" (Prior Art) section of the Google Patents page. All identifiers are read literally; where the page metadata conflicts with the patent's own description of a reference, I flag it rather than resolving it.

1. Legal standard and level of ordinary skill

Under 35 U.S.C. § 103 / Graham v. John Deere and KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a claim is obvious if the differences between the claim and the prior art would have been apparent to a person having ordinary skill in the art (POSITA) at the time of invention, considering (i) the scope/content of the prior art, (ii) the differences, (iii) the level of ordinary skill, and (iv) secondary considerations. KSR makes clear the motivation can be an explicit teaching, an implied suggestion, or a common-sense/design-incentive rationale, and that a "predictable variation" and "obvious to try" analysis can sustain a rejection.

POSITA (as of the Oct. 1994 priority date): A person with a B.S. in electrical engineering (or equivalent) plus ~2–4 years' experience designing bipolar/BiCMOS analog and logic ICs, or an M.S. with ~1–2 years. That person would be familiar with: the NTL and ECL logic families; the emitter‑follower NTL output stage and its logic‑low level; base–emitter (V_BE) matched‑device reference techniques and bandgap/divider references; differential amplifiers and linear‑regulator/MOS‑pass‑element topologies; and on‑chip internal supply generation.

The patent's own Background is an important admission: it concedes NTL gates have been supplied from an external V_CC/GND pair, that the operating window is governed by equations (2)–(4), that "it is very important to control the voltage V_CC supplied externally" to keep the logic‑low level between V1 and V2, and that resistor‑ratio (r1/r2) matching is stable across process/temperature. That admission narrows what can be called non‑obvious.

2. What each cited reference actually teaches

All of the above pre‑date the 1994‑10‑03 priority date and are available as prior art.

3. Claim 1 — strongest combination: JPS59115618A + US5126597 + US5160857 (secondarily US5341042)

Claim 1 requires: (a) a monitoring circuit outputting a monitor voltage proportional (first factor) to the variation between the NTL lower rail and the external higher rail relative to the external lower rail; (b) a reference circuit outputting a reference voltage proportional (second factor) to the same variation; and (c) comparing‑and‑regulating means that forces the NTL lower voltage to a predetermined value.

• JPS59115618A supplies the problem and the architecture: an on‑chip NTL supply circuit that derives the NTL rail from a reference supply circuit with a resistor‑ratio relationship, expressly to survive supply and temperature variation — i.e., a reference circuit plus a derived, ratio‑locked NTL rail. Its stated rationale ("NTL is ~6× more sensitive …") is the same problem the '123 patent sets out to solve.
• US5126597 supplies on‑chip internal NTL supply generation from an external supply, with internal supply wiring, i.e., the "NTL higher/lower rail produced internally" framework of claim 1 (and claim 11).
• US5160857 supplies the explicit motivation to close the loop on the NTL supply rail: it identifies that the NTL emitter‑side supply should be controlled to restore a defined threshold, and it frames the control circuit as the recognized engineering need ("involved control circuit").

Motivation to combine: all three address the same deficiency in NTL — sensitivity to supply/temperature and an ill‑defined logic‑low level — and each supplies a complementary piece (reference/ratio derivation; on‑chip rail generation; rail control). Under KSR, combining references that address the same problem, with a predictable result (a regulated internal NTL rail), is a textbook§ 103 rationale. The "comparing" step itself is met by the ordinary difference amplifier that any servo loop of this kind uses; a differential op‑amp comparing a level‑derived signal to a reference is routine (see also JPS59115618A's reference‑derived rail).

Assessment: Claim 1 is moderately to strongly vulnerable, but this is the one claim where the record is not airtight — see §7.

4. Claims 2–4 — the "dummy NTL gate" monitor

• US5187391 discloses a complete NTL/MNTL gate with an emitter‑follower output whose level is the gate's low level; tying an NTL inverter's input so it "always outputs a logic low" (claim 2) is the trivial degenerate case of that gate. US5341042 FIG. 2 shows the plain NTL inverter/NOR.
• Motivation: the standard analog technique of replica sensing — sense the very quantity you wish to control, using a device identical to the load. Combined with JPS59115618A's teaching that the NTL low level is a resistor‑ratio‑scaled function of the supply, using an NTL inverter as the sensor is a predictable, common‑sense implementation choice.
• Claim 3 (same circuit constants) is the matched‑device/replica principle — the same matching idea JPS59115618A relies on for temperature immunity and that US5160857 invokes when it notes NTL gates can be interconnected "without signal matching" because their characteristics track. Claim 4 (inverter) is an obvious species selection.

5. Claim 5 — the T1/T2/T3 + R1–R5 topology

The claimed monitor is, structurally, an NTL inverter replica: an input emitter‑follower/level‑shifter (T1/R1/R2), an input transistor with collector resistor R3 and emitter resistor R4 (T2), and an output emitter‑follower with emitter resistor R5 (T3) — whose emitter node is the monitor voltage. Compare US5187391's gate (input transistor + collector resistor + emitter resistor + constant current + emitter‑follower output with resistor) and US5341042's NTL inverter (input transistor + collector load + NPN emitter‑follower output). JPS59115618A supplies the resistor‑ratio scaling ("ratio" set by resistors) that the claim's "proportional with a coefficient of (r1/r2)" language recites.

Assessment: Claim 5 is obvious over US5187391 + US5341042 in view of JPS59115618A — the claim largely describes an NTL inverter sensed at its emitter‑follower output, with the well‑known resistor‑ratio proportionality. (Note the patent's internal inconsistency — eqs. (5)/(6) give an r2/r1 coefficient while claim 5 recites r1/r2; the mapping in claim 5 is also self‑inconsistent, which is a § 112 problem as much as a § 103 one.)

6. Claims 6–8, 13–15, 17–19 — the reference circuit, method and IC variants

• Claim 6's reference block = constant‑current source → diode D1 → transistors/resistor divider tapping V_BE. Generating a reference level by passing a constant current through a diode‑connected device and tapping a resistive divider is among the most routine techniques in bipolar/BiCMOS design. US5341042 expressly teaches a diode‑connected device used as "a reference level," and JPH0439805A/06A are cited by the applicant as disclosing reference‑voltage‑setting methods for logic LSIs containing NTL and ECL — an admission that reference generation for NTL/ECL LSIs was known.
• Claims 7–8 / 14–15 / 18–19 (T4's V_BE and the bias current matched to the NTL gates' transistors) are simply the matched‑device design choice — the very rationale the specification gives ("the variation of the voltage V_BE is the same … the resistance ratio r1/r2 is constant regardless of temperature"). Matching an on‑chip reference transistor to the logic transistors is standard and its benefit is predictable. US5187391 even shows a constant current sourced into the NTL gate (V_CSI through transistor 19), giving a concrete basis for matching the bias current.

Assessment: Claims 6–8 and 13–19 are strongly vulnerable — routine reference‑generation plus matched‑device design, supported by US5341042 and the applicant's own admission regarding JPH0439805/06.

7. Claims 9–10 — the pass element (MOS vs. bipolar)

• Claim 9 (diff‑amp + N‑channel MOS pass device) and claim 10 (diff‑amp + NPN bipolar pass device with base resistor R10) are alternative, well‑known regulator output stages. US5160857 teaches MOS transistors as the variable emitter‑side element in NTL circuitry, and US5341042 is a BiCMOS NTL circuit using NFETs — making an MOS pass device an obvious selection. A bipolar pass transistor with a base resistor is the equally ordinary alternative; the claim's asserted benefit (smaller area from higher transconductance) is a predictable property of bipolar devices. These are classic "obvious to try" alternatives within the skill of the art.

8. Motivation‑to‑combine summary

1. Same field / same problem: JPS59115618A, US5160857, US5126597, US5341042 and the '123 patent all concern the NTL logic‑low level and its sensitivity to supply/temperature. References directed to the same problem are combinable (KSR).
2. Complementary teachings: reference‑derived rail (JPS59115618A) + on‑chip rail generation (US5126597) + rail control loop (US5160857) + gate/replica structure (US5187391, US5341042).
3. Predictable result: an on‑chip servo that holds the NTL low rail at a V_BE‑referenced, ratio‑set value — no unexpected result, no teaching‑away in the cited art (JPS59115618A's criticism of unrelated circuits actually encourages linking them; US5160857's criticism of the "involved control circuit" is a design‑cost concern, not a teaching away).

7. Where the § 103 case is weakest (counter‑arguments to weigh)

• No cited reference expressly feeds back the measured logic‑low level of an actual/dummy NTL gate. The through‑line of the '123 patent — monitor the logic‑low output of a replica NTL gate and differentially compare it to a reference — is not squarely disclosed by any single cited reference; it must be assembled from the replica/matched‑device principle plus the rail‑control teaching. A patentee could argue this combination is the point of novelty and is not merely a "predictable variation." The strongest § 103 position is therefore on the dependent claims (5, 6–8, 9–10, 11) and on claims 11, 12, 16 as method/IC recitations of the same architecture, rather than on claim 1 alone.
• US5089724 and JPH0439805A/06A provide only peripheral/admission‑level support; the primary combination does not depend on them.
• Secondary considerations: nothing in the record shows unexpected results, long‑felt need met, or commercial success attributable to these claims; the "same‑chip temperature stability" advantage follows directly from matched on‑chip devices and is not probative of non‑obviousness.

8. Flags, caveats and conflicts

1. Metadata conflict — JPH0439805A / JPH0439806A. The '123 specification characterizes these as reference‑voltage‑setting methods for NTL/ECL logic LSIs; the Google Patents listing shows title "Elevating device," assignee "Tokyo Electric Co Ltd." I have recorded both literally and not auto‑corrected either. This discrepancy should be resolved against the JP originals before relying on these as § 103 art; the applicant's characterization is usable as an admission regardless.
2. Reference numbering is the page's, not verified by me: I retrieved substantive text for JPS59115618A, US5126597, US5187391, US5160857 and US5341042 (plus the EP0584471A2 family). I did not retrieve full text for US5089724 or for JPH0439805/06; statements about those two are limited to the cited snippets and the applicant's characterization.
3. Internal inconsistency in the patent itself (r1/r2 vs. r2/r1 between eqs. (5)/(6) and claim 5), as noted in the prior-generated overview, complicates any precise element‑by‑element mapping for claim 5 — consistent with the earlier caveat.
4. I did not locate any litigation or PTAB/CAFC record for US 5,619,123 (consistent with the prior litigation section); that finding does not affect this § 103 analysis.
5. JP 5619123 B2 (Yagi Seisakusho; wind turbine) remains a distinct document and is not treated as related art here.

Bottom line: Every claim is arguably obvious under § 103 over the cited art, with the strongest cases on claims 5, 6–8, 9–10, 11 and the method/IC claims (12–19), and the least airtight case on independent claim 1, whose novelty rests on the dummy‑NTL‑gate monitor fed into a differential comparison loop — a feature none of the cited references discloses expressly, but which a POSITA applying replica‑sensing and rail‑control principles would have found obvious to try.