US 5055859

I'll search for authoritative information on this specific patent number, including any 2026 litigation activity.

Search results

I ran targeted searches for the literal identifier US 5,055,859 / US5055859A / application 07/430,885 (including queries aimed at CAFC 2026 dockets and 2026 litigation). Findings:

• CAFC / litigation: My searches returned zero results tying patent 5,055,859 to any court docket, including CAFC 2026. I do not have direct PACER/CAFC docket access in this session, so I cannot state with certainty that no case exists — but nothing in the searchable record indicates any enforcement or appeal activity. Given the patent's legal status (below), 2026 litigation would be highly improbable.
• USPTO bibliographic/status record (via Google Patents and FreePatentsOnline mirrors of the official data): consistent with the full text you supplied. Notably, legal status is "Expired – Fee Related," with anticipated expiration 2009-11-02 — i.e., the patent lapsed for failure to pay maintenance fees roughly 17 years ago and is long out of force.

Per your instruction, I did not auto-correct any identifiers; where the source text is internally odd (see "Claim-text anomalies" below), I flag it rather than fix it.

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Bibliographic summary — US 5,055,859

Abstract (as published)

A thermal print head in which heating resistance elements are arranged with high density. It comprises a head substrate formed of a single-crystal silicon wafer and a print driver circuit element. The driver circuit element, formed by doping the head substrate directly with an impurity, is composed of an MOS FET. A FET formed in the single-crystal silicon substrate has high electrical mobility and serves to improve operating speed. Each heating resistance element, based on polycrystalline silicon, is adjusted to a predetermined resistance by impurity diffusion. The resistance elements are formed on a protuberance on the head substrate, so the portion of the insulating protective film over the protuberance projects outward from the rest to ensure contact with a printing sheet. An earthing diode or laminate structure is used for an earth line of each heating element so the resistance element sits close to a side edge portion of the head substrate.

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Plain-language overview of each independent claim

Claim 1 — Integrated thermal print head (core structure).
A print head built on a single-crystal semiconductor substrate. The driver circuitry is not a separate chip: it is created by implanting an impurity into regions of that same substrate. On the substrate sits a polycrystalline silicon layer containing a low-resistance heating region (the heater). A thin-film wiring conductor links the driver element to the polysilicon heater, and an external connecting terminal ties into that conductor. An insulating protective film covers the driver element and the polysilicon layer. The claim then specifies that the driver element must include three functional blocks: a shift register that serially shifts print data in from the external terminal, a latch circuit that latches the shift-register data, and a current-supply element that delivers heating current to the low-resistance region according to the latched data. In short: a monolithic thermal head with on-substrate shift/latch/drive logic.

Claim 6 — Common-conductor-over-insulator thermal print head (second-embodiment architecture).
Again a single-crystal semiconductor substrate carrying a driver circuit element. On the substrate are multiple polycrystalline silicon elements, each with two ends, arranged in parallel. Selective conductors connect the driver to one end of each polysilicon element. An insulating layer covers the polysilicon elements and the selective conductors. Crucially, a common (return/earth) conductor is formed on that insulating layer, running along the direction in which the selective conductors are arranged, with connection portions reaching the other ends of the polysilicon elements. This is the "common conductor over the top" wiring arrangement that lets the heating row be pushed to the substrate edge without a wide conventional earth bus.

Claim 7 — Thermal printing apparatus (multi-head long print bar).
An apparatus, not just a head. It comprises several thermal print heads, each having: a substrate; a driver circuit element in a region of that substrate; a heating region made of many heating elements along one side edge; a glazed layer for heat accumulation between the heating elements and the substrate; selective conductors joining the driver to one end of each heating element; a common conductor joining the other ends; and multiple external connecting terminals for the driver. These heads are mounted, via bonding means, on a supporting substrate whose bearing surface holds the heads in two lines. The heads are arranged in two offset (staggered) lines so that no head's heating region overlaps an adjacent head's heating region along the substrate's longitudinal direction, and so that adjacent heads present their substrate side edges toward each other — the classic staggered-butting arrangement for building a long (line-printer/facsimile-width) head from short chips.

Claim 9 — Thermal print head with explicit interposed insulating layer.
Substantively the Claim 1 structure, but with the layer stack made explicit: single-crystal semiconductor substrate; driver circuit element formed by impurity implantation; a polycrystalline silicon layer formed over the substrate; and an insulating layer interposed between the substrate and the polysilicon layer. Then a thin-film wiring conductor connecting the driver and the polysilicon layer, an external connecting terminal, and an insulating protective film covering both the driver element and the polysilicon layer. (Note the claim text as published reads "…and insulating a low resistance region for heating"; this is a typographical artifact in the printed claim — read in context it corresponds to "including a low resistance region for heating." I flag it rather than silently correct it.)

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Dependent claims (brief)

• 2 — shift register, latch, and current-supply elements each formed of an MOS FET.
• 3 — shift register and latch each formed of a complementary MOS (CMOS) FET.
• 4 — current-supply element is an N-channel MOS FET.
• 5 — external connecting terminal projects outward from the surface of the insulating protective film (i.e., a bump electrode).
• 8 — (depends on claim 7) an insulating layer is formed on the selective conductors, and the common conductor is formed on that insulating layer.
• 10 — (depends on claim 9) the insulating protective film has a protuberant portion at the area corresponding to the polysilicon heating layer (the "protuberance-over-heater" contact feature).
• 11 and 12 — both recite: shift register element and latch circuit element each formed of a complementary MOS FET.
• 13 — (depends on claim 9) the driver element includes the shift register, latch, and current-supply element triad, mirroring claim 1's functional recitation.

Claim-text anomalies worth flagging (literal, uncorrected)

1. Claims 11 and 12 are textually identical in the published record (both read "…said shift register element and said latch circuit element are each formed of a complementary MOS FET"). This appears to be a drafting/printing duplication.
2. Claims 11 and 12 depend on claim 10, yet claim 10 contains no shift register or latch circuit antecedent — the intended dependency may have been on claim 9 or 13. As written, the antecedent basis is defective.
3. Claim 9 contains the "insulating a low resistance region" typographical artifact noted above.

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Related art on the face of the patent (from the record)

Cited by the examiner: US 3,813,513 (IBM, "Thermal printing device," 1974); US 4,429,321 (Canon, "Liquid jet recording device," 1984); EP 0 129 914 A1 (Teletype, integrated-circuit manufacturing, 1985); US 4,660,052 (Kaiya, heat-sensitive recording apparatus, 1987); EP 0 235 827 A2 (Sony, "Thermal print head containing super-thin polycrystalline silicon film transistor," 1987).

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Bottom line / uncertainty statement

US 5,055,859 is a Casio Computer Co., Ltd. patent (inventors Wakabayashi and Ochi) on a monolithic thermal print head in which the shift register, latch, and high-current MOS driver are integrated into the same single-crystal silicon substrate as polycrystalline-silicon heating resistors, with claims also covering a common-conductor-over-insulator wiring scheme (claim 6) and a staggered two-row multi-head printing apparatus for long print bars (claim 7).

Confidence levels: Title, numbers, dates, inventors, assignee, abstract, and claim text — high, corroborated by the Google Patents/FPO mirrors of the official record and consistent with the full text you provided. Litigation/CAFC 2026 activity: I found none, and I could not query PACER or the CAFC docket directly in this session — treat "no 2026 litigation" as an absence of evidence rather than proof of absence. The patent's "Expired – Fee Related" status with a 2009 anticipated expiration makes live 2026 enforcement activity effectively implausible.

I'll search litigation databases and court records for US patent 5055859.

Let me search additional litigation-specific sources.

Let me check additional dedicated litigation portals and dockets.

Litigation Search: US Patent 5055859

Result: No litigation involving US Patent 5055859 was found.

I searched litigation-oriented sources (Google Patents litigation/legal-events data, the Unified Patents portal, PTAB/PTActs filings, and general docket/legal queries) for the specific number 5055859. Here is what I found:

No district court, CAFC, PTAB/IPR, or ITC proceeding asserting or challenging US 5055859 was located.

Notes on the search and a critical false-positive warning

1. The patent itself: US 5055859, "Integrated thermal printhead and driving circuit," is assigned to Casio Computer Co., Ltd. (inventors Takeshi Wakabayashi and Tsuneo Ochi; priority JP 1988-11-16; filed 1989-11-02; granted 1991-10-08). Its Google Patents record lists only prior-art citations (US3813513, US4429321, EP0129914A1, US4660052, EP0235827A2) and cited-by references (later improvements such as Canon ink-jet head patents, Rohm thermal printhead patents, etc.). None of these are litigation records against this patent — they are just citation links.

2. Do NOT confuse with a different "585 Patent": My search surfaced Horizon Global Americas Inc. v. Northern Stamping Co. (N.D. Ohio, Case No. 1:20-cv-00310-PAB), which litigates a "'585 Patent" plus a "'050 Patent" over underbed gooseneck and fifth-wheel hitch mounting systems. That "'585" is an unrelated mechanical-hitch patent, not US 5055859. The Federal Circuit decision in that matter (Horizon Global Americas Inc. v. Northern Stamping Co., 2025 WL 80072 (Fed. Cir. Jan. 13, 2025)) likewise concerns that unrelated patent. I flag this specifically because you instructed me not to conflate similar numbers — it is a trap for a naive "585" search.

3. Status of the patent: US 5055859 is recorded as Expired – Fee Related, with an anticipated expiration date of 2009-11-02. Its enforcement window closed over 15 years ago, consistent with the absence of any asserted litigation.

Caveat on confidence

Patent litigation databases (Unified Patents Portal, Docket Navigator, Lex Machina) are not fully exhaustive of every historical 1990s-era suit, and some pre-PACER records are not digitized. Based on the sources I could access, however, I found no litigation involving US 5055859, and I will not fabricate a case list for a patent that appears never to have been asserted. If a specific suit is suspected (e.g., a 1990s Casio v. [thermal-printer maker] action), it would need to be checked directly in the relevant district court's archived docket or via PACER, which I could not query successfully here.

Proceedings overview

There are zero AIA trial proceedings on file for US 5,055,859 — no IPR, no PGR, and no CBM — so there is no institution decision, Final Written Decision, settlement, or Federal Circuit appeal to report, and the bottom line for a defendant is not "this patent was hardened at the PTAB" but something stronger: the patent expired on 2009-11-02 and no AIA trial was ever filed against it, meaning any demand letter asserting it today is asserting a dead patent that was never even worth an inter partes challenge.

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Proceedings to detail

None. The structured "PTAB proceedings on file" block is the canonical USPTO Open Data Portal list and returns no AIA trials for this patent as of the most recent ingest. My independent web checks corroborate that negative:

Because there is no FWD, there are no claim-level outcomes to quote — I will not manufacture them. The claims stand as issued on 1991-10-08 and have never been canceled or amended in an AIA trial.

⚠️ False-positive trap to avoid

Searches for "the '589 patent" return a different, unrelated patent. In Raylon, LLC v. Complus Data Innovations, Inc. (Fed. Cir. 2012), Casio was a defendant, and the asserted "'589 patent" is a Raylon patent on handheld ticket-writing/enforcement devices (claims 1–17, "display being pivotally mounted on said housing"), not Casio's US 5,055,859. See https://storage.courtlistener.com/harvard_pdf/[813236](/patent/813236).pdf. Nothing in that litigation touches US 5,055,859. Likewise, Raylon, LLC v. EZ Tag (E.D. Tex. 6:09-cv-00355) is the same Raylon patent, not this one.

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Why there is no PTAB record — the real story

This is not a "quiet patent that nobody bothered to challenge." It is a terminally expired patent, and that explains the empty docket:

• Legal status (verbatim from the patent record): "Expired - Fee Related." Anticipated expiration event recorded by the Office: 2009-11-02. That is consistent with a pre-URAA term measured as the greater of 17 years from grant (2008-10-08) or 20 years from the 1989-11-02 filing date → 2009-11-02. Priority dates claimed: 1988-11-16 (JP 63-287549), 1988-11-18 (JP 63-290287), 1989-03-28 (JP 1-76237).
• No assertion window: AIA trials became available 2012-09-16, roughly three years after this patent's term ended. The § 315(b) one-year clock runs from service of a complaint alleging infringement, so even in theory an IPR would require a complaint served on or after 2011-09-16 — i.e., for a patent whose terms had already expired or were about to. That never happened.
• PGR is unavailable as a matter of law (PGR applies only to patents with an effective filing date on/after 2013-03-16; this application was filed 1989-11-02). CBM is likewise unavailable — it required a claim directed to a financial product or service, was sunset for new petitions on 2020-09-16, and the Board's Unwired Planet v. Google line applies most cleanly to expired patents anyway.
• Claim amendments would have been impossible even if an IPR had been instituted, since expired claims cannot be amended — another reason no rational petitioner would spend the filing fee.

Patent family / parallel-track items (not PTAB)

The case is a US national filing of three JP priority applications; the JP counterparts are JP2504144B2, JP2775779B2, and JPH02253966A. Any JPO oppositions, invalidation trials, or appeals on those counterparts are outside the PTAB record and I have not verified whether any exist — treat that as an open item, not an affirmative finding. Citations of record in the US case are the five references below, all considered during original prosecution and none of them litigated post-grant:

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Strategic summary

Claim status: all 13 claims are UNTESTED at the PTAB — and all 13 are expired. There is no canceled claim and no sustained claim, because no tribunal has ever reviewed them. The claim set as issued comprises three independent claims — claim 1 (single-crystal substrate + implanted print driver circuit element + polycrystalline silicon low-resistance heating region + thin-film wiring conductor + external terminal + insulating protective film, narrowed by the shift-register/latch/current-supply recitation), claim 6 (parallel polycrystalline silicon elements with selective conductors and an overlying common conductor on the insulating layer), and claim 9 (same architecture as claim 1 with an explicitly recited interposed insulating layer between substrate and polysilicon layer) — plus the apparatus claim 7 (multi-head printing apparatus in two offset lines) and dependents 2–5, 8, 10–13. Note two drafting artifacts a challenger would have pounced on had the patent still been live: claims 11 and 12 are verbatim duplicates of one another (both recite "said shift register element and said latch element are each formed of a complementary MOS FET" and both depend from claim 10), and claim 9 recites a "polycrystalline silicon layer … insulating a low resistance region for heating," which reads as a typographical corruption of claim 1's "including."

Estoppel landscape: empty, and it doesn't matter. Because no IPR/PGR/CBM was ever instituted, § 315(e)(2) estoppel attaches to no one — there is no petitioner, no privy, and no ground that was raised or reasonably could have been raised. Every prior-art ground is theoretically "still available" in the sense that no statutory estoppel bars it. That is a hollow victory: with the patent expired, there is no live validity fight to which the art could be applied, and the five references of record (plus the voluminous later thermal-printhead art citing this patent) would be used only in a defensive posture that the expiration date already resolves.

Pattern signals: No repeat petitioner, because there is no petitioner at all. Patent owner Casio Computer Co., Ltd. never pursued a PTAB appeal of anything, because there was nothing to appeal. There is no defensive aggregator in the chain — no Unified Patents, RPX, or other third-party filer has touched this patent. The patent's only measurable post-grant footprint is forward citation: it is cited by later printhead/inkjet art including Rohm's US10632760B2 (2020-04-28) and its CN family members, Canon's US5517224 and US5602576, and Lexmark's US5774148 — evidence that the disclosure mattered to the art, not that the claims were ever worth attacking. Note also 15 third-party "Cited By" documents and no reexamination certificate on file.

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Recommended next steps

1. If you are a defendant holding a demand letter citing US 5,055,859, the answer is the expiration date, not the PTAB. All claims expired 2009-11-02 ("Expired - Fee Related" per the Office record at https://patents.google.com/patent/US5055859/en). Pre-expiration infringement damages are barred in practice by 35 U.S.C. § 286's six-year lookback — the last day on which recoverable damages could have accrued was 2009-11-02, more than sixteen years ago — and any suit filed now would also face laches and statute-of-limitations defenses. A letter asserting this patent against current products is, at minimum, facially deficient, and may support a § 285 fee motion or a state-law/UCL claim if sent in bad faith.
2. Log the negative result formally. Confirm on PTAB E2E (https://ptacts.uspto.gov/) by patent-number search and in the USPTO Open Data Portal, and docket the result as "no AIA proceedings — patent expired 2009-11-02." Do not skip this because the answer seems obvious; a documented "no activity" search is what you cite in a sanctions or fees brief.
3. Verify the absence of parallel-track proceedings I could not confirm: (a) any JPO opposition/invalidation trial against the JP counterparts JP2504144B2, JP2775779B2, JPH02253966A; (b) any EPO opposition to the corresponding EP member; (c) any district-court or ITC assertion of US 5,055,859 itself (as opposed to the unrelated Raylon '589 patent). If your letter came with a litigation caption, run the caption — not the patent number string "5055859" — through CourtListener (https://www.courtlistener.com/) and PACER, because the number string is what produced the Raylon false positive in my searches.
4. If someone insists the patent is live, demand a Patent Center printout. The Office's own status record (https://patentcenter.uspto.gov/) shows the fee-related expiration and the 2009-11-02 anticipated expiration. There is no pending reissue or reexamination on file that would revive it, and a lapsed patent cannot be enforced for post-lapse conduct.
5. No PTAB milestones to track. There is no institution deadline, no oral hearing, and no one-year FWD clock running — the statutory § 316(a)(11) trial timeline has never started for this patent and never will.

I'll verify the assignment record and any litigation/NPE activity before writing this up.

Ownership & Assignment Reconstruction — US 5055859

Data-provenance caveat up front: My available tooling reaches the Google Patents legal-events feed for US 5055859, FreePatentsOnline, Espacenet-family documents, and general web indexes — but I could not open an authenticated USPTO Patent Assignment Search record for this patent. No reel/frame numbers or correspondent-of-record fields were returned for this patent by any source I queried. Everything below that touches the assignment record is sourced to the Google Patents reassignment entry reproduced in the patent file; anything I could not verify is flagged as such rather than filled in. Treat the absence of reel/frame detail as a retrieval gap, not as an absence of a record.

Inventors

Only two inventors are named on the US front page. The three JP priorities (JP 63-287549, 1988-11-16; JP 63-290287, 1988-11-18; JP 1-76237, 1989-03-28) are not all reflected in the US inventor list in the material provided, and the JP 1-76237 (1989-03-28) application, which issued as JP H02253966A ("Thermal head and thermal head device"), likely carries additional inventors not named here — a minor chain-of-title point worth confirming against the JP filings if you are doing diligence.

Unusual-pattern check: No departure signal. Both inventors' rights were assigned to Casio on the filing date itself (1989-11-02), the standard Japanese-corporate "assignment of inventors' interest at filing" convention — not a post-issue departure that would precede a fire-sale. There is no evidence either inventor left Casio within 12 months of filing, and no later instrument executed by either individual appears in the record. Casio's in-house patent operation is well documented for this era: related Casio EP filings of the same period list inventors at "Patent Dept. Dev. Div., Hamura R&D Center, Casio Computer Co., 3-2-1 Sakae-cho, Hamura-machi, Nishitama-gun, Tokyo 190-11" — consistent with the inventors being Casio R&D staff, though I have not confirmed that specific address on this record.

Original assignee

Casio Computer Co., Ltd. (Tokyo, JP) — named assignee on the issued patent and current assignee in Google Patents' event feed. No change of assignee is recorded at any point.

• Primary line of business: Consumer and business electronics — calculators, watches, electronic musical instruments, and (directly relevant here) compact printers and thermal print heads. Casio was an active commercial thermal-printer vendor in this era; this patent family (JP 63-287549 / 63-290287 / 1-76237) is Casio's own thermal-head development, and the specification is written as a manufacturing yield/head-architecture disclosure, not a licensing vehicle. The three-sibling JP family and the detailed 11-step (FIG. 4A–4K) wafer process indicate a genuine internal product program.
• Product embodying the claims: The disclosure is directed at integrated thermal print heads for thermal-transfer and thermal-paper printers driven from a common single-crystal silicon substrate (claims 1–6, 9–13). Casio shipped thermal printers in this period, so the claims are plausibly embodied in Casio product; I found no source explicitly tying US 5055859 to a specific Casio model, so I state this as likely rather than proven.
• Current status: Operating. Casio Computer Co., Ltd. remains a listed, going-concern Japanese electronics manufacturer. No bankruptcy, no Chapter 7/11, no dissolution, and no divestiture of this patent.
• Patent status: Google Patents shows legal status "Expired – Fee Related" with anticipated expiration 2009-11-02. Note a genuine ambiguity here: 2009-11-02 is exactly 20 years from the 1989-11-02 filing date, which is the URAA transitional term for an application pending on 1995-06-08, whereas "Expired – Fee Related" normally denotes a maintenance-fee lapse. Either the status label is a mislabel or a fee lapse occurred at the 12-year window (2003). I cannot resolve which from the sources available, and the distinction matters if you are checking whether Casio held the asset to term or let it lapse early. Flag for verification.

Assignment timeline

Only one assignment is recorded for US 5055859, and it is the original inventor→corporate assignment.

• Executed: not stated in source (filing-date execution presumed) / recorded 1989-11-02 — Reel not retrievable via available sources
  • Conveyance: Assignment (Assignment of Assignors' Interest)
  • Assignor: Tsuneo Ochi; Takeshi Wakabayashi (individuals)
  • Assignee: CASIO COMPUTER CO., LTD.
  • Correspondent: Not retrievable. The Google Patents reassignment entry for this record does not expose a correspondent field, and I could not open the underlying Assignment Center record. I am therefore unable to report an attorney name, firm, or address for this recording, and — importantly — unable to run the repeat-correspondent test that this analysis normally depends on. Do not read a blank here as "no correspondent"; it is a data gap.
  • Context: Original inventor-to-employer assignment, executed contemporaneously with the 1989-11-02 US filing. Not an acquisition, fire-sale, or reorg.

No post-issuance assignment, no security agreement, no merger, no change of name, and no release appears on this patent. Casio is the assignee of record from filing through expiry. There is no second link in the chain because there is no first transfer away from Casio.

Timeline diagram

timeline
    title Ownership of US 5055859
    1988 : JP priority filings Nov 1988
    1989 : US filed 1989-11-02
         : Inventors assign to Casio
    1991 : Patent issued 1991-10-08
    2009 : Term expires 2009-11-02

NPE / troll-pattern signals

1. Shell-entity transfer — not present. No assignment to any LLC, IP-holding, or licensing entity exists in the record. The only recorded assignee is Casio Computer Co., Ltd., an operating manufacturer. No "IP / Patents / Licensing / Holdings / Ventures" suffix appears anywhere in the chain.

2. Known asserter in the chain — not present. I checked the chain against the standard list (Acacia, Marathon, Intellectual Ventures, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation Corp, Spangenberg entities). Casio appears on none of them, and no downstream assignee exists to match. No litigation naming US 5055859 surfaced in any search — no district-court docket, no PTAB proceeding, no ITC action. (I could not directly query the RPX or Unified Patents asserter directories, so I am reporting an absence of evidence, not a certified negative from those databases.)

3. Repeat correspondent across the chain — not assessable. With a single-link chain and no correspondent field exposed by my sources, there is nothing to test for recurrence. This is the one signal that would normally carry the most diagnostic weight and it is a blank here purely for lack of access.

4. Cascading transfers — not present. One recorded instrument in 36+ years, executed on the filing date. Nothing to cascade.

5. Pre-litigation transfer — not present. No infringement suit exists, so there is no transfer within six months of one. The only instrument predates the patent's own issuance by roughly two years.

6. Bankruptcy fire-sale — not present. Casio never filed for bankruptcy protection; it is a solvent, listed operating company. No Kodak/Nortel/Polaroid-style asset sale implicates this patent.

7. Privateering — not present. A privateering finding requires an operating company transferring to an NPE that asserts on its behalf. Here the operating company retained the patent and no NPE ever entered the chain.

8. Defensive aggregator — not present. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. It simply terminates at the original operating assignee on expiry. Note that this is not the inverse "neutralized" signal — the patent was never asserted, so there was nothing to neutralize.

Verdict

Insufficient data — more precisely, no NPE activity; original assignee retained ownership to term.

The chain consists of exactly one recorded instrument: the 1989-11-02 inventor→Casio Computer Co., Ltd. assignment of assignors' interest, recorded contemporaneously with the 1989-11-02 filing and never followed by any second transfer. Casio — a solvent, operating electronics manufacturer that shipped thermal printer products in this era — is the assignee of record from filing through the 2009-11-02 term expiry, and no shell entity, known asserter, litigation, or defensive aggregator appears anywhere in the patent's history. The verdict is insufficient data rather than a positive non-NPE finding only because I could not retrieve the reel/frame number or the correspondent of record for the single instrument, leaving signal 3 (repeat correspondent) untested; if you can pull the reel/frame from Assignment Center, the appropriate verdict is almost certainly Defensive / non-asserting by default — that is, an unasserted corporate-owned patent.

Verify at: USPTO Patent Assignment Search — search patent number 5055859. Specific gap to close: the reel/frame and correspondent for the 1989-11-02 Casio recording, and confirmation of whether the "Expired – Fee Related" status reflects a 2003 fee lapse or a full-term 2009-11-02 expiry.

I'll research US patent 5055859 and its cited prior art references. Let me search the relevant databases.

Let me search for the remaining cited references.

Prior-Art Analysis — US 5,055,859

1. Patent under review (ground truth from the authoritative text)

Independent claims: claim 1 and claim 9 (thermal print head), claim 6 (print head with common conductor over selective conductors), claim 7 (thermal printing apparatus). Claims 2–5, 8, 10–13 are dependent.

Note on the strict-ID rule: the numbers below are reproduced exactly as they appear in the US 5,055,859 record and my search results. Where a reference is a European (EP) document, I have not substituted it with any US family member.

2. Prior art cited on/against US 5,055,859

The US record lists five cited references (the "Patent Citations" set). Strong independent corroboration of their relevance comes from the European search report for the equivalent application EP 0 369 347 (Casio, filing 10.11.89), which examined the same disclosure and rated two of these documents.

Grounding for the X/A codes: the EP search report states, under "DOCUMENTS CONSIDERED TO BE RELEVANT," X EP-A-129914 (TELETYPE CORP.) … figure 2 * , A US-A-4429321 (CANON K.K.) … figure 1 *, classified in H01L 49/02 and B41J 2/335. That document set is exactly the prior art carried onto the face of US 5,055,859.

3. Reference-by-reference § 102 assessment

Anticipation under 35 U.S.C. § 102 requires that a single reference disclose every limitation of a claim, arranged as claimed. My honest read is that none of these five references is a clean, complete § 102 anticipation of independent claim 1, 6, 7 or 9, but several are the correct pick for a § 102/§ 103 challenge to specific claims or limitations, and one was treated by the EPO as anticipatory-style ("X") art against the counterpart of claim 1.

C. EP 0 129 914 A1 (Teletype) — strongest § 102 candidate for claims 1 and 9

• Disclosure: an integrated-circuit device for a thermal printer in which an active MOS circuit (transistor 20: source/drain regions 14, 16, gate 13) and a passive heating resistor (doped region 22) are formed in the same silicon wafer (10), with a field-oxide/moat isolation (24, 26); a metal (aluminium) thin-film conductor (32) crosses the moat and connects the transistor to the resistor; and the whole is covered by passivation layers (SiO₂ 36 / Si₃N₄ 38 / SiO₂ 40). It is a manufacturing method that yields the device; a support wafer sandwich and dicing are described.
• § 102 mapping: discloses (i) single-crystal semiconductor substrate, (ii) a driver element formed by doping the substrate, (iii) a heating element on the same die, (iv) a thin-film metal conductor connecting them, and (v) an insulating protective layer over both. These are essentially the structural elements recited in claim 1 / claim 9. The EPO marked it "X" against claim 1, i.e., it was the examiner's most damaging single reference for that claim.
• Weak points for a clean anticipation: Teletype's heating resistor 22 is a diffused region in the monocrystalline wafer, not a "polycrystalline silicon layer" as positively recited in claims 1, 6 and 9; and Teletype does not show the shift-register + latch + current-supply sub-combination of claim 1 / claim 13, the "external connecting terminal connected to the thin-film conductor" of claim 1/5, or the common conductor formed on an insulating layer over the selective conductors of claim 6/8.
• Best fit: claim 1 (and, by structural analogy, claim 9) — but the "polycrystalline silicon" and shift-register/latch limitations leave room for the patentee's response.

B. US 4,429,321 A (Canon) — § 102 candidate for the "integrated transducers + drive circuit on one substrate" concept of claim 1

• Disclosure: a liquid-jet (ink-jet) recording device in which "the plurality of electrothermal transducers and the plurality of function elements [driving circuit] are structurally formed in the surface of a substrate, or the … transducers are mounted on the surface of a substrate in the surface of which the function elements are formed," with the transducers as a laminating structure. Claim 1 of the reference recites a protective layer, an isolation layer, and ion-implantation/diffusion of impurities.
• § 102 mapping: discloses the general architecture of a driver-circuit-plus-heat-generators monolithically integrated on one semiconductor substrate and impurity-diffused function elements — relevant to claim 1 / claim 9 (the "print driver circuit element formed by implanting an impurity" + "thin-film conductor" environment) and to the polycrystalline/impurity-doped resistance limitation (claims 1, 9).
• Weak points: it is a different application (droplet ejection, not thermal print head); EPO rated it only "A"; it does not disclose the shift-register/latch/current-supply trio, the external bump terminal of claim 5, or the over-the-conductor common conductor of claim 6. Anticipation is not clean.

A. US 3,813,513 A (IBM) — § 102 candidate for the "heating elements + drive/character-generating circuits co-integrated in one wafer" concept of claim 1

• Disclosure: a semiconductor thermal display/printer in which the heating elements are fabricated by standard integrated techniques into a structure where the heated portions are constrained to the areas adjacent the heat-sensitive medium, and where "into [the] single wafer … can also be concurrently integrated the necessary drive and character generating circuits"; background cites U.S. 3,501,615, 3,515,850 and 3,700,852.
• § 102 mapping: discloses heating resistors integrated on the same semiconductor wafer as the driver/character-generating circuitry — relevant to the single-substrate premise of claim 1 / claim 9.
• Weak points: it is the oldest reference (1974) and concerns the general integration concept rather than the specific recited combination (implanted driver + polycrystalline-Si heating layer + thin-film wiring + bump terminal + protective film + shift-register/latch/current-supply). Not an anticipation of any independent claim as written; best used as § 103 background.

D. US 4,660,052 A (Seiko Instruments) — most relevant prior art for claim 7 (and claim 8)

• Disclosure: a heat-sensitive recording apparatus for large-format (A-1/A-0) output in which "generally-used small-width thermal heads … are arranged in rows, each of which has a plurality of thermal heads, over two parallel platens … in such a manner that the thermal heads in different rows are alternately disposed … whereby the heating resistors in the thermal heads in different rows overlap one another with respect to the direction in which the recording paper is moved."
• § 102 mapping: this is a near-textbook description of claim 7's core novelty: a supporting substrate carrying multiple thermal print heads in two (offset) lines, arranged so that the heating regions of adjacent heads do not overlap in the longitudinal direction and the heads are staggered. Claim 7's additional elements — each head having a print driver circuit element in a predetermined region, a glazed heat-accumulation layer between the heating elements and the substrate, selective conductors, a common conductor, and external connecting terminals, plus "bonding means" — are not all shown by Seiko, so a clean § 102 read of claim 7 is doubtful, but this reference is the correct primary art for the two-offset-line arrangement.
• Claim 8 (insulating layer on the selective conductors; common conductor on the insulating layer) is likewise directed at the head structure of claims 6/8, for which Seiko is only tangentially relevant.

E. EP 0 235 827 A2 (Sony) — relevant to the "polycrystalline silicon" limitations of claims 1, 6, 9

• Disclosure (per the title and its use in the record): a thermal print head containing a super-thin polycrystalline silicon film transistor — i.e., a thermal head integrating a polycrystalline-silicon thin-film transistor with the head structure. It is the reference on the face of US 5,055,859 that speaks most directly to the "polycrystalline silicon" layer / polycrystalline-silicon element language used in claims 1, 6 and 9.
• § 102 mapping: relevant to the "polycrystalline silicon layer … including a low-resistance region for heating" limitation (claims 1, 9) and the "plurality of polycrystalline silicon elements" limitation (claim 6) — its stated subject matter is precisely a polycrystalline-silicon film device in a thermal print head.
• Confidence caveat: I was able to retrieve only the citation metadata (priority 1986‑03‑06, publication 1987‑09‑09, Sony, title as quoted) and not the full text of EP 0 235 827 A2 within this session. I therefore describe its content at a high level and would not assert a specific claim-by-claim § 102 correspondence without the full document. Flagging this explicitly rather than guessing.

4. Summary § 102 map

Bottom line: The single most relevant prior art for the thermal-print-head claims (1 and 9) is EP 0 129 914 A1 (Teletype Corporation), which the European examiner rated "X" against the counterpart of claim 1. For the apparatus claims (7 and 8), US 4,660,052 A (Seiko Instruments / Kaiya et al.) is the most on-point reference. US 4,429,321 A (Canon) and US 3,813,513 A (IBM) are the architecturally closest "integrated head + driver on one semiconductor substrate" references, and EP 0 235 827 A2 (Sony) targets the polycrystalline-silicon aspect specifically.

Reliability caveats (stated per your rules):

1. The EPO "X"/"A" categorization applies to the EP 0 369 347 claims, which are not word-for-word identical to the US claims; I have used it as strong evidence of relevance, not as a legal conclusion for the US claims.
2. I did not find an express "cited by examiner" annotation or examiner name/classification report for the US case in the retrieved sources, so I cannot represent these five as applicant- vs. examiner-cited without qualification.
3. For EP 0 235 827 A2 I obtained only bibliographic/title data; its claim-level description above is low-confidence relative to the other four references.

I'll ground this analysis by pulling details on the key examiner-cited references before mapping them to the claims.

Obviousness Analysis — US 5,055,859 (Casio) under 35 U.S.C. § 103

Retrospective validity-style analysis. Builds on the bibliographic, claim-mapping, and litigation sections above; does not repeat them. Not legal advice.

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0. Scope, controlling law, and evidentiary caveats

Governing statute. Application 07/430,885 was filed 1989-11-02 with earliest priority 1988-11-16. Pre-AIA 35 U.S.C. § 103(a) therefore controls ("the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art"). The AIA's § 103 rewrite and the KSR-codifying "additional motivations" of AIA § 103 do not apply as written, although KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007) and Graham v. John Deere Co., 383 U.S. 1 (1966) supply the analytical framework.

Posture. The claims here are apparatus claims only (claims 1–13: independent claims 1, 6, 9 are "A thermal print head"; claim 7 is "A thermal printing apparatus"). Despite the specification's thorough manufacturing disclosure (FIGS. 4A–4K), no method claim issues in this patent — a point worth flagging because a § 103 analysis of the disclosed process (Sony/Teletype silicon-gate flow) would be a separate, and in my view weaker-for-the-patent, exercise.

What I actually verified vs. inferred — read this before relying on any element mapping. I retrieved the claims/abstract/selected specification text of some references in this session; for others I have only a title and a snippet. I have not read the full specifications of all five examiner-cited references and have no file wrapper / prosecution history (I cannot say which references the examiner applied, or how). Accordingly:

Where I cannot cite a specific passage I say so rather than fabricate column/line cites. The EP '827 and Teletype excerpts below are quoted verbatim from the sources retrieved.

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1. Person of ordinary skill in the art (POSITA)

A POSITA as of November 1988 would hold a B.S. in electrical engineering, applied physics, or materials science (or equivalent) and have roughly two to four years of experience in one or both of: (a) thermal print head design, and (b) MOS integrated-circuit fabrication. That person would be familiar as a matter of course with:

• silicon-gate MOS processing (thermal oxidation, gate oxidation, ion implantation/diffusion of source/drain, polysilicon deposition and doping, Al metallization, PSG/SiN passivation) — the entire flow recited in FIGS. 4A–4K;
• polysilicon resistors as heating elements (already used in commercial thermal heads and in Sony EP '827);
• the standard thermal-head driver architecture: serial shift register → latch → high-current drive transistor array, one driver per heater (the architecture of the patent's own FIG. 3);
• multi-level metallization with interlevel dielectrics for cross-over wiring; and
• the trade-off that a thermally conductive substrate sinks heat away from surface heating resistors (addressed by glazing/heat-accumulation layers).

Importantly, the patent's own "Description of the Related Art" admits that "Recently… a novel arrangement has been proposed such that heating elements and print driver circuit elements … are formed together on one and the same insulating substrate." That admission fixes the integration concept itself as prior-art-level knowledge and frames the remaining question as substrate choice and layer arrangement, not the idea of monolithic integration.

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2. Prior-art inventory (grounded)

All five examiner-cited references predate 1988-11-16 and qualify under pre-AIA § 102(a)/(b).

(A) EP 0 235 827 A2 — Sony, publ. 1987-09-09 (worldwide.espacenet.com/publicationDetails/claims?...NR=0235827A2; PDF: patentimages.storage.googleapis.com/2c/bf/01/89556c539f57e0/EP0235827A2.pdf). This is the closest art and is the very "recently proposed" arrangement the patent's background blurs. Claim 1 (verbatim):

"A thermal print head containing super-thin polycrystalline silicon film transistors, characterized in: heating resistors (3B, 2l) formed in a thin polycrystalline silicon layer (3) formed over a substrate (l); and a driving circuit comprising super-thin film transistors (4, 5, 6) each having a thin active layer (3c) formed in said polycrystalline silicon layer (3)."

Additional Sony disclosures directly on point:

• Claim 3: "the material forming said heating resistors (3B) is the same as that forming the respective active layers (3c)" of the transistors. Claim 4: heating resistors and gate electrodes (7) "formed of the same material."
• Claim 7: "a convex second thermal resistance layer (22) is formed between each said heating resistor (3B) and said insulating silicon substrate (l)." → the protuberance analog.
• Claim 9: "a layer (l3) of abrasion resistant material is applied over the areas of said resistors (3B, 2l) and said driving circuits (4, 5, 6)." → the protective-film analog.
• Spec: "since the insulating substrate is a highly heat-conductive silicon substrate, and a 1 to 500 µm thick thermal resistance layer … is formed over the insulating substrate …"; and "the thermal print head of the present invention is manufactured without resorting to complex processes including a wire bonding process, the reliability thereof is enhanced."

(B) US 4,429,321 — Canon (Matsumoto), issued 1984-01-31 (patents.google.com/patent/US4429321A/en). Abstract (verbatim): a device comprising "an electrothermal transducer provided for each heat actuating chamber … and a driving circuit portion comprising a plurality of function elements for separating signals to drive independently each of the electrothermal transducers and for driving the electrothermal transducers. The plurality of electrothermal transducers and the plurality of function elements are structurally formed in the surface of a substrate, or the plurality of electrothermal transducers are mounted on the surface of a substrate in the surface of which the function elements are formed, and the electrothermal transducers are mounted in a form of a laminating structure." The background discusses the drive "signal separating element array (e.g. transistor array and diode array accompanied with a signal amplifying means)" and the need for "a highly integrated recording head of high density and long head length," criticizing the practice of making element arrays "independently … in a form of chip."

(C) US 3,813,513 — IBM, issued 1974-05-28 (patents.google.com/patent/US3813513A/en). Snippet: "the heating elements are formed by conventional integrated circuit techniques, they can be formed in a single wafer into which can also be concurrently integrated the necessary drive and character generating circuits"; and disclosure of "a semiconductor substrate comprised of coplanar layers of opposite conductivity type … a base layer of one conductivity type on which is grown an epitaxial layer of opposite conductivity type in which are formed the required number of active and passive components." Note the "character generating circuits" — i.e., serial data handling integrated with the heaters.

(D) EP 0 129 914 A1 — Teletype (Christian & Zuercher); U.S. counterpart US 4,468,857 (patents.google.com/patent/EP0129914A1/en; uspto.report/patent/grant/4,468,857). Expressly a method "particularly adapted for thermal printing." Step 1 (verbatim): "an N-type silicon wafer 10 … has formed therein several individual integrated circuits 12 … by way of example MOS structures … source-drain doped regions 14 and 16 and a gate region 18, which in combination forms a transistor 20 … Another doped region 22 in the surface of the wafer forms a resistor." Step 3: "metallic conductors 32 … connecting the transistor 20 to the resistor doped region 22." Steps 4, 10: triple SiO₂/SiN passivation and photoshaping "wafer segments 68 positioned over resistor doped regions 22" (thermal isolation). Abstract: "The integrated circuit includes an active circuit and a passive heating element controlled by the active circuit."

(E) US 4,660,052 — Kaiya, issued 1987-04-21. I could not retrieve any disclosure text. I will not characterize its teaching. It is on the face of the patent and should be verified against the full document before being relied upon in any formal proceeding.

Not usable as § 103 prior art: every "Cited By" reference in the record (Canon US 5,517,224; US 5,602,576; Rohm; Lexmark US 5,774,148; HP US 6,883,894; the 2019 Rohm publication, etc.) postdates the 1988-11-16 priority date. They are relevant only as evidence of how the field developed (i.e., that the claimed architecture became routine) — not as prior art.

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3. Element mapping — independent claims

Claim 1

No single reference anticipates claim 1 (Sony has poly-Si heaters + poly-Si TFT drivers but not single-crystal implanted drivers; IBM/Teletype have single-crystal implanted devices but not poly-Si heaters). Claim 1 is therefore a § 103 case, not § 102.

Claim 6 (common conductor over an interposed insulator)

Claim 6 requires: parallel poly-Si elements; selective conductors from the driver to one end of each; an insulating layer covering the poly-Si elements and the selective conductors; and a common conductor formed on that insulating layer, along the direction of the selective conductors, connecting the other ends.

Mapping: Sony claim 9 (insulating/abrasion layer applied over the resistors and driving circuits) plus Canon/IBM (a driver-side array feeding individual heaters with a return path) supplies the layer stack. The cross-over common return conductor as such is not, on the record I retrieved, squarely shown by a single reference — this is the patent's most defensible independent claim against a single reference. But two-level metallurgy (metal-1 = selective conductors, interlevel oxide, metal-2 = common bus) was generic IC practice by 1988, and Teletype itself builds a multi-layer sandwich over conductors. This is a classic § 103 combination of a device reference + a known IC fabrication technique, not a novel device.

Claim 7 (staggered two-line multi-head printing apparatus)

Requires: multiple heads each with substrate + driver + edge-aligned heating region + glazed heat-accumulation layer + selective conductors + common conductor + external terminals; a supporting substrate carrying the heads in two lines; bonding means; staggered so no two heating regions overlap longitudinally; adjacent substrates' side edges facing each other.

Mapping: the glazed layer is disclosed in substance by Sony EP '827 (thermal-resistance/heat-accumulation layer over the silicon substrate, thickness 1–500 µm to "prevent the excessive accumulation of heat"). The per-head architecture comes from claims 1/6-type references. The staggered two-row butted array is the standard way to assemble a long line head from short chips; Canon '321 and IBM '513 both discuss "full line" / "long head length" integration and "a linear array of a series of character matrixes can be employed in printer fields" (IBM snippet). Whether staggering with no longitudinal overlap is squarely shown is something I cannot confirm from the retrieved text — flag as the strongest obviousness question in the patent.

Claim 9 (claim 1 + interposed insulating layer between substrate and poly-Si)

This is easier to invalidate than claim 1, because the added limitation is the one the prior art most clearly supplies: Sony EP '827 puts the poly-Si layer over an insulating/thermal-resistance layer on the silicon substrate; Teletype uses field oxide; Canon '321 uses an interposed (laminating) structure. The claim-9 "insulating a low resistance region" typo (flagged in the prior section) does not change the scope.

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4. Grounds of obviousness (§ 103 combinations)

Ground 1 — Claim 1 (and claims 2–5, 13) obvious over IBM '513 in view of Sony EP '827, further in view of Teletype ('857/EP '914)

• IBM '513 teaches the core concept: heating elements fabricated by conventional IC techniques in a single wafer into which drive and character-generating circuits are concurrently integrated (→ single-crystal substrate, integrated driver, ≤ integrated data-handling logic).
• Sony EP '827 teaches replacing diffused semiconductor heaters with polycrystalline-silicon heating resistors on the same substrate as the driver, plus a same-material poly-Si gate electrode, a protective layer, and a convex layer under each heater.
• Teletype '857 teaches the enabling silicon-gate MOS flow in an N-type silicon wafer in which an implanted/doped MOS transistor and a doped resistor are connected by an aluminum film conductor and passivated — i.e., the exact "impurity-implanted driver + thin-film wiring + protective film" structure.
• Canon '321 independently confirms it was known to put "electrothermal transducers and … function elements … in the surface of a substrate" and to desire "high density and long head length."

Result: every element of claim 1 is taught or suggested across these references; the only "assembling" step is placing the poly-Si heater of Sony onto the single-crystal implanted-driver structure of IBM/Teletype.

Ground 2 — Claim 9 obvious over Sony EP '827 in view of Teletype '857 (and Canon '321)

Sony supplies poly-Si heater over an insulating layer on a silicon substrate with an integrated driver; Teletype supplies the single-crystal, impurity-implanted driver and the metal wiring. Claim 9's added "interposed insulating layer" is literally Sony's structure.

Ground 3 — Claims 10–13 obvious over Sony EP '827 + claim 1 grounds

• Claim 10 (protuberant protective film over the heater): Sony claim 7 discloses "a convex second thermal resistance layer" between each heating resistor and the substrate — the same edge-standout/contact function the Casio specification attributes to the protuberance 12 and its overlying raised protective film.
• Claims 11/12 (CMOS shift register/latch): CMOS logic was standard; motivation = low-power logic alongside a high-current N-MOS output stage. Claim 13 mirrors claim 1's functional recitation and falls with Ground 1.

Ground 4 — Claims 2–5 obvious

• 2 (all-MOS): Sony's TFTs and Teletype's MOS structures are MOS-type; IBM/Canon use transistor arrays.
• 3 (CMOS logic): routine design choice.
• 4 (N-channel output MOS): the ordinary choice for a high-current, single-supply (ground-referenced) heater driver; the patent itself calls the N-MOS output FET a "high-current transistor."
• 5 (terminal projecting from the protective film = bump): Teletype '857 claim 3 and IBM teach external electrical connections; projecting bump/beam-lead contacts were conventional.

Ground 5 — Claims 6 and 8 obvious over (Sony EP '827 + Canon '321/IBM '513) in view of the routine two-level-metallization technique of Teletype '857

The insulator-over-conductors-and-resistors structure is Sony claim 9 / Teletype passivation; the routing of a common return bus on a second metal level over an interlevel dielectric is a generic IC technique whose use to move the heating row to the substrate edge is motivated by the ordinary desire for uniform record-medium contact (the patent's own stated purpose).

Ground 6 — Claim 7 obvious over Sony EP '827 + Canon '321 in view of the known staggered-array assembly of a long print bar

Each head element (glazed layer per Sony; edge heaters; selective and common conductors; external terminals) is supplied; mounting multiple short heads on a support in two staggered rows to build a full-width bar is the known engineering answer to Canon's articulated "full line recording head" objective. This is the ground I'd scrutinize hardest — see § 5.

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5. Motivation to combine (KSR factors)

1. Same field, same problem. IBM '513, Sony EP '827, Canon '321, and Teletype '857 all address thermal/element recording heads; all four confront the identical problem the Casio background states: integrating heat generators with their drive circuitry to raise dot density and shrink/ruggedize the head. There is no field-crossing leap.
2. The prior art itself announces the motivation. Sony states the point-blank rationale the Casio claims rely on: integration "without resorting to complex processes including a wire bonding process" enhances reliability. Canon states the goal of "high density and long head length" and condemns the "chip"-per-array practice as "troublesome and the mass production efficiency … very low." IBM states concurrent integration of drive and character-generating circuitry into the same wafer. These are explicit "reason that would have prompted" statements (KSR; MPEP 2144.01).
3. Predictable result / routine substitution. Placing a poly-Si resistor layer and a metal interconnect over a single-crystal silicon wafer carrying implanted MOS devices is the ordinary silicon-gate process (Teletype). The claimed result — an integrated thermal head — is the predictable output of combining known elements with no change in their respective functions (KSR; MPEP 2143.01).
4. Finite, predictable design choices. The field had essentially two substrate families — insulating/ceramic substrates (patent background) and silicon substrates with a thermal-resistance layer (Sony) — and one device family — poly-Si TFT vs. single-crystal MOS. Choosing the higher-mobility single-crystal MOS option (which the patent's own abstract touts) is a design choice with a predictable speed benefit, not a discovery.
5. Design incentive / market force. The contemporaneous push to higher dot density (the patent recites 16–32 dots/mm) and longer heads (widely used later, up to 600 DPI) created exactly the "design incentive … market demand" KSR treats as a motivation to combine.

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6. Nonobviousness considerations (and why I do not think they save the claims)

(a) Arguable teaching-away: silicon as a heat sink. A single-crystal silicon substrate conducts heat away from surface heating resistors, reducing print efficiency. Sony accordingly interposes a 1–500 µm "thermal resistance layer" over its silicon substrate, and Casio's own solution uses the protuberance 12 (embodiment 1) and the glazed layer 51 (embodiment 2) for the same purpose. A patentee could argue this dissuades a POSITA from using bare single-crystal silicon.

Assessment: the argument is weak to moderate. It is weak against claims 1/9, because Sony expressly contemplates a silicon substrate and the claims accommodate an interposed insulating layer; and it is weak against claim 10, because Sony's convex thermal-resistance layer (claim 7) is the standout-contact solution. It bites hardest on claim 7's glazed layer absent Sony — but Sony supplies precisely that layer. The argument amounts to "the reference teaches the countermeasure, so we'd use the reference," which reinforces rather than defeats combination.

(b) Secondary considerations. The record I can access contains no evidence of unexpected results, commercial success tied by nexus to the claimed features, long-felt-but-unsolved need, failure of others, copying, or licensing. The patent's own background concedes that same-substrate integration had already been "proposed," which dissipates any nexus between "integration" and an objective indicia. Under Graham/KSR, absent rebuttal evidence, the prima facie case stands.

(c) Claim-drafting weaknesses that narrow the distance. As noted in the prior section, claims 11 and 12 are textually identical and depend on claim 10, which contains no shift-register/latch antecedent; claim 9 contains the "insulating a low resistance region" artifact. These are validity-cleanup defects, not nonobviousness arguments.

(d) Prosecution history unknown. I lack the file wrapper, so I cannot say whether the examiner already relied on these same references under § 103 or only under § 102. That matters for how much weight a court would give the examiner's citation, and it should be checked before finalizing any opinion.

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7. Bottom line

• Claim 1 (and 13): strong § 103 case — IBM '513 + Sony EP '827 + Teletype '857 (Canon '321 corroborating).
• Claim 9: stronger still — Sony EP '827 + Teletype '857.
• Claim 10: strong via Sony claim 7 (convex layer = protuberance analog).
• Claims 2–5: strong as routine design choices on the Ground-1 record.
• Claim 6 (and 8): moderate — requires adding the known two-level-metallization technique to route the common bus; the strongest independent claim against a single reference, but still a conventional-fabrication combination.
• Claim 7: weakest ground — I could not verify that any single reference (or obvious combination) squarely discloses staggered, non-longitudinally-overlapping heads with facing substrate edges; this claim needs a targeted search (e.g., 1980s full-line/staggered thermal-head art) before an opinion is firm.
• US 4,660,052 (Kaiya) must be read in full before being relied on; I could not characterize it.

Confidence: The element mappings for claims 1, 9, 10, and the dependent claims rest on verbatim claims/abstracts/spec excerpts I retrieved for Sony EP '827, Canon '321, IBM '513, and Teletype '857 — high. The claim 6 and claim 7 grounds, and any characterization of Kaiya, are provisional and should be confirmed against the full documents and the file wrapper. No reference here anticipates claim 1 outright; the case is a § 103 combination case, and the combination rationale is well-supported by the references' own stated purposes (eliminating wire bonding, raising density, enabling long heads).