US 10937880

Here is a concise summary of US patent 10937880:

US Patent 10,937,880 B2

• Title: Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
• Current Assignee: Oak Ip LLC
• Original Assignee: Acorn Semi LLC
• Inventors: Daniel E. Grupp, Daniel J. Connelly
• Filing Date: May 12, 2020 (This patent is a continuation of application Ser. No. 15/929,592, filed May 12, 2020)
• Issue Date: March 2, 2021
• Abstract: An electrical device is described, featuring an interface layer placed between and in contact with a conductor and a semiconductor.

Plain-Language Overview of Independent Claims:

• Claim 1: This claim describes an electrical device that includes a semiconductor, a metal, and an interface layer positioned between them. This interface layer is designed to achieve two main goals: (1) "depin" the Fermi level of the semiconductor (meaning it prevents the Fermi level from being fixed by surface effects), and (2) still allow electrical current to flow between the metal and the semiconductor when the device is under electrical bias. A key characteristic is that the device has a specific contact resistance of less than approximately 10 Ω-μm². The interface layer can consist of a single passivation layer or a combination of a passivation layer and a separation layer.
• Claim 11: This claim also describes an electrical device, featuring a silicon-based semiconductor, a conductor, and an interface layer situated between them. This interface layer is designed to make the Fermi level of the conductor (i) align with the conduction band of the semiconductor, (ii) align with the valence band of the semiconductor, or (iii) be independent of the Fermi level of the semiconductor. Importantly, the interface layer is thin enough to allow current flow with a specific contact resistance of less than or equal to approximately 10 Ω-μm². The interface layer is formed by heating the semiconductor in the presence of a nitrogenous material (like ammonia, nitrogen gas, or plasma-generated nitrogen) within a vacuum chamber.
• Claim 17: This claim outlines a method for creating an electrical junction that "depins" the Fermi level of a semiconductor. The method involves placing an interface layer between a surface of the semiconductor and a conductor. This interface layer is specifically designed to (i) be thick enough to reduce the effects of metal-induced gap states (MIGS) in the semiconductor, and (ii) passivate the surface of the semiconductor (terminate dangling bonds). Despite the presence of this layer, the method ensures that significant current can flow between the conductor and the semiconductor because the interface layer's thickness is chosen to achieve a minimum (or near minimum) specific contact resistance for the junction. The interface layer can be a passivating material like a nitride, oxide, oxynitride, arsenide, hydride, and/or fluoride.

USPTO and CAFC 2026 Docket Information:

As of April 26, 2026, general searches for US patent 10937880 on public patent databases indicate its legal status as "Expired - Fee Related". The search for CAFC 2026 dockets did not return any specific litigation cases directly involving US Patent 10937880.

Known litigation involving US patent 10937880 includes:

• Case Number: IPR2025-01129

  • Plaintiff(s): Unified Patents
  • Defendant(s): (Not explicitly stated in the provided snippet, but Unified Patents typically challenges patents on behalf of its members, making them the petitioner against a patent owner).
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Filing Date: (Not explicitly stated in the provided snippet, but implied by the case number IPR2025-XXXXX to be filed in 2025)
  • Outcome/Current Status: Settlement

• Case Number: 1:25-cv-00142

  • Plaintiff(s): (Not explicitly stated in the provided snippet, but the context suggests Acorn Semi LLC or Oak IP LLC as the patent owner at various times)
  • Defendant(s): (Not explicitly stated in the provided snippet)
  • Jurisdiction: Delaware District Court
  • Filing Date: (Not explicitly stated in the provided snippet, but implied by the case number 1:25-cv-XXXXX to be filed in 2025)
  • Outcome/Current Status: Litigation

Additionally, the patent family has "First worldwide family litigation filed" according to Darts-ip.

Proceedings overview

One AIA trial proceeding has been filed against US patent 10937880. This proceeding was terminated due to settlement, meaning no claims were invalidated or sustained by the PTAB. As the sole proceeding concluded with a settlement rather than a merits decision, the patent's claims remain untested by the PTAB, offering limited defensive hardening or vulnerability from this particular challenge.

IPR2025-01129 — GLOBALFOUNDRIES Inc. et al. v. Oak Ip LLC

• Type: Inter Partes Review
• Filed: 2025-06-11
• Status: Terminated-Settled. This indicates the parties resolved the matter outside of a full PTAB trial.
• Judge panel: Not publicly available due to termination before institution or final decision.
• Petition grounds: Specific claims challenged, prior art, and statutory bases (e.g., § 102, § 103, § 112) are not publicly available as the proceeding terminated prior to a full institution decision or final written decision.
• Institution decision: Not applicable; the proceeding was terminated-settled before a decision on institution was reached.
• Final Written Decision: Not issued due to the settlement and termination of the proceeding.
• Settlement / termination: The proceeding was last modified and terminated as settled on 2025-12-11. The specific terms of the settlement are confidential.
• Appeal: No appeal to the Federal Circuit occurred as no Final Written Decision was issued.
• Defensive value: This proceeding provides no PTAB-adjudicated claim invalidity or patentability findings. While it indicates the patent was asserted or challenged, the settlement means the claims of US10937880 remain untested by PTAB review. Any future IPR would need to establish its own grounds.

Strategic summary

All claims of US10937880 remain untested by PTAB adjudication. The single IPR proceeding, IPR2025-01129, was terminated as settled between GLOBALFOUNDRIES Inc. et al. and the patent owner, Oak Ip LLC, on 2025-12-11. This means there has been no decision on the merits regarding the patentability of any claims within US10937880. Consequently, no claims have been canceled or sustained by the PTAB through a Final Written Decision.

The estoppel landscape under § 315(e)(2) for IPR2025-01129 is limited. Since the proceeding terminated via settlement and not a Final Written Decision, the petitioner (GLOBALFOUNDRIES Inc. et al.) and its privies are not formally estopped from raising grounds that were raised or reasonably could have been raised, in the same way they would be following an FWD. However, specific settlement agreements often include covenants not to sue or challenge, which would bind the settling parties. For other potential defendants, all prior art grounds remain theoretically available for future PTAB challenges. There is no clear pattern signal from this single, settled proceeding regarding the patent owner's strategy beyond their willingness to settle.

Recommended next steps

The patent US10937880 currently has no claims invalidated by the PTAB. The existing IPR2025-01129 was terminated due to settlement. A defendant facing assertion of this patent should be aware that the claims have not been formally reviewed by the PTAB. If considering a new PTAB challenge, all prior art grounds against the claims of US10937880 are still available, assuming no privy relationship with the prior petitioner or specific terms of the IPR2025-01129 settlement agreement are implicated. The termination status for IPR2025-01129 can be viewed on the USPTO Open Data Portal.

Inventors

• Daniel E. Grupp: Employer at time of filing not determinable from the patent text or available public records.
• Daniel J. Connelly: Employer at time of filing not determinable from the patent text or available public records.

No unusual patterns observed regarding inventor departures, as employment information at the time of filing is not readily available.

Original assignee

The original assignee, as listed on the issued patent US10937880B2, is Acorn Semi LLC.

Their primary line of business and whether they shipped a product embodying the claims is not explicitly stated in the patent. However, the nature of the patent (semiconductor processing and devices) suggests that Acorn Semi LLC was likely involved in semiconductor technology.

Current Status: Based on the assignment records, Acorn Semi LLC has reassigned the patent multiple times, most recently to Oak IP LLC in 2024. Their current operating status as an independent entity is not definitively known from the provided information, but the reassignment pattern suggests a divestment of this particular patent.

Assignment timeline

• 2020-09-15 (executed) / recorded 2020-09-15 — Reel 055106/0831

  • Conveyance: Assignment
  • Assignor: GRUPP, DANIEL E., CONNELLY, DANIEL J. (Inventors)
  • Assignee: ACORN TECHNOLOGIES, INC.
  • Correspondent: BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN LLP, 1279 OAKMEAD PARKWAY, SUNNYVALE, CALIFORNIA, 94085-4040.
  • Context: Internal transfer from inventors to a related corporate entity.

• 2020-09-15 (executed) / recorded 2020-09-15 — Reel 055106/0831

  • Conveyance: Assignment
  • Assignor: ACORN TECHNOLOGIES, INC.
  • Assignee: ACORN SEMI, LLC
  • Correspondent: BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN LLP, 1279 OAKMEAD PARKWAY, SUNNYVALE, CALIFORNIA, 94085-4040. This correspondent recurs in this chain.
  • Context: Internal reorganization / transfer within related corporate entities.

• 2024-12-26 (executed) / recorded 2024-12-26 — Reel 066708/0462

  • Conveyance: Assignment
  • Assignor: ACORN SEMI, LLC
  • Assignee: OAK IP, LLC
  • Correspondent: Daniel J. Connelly, 12909 SW 13TH STREET, VANCOUVER, WA, 98684. This correspondent recurs in this chain.
  • Context: Transfer to asserter.

• 2024-12-26 (executed) / recorded 2024-12-26 — Reel 066708/0462

  • Conveyance: Release By Secured Party
  • Assignor: THE PETER NORTON LIVING TRUST
  • Assignee: ACORN SEMI, LLC
  • Correspondent: Daniel J. Connelly, 12909 SW 13TH STREET, VANCOUVER, WA, 98684. This correspondent recurs in this chain.
  • Context: Release of security interest from a prior secured party.

• 2024-12-26 (executed) / recorded 2024-12-26 — Reel 066708/0462

  • Conveyance: Release By Secured Party
  • Assignor: THE PETER NORTON LIVING TRUST
  • Assignee: ACORN TECHNOLOGIES, INC.
  • Correspondent: Daniel J. Connelly, 12909 SW 13TH STREET, VANCOUVER, WA, 98684. This correspondent recurs in this chain.
  • Context: Release of security interest from a prior secured party.

Timeline diagram

timeline
    title Ownership of US 10937880
    2020 : Assigned to Acorn Technologies
         : Assigned to Acorn Semi LLC
    2021 : Issued
    2024 : Assigned to Oak IP LLC
         : Security interest released

NPE / troll-pattern signals

1. Shell-entity transfer — present. The patent was assigned from Acorn Semi LLC to Oak IP LLC on 2024-12-26 (Reel 066708/0462). The name "Oak IP, LLC" strongly suggests a licensing-only entity, and the correspondent, Daniel J. Connelly, is also listed as an inventor, which is a common pattern for inventor-controlled assertion entities. Further, Unified Patents lists litigation for this patent naming "Oak IP LLC" as petitioner.

2. Known asserter in the chain — present. Unified Patents lists IPR2025-01129 filed (Settlement) for this patent, indicating assertion activity by a petitioner. While Oak IP LLC is not one of the named entities in your prompt, it is identified as an asserter by Unified Patents.

3. Repeat correspondent across the chain — present.

   • BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN LLP appears on both 2020-09-15 assignments (Reel 055106/0831).
   • Daniel J. Connelly (identified as an inventor) from 12909 SW 13TH STREET, VANCOUVER, WA, 98684, appears on all three 2024-12-26 recordings (Reel 066708/0462). His involvement as both an inventor and the correspondent for the transfer to an IP-named LLC is a significant signal.

4. Cascading transfers — not present. While there are two assignments on the same date in 2020, they appear to be internal transfers. The transfer to Oak IP LLC is a single step four years later.

5. Pre-litigation transfer — present. The assignment to Oak IP LLC was recorded on 2024-12-26. Unified Patents indicates a PTAB case IPR2025-01129 was filed, and a US case was filed in Delaware District Court (1:25-cv-00142). The filing of these actions shortly after the assignment strongly suggests the transfer was made in anticipation of litigation. The specific date of the Delaware District Court filing is not provided but is indicated as being in 2025, within 6 months of the assignment.

6. Bankruptcy fire-sale — not present. There is no indication of bankruptcy proceedings for Acorn Semi LLC or Acorn Technologies, Inc.

7. Privateering — unclear. While the assignment to Oak IP LLC and subsequent litigation activity suggest assertion, there's no public information in the provided context directly linking Oak IP LLC's assertions to an operating company's competitive strategy.

8. Defensive aggregator (anti-NPE) — not present. The chain ends with Oak IP LLC, which is involved in patent assertion.

Verdict

NPE — high confidence. The presence of an IP-named assignee (Oak IP LLC), direct evidence of patent litigation shortly after the assignment to Oak IP LLC, and the repeated appearance of Daniel J. Connelly (an inventor) as correspondent for the final transfer to Oak IP LLC, all strongly indicate an NPE strategy. These patterns are clearly visible in the USPTO assignment records for reel 066708/0462, dated 2024-12-26, and corroborated by the litigation data on Google Patents.

USPTO Assignment Center search page for US10937880

Here is an analysis of the most relevant prior art for US Patent 10,937,880, focusing on patent citations with priority dates before August 12, 2002, which is the priority date of US10937880. The information is drawn from the provided patent text and the "Prior art citations" section of the Google Patents page for US10937880.

Key Claims of US10937880 for Anticipation Analysis:

• Claim 1 (Electrical device): An electrical device comprising a semiconductor, a metal, and an interface layer between them. The interface layer is configured to depin the Fermi level of the semiconductor (by terminating dangling bonds and reducing MIGS by displacement) and allow current flow. The specific contact resistance is less than approximately 10 Ω-μm².
• Claim 11 (Electrical device): An electrical device with a silicon-based semiconductor, a conductor, and an interface layer. The interface layer causes the Fermi level of the conductor to align with the conduction band, valence band, or be independent of the Fermi level of the semiconductor. The specific contact resistance is less than or equal to approximately 10 Ω-μm². The interface layer is formed by heating the semiconductor in a nitrogenous material within a vacuum chamber.
• Claim 17 (Method): A method for creating an electrical junction that depins the Fermi level of a semiconductor by placing an interface layer between the semiconductor and a conductor. The interface layer (i) is thick enough to reduce effects of MIGS and (ii) passivates the surface. Its thickness is chosen to provide a minimum (or near minimum) specific contact resistance. The interface layer includes a passivating material (e.g., nitride, oxide, hydride).

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Most Relevant Prior Art (Anticipating under 35 U.S.C. § 102)

The following prior art patents are identified as highly relevant due to their disclosure of interface layers or thin dielectric films for modifying Schottky barrier heights, with priority dates predating US10937880's priority date of August 12, 2002.

1. US 6,433,385 B1

• Full Citation: US 6,433,385 B1 to Ramdani et al., titled "Device and method for reducing Schottky barrier height in a metal-semiconductor contact"
• Publication Date: August 13, 2002
• Filing Date: April 20, 2001 (Predates US10937880's priority date)
• Brief Description: This patent describes a semiconductor device that includes a metal contact on a semiconductor surface with an intermediate layer between them. The intermediate layer consists of a silicon compound with a thickness and composition sufficient to reduce the Schottky barrier height between the metal and the semiconductor.
• Potential Anticipation (35 U.S.C. § 102):
  • Claim 1: Potentially anticipates the broad concept of an electrical device with a metal, semiconductor, and an intermediate layer to reduce Schottky barrier height. However, it does not explicitly disclose "depinning the Fermi level" as defined by US10937880 (i.e., by terminating dangling bonds and reducing MIGS by displacement), nor does it specify the target specific contact resistance of less than approximately 10 Ω-μm².
  • Claim 11: The patent describes an intermediate layer affecting electrical properties between a conductor and a semiconductor. However, it lacks specific disclosures regarding the Fermi level aligning with the conduction/valence band or being independent, the precise low specific contact resistance values, and the method of forming the layer by heating in a nitrogenous material within a vacuum chamber.
  • Claim 17: Potentially anticipates the general method of using an intermediate layer to reduce Schottky barrier height. However, it does not explicitly teach the specific combined mechanisms of reducing MIGS through displacement and full surface passivation for depinning the Fermi level, nor the optimization for achieving a minimum specific contact resistance.

2. US 6,166,405 A

• Full Citation: US 6,166,405 A to Lin et al., titled "High-performance Schottky source/drain MOSFET and method of manufacture"
• Publication Date: December 26, 2000
• Filing Date: October 8, 1998 (Predates US10937880's priority date)
• Brief Description: This patent discloses a MOSFET with Schottky source/drain contacts, where a thin dielectric layer (e.g., nitride or oxide) is formed between the metal and the semiconductor to effectively lower the Schottky barrier height.
• Potential Anticipation (35 U.S.C. § 102):
  • Claim 1: Highly relevant, describing an electrical device (MOSFET) with a metal, semiconductor, and a thin dielectric interface layer (nitride/oxide) to lower Schottky barrier height and permit current flow. The core structural elements and the function of modifying barrier height with an interface layer are present. However, similar to US6433385B1, it lacks the explicit definition of "depinning the Fermi level" (including MIGS reduction by displacement) and the specific contact resistance range of less than 10 Ω-μm².
  • Claim 11: Describes using a thin dielectric layer (like nitride) as an interface between a conductor and a silicon-based semiconductor to affect electrical properties. It does not explicitly detail the Fermi level alignment conditions or the specific method of formation involving heating in a nitrogenous material under vacuum as broadly claimed in US10937880.
  • Claim 17: The method of forming a thin dielectric layer (nitride/oxide) to lower barrier height is disclosed. The explicit combined depinning mechanisms (passivation + MIGS reduction by displacement) and the optimization for minimum specific contact resistance are not explicitly described or claimed.

3. US 6,081,014 A

• Full Citation: US 6,081,014 A to Furukawa et al., titled "Device and method for forming semiconductor device contact having reduced Schottky barrier height"
• Publication Date: June 27, 2000
• Filing Date: October 26, 1999 (Predates US10937880's priority date)
• Brief Description: This patent details a semiconductor device contact that includes a heavily doped semiconductor region and a Schottky contact. An insulating layer (formed by nitridation or oxidation of the semiconductor surface) with a controlled thickness is placed between the metal and the heavily doped semiconductor layer to reduce the Schottky barrier height.
• Potential Anticipation (35 U.S.C. § 102):
  • Claim 1: Presents an electrical device with a metal, semiconductor, and an insulating layer (nitride/oxide) to reduce barrier height. The use of nitridation/oxidation is aligned with US10937880. However, it relies on heavily doped semiconductors and does not explicitly teach "depinning the Fermi level" as defined in 10937880 (passivation and MIGS reduction by displacement) or the specific contact resistance.
  • Claim 11: Mentions nitridation/oxidation for forming the insulating layer, which aligns with the nitrogenous material aspect. However, it relies on heavy doping and does not broadly claim specific Fermi level alignments or the precise vacuum conditions for layer formation in a manner that fully anticipates Claim 11.
  • Claim 17: The method involves forming an insulating layer by nitridation or oxidation to reduce barrier height. This overlaps with material types and general function. However, the explicit requirements of (i) reducing MIGS by thickness and (ii) passivating the surface for depinning the Fermi level, and specifically selecting thickness for minimum specific contact resistance, distinguish US10937880.

4. US 5,883,401 A

• Full Citation: US 5,883,401 A to Lin et al., titled "Schottky source/drain MOSFET with low Schottky barrier height"
• Publication Date: March 16, 1999
• Filing Date: May 29, 1997 (Predates US10937880's priority date)
• Brief Description: This patent describes a MOSFET where low Schottky barrier height for the source/drain contacts is achieved by forming a thin insulating film (e.g., SiO2, Si3N4) between the metal and the semiconductor.
• Potential Anticipation (35 U.S.C. § 102):
  • Claim 1: Very similar to US6166405A. Discloses a MOSFET with metal, semiconductor, and a "thin insulating film" (SiO2, Si3N4) to achieve low Schottky barrier height. This anticipates the structural elements and the function of lowering barrier height using an interface layer. It lacks explicit disclosure of "depinning the Fermi level" as defined by US10937880 and the specific contact resistance range.
  • Claim 11: Mentions Si3N4 (a nitrogenous material) as a thin insulating film. Similar to US6166405A, it does not explicitly detail Fermi level alignment conditions or the specific vacuum formation method.
  • Claim 17: The method of forming a thin insulating film of SiO2 or Si3N4 to lower barrier height is disclosed. The explicit combined depinning mechanisms (passivation + MIGS reduction by displacement) and the optimization for achieving minimum specific contact resistance are not explicitly present as claimed in US10937880.

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Other Patent Citations (Pre-August 12, 2002 Priority Date)

The following patents are also cited but are generally less directly anticipatory of the core claims of US10937880 due to differing mechanisms, materials, or scope.

• US 6,284,646 B1 (Sep 4, 2001; Filed: Jun 30, 2000): Describes forming self-assembled monolayers on hydrogen-terminated silicon, related to surface preparation but not the specific depinning and contact resistance aspects of US10937880.
• US 6,107,659 A (Aug 22, 2000; Filed: Jun 10, 1999): Focuses on optimizing Schottky barrier height by selecting different metals or doping, not through an interface layer that specifically depins the Fermi level by passivation and MIGS reduction.
• US 6,057,582 A (May 2, 2000; Filed: Jun 11, 1998): Focuses on reducing parasitic resistance using doping, not an interface layer for Fermi level depinning.
• US 5,977,583 A (Nov 2, 1999; Filed: May 15, 1998): Discusses silicide-free Schottky source/drain regions using direct metal-silicon contact, without the specific interface layer to depin the Fermi level as in US10937880.
• US 5,844,274 A (Dec 1, 1998; Filed: Oct 28, 1997): Relies on metal silicides for Schottky contacts, which US10937880 seeks to avoid or provide an alternative to due to Fermi level pinning.
• US 5,729,035 A (Mar 17, 1998; Filed: Jul 26, 1996): Similar to the other Schottky MOSFET patents, describes a thin dielectric layer to reduce barrier height, but without the explicit "depinning the Fermi level" definition or minimum specific contact resistance claims of US10937880.
• US 5,693,963 A (Dec 2, 1997; Filed: Jan 12, 1996): Relies on metal silicides.
• US 5,625,219 A (Apr 29, 1997; Filed: Aug 15, 1995): Focuses on low work function metals and doping, not an intermediate interface layer for Fermi level depinning via passivation and MIGS reduction.
• US 5,523,604 A (Jun 4, 1996; Filed: Oct 21, 1994): General Schottky MOSFET, no specific interface layer for Fermi level depinning.
• US 5,471,066 A (Nov 28, 1995; Filed: Mar 28, 1994): Relies on metal silicides.
• US 5,103,280 A (Apr 7, 1992; Filed: Sep 25, 1990): Focuses on silicided gates, not the source/drain interface layer for depinning.
• US 4,998,144 A (Mar 5, 1991; Filed: Dec 21, 1989): Describes a Schottky barrier diode with a guard ring, not the interface layer mechanism for Fermi level depinning.
• US 4,975,760 A (Dec 4, 1990; Filed: May 19, 1989): Describes a trench gate structure, not relevant to the core innovation of US10937880.
• US 4,933,737 A (Jun 12, 1990; Filed: Jun 30, 1989): General Schottky FET, no specific interface layer for Fermi level depinning.
• US 4,751,563 A (Jun 14, 1988; Filed: Apr 28, 1987): Relies on silicided source and drain.
• US 4,723,149 A (Feb 2, 1988; Filed: Jul 28, 1986): General Schottky FET, no specific interface layer for Fermi level depinning.
• US 4,698,656 A (Oct 6, 1987; Filed: Mar 28, 1986): Describes a Schottky diode with a guard ring.
• US 4,524,419 A (Jun 18, 1985; Filed: Jul 3, 1984): Describes a Schottky diode on amorphous silicon. US10937880 specifies silicon-based semiconductors which typically refers to crystalline silicon or its alloys.
• US 4,486,766 A (Dec 4, 1984; Filed: Oct 28, 1982): Describes a silicide Schottky contact.
• US 4,460,914 A (Jul 17, 1984; Filed: Dec 29, 1981): Describes a Schottky diode on amorphous semiconductor.
• US 4,456,926 A (Jun 26, 1984; Filed: Oct 29, 1981): General Schottky diode fabrication.
• US 4,384,299 A (May 17, 1983; Filed: Feb 24, 1981): Describes a Schottky diode with a metal silicide electrode.
• US 4,261,001 A (Apr 7, 1981; Filed: Jun 28, 1979): Describes a Schottky diode utilizing silicide.
• US 4,104,764 A (Aug 8, 1978; Filed: Oct 28, 1977): Schottky gate FET device.
• US 4,029,471 A (Jun 14, 1977; Filed: Dec 29, 1975): Schottky barrier type field effect transistor.
• US 4,000,508 A (Dec 27, 1976; Filed: Jan 28, 1976): Gallium arsenide Schottky barrier FETs (different semiconductor material).
• US 3,701,955 A (Oct 31, 1972; Filed: Apr 20, 1971): Schottky barrier field effect transistor.
• US 3,678,358 A (Jul 18, 1972; Filed: Dec 28, 1970): Schottky barrier type field effect transistor.
• US 3,490,013 A (Jan 13, 1970; Filed: Oct 26, 1966): Insulated gate field effect transistor.
• US 3,401,314 A (Sep 10, 1968; Filed: Aug 15, 1966): Schottky barrier diode.
• US 3,012,204 A (Dec 5, 1961; Filed: Feb 10, 1958): General semiconductor devices.

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Non-Patent Literature

• J. Tersoff, “Schottky Barrier Heights and the Continuum of Gap States,” Phys. Rev. Lett. 52 (6), Feb. 6, 1984.

  • Description: This scientific paper is fundamental to the understanding of Schottky barrier formation, proposing Metal-Induced Gap States (MIGS) as a key mechanism for Fermi level pinning.
  • Potential Anticipation (35 U.S.C. § 102): This reference explains the scientific problem (Fermi level pinning due to MIGS) that US10937880 seeks to overcome. It does not, however, disclose the specific technical solution of using an engineered interface layer to depin the Fermi level, passivate dangling bonds, reduce MIGS by displacement, and achieve specific low contact resistances as claimed in US10937880.

• Louie, Chelikowsky, and Cohen, “Ionicity and the theory of Schottky barriers,” Phys. Rev. B 15, 2154 (1977)

  • Description: This academic paper contributes to the theoretical framework of Schottky barriers and interface properties.
  • Potential Anticipation (35 U.S.C. § 102): Similar to Tersoff's work, this paper provides theoretical background rather than disclosing the specific inventive methods and devices of US10937880.

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Note on US 6,833,556 B2:
U.S. Pat. No. 6,833,556 B2 is explicitly mentioned in US10937880 as a "co-pending" application by the "present inventors". While it describes highly similar technology (e.g., FETs with passivated Schottky barriers, depinning the Fermi level), its filing date (January 14, 2003) is after the priority date of US10937880 (August 12, 2002). Therefore, it cannot be considered prior art under 35 U.S.C. § 102 for anticipation purposes against US10937880. It represents related inventive work by the same inventors and could be relevant for obviousness-type double patenting considerations, but not direct anticipation.

Obviousness Analysis of US Patent 10937880 under 35 U.S.C. § 103

This analysis identifies combinations of prior art references (as disclosed within the patent itself) that a person having ordinary skill in the art (PHOSITA) would have been motivated to combine, and evaluates whether such combinations would render the claims of US patent 10937880 obvious. The current date is April 26, 2026.

Overview of the Invention's Asserted Novelty

US patent 10937880 focuses on a method and device for "depinning the Fermi level" of a semiconductor at an electrical junction by introducing a thin interface layer between a metal and the semiconductor. This interface layer serves a dual purpose: (1) it passivates the semiconductor surface by terminating dangling bonds and reducing surface states, and (2) it displaces the semiconductor from the metal to reduce the effect of metal-induced gap states (MIGS). The patent asserts that this approach allows for controlled tuning of the Schottky barrier height and, critically, achieves a minimum specific contact resistance (e.g., less than approximately 10 Ω-μm²) through an "optimum thickness" of the interface layer. This optimum thickness balances the desire for a thin layer to permit tunneling current with a thick enough layer to reduce MIGS, which otherwise increase resistance by pinning the Fermi level near mid-gap.

Identified Prior Art References (from the patent's disclosure)

The patent's background section describes the state of the art and known problems, which serve as the basis for this obviousness analysis. No specific prior art patents, other than general concepts, are detailed that would anticipate the core inventive step.

• A1: Schottky (1938) and Bardeen's Model: These describe the fundamental concept of a Schottky barrier at metal-semiconductor junctions and introduce the idea of surface states causing Fermi level pinning, making the barrier height largely independent of the metal's work function. The patent states that Bardeen's model, like Schottky's, is best considered a "limiting case" rarely observed experimentally.
• A2: Tersoff (1984) and Louie, Chelikowsky, and Cohen (1977): These references explain that Fermi level pinning is primarily due to metal-induced gap states (MIGS), where metal electron wave functions decay into the semiconductor bandgap. These MIGS populate energy states that pin the Fermi level.
• A3: Conventional Semiconductor Surface Passivation: The patent describes surface passivation (e.g., with silicon dioxide) as a "common processing operation" to chemically neutralize dangling bonds and physically protect silicon. However, it notes that silicon dioxide is an "insulating dielectric" that poses a "significant barrier to the flow of current" and is difficult to grow as a thin, controlled layer.
• A4: Prior Attempts to Control Barrier Height: The patent mentions prior attempts using silicides as contact metals (which limit metal choices and result in a pinned, fixed barrier height) and high doping levels (which reduce resistance through tunneling but do not truly tune the barrier height).

Obviousness Analysis

Combination 1: A1 (Schottky/Bardeen's problem of pinning) + A2 (Tersoff's explanation of MIGS) + A3 (Conventional passivation shortcomings) + A4 (Limitations of existing solutions)

• PHOSITA's Motivation to Combine: A PHOSITA, aware of the persistent problem of Fermi level pinning (A1) and Tersoff's explanation of MIGS (A2) as a primary cause, would be highly motivated to find a solution that effectively "depins" the Fermi level. They would also be aware that conventional passivation techniques (A3) address surface states but often introduce high resistance (e.g., SiO2), and that other methods like silicides or heavy doping (A4) do not fully solve the pinning or allow for barrier height tuning. Therefore, a PHOSITA would seek an improved interface that simultaneously addresses both surface states and MIGS to achieve a truly tunable and electrically efficient junction. It would be a logical step to consider an interface layer that chemically passivates the semiconductor surface while also creating a physical separation between the metal and semiconductor to reduce MIGS effects.

• Why Claims Would Not Be Rendered Obvious by this Combination (Core Non-Obviousness):
  While the motivation exists to combine these prior art teachings to attempt depinning, this combination does not explicitly teach or suggest the critical discovery claimed by US10937880: the existence of an "optimum thickness" for the interface layer that leads to a minimum specific contact resistance (e.g., less than approximately 10 Ω-μm² or 1 Ω-μm²) by balancing the competing effects of increasing tunneling current (with decreasing thickness) and increasing MIGS-induced barrier formation (with further decreasing thickness below a certain point).

  The patent explicitly describes this as a discovery: "The present inventors have determined that for thin interface layers disposed between a metal and a silicon-based semiconductor... there exist corresponding minimum specific contact resistances." It further illustrates this "competition" and "optimum thickness" with FIG. 8. Prior art generally understood that thinner layers typically lead to lower tunneling resistance, and that separating metal from semiconductor reduces MIGS. However, the counter-intuitive observation that resistance increases again at very thin layers due to MIGS reasserting pinning, thus creating a minimum, is not taught by the combined references A1-A4. Without this insight, a PHOSITA would likely struggle to achieve the specific low contact resistances (e.g., <10 Ω-μm²) while simultaneously achieving depinning, as merely making the layer very thin for tunneling might run into the increased resistance due to MIGS.

  Therefore, the invention's emphasis on selecting an interface layer thickness to achieve this minimum specific contact resistance (as specified in Claim 1, Claim 11, and Claim 17) through the described mechanism of balancing MIGS reduction and tunneling current represents a non-obvious advancement over the collective teachings of A1, A2, A3, and A4.

Additional Considerations Regarding Specific Embodiments (e.g., Claim 11's nitrogenous formation):

Claim 11 specifically recites an interface layer formed by "heating the semiconductor in presence of nitrogenous material in a vacuum chamber." The patent itself notes that "Rapid Thermal Nitridation (RTN)" is a conventional process, implying that nitridation as a passivation technique was known. However, the patent then describes specific processing conditions (e.g., lower temperatures of 300-750° C., or high temperatures of 900-1000° C.+ in ultra-high vacuum with short pulses/small amounts of nitrogenous material) to "controllably form thin yet effective interface layers" (e.g., <1nm, monolayer thickness).

While a PHOSITA would know about nitridation, the specific combination of these precise processing parameters with the goal of achieving the "optimal thickness" for minimum specific contact resistance and Fermi level depinning, driven by the previously mentioned discovery, would not be obvious. Without the underlying understanding of the resistance-thickness curve (FIG. 8) and the resulting "optimum thickness," merely applying known nitridation techniques would likely not consistently yield the claimed device properties (depinning + very low specific contact resistance).

Conclusion

Based on the information provided within the patent document US10937880, the core inventive step, which is the discovery and application of an "optimum thickness" for an interface layer that simultaneously achieves Fermi level depinning (by both surface passivation and MIGS reduction) and a minimum specific contact resistance, is not explicitly taught or strongly suggested by the prior art acknowledged in the patent's background. While a PHOSITA would be motivated to combine existing knowledge to address the problems of Fermi level pinning, they would not be led to the specific insight of the "optimal thickness" where resistance first decreases due to tunneling but then increases again due to MIGS-induced barrier formation. This unexpected phenomenon and its exploitation to achieve specific low contact resistances represent a non-obvious contribution.

Patent Term Adjustments (PTA) and Patent Term Extensions (PTE) for US Patent 10937880

Based on the available information, here's a breakdown of the patent term adjustments, patent term extensions, related applications, and projected expiration date for US Patent 10937880:

Patent Term Adjustments (PTA)

Patent Term Adjustment (PTA) compensates patent owners for administrative delays by the USPTO during the prosecution of a utility or plant patent application. This includes delays such as not issuing an office action within 14 months of filing, not responding to an applicant's reply within four months, or not issuing a patent within three years of the filing date.

US patent 10937880 does not explicitly state any awarded Patent Term Adjustments on its Google Patents page. To determine if any PTA was granted, one would typically need to consult the patent's issue certificate or official patent data directly from the USPTO. The USPTO does not calculate expiration dates for patents, but provides resources like a downloadable patent term calculator for estimation, considering factors like PTA and PTE.

Patent Term Extensions (PTE)

Patent Term Extension (PTE) is granted for patents covering pharmaceutical products, medical devices, animal drugs, veterinary biologics, or food/color additives to compensate for time lost during the regulatory approval process by agencies like the FDA. A PTE can extend a patent's term by up to five years, but not beyond 14 years from the date of FDA approval. Only one patent can be extended for a regulatory review period for any given product.

Given the technical field of US patent 10937880, which relates to "Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions," it is highly unlikely to be eligible for Patent Term Extension (PTE) under 35 U.S.C. § 156, as it does not appear to cover a product requiring regulatory approval like a drug or medical device.

Continuation and Divisional Applications

US patent 10937880 is explicitly stated as a CONTINUATION of several earlier applications. This means it claims priority back to an earlier-filed application and typically covers the same or substantially similar subject matter as its parent application, but with different claims.

The patent text states: "The present application is a CONTINUATION of U.S. patent application Ser. No. 16/847,878, filed Apr. 14, 2020, which is a CONTINUATION of U.S. patent application Ser. No. 16/506,022, filed Jul. 9, 2019, which is a CONTINUATION of U.S. patent application Ser. No. 15/728,002, filed Oct. 9, 2017, now U.S. Pat. No. 10,388,748, which is a CONTINUATION of U.S. patent application Ser. No. 15/251,210, filed Aug. 30, 2016, now U.S. Pat. No. 9,812,542, which is a CONTINUATION of U.S. patent application Ser. No. 15/048,877, filed Feb. 19, 2016, now U.S. Pat. No. 9,905,691, which is a CONTINUATION of U.S. patent application Ser. No. 13/552,556, filed Jul. 18, 2012, now U.S. Pat. No. 9,425,277, which is a CONTINUATION of U.S. patent application Ser. No. 13/022,522, filed Feb. 7, 2011, now U.S. Pat. No. 8,431,469, which is a DIVISIONAL of U.S. patent application Ser. No. 12/197,996, filed Aug. 25, 2008, now U.S. Pat. No. 7,884,003, which is a DIVISIONAL of U.S. patent application Ser. No. 11/181,217, filed Jul. 13, 2005, now U.S. Pat. No. 7,462,860, which is a CONTINUATION of U.S. patent application Ser. No. 10/217,758, filed Aug. 12, 2002, now U.S. Pat. No. 7,084,423, all of which are hereby incorporated by reference."

This chain indicates that US10937880 is a continuation of many applications, ultimately tracing its priority back to U.S. patent application Ser. No. 10/217,758, filed on August 12, 2002.

The patent also specifies two DIVISIONAL applications in its family tree:

• U.S. patent application Ser. No. 12/197,996, filed Aug. 25, 2008, now U.S. Pat. No. 7,884,003
• U.S. patent application Ser. No. 11/181,217, filed Jul. 13, 2005, now U.S. Pat. No. 7,462,860

Related Family Members

The explicit chain of continuation and divisional applications detailed above constitutes the primary related family members described within the patent itself.

• Parent applications (in chronological order of filing from earliest to latest leading to US10937880):
  • U.S. patent application Ser. No. 10/217,758, filed Aug. 12, 2002, now U.S. Pat. No. 7,084,423
  • U.S. patent application Ser. No. 11/181,217, filed Jul. 13, 2005, now U.S. Pat. No. 7,462,860 (Divisional)
  • U.S. patent application Ser. No. 12/197,996, filed Aug. 25, 2008, now U.S. Pat. No. 7,884,003 (Divisional)
  • U.S. patent application Ser. No. 13/022,522, filed Feb. 7, 2011, now U.S. Pat. No. 8,431,469 (Continuation)
  • U.S. patent application Ser. No. 13/552,556, filed Jul. 18, 2012, now U.S. Pat. No. 9,425,277 (Continuation)
  • U.S. patent application Ser. No. 15/048,877, filed Feb. 19, 2016, now U.S. Pat. No. 9,905,691 (Continuation)
  • U.S. patent application Ser. No. 15/251,210, filed Aug. 30, 2016, now U.S. Pat. No. 9,812,542 (Continuation)
  • U.S. patent application Ser. No. 15/728,002, filed Oct. 9, 2017, now U.S. Pat. No. 10,388,748 (Continuation)
  • U.S. patent application Ser. No. 16/506,022, filed Jul. 9, 2019 (Continuation)
  • U.S. patent application Ser. No. 16/847,878, filed Apr. 14, 2020 (Continuation)
  • U.S. patent application Ser. No. 15/929,592, filed May 12, 2020 (Continuation) (Note: The provided summary states US10937880 is a continuation of 15/929,592, filed May 12, 2020. The detailed description states it's a continuation of 16/847,878, filed Apr. 14, 2020. The abstract and filing date for US10937880 also lists 15/929,592, filed May 12, 2020. This indicates a potential discrepancy in the provided text regarding the immediate parent application for US10937880. However, both ultimately trace back to the same earliest priority date).

Projected Expiration Date

The term for a utility patent, such as US10937880, is generally 20 years from the filing date of the earliest non-provisional application for which a benefit is claimed. In this case, the earliest priority date is August 12, 2002, from U.S. patent application Ser. No. 10/217,758.

Therefore, the anticipated expiration date for US Patent 10937880, without considering any potential Patent Term Adjustments or Extensions, would be 20 years from August 12, 2002, which is August 12, 2022.

However, the Google Patents information for US10937880 states its legal status as "Expired - Fee Related" and lists an "Anticipated expiration" date of "2022-08-12". This confirms the calculation based on the earliest priority date.

Here is a comprehensive "Defensive Disclosure" document for US patent 10937880, focusing on generating "Prior Art" to render future incremental improvements obvious or non-novel, based on the provided independent claims.

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Defensive Disclosure for US Patent 10937880

This document describes various technical derivatives and extensions of the core inventions claimed in US Patent 10937880, "Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions." The purpose is to establish prior art for potential future incremental innovations, making them appear obvious or non-novel, thereby limiting the scope of future patentability for competitors.

Derivations from Claim 1

Claim 1: An electrical device, comprising: a semiconductor; a metal; and an interface layer disposed between and in contact with the metal and the semiconductor and configured to depin a Fermi level of the semiconductor while still permitting current flow between the metal and the semiconductor when the electrical device is biased, wherein a specific contact resistance of the electrical device is less than approximately 10 Ω-μm², wherein the interface layer comprises a passivation layer, and wherein the passivation layer comprises at least one of a nitride, an oxide, an oxynitride, an arsenide, a hydride and a fluoride.

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Derivative 1.1: Material & Component Substitution - Two-Dimensional (2D) Semiconductor with Transition Metal Dichalcogenide (TMD) Interface

• Enabling Description: An electrical device comprising a graphene sheet (semiconductor) and a platinum (Pt) contact (metal). An interface layer, comprising a monolayer or few-layer tungsten disulfide (WS₂) film, is disposed between the graphene and the Pt. The WS₂ layer, acting as both a passivation layer and a separation layer, is formed via chemical vapor deposition (CVD) or atomic layer deposition (ALD) to achieve a thickness between 0.5 nm and 2 nm. This WS₂ interface provides a large enough bandgap to reduce metal-induced gap states (MIGS) in the graphene and passivates dangling bonds at the graphene surface, thereby depinning the Fermi level of the graphene. The specific contact resistance is maintained below 10 Ω-μm² due to efficient tunneling through the thin WS₂ layer. The choice of Pt and WS₂ enables precise tuning of the work function difference at the junction for optimized carrier injection.

graph TD
    A[Graphene Semiconductor] --> B{WS2 Interface Layer};
    B --> C[Platinum Metal Contact];
    C -- Electrical Bias --> A;
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style B fill:#bbf,stroke:#333,stroke-width:2px
    style C fill:#ccf,stroke:#333,stroke-width:2px

---

Derivative 1.2: Operational Parameter Expansion - Cryogenic High-Frequency Device with Quantum Dot Interface

• Enabling Description: An electrical device incorporating a silicon-germanium (SiGe) heterostructure (semiconductor) and a niobium (Nb) alloy (metal) contact, designed for operation at cryogenic temperatures (e.g., 4 K) and THz frequencies (e.g., 300 GHz). The interface layer consists of an array of cadmium selenide (CdSe) quantum dots embedded within a thin (< 1 nm) hafnium oxide (HfO₂) matrix. The quantum dots are precisely controlled in size (2-5 nm diameter) to introduce specific energy states that facilitate resonant tunneling, effectively depinning the SiGe Fermi level and minimizing MIGS at 4 K. The HfO₂ matrix provides passivation and structural integrity. The device exhibits a specific contact resistance well below 1 Ω-μm² under these extreme conditions, optimizing charge transport for high-frequency quantum computing or superconducting circuit applications.

graph TD
    A[SiGe Semiconductor] --> B{HfO2/CdSe QD Interface};
    B -- Resonant Tunneling --> C[Niobium Alloy Metal];
    A -- Cryogenic/THz Operation --> D[External Control Unit];
    C -- Cryogenic/THz Operation --> D;
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style B fill:#bbf,stroke:#333,stroke-width:2px
    style C fill:#ccf,stroke:#333,stroke-width:2px
    style D fill:#ddf,stroke:#333,stroke-width:2px

---

Derivative 1.3: Cross-Domain Application - Bio-Integrated Neural Interface

• Enabling Description: A bio-integrated neural interface device comprising a biocompatible silicon carbide (SiC) semiconductor substrate (biologically inert and robust) and a gold (Au) microelectrode (metal) for neural signal detection. An ultrathin (0.8 nm) silicon oxynitride (SiON) interface layer is formed between the SiC and Au via plasma-enhanced atomic layer deposition. This SiON layer is engineered to depin the Fermi level of the SiC, optimizing charge transfer with neural tissue while maintaining biocompatibility. The specific contact resistance is kept below 5 Ω-μm², ensuring efficient and low-noise electrical communication with neurons for prosthetic control or brain-computer interfaces. The SiON layer provides robust passivation against biofluids, reducing impedance drift over long-term implantation.

flowchart LR
    A[SiC Semiconductor] --> B{SiON Interface Layer};
    B --> C[Gold Microelectrode];
    C -- Neural Signal Transduction --> D(Neural Tissue);
    A -- Biocompatible --> D;
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style B fill:#bbf,stroke:#333,stroke-width:2px
    style C fill:#ccf,stroke:#333,stroke-width:2px
    style D fill:#afa,stroke:#333,stroke-width:2px

---

Derivative 1.4: Integration with Emerging Tech - AI-Optimized Interface Layer for Reconfigurable Computing

• Enabling Description: A reconfigurable computing device utilizing gallium nitride (GaN) high-electron-mobility transistors (HEMTs) as semiconductors and titanium nitride (TiN) gate contacts (metal). An interface layer, comprising a self-assembled monolayer of an organosilane derivative (e.g., aminopropyltriethoxysilane, APTS) followed by an ultrathin plasma-nitrided aluminum oxide (AlON) layer, is dynamically optimized via an integrated AI controller. During fabrication, the AI system monitors in situ deposition parameters (temperature, pressure, precursor flow) to achieve a desired interface thickness (0.3-1.5 nm) and composition, targeting minimal specific contact resistance (< 1 Ω-μm²) and precise Fermi level depinning for a particular GaN doping profile. Post-fabrication, the AI can apply small, localized electrical biases to subtly adjust interface trap states, dynamically reconfiguring the Schottky barrier height for optimal performance in different computational tasks. IoT sensors embedded in the device provide real-time electrical characteristics to the AI.

graph TD
    A[GaN HEMT Semiconductor] --> B{APTS/AlON Interface Layer};
    B --> C[TiN Gate Metal];
    D[IoT Sensors] -- Real-time Data --> E(AI Controller);
    E -- Optimization Feedback --> B;
    E -- Dynamic Tuning --> B;
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style B fill:#bbf,stroke:#333,stroke-width:2px
    style C fill:#ccf,stroke:#333,stroke-width:2px
    style D fill:#afa,stroke:#333,stroke-width:2px
    style E fill:#dde,stroke:#333,stroke-width:2px

---

Derivative 1.5: The "Inverse" or Failure Mode - Self-Limiting Current for Safe Operation in Power Electronics

• Enabling Description: A power semiconductor device, such as a silicon carbide (SiC) MOSFET, with aluminum (Al) ohmic contacts. The interface layer, in this case, is a tailored hydrogenated amorphous silicon (a-Si:H) layer deposited between the SiC and Al, with a precise thickness (2-5 nm) and hydrogen content (5-15%). This layer is designed such that, under nominal operating conditions, it behaves as described in Claim 1, providing depinning and low contact resistance (< 10 Ω-μm²). However, upon an overcurrent event (e.g., short circuit), the a-Si:H layer is engineered to undergo a localized, self-limiting structural transformation (e.g., increase in trap density, slight delamination or local crystallization) that intentionally increases its specific contact resistance by several orders of magnitude (> 100 Ω-μm²). This controlled failure mode acts as an integrated fuse, limiting current flow and protecting downstream circuitry and the device from catastrophic thermal runaway, without causing permanent damage to the bulk semiconductor. The device can then be reset or replaced.

stateDiagram-v2
    state NormalOperation {
        Semiconductor --> InterfaceLayer: Low Resistance (<10 Ω-μm²)
        InterfaceLayer --> Metal: Depinned Fermi Level
        NormalOperation --> OvercurrentDetected: Current > Threshold
    }
    state OvercurrentDetected {
        OvercurrentDetected --> ControlledResistanceIncrease: Interface Layer Transformation
        ControlledResistanceIncrease --> HighResistanceMode: Current Limited
        HighResistanceMode --> SafeShutdown: System Protection
    }
    HighResistanceMode --> NormalOperation: Reset/Replacement

---

Derivations from Claim 11

Claim 11: An electrical device, comprising: a silicon-based semiconductor; a conductor; and an interface layer disposed between and in contact with the conductor and the silicon-based semiconductor and configured to allow a Fermi level of the conductor to (i) align with a conduction band of the silicon-based semiconductor, (ii) align with a valence band of the silicon-based semiconductor, or (iii) be independent of the Fermi level of the silicon-based semiconductor, wherein current flows between the conductor and the silicon-based semiconductor when the electrical device is biased, wherein the interface layer has a thickness corresponding to a minimum or near minimum specific contact resistance for the junction of less than or equal to approximately 10 Ω-μm², and wherein the interface layer is formed by heating the silicon-based semiconductor in the presence of a nitrogenous material selected from the group consisting of ammonia (NH3), nitrogen (N2) and unbound gaseous nitrogen (N) generated from a plasma process while in a vacuum chamber.

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Derivative 11.1: Material & Component Substitution - Germanium Semiconductor with Metal Nitride Conductor and Boron Nitride Interface

• Enabling Description: An electrical device using a p-type germanium (Ge) substrate (silicon-based semiconductor analog) and a molybdenum nitride (MoN) film (conductor). The interface layer is a hexagonal boron nitride (h-BN) film, formed by heating the Ge substrate in an ultra-high vacuum chamber at 700°C under a partial pressure of nitrogen gas (N₂) derived from a remote plasma source. This method ensures a precisely controlled h-BN monolayer or bilayer (<1 nm) growth. The h-BN layer enables the Fermi level of the MoN conductor to align with the valence band of the p-type Ge, or to be intentionally shifted via localized strain engineering to be independent. The specific contact resistance is maintained below 1 Ω-μm². This architecture is optimized for high-speed p-channel devices with tailored barrier heights.

graph TD
    A[Germanium Semiconductor (p-type)] --> B{h-BN Interface Layer};
    B --> C[Molybdenum Nitride Conductor];
    D(UHV Chamber + Plasma N2) -- Heating --> B;
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style B fill:#bbf,stroke:#333,stroke-width:2px
    style C fill:#ccf,stroke:#333,stroke-width:2px
    style D fill:#ddf,stroke:#333,stroke-width:2px

---

Derivative 11.2: Operational Parameter Expansion - High-Pressure, High-Temperature Deep-Well Junction

• Enabling Description: An electrical device designed for extreme downhole drilling environments (e.g., 200 MPa, 400°C) using a deep-well silicon carbide (SiC) semiconductor (silicon-based analog). The conductor is a refractory metal alloy, specifically a tungsten-rhenium (W-Re) alloy. The interface layer is a highly stable, dense silicon nitride (Si₃N₄) film, precisely formed by rapid thermal annealing of the SiC substrate in a sealed high-pressure chamber (e.g., 10 MPa) with an ammonia (NH₃) ambient at 1200°C. This high-pressure, high-temperature synthesis produces an ultrathin (1-3 nm) Si₃N₄ layer that can withstand the operational extremes while ensuring Fermi level control (e.g., alignment with conduction band for n-type SiC). The specific contact resistance remains below 5 Ω-μm² under these severe conditions.

graph TD
    A[SiC Semiconductor (Deep Well)] --> B{Dense Si3N4 Interface Layer};
    B --> C[W-Re Alloy Conductor];
    D(High Pressure/Temp Chamber) -- NH3 Ambient --> B;
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style B fill:#bbf,stroke:#333,stroke-width:2px
    style C fill:#ccf,stroke:#333,stroke-width:2px
    style D fill:#ddf,stroke:#333,stroke-width:2px

---

Derivative 11.3: Cross-Domain Application - Space-Hardened Radiation Detector

• Enabling Description: A radiation detector for space applications, employing a high-purity silicon (Si) semiconductor and a tantalum (Ta) conductor. The interface layer is a plasma-nitrided silicon layer, approximately 0.5 nm to 1.5 nm thick, formed by exposing the Si substrate to an unbound gaseous nitrogen (N) plasma in a vacuum chamber at 450°C. This specific process creates a radiation-hardened interface that maintains Fermi level depinning and low contact resistance (< 10 Ω-μm²) even after exposure to significant ionizing radiation doses. The controlled Fermi level allows for precise adjustment of the Schottky barrier for optimal signal-to-noise ratio in radiation detection. The device is designed to operate reliably in the extreme temperature fluctuations and radiation fields of space.

flowchart LR
    A[High-Purity Silicon Semiconductor] --> B{Plasma-Nitridated Si Interface Layer};
    B --> C[Tantalum Conductor];
    D(Vacuum Chamber + N Plasma) -- Exposure --> B;
    C -- Radiation Detection --> E(Signal Processing);
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style B fill:#bbf,stroke:#333,stroke-width:2px
    style C fill:#ccf,stroke:#333,stroke-width:2px
    style D fill:#ddf,stroke:#333,stroke-width:2px
    style E fill:#afa,stroke:#333,stroke-width:2px

---

Derivative 11.4: Integration with Emerging Tech - IoT Edge Device with Self-Calibrating Junctions

• Enabling Description: An IoT edge computing device incorporating low-power silicon-on-insulator (SOI) transistors (silicon-based semiconductor) and aluminum (Al) interconnects (conductor). Each junction utilizes a nitrogen-based interface layer (e.g., amorphous silicon nitride, SiNₓ) formed by pulsed-ammonia annealing in a vacuum chamber. Integrated IoT sensors measure the instantaneous specific contact resistance and barrier height of individual junctions in real-time. This data is fed to a local AI module that uses machine learning models to self-calibrate the device by predicting and compensating for performance drift due to aging or environmental factors. Firmware updates, potentially verified via blockchain, can then dynamically adjust operational parameters (e.g., gate voltage timings) to maintain optimal Fermi level alignment and contact resistance below 10 Ω-μm² over the device's lifespan.

sequenceDiagram
    participant S as SOI Semiconductor
    participant I as SiNx Interface
    participant C as Aluminum Conductor
    participant O as IoT Sensors
    participant A as AI Module (Edge)
    participant B as Blockchain (Cloud)

    S->>I: Bias Current
    I->>C: Current Flow
    O->>A: Measure (Resistance, Barrier Height)
    A->>A: Analyze Drift (ML Model)
    A->>I: Calibrate (Adjust Params)
    A->>B: Log Performance (Secure)
    B->>A: Verify Firmware Updates

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Derivative 11.5: The "Inverse" or Failure Mode - Tunable Rectification for Adaptive Power Management

• Enabling Description: An adaptive power management unit for a complex system (e.g., autonomous vehicle) where the silicon-based semiconductors (e.g., power SiGe rectifiers) require dynamic rectification characteristics. Each rectifier features a copper (Cu) conductor and a nitrogen-doped amorphous silicon (a-Si:N) interface layer. This a-Si:N layer is formed by heating the SiGe in a vacuum with controlled pulses of ammonia (NH₃) to achieve a thickness between 1-4 nm, precisely setting the initial Fermi level alignment for a specific rectification ratio. When the system detects an anomalous power surge or drop, the a-Si:N interface is subjected to a transient, reversible thermal or electrical pulse. This pulse induces a temporary, controlled change in the nitrogen bonding configuration within the a-Si:N, which in turn alters the effective work function difference and thus the Schottky barrier height. This deliberately increases the reverse bias current (reducing the rectification ratio) or increases the forward bias resistance, providing an adaptive current-limiting or voltage-clamping behavior as a fail-safe or power-saving mode, rather than merely maintaining low resistance. Upon cessation of the anomalous condition, the interface reverts to its original properties.

stateDiagram-v2
    state NormalRectification {
        SiGe --> Interface: Desired Barrier
        Interface --> Cu: Optimal Rectification
        NormalRectification --> AnomalyDetected: Power Surge/Drop
    }
    state AnomalyDetected {
        AnomalyDetected --> AdaptiveTuning: Thermal/Electrical Pulse
        AdaptiveTuning --> ModifiedRectification: Barrier Altered
        ModifiedRectification --> SafeOperation: Current Limited/Clamped
        ModifiedRectification --> NormalRectification: Anomaly Resolved
    }

---

Derivations from Claim 17

Claim 17: A method for depinning a Fermi level of a semiconductor in an electrical junction, the method comprising: disposing an interface layer between a surface of the semiconductor and a conductor, the interface layer being configured to (i) be of a thickness sufficient to reduce effects of metal-induced gap states (MIGS) in the semiconductor, and (ii) passivate the surface of the semiconductor, wherein significant current flows between the conductor and the semiconductor because the thickness of the interface layer is chosen to provide a minimum or near minimum specific contact resistance for the junction, and wherein the interface layer comprises at least one of a nitride, an oxide, an oxynitride, an arsenide, a hydride and a fluoride.

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Derivative 17.1: Material & Component Substitution - Organic Semiconductor with Conductive Polymer and Graphene Oxide Interface

• Enabling Description: A method for depinning the Fermi level in an electrical junction using an organic semiconductor (e.g., P3HT:PCBM bulk heterojunction film) and a conductive polymer (e.g., PEDOT:PSS) as the conductor. The interface layer is a chemically modified graphene oxide (GO) film, partially reduced to tune its electronic properties. The method involves spin-coating the GO dispersion onto the organic semiconductor surface, followed by a controlled thermal annealing step in a reducing atmosphere (e.g., hydrogen/argon mix) to create a reduced graphene oxide (rGO) layer with a thickness between 1-3 nm. This rGO layer is configured to (i) reduce MIGS in the organic semiconductor by providing an effective displacement, and (ii) passivate the organic semiconductor surface by terminating charge trapping sites. The rGO's tunable work function and high conductivity ensure significant current flow, with its thickness chosen for a minimum specific contact resistance for the organic junction, typically below 50 Ω-μm² for organic devices.

flowchart TD
    A[Organic Semiconductor Surface] --> B{Spin-Coat Graphene Oxide (GO)};
    B --> C{Anneal in Reducing Atmosphere};
    C --> D[Reduced Graphene Oxide (rGO) Interface Layer];
    D --> E[Conductive Polymer (PEDOT:PSS) Conductor];
    E -- Current Flow --> A;
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style D fill:#bbf,stroke:#333,stroke-width:2px
    style E fill:#ccf,stroke:#333,stroke-width:2px

---

Derivative 17.2: Operational Parameter Expansion - High-Vacuum Atomic Layer Deposition (ALD) with Sub-Angstrom Control

• Enabling Description: A method for depinning the Fermi level of a semiconductor (e.g., indium gallium arsenide, InGaAs) in an electrical junction with a gold (Au) conductor. The interface layer is an aluminum oxide (Al₂O₃) film, precisely grown via ultra-high vacuum (UHV) atomic layer deposition (ALD) using trimethylaluminum (TMA) and water vapor precursors. The method disposes the Al₂O₃ layer with sub-angstrom thickness control (e.g., 0.3 nm to 1.0 nm, corresponding to 1-3 atomic layers) at a substrate temperature of 150°C. This extreme precision in thickness ensures (i) optimal reduction of MIGS in the InGaAs by minimizing tunneling path and maximizing separation, and (ii) atomic-scale passivation of the InGaAs surface. The specific ALD parameters are rigorously calibrated to achieve the minimum specific contact resistance, potentially below 0.1 Ω-μm², by tailoring the Al₂O₃ to act as a quantum mechanical tunnel barrier rather than a conventional dielectric.

sequenceDiagram
    participant S as InGaAs Semiconductor
    participant U as UHV ALD Chamber
    participant A as TMA Precursor
    participant W as H2O Precursor
    participant C as Gold Conductor

    U->>S: Place Substrate
    loop ALD Cycles (1-3)
        U->>A: Pulse TMA
        A->>S: Adsorb TMA
        U->>U: Purge
        U->>W: Pulse H2O
        W->>S: React to Form Al2O3
        U->>U: Purge
    end
    S->>C: Deposit Gold Conductor
    C->>S: Electrical Junction Formed

---

Derivative 17.3: Cross-Domain Application - Photoelectrochemical Energy Conversion Cells

• Enabling Description: A method for manufacturing a photoelectrochemical (PEC) cell, where a wide bandgap semiconductor (e.g., titanium dioxide, TiO₂) acts as a photoanode, and a platinum (Pt) mesh serves as the electrocatalytic conductor. The method disposes an interface layer of hafnium oxynitride (HfON) between the TiO₂ and the Pt mesh. The HfON layer is formed by plasma-enhanced ALD, tuning the nitrogen flow during deposition to achieve a specific composition and a thickness of 2-4 nm. This HfON layer is configured to (i) reduce MIGS at the TiO₂/electrolyte interface, enhancing charge separation efficiency, and (ii) passivate surface defects on the TiO₂ photoanode, suppressing recombination pathways. The thickness is chosen to provide a minimum specific contact resistance for charge transfer to the electrolyte and through the Pt mesh, optimizing the PEC cell's efficiency for solar hydrogen production or CO₂ reduction.

flowchart LR
    A[TiO2 Photoanode Semiconductor] --> B{HfON Interface Layer (ALD)};
    B --> C[Platinum Mesh Conductor];
    C -- Electrocatalytic Reaction --> D(Electrolyte);
    A -- Photoexcitation --> D;
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style B fill:#bbf,stroke:#333,stroke-width:2px
    style C fill:#ccf,stroke:#333,stroke-width:2px
    style D fill:#afa,stroke:#333,stroke-width:2px

---

Derivative 17.4: Integration with Emerging Tech - Automated Robotic Fabrication with Real-time Defect Detection

• Enabling Description: A method for automated, robotic fabrication of electrical junctions on flexible semiconductor substrates (e.g., polysilicon on Kapton). The process disposes a fluorinated graphene (FG) interface layer between the polysilicon and a silver (Ag) conductor. The FG layer is applied via a robotic arm using a controlled spray deposition of fluorinated graphene nanoplatelets, followed by UV curing and annealing. High-resolution optical and electron microscopy, coupled with AI-driven image recognition, performs real-time defect detection during deposition. The AI system adjusts the spray parameters (nozzle pressure, droplet size, movement speed) to achieve a precise FG thickness (1-5 nm) across the flexible substrate, ensuring optimal MIGS reduction and surface passivation. Anomalies detected by the AI trigger immediate corrective actions or flagging for rework, ensuring that each junction achieves the minimum specific contact resistance (e.g., < 10 Ω-μm²) and validated via blockchain ledger for quality assurance.

graph TD
    A[Flexible Polysilicon Substrate] --> B(Robotic Spray Deposition of FG);
    B --> C{UV Curing & Annealing};
    C --> D[FG Interface Layer];
    D --> E[Silver Conductor Deposition];
    E -- Electrical Connection --> A;
    F(AI Vision System) -- Real-time Monitoring --> B;
    F -- Parameter Adjustment --> B;
    F -- Defect Flagging --> G{Blockchain Ledger};
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style D fill:#bbf,stroke:#333,stroke-width:2px
    style E fill:#ccf,stroke:#333,stroke-width:2px
    style F fill:#afa,stroke:#333,stroke-width:2px
    style G fill:#dde,stroke:#333,stroke-width:2px

---

Derivative 17.5: The "Inverse" or Failure Mode - Reversible High-Impedance Switching for Redundant Systems

• Enabling Description: A method for fabricating electrical junctions in a redundant system (e.g., aerospace avionics) where a semiconductor (e.g., silicon-on-sapphire, SOS) must selectively enter a high-impedance, low-leakage state. The conductor is a platinum-iridium (PtIr) alloy. The interface layer is a dynamically tunable strontium titanate (SrTiO₃) thin film, deposited via pulsed laser deposition (PLD) to a thickness of 3-5 nm. This SrTiO₃ layer is configured to provide passivation and MIGS reduction under normal operation, achieving low specific contact resistance (< 10 Ω-μm²). However, upon a system-level fault detection, a controlled, localized electric field or thermal pulse is applied to the SrTiO₃ layer. This induces a reversible phase transition or defect engineering within the SrTiO₃, which increases the junction's specific contact resistance to > 10⁸ Ω-μm² (effectively a high-impedance "off" state) and maximizes the Schottky barrier height. This enables the faulty section to be electrically isolated with minimal leakage, allowing the redundant system to continue operation without a full shutdown. The "on" state can be restored by reversing the applied field/pulse.

stateDiagram-v2
    state NormalOperation_LowResistance {
        SOS --> SrTiO3: Low Z (<10 Ω-μm²)
        SrTiO3 --> PtIr: Current Flow
        NormalOperation_LowResistance --> FaultDetected: System Fault
    }
    state FaultDetected {
        FaultDetected --> ApplyElectricField: Induce Phase Transition
        ApplyElectricField --> HighImpedanceState: Z > 10^8 Ω-μm²
        HighImpedanceState --> SystemIsolation: Redundant Operation
        HighImpedanceState --> RestoreNormalOperation: Clear Fault
    }
    state RestoreNormalOperation {
        RestoreNormalOperation --> RemoveElectricField: Revert Phase
        RemoveElectricOperation --> NormalOperation_LowResistance
    }

---

Combination Prior Art Scenarios

Here are three "Combination Prior Art" scenarios where US Patent 10937880 is combined with existing open-source standards, demonstrating how future improvements could be considered obvious:

1. US10937880 + Open-Source Semiconductor Process Design Kit (PDK) Libraries:

   • Description: The methodologies for forming interface layers and controlling Fermi level pinning, as described in US10937880, could be readily integrated into standard, open-source Process Design Kit (PDK) libraries (e.g., those developed by academic consortia or community efforts for specific fabrication foundries like SkyWater Technology's open-source PDK). A skilled engineer, using a PDK that specifies standard processes for thin film deposition (e.g., ALD, CVD) and surface passivation (e.g., nitridation, oxidation), would find it obvious to apply the principles of US10937880 to existing semiconductor device architectures. Specifically, the PDK could include recipes for depositing ultra-thin (0.1-5 nm) passivation layers (nitrides, oxides, fluorides) at metal-semiconductor contacts, with parameters tuned to achieve specific contact resistances below 10 Ω-μm². This would enable designers to implement depinned Fermi level junctions in various standard devices (e.g., MOSFETs, diodes) for performance enhancement, without inventive effort.

2. US10937880 + IPC-2221 Generic Standard for Printed Board Design (or similar electronics manufacturing standards):

   • Description: The principles of forming a depinned Fermi level junction using an interface layer (as per US10937880) can be extended to advanced packaging and interconnect technologies governed by open standards such as IPC-2221. Given the drive for miniaturization and performance in package-level integration, it would be obvious to apply these interface layer techniques to improve the electrical characteristics of solder joints or direct metal-to-semiconductor bonds within a 3D integrated circuit (3D-IC) stack. For instance, before bonding a micro-bump of copper to a silicon die, a thin (e.g., 2 nm) interface layer of silicon nitride or an oxynitride could be selectively grown on the silicon contact pad. This application of US10937880 would reduce contact resistance and mitigate Fermi level pinning at the inter-die interface, thereby improving the overall performance and reliability of the 3D-IC, a known challenge in advanced packaging. The methods described in US10937880, when applied in the context of improving established interconnect standards, would be obvious to those skilled in semiconductor packaging.

3. US10937880 + Open-Source Materials Characterization & Simulation Software (e.g., VASP, Quantum ESPRESSO):

   • Description: The inventive concept of US10937880 hinges on understanding and controlling phenomena like MIGS and surface passivation. The use of open-source computational materials science software packages (e.g., VASP for Vienna Ab initio Simulation Package, or Quantum ESPRESSO for ab initio calculations of electronic structure and materials properties) has become standard practice in academic and industrial research for predicting and analyzing material behavior at the atomic scale. Given the detailed descriptions in US10937880 regarding the effects of interface layer thickness and material properties on Fermi level depinning, a person skilled in the art of computational materials science would find it obvious to use these open-source tools to predictively design novel interface layers or optimize existing ones. For example, simulating the electron wave function decay and band alignment at metal/interface layer/semiconductor junctions for various passivation materials (e.g., different nitrides, oxides, arsenides) and thicknesses would be a routine exercise to achieve the desired depinning and minimal specific contact resistance, thereby extending or refining the disclosed inventions without requiring inventive steps.