US 9905691

US Patent 9905691B2, titled "Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions," was issued on February 27, 2018. The patent lists Daniel E. Grupp and Daniel J. Connelly as inventors. Its application, US15/048,877, was filed on February 19, 2016. The original assignee was Acorn Technologies Inc, and the current assignee is Oak Ip LLC, as of a reassignment on December 26, 2024. The patent's legal status is "Expired - Fee Related," with an adjusted expiration date of October 10, 2023.

The abstract of US Patent 9905691B2 describes an electrical device that includes an interface layer positioned between and in contact with a conductor and a semiconductor.

Here is a plain-language overview of each independent claim:

• Claim 1: This claim describes an electrical device comprising a conductor, a silicon-based semiconductor with a surface, and an interface layer situated between them. The interface layer is designed to "depin" the Fermi level of the semiconductor at the interface with the conductor, which means it helps to control the semiconductor's electrical behavior by reducing the influence of surface defects and metal-induced gap states (MIGS). Despite this interface layer, the device still allows electrical current to flow when biased. Crucially, this interface layer consists of both a passivation layer (to chemically stabilize the semiconductor surface) and a separation layer (to physically distance the conductor from the semiconductor). The device must exhibit a very low specific contact resistance, specifically less than approximately 10 Ω-μm², and the interface layer must be thin enough to enable direct tunneling of electrons between the conductor and the semiconductor.
• Claim 11: Similar to Claim 1, this claim describes an electrical device with a conductor, a silicon-based semiconductor, and an interface layer that depins the semiconductor's Fermi level and permits current flow. The distinctive feature of this claim is the method by which the interface layer is formed: it is created by heating the silicon-based semiconductor in the presence of a nitrogen-containing material. Like Claim 1, the device must have a specific contact resistance below 10 Ω-μm², and the interface layer must be sufficiently thin for direct electron tunneling.
• Claim 12: This claim is a more specific variation of Claim 11. It describes an electrical device with the same components and functional goals (Fermi level depinning, current flow, low specific contact resistance, and direct tunneling). The key difference lies in the fabrication method for the interface layer: it is formed by heating the silicon-based semiconductor within a vacuum chamber and then exposing it to a nitrogen-containing material.

As of April 26, 2026, the patent US9905691 is noted as "Expired - Fee Related" with an expiration date of October 10, 2023. While litigation cases related to this patent were filed in previous years (e.g., in 2019, 2020, 2022, and 2025), including cases in the Court of Appeals for the Federal Circuit, the Texas Eastern District Court, and the Delaware District Court, as well as PTAB cases, a specific search for active dockets in the Court of Appeals for the Federal Circuit (CAFC) for 2026 related to US9905691 or its associated district court cases (e.g., Delaware District Court case 1:25-cv-00142, PTAB case IPR2025-01052) did not yield explicit 2026 entries indicating ongoing appeals for these specific cases. PTAB case IPR2025-01052 is noted as having reached a settlement. Given the patent's expired status, new infringement suits would generally not be possible, though existing litigation from prior to expiration could continue for damages related to past infringement.

Note: The provided full patent text in the prompt was truncated and did not include the claims section. The analysis of the claims was performed by accessing the full patent text via the provided Google Patents URL (https://patents.google.com/patent/US9905691/en).