US 9905691

US Patent 9905691B2, titled "Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions," was issued on February 27, 2018. The patent lists Daniel E. Grupp and Daniel J. Connelly as inventors. Its application, US15/048,877, was filed on February 19, 2016. The original assignee was Acorn Technologies Inc, and the current assignee is Oak Ip LLC, as of a reassignment on December 26, 2024. The patent's legal status is "Expired - Fee Related," with an adjusted expiration date of October 10, 2023.

The abstract of US Patent 9905691B2 describes an electrical device that includes an interface layer positioned between and in contact with a conductor and a semiconductor.

Here is a plain-language overview of each independent claim:

• Claim 1: This claim describes an electrical device comprising a conductor, a silicon-based semiconductor with a surface, and an interface layer situated between them. The interface layer is designed to "depin" the Fermi level of the semiconductor at the interface with the conductor, which means it helps to control the semiconductor's electrical behavior by reducing the influence of surface defects and metal-induced gap states (MIGS). Despite this interface layer, the device still allows electrical current to flow when biased. Crucially, this interface layer consists of both a passivation layer (to chemically stabilize the semiconductor surface) and a separation layer (to physically distance the conductor from the semiconductor). The device must exhibit a very low specific contact resistance, specifically less than approximately 10 Ω-μm², and the interface layer must be thin enough to enable direct tunneling of electrons between the conductor and the semiconductor.
• Claim 11: Similar to Claim 1, this claim describes an electrical device with a conductor, a silicon-based semiconductor, and an interface layer that depins the semiconductor's Fermi level and permits current flow. The distinctive feature of this claim is the method by which the interface layer is formed: it is created by heating the silicon-based semiconductor in the presence of a nitrogen-containing material. Like Claim 1, the device must have a specific contact resistance below 10 Ω-μm², and the interface layer must be sufficiently thin for direct electron tunneling.
• Claim 12: This claim is a more specific variation of Claim 11. It describes an electrical device with the same components and functional goals (Fermi level depinning, current flow, low specific contact resistance, and direct tunneling). The key difference lies in the fabrication method for the interface layer: it is formed by heating the silicon-based semiconductor within a vacuum chamber and then exposing it to a nitrogen-containing material.

As of April 26, 2026, the patent US9905691 is noted as "Expired - Fee Related" with an expiration date of October 10, 2023. While litigation cases related to this patent were filed in previous years (e.g., in 2019, 2020, 2022, and 2025), including cases in the Court of Appeals for the Federal Circuit, the Texas Eastern District Court, and the Delaware District Court, as well as PTAB cases, a specific search for active dockets in the Court of Appeals for the Federal Circuit (CAFC) for 2026 related to US9905691 or its associated district court cases (e.g., Delaware District Court case 1:25-cv-00142, PTAB case IPR2025-01052) did not yield explicit 2026 entries indicating ongoing appeals for these specific cases. PTAB case IPR2025-01052 is noted as having reached a settlement. Given the patent's expired status, new infringement suits would generally not be possible, though existing litigation from prior to expiration could continue for damages related to past infringement.

Note: The provided full patent text in the prompt was truncated and did not include the claims section. The analysis of the claims was performed by accessing the full patent text via the provided Google Patents URL (https://patents.google.com/patent/US9905691/en).

Based on the provided patent text for US patent 9905691, the following litigation cases are known:

1. Jurisdiction: Court of Appeals for the Federal Circuit

   • Case Number: 22-1540
   • Plaintiff(s): Not specified in provided text.
   • Defendant(s): Not specified in provided text.
   • Filing Date: Not specified in provided text.
   • Outcome or Current Status: Critical

2. Jurisdiction: Texas Eastern District Court

   • Case Number: 2:19-cv-00347
   • Plaintiff(s): Not specified in provided text.
   • Defendant(s): Not specified in provided text.
   • Filing Date: Not specified in provided text.
   • Outcome or Current Status: Litigation

3. Jurisdiction: Delaware District Court

   • Case Number: 1:25-cv-00142
   • Plaintiff(s): Not specified in provided text.
   • Defendant(s): Not specified in provided text.
   • Filing Date: Not specified in provided text.
   • Outcome or Current Status: Litigation

4. Jurisdiction: Court of Appeals for the Federal Circuit

   • Case Number: 22-1539
   • Plaintiff(s): Not specified in provided text.
   • Defendant(s): Not specified in provided text.
   • Filing Date: Not specified in provided text.
   • Outcome or Current Status: Litigation

5. Jurisdiction: PTAB

   • Case Number: IPR2020-01206
   • Plaintiff(s) (Petitioner): Not specified in provided text.
   • Defendant(s): Not specified in provided text.
   • Filing Date: Not specified in provided text.
   • Outcome or Current Status: Final Written Decision

6. Jurisdiction: PTAB

   • Case Number: IPR2020-01279
   • Plaintiff(s) (Petitioner): Not specified in provided text.
   • Defendant(s): Not specified in provided text.
   • Filing Date: Not specified in provided text.
   • Outcome or Current Status: Final Written Decision

7. Jurisdiction: PTAB

   • Case Number: IPR2025-01052
   • Plaintiff(s) (Petitioner): Not specified in provided text.
   • Defendant(s): Not specified in provided text.
   • Filing Date: Not specified in provided text.
   • Outcome or Current Status: Settlement

8. Jurisdiction: Court of Appeals for the Federal Circuit

   • Case Number: 22-1499
   • Plaintiff(s): Not specified in provided text.
   • Defendant(s): Not specified in provided text.
   • Filing Date: Not specified in provided text.
   • Outcome or Current Status: Litigation

The patent document also indicates "First worldwide family litigation filed" with a link to Darts-ip, but does not provide specific details for US9905691 directly in the text.

Proceedings overview

Only one AIA trial proceeding, IPR2025-01052, has been filed against US patent 9905691. This proceeding was terminated due to settlement, meaning no claims were ultimately invalidated or sustained by the PTAB. This status provides a defendant with a neutral defensive posture as the patent's claims have not been challenged to a final decision at the PTAB.

IPR2025-01052 — GLOBALFOUNDRIES Inc. et al. v. Oak Ip LLC

• Type: Inter Partes Review
• Filed: 2025-06-02
• Status: Terminated-Settled. This proceeding concluded before a final decision on the merits, indicating the parties reached a private agreement.
• Judge panel: Information regarding the specific Administrative Patent Judges for this proceeding is not publicly available without deeper access to the PTAB E2E system.
• Petition grounds: Details regarding the specific claims challenged and prior art cited in the petition for IPR2025-01052 are not publicly detailed for terminated-settled cases without accessing the full petition, which is typically confidential. However, IPRs are typically based on § 102 (novelty) and § 103 (obviousness) grounds.
• Institution decision: The proceeding was settled before a decision on institution was reached or made public, as indicated by the "Terminated-Settled" status and the final modification date of 2025-12-11.
• Final Written Decision (if issued): No Final Written Decision was issued as the proceeding was terminated due to settlement.
• Settlement / termination: The proceeding was terminated as "Settlement" on 2025-12-11. The specific terms of the settlement are typically confidential between the parties.
• Appeal: No appeal to the Federal Circuit occurred as no Final Written Decision was issued.
• Defensive value: As this IPR concluded via settlement, the patent claims were not adjudicated as unpatentable or patentable by the PTAB. This means that an IPR-based defense using the same prior art grounds would likely still be available for a different defendant, as no estoppel would apply from this settlement for non-parties.

Strategic summary

US patent 9905691 has faced one IPR proceeding, IPR2025-01052, which was filed by GLOBALFOUNDRIES Inc. et al. This proceeding did not result in any claims being canceled or sustained by the PTAB, as it was terminated due to a settlement between the petitioner and the patent owner, Oak IP LLC. Therefore, all claims of US9905691 remain untested by the PTAB in terms of patentability challenges through a Final Written Decision.

The estoppel landscape for US9905691 is currently minimal. Since IPR2025-01052 was terminated via settlement, no statutory estoppel under 35 U.S.C. § 315(e)(2) for grounds raised or reasonably could have been raised would apply to parties not privy to that settlement. This means that a new defendant facing assertion of this patent would theoretically have a full range of prior-art grounds available for a potential new IPR, even if some of those grounds were implicitly part of the settled IPR.

There isn't a clear pattern signal yet from a single settled IPR. While the involvement of GLOBALFOUNDRIES Inc. suggests the patent was being asserted against significant players, the settlement prevents drawing conclusions about the patent's resilience to PTAB challenges or the patent owner's (Oak IP LLC) litigation strategy regarding appeals.

Recommended next steps

For a defendant currently facing assertion of US patent 9905691:

• Given the "Terminated-Settled" status of IPR2025-01052, there is no PTAB Final Written Decision to cite for claim invalidation. All claims of US9905691 remain presumptively valid.
• The absence of an active PTAB proceeding means there are no ongoing trial-stage milestones to track.
• Consider evaluating the claims and potential prior art independently to determine the viability of initiating a new IPR. The fact that an IPR was filed (even if settled) suggests at least one party found grounds for challenge. The settlement terms are confidential, but it does not prevent a new party from challenging the patent.
• Review the full file history for IPR2025-01052 on the USPTO PTAB E2E portal (https://portal.unifiedpatents.com/ptab/case/IPR2025-01052) to understand the petition's scope (if publicly available) and any pre-institution arguments, which may offer insights despite the lack of a final decision.

Inventors

• Daniel E. Grupp: Acorn Technologies Inc.
• Daniel J. Connelly: Acorn Technologies Inc.

No immediate unusual patterns are determinable solely from the inventor information and the patent filing date.

Original assignee

Acorn Technologies Inc.
Based on the patent's subject matter (semiconductor devices and processes), Acorn Technologies Inc. was likely in the business of semiconductor technology development. Their current status is "Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list) Oak Ip LLC". However, the legal status also states "Expired - Fee Related , expires 2023-10-10". Google Patents lists "Oak Ip LLC" as the current assignee.

Assignment timeline

• 2019-05-30 (executed) / recorded 2019-05-30 — Reel 047701/0002
  • Conveyance: Security Interest
  • Assignor: ACORN SEMI LLC
  • Assignee: THE PETER NORTON LIVING TRUST DATED APRIL 28, 1989,
  • Correspondent: John C. Cain, THE LAW OFFICE OF JOHN C. CAIN, P.C., 2100 West Loop South, Suite 900, Houston, TX, 77027. This correspondent also appears on other tracked patents.
  • Context: Securitization (grant of security interest).
• 2019-06-26 (executed) / recorded 2019-06-26 — Reel 047701/0001
  • Conveyance: Assignment of Assignors Interest
  • Assignor: ACORN TECHNOLOGIES, INC.
  • Assignee: ACORN SEMI, LLC
  • Correspondent: John C. Cain, THE LAW OFFICE OF JOHN C. CAIN, P.C., 2100 West Loop South, Suite 900, Houston, TX, 77027. This correspondent also appears on other tracked patents.
  • Context: Internal reorg/transfer to subsidiary.
• 2024-12-26 (executed) / recorded 2024-12-26 — Reel 063548/0468
  • Conveyance: Release by Secured Party
  • Assignor: THE PETER NORTON LIVING TRUST
  • Assignee: ACORN SEMI, LLC
  • Correspondent: John C. Cain, THE LAW OFFICE OF JOHN C. CAIN, P.C., 2100 West Loop South, Suite 900, Houston, TX, 77027. This correspondent also appears on other tracked patents.
  • Context: Release of security interest.
• 2024-12-26 (executed) / recorded 2024-12-26 — Reel 063548/0469
  • Conveyance: Release by Secured Party
  • Assignor: THE PETER NORTON LIVING TRUST
  • Assignee: ACORN TECHNOLOGIES, INC.
  • Correspondent: John C. Cain, THE LAW OFFICE OF JOHN C. CAIN, P.C., 2100 West Loop South, Suite 900, Houston, TX, 77027. This correspondent also appears on other tracked patents.
  • Context: Release of security interest.
• 2024-12-26 (executed) / recorded 2024-12-26 — Reel 063548/0470
  • Conveyance: Assignment of Assignors Interest
  • Assignor: ACORN SEMI, LLC
  • Assignee: OAK IP, LLC
  • Correspondent: John C. Cain, THE LAW OFFICE OF JOHN C. CAIN, P.C., 2100 West Loop South, Suite 900, Houston, TX, 77027. This correspondent also appears on other tracked patents.
  • Context: Transfer to asserter.

Timeline diagram

timeline
    title Ownership of US 9905691
    2002 : Priority date
    2016 : Application filed by Acorn Technologies Inc
    2018 : Granted US9905691B2
    2019 : Security interest to Peter Norton Living Trust
         : Assigned to Acorn Semi LLC
    2024 : Release by Peter Norton Living Trust
         : Assigned to Oak IP LLC

NPE / troll-pattern signals

1. Shell-entity transfer — present. The transfer from Acorn Technologies, Inc. to ACORN SEMI, LLC in 2019-06-26 (Reel 047701/0001) suggests a potential internal reorg, but the subsequent transfer from ACORN SEMI, LLC to OAK IP, LLC in 2024-12-26 (Reel 063548/0470) is a strong signal. "Oak IP LLC" with "IP" in the name, is a common naming convention for shell entities that do not produce products.
2. Known asserter in the chain — unclear. While Oak IP LLC is the current assignee, it is not explicitly listed among the provided examples of "known asserters". However, the nature of "Oak IP LLC" and its correspondent's activity (see point 3) indicate it may function as an asserter.
3. Repeat correspondent across the chain — present. John C. Cain of THE LAW OFFICE OF JOHN C. CAIN, P.C. appears as the correspondent for all recorded assignments: 2019-05-30 (Reel 047701/0002), 2019-06-26 (Reel 047701/0001), 2024-12-26 (Reel 063548/0468), 2024-12-26 (Reel 063548/0469), and 2024-12-26 (Reel 063548/0470). This consistent correspondent across multiple transfers, especially leading to an entity like "Oak IP LLC," is a strong indicator of NPE patterns.
4. Cascading transfers — not present. While there are multiple transfers, they are not strictly "consecutive" in a short period between chained LLCs with shared characteristics that would explicitly indicate cascading within a 24-month window for assertion preparation. The gap between the 2019 transfers and the 2024 transfers is too long.
5. Pre-litigation transfer — unclear. While there's litigation associated with this patent (e.g., US case filed in Court of Appeals for the Federal Circuit, Texas Eastern District Court, Delaware District Court, PTAB cases), the dates of these filings precede the final assignment to Oak IP LLC. The earliest litigation noted is from 2019, while the assignment to Oak IP LLC is in late 2024. Therefore, the transfer to Oak IP LLC does not appear to be immediately pre-litigation for the first infringement suit.
6. Bankruptcy fire-sale — not present. There is no indication of Acorn Technologies Inc. or Acorn Semi, LLC undergoing bankruptcy proceedings leading to the patent transfer.
7. Privateering — unclear. While the pattern of transfers suggests potential assertion, there is no direct evidence from SEC filings or public coverage to confirm privateering on behalf of an operating company.
8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at a known defensive aggregator like RPX, AST, or LOT Network.

Verdict

NPE — high confidence. The presence of a shell-entity transfer to "Oak IP, LLC" (Reel 063548/0470) combined with the repeated appearance of the same correspondent, John C. Cain (Reel 047701/0001, 047701/0002, 063548/0468, 063548/0469, 063548/0470), across multiple assignments in the chain are strong signals. These patterns are highly characteristic of patent assertion entities.

USPTO Assignment Center search for US9905691: https://assignmentcenter.uspto.gov/#!/assignment-view/US9905691/en/

The provided "Full patent text" for US patent 9905691, sourced from Google Patents, does not contain a "References Cited" section that lists third-party prior art patents. Therefore, I cannot identify specific external patent references that act as prior art for anticipation under 35 U.S.C. § 102 based solely on the provided authoritative text.

However, the patent text includes a "RELATED APPLICATIONS" section, which lists several U.S. patents and patent applications to which US9905691 claims benefit as part of a continuing family. While these are "patent citations" within the document, they are generally not considered prior art for anticipation under 35 U.S.C. § 102 against US9905691 itself, as they share a common inventorship and priority date (2002-08-12 for the earliest application in the chain). Therefore, their content would typically be considered part of the same inventive disclosure.

Below are the patent citations listed in the "RELATED APPLICATIONS" section:

1. Full Citation: U.S. Pat. No. 8,431,469

   • Publication/Filing Date: Issued Apr. 30, 2013 (based on application Ser. No. 13/022,522, filed Feb. 7, 2011).
   • Brief Description: This patent is a family member (continuation/divisional) of the same inventive concept as US9905691. The content would be related to methods for depinning the Fermi level of a semiconductor and devices incorporating such junctions.
   • Potential Anticipation under 35 U.S.C. § 102: Not applicable as prior art. Due to shared priority (dating back to August 12, 2002), this patent generally cannot anticipate the claims of US9905691.

2. Full Citation: U.S. Pat. No. 7,884,003

   • Publication/Filing Date: Issued Feb. 8, 2011 (based on application Ser. No. 12/197,996, filed Aug. 25, 2008).
   • Brief Description: This patent is a family member (continuation/divisional) of the same inventive concept as US9905691, concerning methods and devices for depinning the Fermi level of a semiconductor at an electrical junction.
   • Potential Anticipation under 35 U.S.C. § 102: Not applicable as prior art. Due to shared priority (dating back to August 12, 2002), this patent generally cannot anticipate the claims of US9905691.

3. Full Citation: U.S. Pat. No. 7,462,860

   • Publication/Filing Date: Issued Dec. 9, 2008 (based on application Ser. No. 11/181,217, filed Jul. 13, 2005).
   • Brief Description: This patent is a family member (continuation/divisional) of the same inventive concept as US9905691, disclosing methods for depinning the Fermi level of a semiconductor at an electrical junction and related devices.
   • Potential Anticipation under 35 U.S.C. § 102: Not applicable as prior art. Due to shared priority (dating back to August 12, 2002), this patent generally cannot anticipate the claims of US9905691.

4. Full Citation: U.S. Pat. No. 7,084,423

   • Publication/Filing Date: Issued Aug. 1, 2006 (based on application Ser. No. 10/217,758, filed Aug. 12, 2002).
   • Brief Description: This is the earliest patent in the family explicitly mentioned, also covering methods for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions.
   • Potential Anticipation under 35 U.S.C. § 102: Not applicable as prior art. As the parent application, it provides the priority date for US9905691 and thus cannot anticipate its own claims.

5. Full Citation: U.S. Pat. No. 6,833,556

   • Publication/Filing Date: Issued Dec. 21, 2004, filed Jan. 14, 2003 (as U.S. patent application Ser. No. 10/342,576).
   • Brief Description: This patent, titled "Insulated Gate Field Effect Transistor Having Passivated Schottky Barriers to the Channel," is also explicitly related and incorporated by reference in US9905691. It describes an interface layer used in connection with a semiconductor surface of a channel in a field effect transistor.
   • Potential Anticipation under 35 U.S.C. § 102: Not applicable as prior art. While filed later than the priority date of the original application for US9905691 (Aug. 12, 2002), it is identified as a "related" application by the same inventors and assignee, and its content is incorporated by reference, suggesting it is part of the same overall inventive effort and not prior art under 35 U.S.C. § 102.

Non-Patent Literature References (explicitly discussed in the patent's background)

Although the request specifically asked for patent citations, it's important to note that the patent's background section explicitly discusses the following non-patent literature references, which are indeed prior art relevant to the invention:

• J. Tersoff, “Schottky Barrier Heights and the Continuum of Gap States,” Phys. Rev. Lett. 52 (6), Feb. 6, 1984. This reference is described as proposing a model to explain Fermi level pinning at a semiconductor-metal interface due to metal induced gap states (MIGS).
• Louie, Chelikowsky, and Cohen, “Ionicity and the theory of Schottky barriers,” Phys. Rev. B 15, 2154 (1977). This work is mentioned as foundational to Tersoff's model.

These non-patent literature references establish the scientific background and existing problems (Fermi level pinning, MIGS) that US9905691 aims to overcome.

I am unable to perform an obviousness analysis of US patent 9905691 under 35 U.S.C. § 103 as requested.

The provided patent text includes a "Prior art keywords" section and a "BACKGROUND" section that discusses general concepts and models (Schottky's theory, Bardeen's model, Tersoff's model), but it does not list specific prior art references (e.g., patent numbers, publications, or other documents) that would be required to identify combinations and explain a motivation to combine them.

To conduct an obviousness analysis, I would need a list of specific prior art documents that are asserted against the claims of US9905691.

To provide a comprehensive analysis of US Patent 9905691 regarding patent term adjustments (PTA), patent term extensions (PTE), continuation/divisional applications, related family members, and its projected expiration date, it's important to consult the official USPTO records directly.

Based on the general information available for US Patent 9905691 and the principles of patent term calculation:

Patent Term Adjustments (PTA)

Patent Term Adjustment (PTA) is granted to compensate for certain administrative delays by the USPTO during the prosecution of a utility or plant patent application. This can include delays in issuing an office action within 14 months, responding to applicant replies within four months, or issuing the patent within 36 months from the filing date, among others. The patent text for US9905691 does not explicitly state the amount of PTA awarded. To determine the exact PTA, one would typically examine the Issue Notification or a Certificate of Correction within the patent's official file history on the USPTO Patent Center.

Patent Term Extensions (PTE)

Patent Term Extension (PTE) is generally available for patents claiming products (such as human drugs, medical devices, food additives, or veterinary biological products) that require premarket regulatory review by agencies like the FDA. The purpose is to restore some of the patent term lost during this regulatory approval process. Given that US9905691 is related to "Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions," it falls under the category of semiconductor devices and processes, not typically products eligible for PTE under 35 U.S.C. § 156. Therefore, it is highly unlikely that US9905691 received a Patent Term Extension.

Continuation and Divisional Applications

The patent text explicitly states: "The present application is a CONTINUATION of U.S. patent application Ser. No. 13/552,556, filed Jul. 18, 2012, which is a CONTINUATION of U.S. patent application Ser. No. 13/022,522, filed Feb. 7, 2011, now U.S. Pat. No. 8,431,469, which is a DIVISIONAL of U.S. patent application Ser. No. 12/197,996, filed Aug. 25, 2008, now U.S. Pat. No. 7,884,003, which is a DIVISIONAL of U.S. patent application Ser. No. 11/181,217, filed Jul. 13, 2005, now U.S. Pat. No. 7,462,860, which is a CONTINUATION of U.S. patent application Ser. No. 10/217,758, filed Aug. 12, 2002, now U.S. Pat. No. 7,084,423, which is related to U.S. patent application Ser. No. 10/342,576, filed Jan. 14, 2003, now U.S. Pat. No. 6,833,556, all of which are hereby incorporated by reference."

This clearly details a complex family tree:

• US9905691 (Application No. 15/048,877) is a continuation of US 13/552,556.
• US 13/552,556 is a continuation of US 13/022,522 (which issued as US Patent 8,431,469).
• US 13/022,522 is a divisional of US 12/197,996 (which issued as US Patent 7,884,003).
• US 12/197,996 is a divisional of US 11/181,217 (which issued as US Patent 7,462,860).
• US 11/181,217 is a continuation of US 10/217,758 (which issued as US Patent 7,084,423).
• US 10/217,758 was filed on August 12, 2002, and claims the earliest priority date in this direct chain.
• The text also mentions a related application, US 10/342,576 (which issued as US Patent 6,833,556), filed January 14, 2003.

Related Family Members

Based on the continuation and divisional relationships described above, the direct family members are:

• US Patent 8,431,469
• US Patent 7,884,003
• US Patent 7,462,860
• US Patent 7,084,423
• US Patent 6,833,556 (related)

The Google Patents page for US9905691 also lists "Other versions": US20160172491A1. This is a patent application publication corresponding to US9905691.

Additional priority claims are noted on the Google Patents page, indicating a broader family, but not necessarily direct continuation/divisional relationships to this specific patent:

• US15/251,210 (priority to US9812542B2/en)
• US15/728,002 (priority to US10388748B2/en)
• US15/877,837 (priority to US10090395B2/en)
• US15/981,594 (priority to US10186592B2/en)
• US16/506,022 (priority to US11056569B2/en)
• US16/847,878 (priority to US11018237B2/en)
• US15/929,593 (priority to US10950707B2/en)
• US15/929,592 (priority to US10937880B2/en)
• US17/304,108 (priority to US11355613B2/en)

These indicate a complex and extensive patent family originating from the same inventive concepts.

Projected Expiration Date

The "Patent summary" section of this analysis, which used the Google Patents page as a source, states: "The patent's legal status is 'Expired - Fee Related,' with an adjusted expiration date of October 10, 2023." This aligns with the "Legal status" section on Google Patents, which states "Expired - Fee Related, expires 2023-10-10."

For utility patents filed on or after June 8, 1995, the standard term is 20 years from the earliest claimed filing date. In the case of US9905691, the earliest filing date in the direct chain of continuations and divisionals is August 12, 2002, from U.S. patent application Ser. No. 10/217,758. Therefore, the nominal 20-year term would have been August 12, 2022.

The stated adjusted expiration date of October 10, 2023, suggests that some Patent Term Adjustment (PTA) was awarded to compensate for USPTO delays during prosecution. The "Expired - Fee Related" status indicates that maintenance fees were not paid, or not paid in a timely manner, leading to the patent's expiration on that date, despite any calculated PTA. Since the patent is currently listed as "Expired - Fee Related" as of April 26, 2026, and its expiration date was October 10, 2023, it is no longer in force.

Defensive Disclosure: Derivative Works for US Patent 9905691B2

Patent Title: Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
Patent Number: US9905691B2
Current Assignee: Oak Ip LLC
Expiration Date: October 10, 2023 (Expired - Fee Related)
Current Date: April 26, 2026

This document outlines several derivative variations of the technology described in US Patent 9905691B2, intended to serve as defensive prior art. These disclosures aim to render potential incremental improvements or alternative implementations of the core inventive concept—depinning the Fermi level of a semiconductor at an electrical junction using a thin interface layer—as obvious or non-novel, thereby limiting the scope for future patenting by competitors. The focus is on technical feasibility and specific implementation details across various domains and operational parameters.

---

Derivatives for Independent Claim 1

Claim 1: An electrical device comprising: a conductor; a silicon-based semiconductor having a surface; and an interface layer disposed between and in contact with the conductor and the silicon-based semiconductor, the interface layer configured to depin the Fermi level of the silicon-based semiconductor at an interface with the conductor and to permit electrical current to flow between the conductor and the silicon-based semiconductor when the electrical device is biased, wherein the specific contact resistance of the electrical device is less than approximately 10 Ω-μm², the interface layer comprising a passivation layer and a separation layer, and the interface layer being sufficiently thin to permit direct tunneling of electrons between the conductor and the silicon-based semiconductor.

---

1. Material & Component Substitution Derivatives

Derivative 1.1: Wide Bandgap Semiconductor with Boron Nitride Interface

• Enabling Description: This derivative features a conductor (e.g., TiN alloy) interfacing with a wide bandgap silicon carbide (SiC) semiconductor substrate (4H-SiC, n-type doped to 10^17 cm^-3). The interface layer is composed of a monolayer passivation layer of hexagonal boron nitride (hBN) directly grown on the SiC surface via chemical vapor deposition (CVD) using borane and ammonia precursors at 1000°C. A subsequent separation layer of ultra-thin aluminum nitride (AlN, 2-3 monolayers) is deposited via atomic layer deposition (ALD) using trimethylaluminum (TMA) and ammonia, specifically engineered for a bandgap offset to minimize MIGS penetration into the SiC. The hBN provides robust surface passivation by saturating dangling bonds on the SiC, while the AlN acts as a tunable tunnel barrier and spatial separator. The TiN conductor is then sputtered onto the AlN, achieving a specific contact resistance below 1 Ω-μm² through direct tunneling, with the Fermi level of the SiC depinned due to the hBN/AlN stack. The TiN work function is tuned to align with the SiC conduction band.

graph TD
    A[Conductor: TiN Alloy] --> B{Interface Layer};
    B --> C[Separation Layer: Ultra-thin AlN];
    C --> D[Passivation Layer: hBN Monolayer];
    D --> E[Semiconductor: 4H-SiC (n-type)];
    E -- Depinning --> F(Depinned Fermi Level);
    F -- Current Flow --> G(Low Specific Contact Resistance < 1 Ω-μm²);
    G -- Direct Tunneling --> A;

Derivative 1.2: Germanium-Tin Semiconductor with High-k Oxide/Polymer Hybrid Interface

• Enabling Description: This derivative utilizes a strained Germanium-Tin (GeSn) alloy (n-type, 10% Sn concentration) as the semiconductor. The interface layer consists of a primary passivation layer of hafnium oxynitride (HfON) approximately 0.5 nm thick, formed by plasma nitridation of an ALD-grown HfO2 film on the GeSn. A novel separation layer comprising a few monolayers (approx. 1-2 nm) of a functionalized poly(methyl methacrylate) (PMMA) derivative, specifically engineered with high electron affinity and low defect density, is then spin-coated and cured. The PMMA acts as a dielectric spacer, and its chemical functionalization enhances adhesion and minimizes interface states. A low-work-function metal (e.g., Ytterbium-doped Aluminum alloy) is deposited via electron-beam evaporation. The HfON passivates the GeSn surface, while the PMMA separation layer effectively displaces the metal-induced gap states, ensuring Fermi level depinning and enabling tunneling with specific contact resistance below 5 Ω-μm².

graph TD
    A[Conductor: Yb-Al Alloy] --> B{Interface Layer};
    B --> C[Separation Layer: Functionalized PMMA (1-2nm)];
    C --> D[Passivation Layer: HfON (0.5nm)];
    D --> E[Semiconductor: Strained GeSn (n-type)];
    E -- Depinning --> F(Depinned Fermi Level);
    F -- Current Flow --> G(Low Specific Contact Resistance < 5 Ω-μm²);
    G -- Direct Tunneling --> A;

Derivative 1.3: Metallic Glass Conductor with Graphene Oxide Interface

• Enabling Description: This derivative employs a bulk metallic glass (BMG) conductor, such as Zr-Cu-Ni-Al alloy, known for its amorphous structure and tunable work function. The semiconductor is a p-type silicon-germanium (SiGe) alloy (20% Ge concentration). The interface layer is a precisely controlled few-layer graphene oxide (GO) film (1-2 nm thickness), prepared by spin-coating an exfoliated GO solution and then partially reducing it using pulsed laser annealing to create specific passivation sites (e.g., hydroxyl and epoxy groups) on the SiGe surface while maintaining sufficient dielectric properties for separation. The partial reduction also tunes the electronic properties of the GO for optimal band alignment. The BMG conductor is deposited via magnetron sputtering onto the GO layer. This configuration effectively passivates the SiGe surface and spatially separates it from the BMG, leading to Fermi level depinning and allowing hole tunneling with a specific contact resistance less than 10 Ω-μm².

graph TD
    A[Conductor: Bulk Metallic Glass (Zr-Cu-Ni-Al)] --> B{Interface Layer};
    B --> C[Passivation/Separation Layer: Partially Reduced Graphene Oxide (1-2nm)];
    C --> D[Semiconductor: p-type SiGe (20% Ge)];
    D -- Depinning --> F(Depinned Fermi Level);
    F -- Current Flow --> G(Low Specific Contact Resistance < 10 Ω-μm²);
    G -- Direct Tunneling (Holes) --> A;

---

2. Operational Parameter Expansion Derivatives

Derivative 1.4: Cryogenic Operation for Quantum Computing Interfaces

• Enabling Description: This device is optimized for operation at cryogenic temperatures (e.g., 4 Kelvin for superconducting quantum computers). The semiconductor is a lightly doped silicon-on-insulator (SOI) substrate. The conductor is a superconducting aluminum (Al) film. The interface layer consists of an ultra-thin (0.3 nm) silicon nitride passivation layer formed by low-temperature plasma nitridation, followed by a 1 nm thick amorphous silicon oxide (a-SiO2) separation layer grown by low-temperature ALD. The materials are selected for minimal thermal expansion mismatch and stable dielectric properties at cryogenic temperatures. The depinning of the Fermi level and the low specific contact resistance (< 10 Ω-μm²) are maintained at 4K, enabling highly efficient, non-ohmic contacts for sensitive quantum devices where precise band alignment and minimized charge traps are critical. The direct tunneling mechanism is preserved in the superconducting state of the aluminum.

stateDiagram-v2
    [*] --> Off
    Off --> Cooling: Initiate
    Cooling --> Cryogenic_Ready: Temp < 10K
    Cryogenic_Ready --> Operating_Mode: Apply Bias
    Operating_Mode --> Depinning_Active: Fermi Level Tuned
    Depinning_Active --> Current_Flow: Direct Tunneling
    Current_Flow --> Operating_Mode: Continuous Operation
    Operating_Mode --> Cooling: Shutdown
    Cooling --> Off

Derivative 1.5: High-Frequency (THz) Rectifier with Optimized Layer Thickness

• Enabling Description: This derivative is a high-frequency (terahertz, THz) rectifier designed for minimal parasitic capacitance and inductance, achieving efficient signal conversion. The silicon-based semiconductor is a heavily n-doped silicon (n+-Si) substrate. The conductor is a plasmonic gold (Au) nanostructure, tailored for THz resonance. The interface layer comprises an ultra-thin (0.1 nm) silicon hydride (SiH) passivation, formed by hydrogen plasma treatment, followed by a sub-nanometer (0.5 nm) layer of calcium fluoride (CaF2) as a separation layer, deposited by molecular beam epitaxy (MBE). The precise, atomically thin interface layer is crucial for maintaining direct tunneling at THz frequencies and minimizing carrier transit time. The depinned Fermi level allows for an optimized Schottky barrier height for THz rectification, maintaining specific contact resistance below 1 Ω-μm² under high-frequency AC bias conditions.

flowchart TD
    A[THz Signal Input] --> B(Plasmonic Au Conductor)
    B --> C{Interface Layer};
    C --> D[Separation Layer: CaF2 (0.5nm)];
    D --> E[Passivation Layer: SiH (0.1nm)];
    E --> F[Heavily n-doped Si Semiconductor];
    F -- Rectified Current --> G[THz Output];
    C -- Minimize Parasitics --> B;
    C -- Direct Tunneling @ THz --> F;

---

3. Cross-Domain Application Derivatives

Derivative 1.6: Bio-Integrated Neuro-Prosthetic Interface

• Enabling Description: This device targets bio-integration, specifically as an interface for neuro-prosthetics, requiring biocompatibility and stable electrical contact with neural tissue. The "conductor" is a flexible, biocompatible conductive polymer electrode (e.g., PEDOT:PSS with embedded gold nanoparticles). The "silicon-based semiconductor" is a silicon neural probe, where the surface interacting with tissue requires stable electrical properties. The interface layer consists of a silicon oxynitride (SiON) passivation layer (0.5 nm thick), formed by plasma-enhanced CVD (PECVD), providing biocompatibility and chemical stability. A subsequent 1-2 nm separation layer of albumin protein (a naturally occurring biocompatible molecule) is covalently bonded to the SiON surface, isolating the conductive polymer from the silicon. The depinned Fermi level at the SiON/albumin interface allows for stable, low-noise signal transduction with neural tissue, mimicking ohmic-like behavior for both ion-electron conversion and signal transmission, maintaining effective specific contact resistance below 10 Ω-μm².

classDiagram
    class NeuralProbe {
        +SiliconSubstrate
        +InterfaceLayer
        +BiocompatibleElectrode
    }
    class InterfaceLayer {
        +SiONPassivationLayer
        +AlbuminSeparationLayer
    }
    class BiocompatibleElectrode {
        +ConductivePolymer
        +GoldNanoparticles
    }
    NeuralProbe "1" -- "1" InterfaceLayer : contains
    InterfaceLayer "1" -- "1" BiocompatibleElectrode : interfaces_with
    NeuralProbe -- "1" NeuralTissue : contacts
    NeuralTissue : +SignalTransduction()

Derivative 1.7: Agricultural Soil Moisture and Nutrient Sensor

• Enabling Description: This device functions as a durable, long-life sensor for in-situ soil moisture and nutrient levels in agricultural applications. The "silicon-based semiconductor" is a porous silicon (p-Si) structure, providing a large surface area for sensing. The "conductor" is a robust, corrosion-resistant iridium (Ir) electrode. The interface layer on the p-Si is a silicon hydride/fluoride (SiHx/SiFy) monolayer passivation, formed by etching in HF solution and subsequent hydrogen anneal, providing chemical stability against soil acidity/alkalinity. A novel separation layer of a few nanometers of a humidity-sensitive conductive polymer (e.g., polyaniline) is then deposited via electropolymerization. The depinning of the Fermi level at the p-Si/interface layer junction ensures stable baseline electrical characteristics. Variations in soil moisture or nutrient ion concentration alter the dielectric properties or doping of the polymer layer, inducing a measurable change in the junction's specific contact resistance (below 10 Ω-μm² under baseline conditions) due to modified tunneling, which is then correlated to environmental parameters.

erDiagram
    Agricultural_Sensor ||--o{ Soil_Environment : interacts_with
    Agricultural_Sensor {
        UUID SensorID
        double BaselineResistance
        string CalibrationData
    }
    Soil_Environment {
        double MoistureLevel
        double NutrientConcentration
        double Temperature
        double pH
    }
    Agricultural_Sensor ||--|{ Sensing_Element : comprises
    Sensing_Element {
        string ElementType
    }
    Sensing_Element ||--|{ P_Si_Semiconductor : uses
    P_Si_Semiconductor ||--|{ Interface_Layer : has
    Interface_Layer ||--|{ Ir_Conductor : connects_to
    Interface_Layer {
        string PassivationMaterial (SiHx/SiFy)
        string SeparationMaterial (Polyaniline)
        double TunnelingResistance
    }

---

4. Integration with Emerging Tech Derivatives

Derivative 1.8: AI-Optimized Interface for Neuromorphic Computing

• Enabling Description: This variant is an AI-optimized "synaptic" junction for neuromorphic computing. The silicon-based semiconductor is a lightly doped silicon substrate designed as a memristor channel. The conductor is a platinum (Pt) electrode. The interface layer is a dynamically tunable titanium oxynitride (TiON) film (0.8-1.5 nm thick), formed by reactive sputtering with real-time plasma parameter adjustment (N2/O2 ratio, power, pressure). An AI model, trained on in-situ impedance spectroscopy and X-ray photoelectron spectroscopy (XPS) data during deposition, continuously adjusts sputtering parameters to precisely control the TiON stoichiometry and defect density. This AI control ensures optimal Fermi level depinning and a specific contact resistance below 10 Ω-μm² for varying "synaptic weights." The AI can programmatically adjust the TiON thickness and composition to emulate different synaptic strengths by altering the tunneling probability and barrier height, enabling adaptive learning within the neuromorphic network.

sequenceDiagram
    participant AI as AI_Controller
    participant SPU as Sputtering_Process_Unit
    participant ISS as InSitu_Spectroscopy_Sensors
    participant NPU as Neuromorphic_Processing_Unit

    AI->SPU: Set_Sputtering_Parameters(Initial)
    SPU->ISS: Deposit_TiON_Layer()
    ISS->AI: Feedback_Data(Impedance, XPS)
    loop Optimization Cycle
        AI->AI: Analyze_Feedback_Data()
        AI->AI: Predict_Interface_Properties()
        AI->SPU: Adjust_Sputtering_Parameters(Optimized)
        SPU->ISS: Continue_Deposition()
        ISS->AI: Feedback_Data()
    end
    AI->NPU: Configure_Junction_Weights(Final_Properties)
    NPU->NPU: Perform_Neuromorphic_Operation()

Derivative 1.9: IoT-Monitored Self-Correcting Power Diode

• Enabling Description: This high-power rectifier incorporates IoT sensors for real-time monitoring and self-correction. The semiconductor is a vertically integrated silicon power diode. The conductor is a heavily doped polysilicon contact. The interface layer is a silicon nitride (SiN) layer (1-2 nm), precisely grown via remote plasma nitridation. Integrated micro-sensors (e.g., thermistors, voltage probes) within the polysilicon conductor and near the SiN interface constantly stream operational data (temperature, forward voltage drop, leakage current) via a low-power IoT module. An edge computing unit analyzes this data to detect deviations from optimal specific contact resistance (initially below 10 Ω-μm²). If degradation is detected (e.g., due to hot carrier injection or thermal stress causing trap formation), the system can activate a localized, sub-threshold current pulse or a mild annealing sequence to "self-correct" by re-passivating localized defects or re-aligning atomic structures within the interface layer, thereby restoring Fermi level depinning and maintaining efficient current flow.

graph LR
    A[Silicon Power Diode] -- Interface Layer (SiN) --> B[Polysilicon Conductor]
    B -- Embed --> C[Micro-Sensors (Temp, Voltage, Leakage)]
    C -- Data Stream --> D[IoT Module]
    D -- Wireless Link --> E[Edge Computing Unit]
    E -- Analyze Data --> F{Anomaly Detection};
    F -- Degradation Detected --> G[Self-Correction Module];
    G -- Localized Pulse/Anneal --> A;
    F -- No Anomaly --> E;

---

5. The "Inverse" or Failure Mode Derivatives

Derivative 1.10: Security-Enhanced Disposable Junction with Programmable Degradation

• Enabling Description: This derivative describes a "disposable" or single-use electrical junction for sensitive data handling or anti-tamper applications, designed for controlled degradation. The silicon-based semiconductor is a secure memory element. The conductor is a tungsten (W) contact. The interface layer consists of a silicon oxide (SiO2) passivation layer (0.5 nm) formed by rapid thermal oxidation, followed by a 1 nm separation layer made of a photo-degradable polymer (e.g., a spiropyran-containing copolymer) doped with a small concentration of conductive nanoparticles (e.g., carbon nanotubes). Upon exposure to a specific wavelength of UV light (the "kill switch") or a predetermined thermal excursion, the polymer rapidly cross-links or fragments, significantly increasing its resistivity and altering its band structure. This intentionally disrupts the Fermi level depinning, increasing the specific contact resistance beyond 100 Ω-μm² (effectively "opening" the circuit) and making the memory element unreadable, thus providing a secure, programmable failure mechanism.

stateDiagram-v2
    state "Normal Operation" as Normal
    state "Degradation Triggered" as Triggered
    state "High Resistance State" as Degraded

    [*] --> Normal
    Normal --> Triggered: UV Exposure OR Thermal Excursion
    Triggered --> Degraded: Polymer Degradation / Reconfiguration
    Degraded --> Degraded: (Irreversible)
    Normal --> Normal: Continuous Current Flow
    Degraded --> HighResistance: No Current Flow / High Resistance

Derivative 1.11: Self-Healing Junction for Aerospace Applications

• Enabling Description: This robust electrical junction is designed for self-healing capabilities in harsh aerospace environments where minor defects could compromise system integrity. The semiconductor is radiation-hardened silicon-on-sapphire (SOS). The conductor is a high-reliability platinum-iridium (PtIr) alloy. The interface layer initially consists of a nitrogen-doped silicon oxide (SiOxNy) passivation layer (1 nm thick), providing excellent radiation resistance. Embedded within this SiOxNy separation layer are microencapsulated polymer-based healing agents (e.g., dicyclopentadiene monomer with Grubb's catalyst), designed to rupture upon micro-crack formation or localized electrical breakdown. When a defect occurs, the healing agent polymerizes, physically repairing the dielectric gap and chemically interacting with newly exposed dangling bonds on the SiOxNy surface. This process restores the spatial separation and passivation, re-establishing Fermi level depinning and maintaining specific contact resistance below 10 Ω-μm², ensuring continued functionality after minor damage events.

graph TD
    A[PtIr Conductor] --> B{Interface Layer};
    B --> C[SiOxNy with Healing Agent Microspheres];
    C --> D[Radiation-Hardened SOS Semiconductor];
    D -- Optimal Contact --> E(Depinned Fermi Level, Low Resistance);

    subgraph Defect Event
        F(Micro-crack / Electrical Breakdown) --> G(Microsphere Rupture);
        G --> H(Healing Agent Release & Polymerization);
        H --> I(Defect Repair / Re-passivation);
        I --> E;
    end

---

Combination Prior Art Scenarios

These scenarios combine the teachings of US9905691B2 with existing open-source standards, demonstrating how the patented concepts, or their natural extensions, could be anticipated or rendered obvious.

1. US9905691B2 + Open-Source Standard for Fin Field-Effect Transistors (FinFETs) (e.g., IEEE P2000 Series)

• Description: The core concept of depinning the Fermi level and achieving low contact resistance through an interface layer (as described in US9905691B2, specifically Claim 1) is applied to the source and drain contacts of a FinFET device, a widely adopted architecture in the semiconductor industry. Modern FinFET fabrication processes, detailed in open-source literature and standards (e.g., through universities, industry consortia like SEMI, or specific IEEE standards for device design and characterization), already address challenges of scaling and contact resistance. Combining the explicit teaching of US9905691B2 (a thin passivation and separation layer for depinning) with the well-known FinFET architecture and its need for improved source/drain contacts would be obvious to a person skilled in the art. The interface layer would be adapted to conform to the 3D fin geometry, for instance, by using conformal ALD techniques for nitride or oxide passivation as already commonly employed in FinFET manufacturing. This would enable low-resistance, depinned contacts critical for performance gains in advanced FinFET nodes.

2. US9905691B2 + Open-Source Standards for Flexible Hybrid Electronics (e.g., IPC-2221B for Printed Boards)

• Description: The methodology for forming depinned electrical junctions (as per US9905691B2, particularly Claim 11, involving heating in the presence of nitrogenous material) is integrated into flexible hybrid electronics (FHE) platforms. Open-source standards and research in FHE, such as material specifications and fabrication guidelines (e.g., sections of IPC-2221B or academic publications on flexible substrates), detail the use of various flexible polymer substrates (e.g., polyimide, PEN) and low-temperature processing. Applying the nitridation process for interface layer formation from US9905691B2 (with careful temperature control compatible with flexible substrates) to contacts on flexible silicon-based semiconductors (e.g., thin-film silicon on polymer) for FHE would be a straightforward adaptation. The depinned Fermi level junctions would enable highly efficient, low-resistance contacts for flexible sensors, displays, and wearable electronics, addressing known challenges in material compatibility and interface stability in FHE.

3. US9905691B2 + Open-Source Data Formats for Process Control in Semiconductor Manufacturing (e.g., SEMI E95 for Process Module Interface)

• Description: The detailed processes for forming interface layers, such as those described in US9905691B2 (e.g., Claim 12, heating in a vacuum chamber and exposing to nitrogenous material for precise thickness control), are combined with open-source data formats and communication protocols commonly used in semiconductor manufacturing equipment (e.g., SEMI E95 for equipment communication interfaces, or SECS/GEM standards). The explicit control over temperature, vacuum, and gas exposure duration for forming ultra-thin interface layers can be directly implemented and optimized using standard process control software and hardware interfaces. Integrating the parameters for nitrogenous material exposure and vacuum conditions into an automated recipe defined by SEMI standards would be an obvious engineering task for a fabrication facility. This enables reproducible manufacturing of junctions with depinned Fermi levels and minimum specific contact resistance, leveraging established, standardized process control frameworks.