US 9331148

I'll verify the patent details against current sources before summarizing.

Let me check specifically for any litigation or PTAB proceedings involving this patent.

US Patent 9,331,148 — Verification Summary

I checked the patent against the authoritative full text (Google Patents, fetched 2026-09-24), plus uspto.report and Justia mirrors, and searched for litigation/PTAB activity. Bibliographic data was consistent across sources.

1. Bibliographic data

Family (same spec, filed as divisionals on 2016-04-22):

• US 15/135,844 → US 9,515,141 B1 (issued 2016-12-06; status "Expired – Fee Related")
• US 15/135,850 → US 9,640,640 B1 (issued 2017-05-02; Active)

Note: the assignment record lists inventor signing dates ranging from 2012-01-16 to 2015-11-25, and the grant issued roughly five months after filing — both unusual, though neither affects the identifiers.

2. Abstract (as issued)

"A method for fabricating a semiconductor device, the method comprises forming a fin on a substrate, forming a dummy gate stack on the fin and the substrate, removing a portion of an exposed portion of the fin, forming a source/drain region on an exposed portion of the fin, forming a conductive contact on the source/drain region, removing the dummy gate stack to expose a channel region of the fin, implanting ions in the channel region of the fin, performing an annealing process, and forming a gate stack on the channel region of the fin."

3. Plain-language claim overview

Claim 1 (the sole independent claim) — a fabrication method, comprising these steps in order:

1. Form a fin on a substrate.
2. Form a dummy (sacrificial) gate stack on the fin and the substrate.
3. Remove a portion of the exposed fin (the recess/etch that creates space for epitaxy).
4. Form a source/drain region on an exposed portion of the fin.
5. Form a conductive contact on the source/drain region.
6. Remove the dummy gate stack to expose the fin's channel region.
7. Implant ions into the channel region.
8. Perform an annealing process.
9. Form a gate stack (replacement metal gate) on the channel region.

In plain terms: it is a "gate-last / replacement-metal-gate" flow in which, after the dummy gate is pulled and after the source/drain and contacts are already built, the exposed channel is ion-implanted and annealed to restore/add channel strain that was lost during fin etching.

Dependent claims (each reads on claim 1):

• 2 — the fin-removal step reduces strain in the channel region.
• 3 — the implant + anneal step increases strain in the channel region.
• 4 — the implanted ions are germanium ions.
• 5 — the fin is already strained when formed on the substrate.
• 6 — the fin comprises a semiconductor material.
• 7 — annealing exposes the channel region to at least about 900 °C.
• 8 — the fin comprises silicon germanium when formed on the substrate.
• 9 — the fin is formed by a lithographic patterning and etching process. (Claim 9 is literally printed as "The method of claim, 1 wherein…" — the stray comma appears in the source text.)

Important observation: the specification's Summary section recites three aspects, including a device aspect ("a gate stack arranged over a channel region of the fin, wherein the channel region … includes implanted germanium ions that are operative to induce a strain"). However, the issued claims of 9,331,148 are all method claims — the apparatus aspect is not claimed in this patent. Anyone analyzing infringement or validity of the '148 patent must work from the method claim 1, not the Summary language. (The sister patents 9,515,141 and 9,640,640 are the divisionals, and I have not separately verified their claim sets here.)

Relevant disclosed process parameters (specification, not claims): Ge dose of 2E14 to over 5E16 atoms/cm² targeting mid-fin placement; spike anneal at ≥900 °C, or alternatively ~600 °C for ~30 min or longer, with Ge distributing roughly uniformly through the fin.

4. Litigation and PTAB check

I searched for US 9,331,148 in CAFC 2026 dockets and in USPTO/PTAB and district-court records:

• No CAFC 2026 appeal or order involving US 9,331,148 was found. The 2026 CAFC material returned by search (e.g., Intuit v. SameSurf, No. 2024-2298; Apple v. Smart Mobile Technologies) concerns unrelated patents.
• No IPR/PGR petition against US 9,331,148 appeared in the results.
• Caution on a false hit: several complaints refer to an "'148 Patent," but in a different family — e.g., Nokia's assertion against Amazon (complaint dated 2023-10-31) refers to a Nokia-owned '148 patent with licensing negotiations between Nokia and Amazon. Those references are not to IBM's US 9,331,148 as far as I can determine, and I did not verify which Nokia patent number is meant. Do not attribute that litigation to US 9,331,148 without confirming the full number.

5. Uncertainty / confidence

• High confidence in the bibliographic data, abstract, and claim text — these come from the authoritative full patent text, corroborated by uspto.report and Justia.
• High confidence that claim 1 is the only independent claim and all 8 remaining claims depend from it, per the "Claims (9)" listing as published.
• Moderate confidence that no litigation or PTAB proceeding exists against this patent; absence of search hits is not proof of absence, and I did not query PACER or the CAFC docket system directly in a systematic way. A PACER/Docket Alarm or Lex Machina check on "9,331,148" would be needed to state this definitively.
• I did not independently verify the claim sets of the two divisionals (9,515,141 and 9,640,640); if the device claim is relevant to your analysis, it is more likely to reside in one of those.

I'll research litigation involving US Patent 9,331,148. Let me run several targeted searches.

Let me run additional targeted searches to be thorough.

Let me run a few more checks, including PTAB/IPR and CourtListener.

Findings: Litigation Involving U.S. Patent 9,331,148

Short answer: I found no known litigation — district court, ITC, or PTAB — involving U.S. Patent 9,331,148 ("FinFET device with channel strain," IBM).

Searches performed (April 26, 2026)

What the search did confirm about this patent

• Patent: U.S. 9,331,148 B1, "FinFET device with channel strain," App. No. 14/962,194, filed 2015-12-08, granted 2016-05-03. Inventors: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie. Assignee: International Business Machines Corporation.
• Family (divisionals, filed 2016-04-22): U.S. 9,515,141 B1 and U.S. 9,640,640 B1 — both from the same disclosure. Neither appears in any litigation either.
• Maintenance fees paid (4th year 2019-10-16; 8th year 2023-10-17), consistent with an actively maintained, never-asserted IBM portfolio patent.
• The only "results" matching the numeral 9331148 in public records outside patent databases were unrelated non-patent items (e.g., a Travis County, Texas payroll entry), which I have disregarded as false positives.

Important caveat on the "near-miss" IBM cases

My searches surfaced several active patent suits against IBM, but none of them asserts U.S. 9,331,148. I list them only to show I checked and to prevent confusion with the target patent:

• ExactoJoin LLC v. International Business Machines Corp., No. 7:26-cv-00105 (W.D. Tex.) — filed 2026-03-24; § 271 infringement. I could not confirm which patents are asserted from the available docket text, but nothing indicated the '148 patent. (This is the most recent and most likely candidate to be misattributed; you should verify the asserted patents directly against the complaint if this matters.)
• Ziedman Technologies II, LLC v. IBM Corp., No. 2:25-cv-01002 (E.D. Tex.) — filed 2025-10-03; asserted patents referenced as "947," "488," and "187"; voluntarily dismissed without prejudice 2026-03-04/05.
• Secure Matrix LLC v. IBM Corp., No. 2:24-cv-00458 (E.D. Tex.) — filed 2024-06-18.
• Muvox LLC v. IBM Corp., No. 2:24-cv-00693 (E.D. Tex.) — filed 2024-08-21.
• VirtaMove Corp. v. Hewlett Packard Enterprise Co. (IBM as defendant/counterclaimant), No. 2:24-cv-00093 (E.D. Tex.).

None of the above dockets, at the level of detail available to me, reference U.S. 9,331,148.

Bottom line

• Litigation (district court): None identified.
• ITC § 337 investigations: None identified.
• PTAB (IPR/PGR/CBM): None identified.
• Post-grant or reissue: None identified.

Confidence and limitations

I have moderate-to-high confidence that no litigation asserting U.S. 9,331,148 exists as of today. Reasons: (1) it is a semiconductor manufacturing-method patent owned by IBM, a company that has historically monetized its semiconductor portfolio through broad cross-licenses and portfolio licensing rather than offensive assertion of individual fab-process patents; (2) the patent's own public record shows only maintenance-fee activity, no assignment away from IBM, and no third-party challenger; and (3) no docket, ITC, or PTAB record surfaced in repeated searches.

Caveats you should weigh before relying on this:

1. Docket coverage is imperfect. PACER is not full-text searchable, and free services (CourtListener/RECAP, UniCourt, Justia) do not capture every complaint, particularly recent filings in which the patent at issue is listed only in an exhibit or an AO-120 form. A complaint could assert '148 without the number appearing in readily indexed text.
2. Terminal-disclaimer / family confusion. Because the '148 patent has two divisionals ('141 and '640) with the same title and inventors, any litigation asserting a sibling could be mislabeled by secondary sources — and vice versa. If you have a specific case in mind, confirm by reading the AO-120 form or the complaint's patent list rather than relying on the case name.
3. Defensive aggregators. This patent is plausibly the type of asset held in IBM's defensive portfolio (note the later IBM patent "Creation of stress in the channel of a nanosheet transistor," U.S. 11,049,933, cites the '148 family), which further supports the "never asserted" conclusion but is not conclusive.

Recommendation: To close the gap definitively, run a PACER/LexMachina (or Docket Navigator) full-text search on "9,331,148" and "9331148", plus a PTAB search on the same number, and independently verify the asserted patents in ExactoJoin v. IBM (7:26-cv-00105). I could not access those paywalled full-text dockets within this session, so I cannot state with certainty that the number is absent from them — only that it did not appear in any indexed source I could reach.

I'll verify the structured "no proceedings" result against live sources before reporting.

Let me run a couple more targeted checks before finalizing.

One more check on assertion history, which bears on why no IPR was ever filed.

Proceedings overview

Total AIA trial proceedings on US 9,331,148: 0. Zero IPRs, zero PGRs, zero CBM reviews — no petitions, no institution decisions, no final written decisions, no terminations, no appeals. Defensive posture: the patent is completely untested, not "hardened." There is no claim-level adjudication to work from and—critically—no § 315(e)(2) estoppel against anyone, so you retain the full universe of § 102/§ 103 ground available at the PTAB, subject only to the § 315(b) one-year clock. Do not let an adversary tell you this patent "survived IPR" — it never faced one.

Proceedings (none on file)

There are no proceedings to list. The structured PTAB-proceedings block — the canonical USPTO Open Data Portal list — is empty for this patent, and I independently searched for petitions, institution decisions, FWDs, terminations, and CAFC appeals naming US 9,331,148. Nothing surfaced. Per the operating rule, I will not invent proceeding numbers, and I am not going to pad the template with fabricated IPR20xx-xxxxx headings.

Search surfaces checked (all negative):

• USPTO ODP AIA-trial data (structured block provided in-prompt) — no record.
• General web search on the patent number paired with IPR / PTAB / PGR / AIA-trial keywords — returned only unrelated proceedings (e.g., IPR2025-01090 on U.S. 8,907,425; IPR2023-01120 and IPR2025-00864 involving TSMC; IPR2022-01083; IPR2026-00097), none naming 9,331,148.
• Unified Patents / defensive-aggregator angle — no filing found on this patent.
• Assertion history — no district-court or ITC action naming 9,331,148 surfaced (consistent with the earlier section of this analysis).

Two false-positive traps to avoid, both confirmed by the earlier section of this analysis:

1. "The '148 patent" in Nokia v. Amazon (complaint dated 2023-10-31) is a different, Nokia-owned patent. It is not IBM's 9,331,148. Do not attribute that litigation — or any IPR arising from it — to this patent.
2. Google Patents "Cited By" listings are not PTAB proceedings. US 9,515,141 B1 and US 9,640,640 B1 appearing under 9,331,148 are its own divisionals filed 2016-04-22 (same inventors, same assignee, same specification). Likewise, Samsung's US 9,871,139 B2 ("Sacrificial epitaxial gate stressors") and US 9,893,187 B2 ("Sacrificial non-epitaxial gate stressors") merely cite the '148 as prior art in their own examination. None of these is an AIA trial.

Why the list is likely empty: IPRs are almost always petitioner-driven and follow assertion. A never-asserted, IBM-owned patent that ceased being commercially central after IBM's chip-manufacturing divestiture to GlobalFoundries in 2014-2015 is exactly the profile that attracts no challenger — there is no accused product to defend.

Strategic summary

Claim status. No claim of 9,331,148 has been canceled, narrowed, or sustained. All nine claims — claim 1 (the sole independent method claim) plus dependent claims 2, 3, 4, 5, 6, 7, 8, 9 — are untested. The earlier section of this analysis correctly notes that despite the specification's Summary reciting a device aspect, the issued claim set of the '148 patent is entirely method claims; the apparatus aspect is not claimed here. There has been no certificate of correction, disclaimer, or reexamination cancellation of record (only maintenance-fee payments on 2019-10-16 and 2023-10-17).

Estoppel landscape. § 315(e)(2) estoppel attaches only upon a final written decision. With no FWD, no estoppel attaches to anyone — you, your privies, and even an unrelated party are free to raise any patent-or-printed-publication ground under §§ 102/103. There is also no PTAB estoppel blocking parallel district-court invalidity theories. The only meaningful gates are:

• § 315(b): a petition is time-barred if filed more than one year after you are served with a complaint alleging infringement. If you have already been served, that clock is the single most important date on your calendar.
• § 325(d): the Board may discretionarily deny grounds cumulative to what the examiner considered. The '148 file history used a small art set (the 11 cited references include Amberwave's US 7,335,545, Intel's US 7,138,323, TSMC's US 7,335,929, and GlobalFoundries' US 7,871,877 — the last of which is a strain-inducing implant layer under the channel reference and is the most on-point piece of art of record), so a well-chosen § 103 combination that the examiner never confronted has a clean § 325(d) path.
• Director discretion (§ 314(a)): be aware the climate has tightened. Recent precedential guidance (e.g., the Director's decision in Magnolia Med. Techs., Inc. v. Kurin, Inc., IPR2026-00097, 2026-05-14, as summarized in NYIPLA's PTAB committee update) emphasizes denial where a petition looks like a late, duplicative, or leverage-seeking second bite rather than a true litigation alternative. Timing your petition early, with a Sotera-type stipulation, materially improves your odds.

Pattern signals. None to report. There is no repeat petitioner, no patent-owner appeal history, and no defensive aggregator in the chain — because there is no chain. For a patent of this vintage (issued 2016-05-03) and this technology area (FinFET strain engineering, a hotly litigated field in 2016-2020), the total absence of any challenge is itself informative: it is the fingerprint of an unasserted portfolio asset, not of a hardened patent.

Post-grant windows. The patent's effective filing date is 2015-12-08, so it is post-AIA. The PGR window closed roughly 2017-02-03 (nine months from grant) and is no longer available. CBM is unavailable both substantively (this is a semiconductor fabrication method, not a financial-services covered business method) and as a program (the CBM transitional program has sunset). IPR under § 311 is the only AIA vehicle still live, and it is available to any petitioner not time-barred under § 315(b).

Recommended next steps

1. If you are a defendant being asserted on, PTAB is fully open to you. There is no FWD and no estoppel, so nothing is foreclosed. Target claim 1 first: it is a pure gate-last (replacement-metal-gate) sequence — dummy gate → recess fin → epitaxial S/D → contact → pull dummy gate → implant into the channel → anneal → form gate stack. The key patentable hook is the order: implant-and-anneal into the channel after S/D and contact formation. That is a § 102/§ 103 attack surface — search for gate-last flows that implant a channel-strain species post-dummy-gate-pull, including the strain-inducing-implant-layer art already of record (US 7,871,877) combined with a FinFET replacement-gate reference such as TSMC's US 2014/0145242 A1 ("Fin-Last FinFET and Methods of Forming Same," cited on the face of the '148).
2. Calendar the § 315(b) date immediately. If you have been served with a complaint asserting 9,331,148, you have one year from service to petition. If you have not been served and face only a demand letter, you can petition preemptively — but note that PGR is gone, so IPR is your only route.
3. Preserve and design around claims 2-4 and 7 now. Dependency is the whole case:
   • Claim 3 (implant + anneal increases strain) and claim 4 (germanium ions) are narrow. If your process uses a non-Ge species (e.g., C, Si, or a neutral implant) or your anneal does not measurably increase channel strain, claims 3 and 4 drop out, and you are fighting only claim 1's ordering.
   • Claim 7 (at least about 900 °C) is in direct tension with the specification, which expressly offers a lower-temperature alternative (~600 °C for ~30 min), and with ordinary gate-last thermal-budget constraints. A real, evidentiary non-infringement position on claim 7 may exist depending on your actual anneal recipe — document those recipes.
4. Mind the litigated-file-history hazard. The '148 patent has no PTAB record, so there is no IPR-driven prosecution history estoppel or claim construction to lean on — and, conversely, no helpful disclaimer to exploit. The claim scope is whatever ordinary-and-customary meaning gives it. That cuts both ways: the claim is broad and broad means easy to read on a replacement-gate flow, but also easier to invalidate with art that a narrow amendment would have avoided.
5. If you want a definitive negative, run the paid databases. Absence of web-search hits is not proof of absence. A PACER / Docket Alarm / Lex Machina query on "9,331,148" and a PTAB E2E patent-number search at https://ptacts.uspto.gov/ would convert my finding from "no proceedings found" into "no proceedings exist." I did not run those systems directly.
6. Bottom line: state plainly in any demand-letter response that there are no PTAB proceedings on US 9,331,148, that no claim has ever been adjudicated, and that no estoppel bars any ground. If opposing counsel invokes "the IPRs" on this patent, ask for the proceeding numbers — there are none to give.

Confidence. High that the ODP structured list is empty and that my searches found nothing. Moderate-to-high that no proceeding exists at all, limited only by the fact that I did not query PACER, Docket Alarm, Lex Machina, or the PTAB E2E docket system directly.

I'll research the assignment record and ownership chain for US 9,331,148 before drafting.

Let me pull the assignment record details and check the divisionals and any IBM portfolio transfers.

Ownership Chain Analysis — US Patent 9,331,148

Scope note: I reconstructed this chain from the authoritative full patent text (Google Patents legal events, fetched 2026-09-24), the uspto.report mirror of the issue record, and targeted searches for post-issuance assignments, litigation, and IBM portfolio transfers. I attempted to pull the raw USPTO Assignment Center record (reel/frame detail and correspondent of record) but was unable to retrieve the underlying assignment abstract for application 14/962,194 through the sources available to me. Where that leaves a gap, I say so rather than invent a correspondent name.

Inventors

All five are IBM semiconductor-process inventors; the list is a cohort pattern typical of IBM's Albany NanoTech / Yorktown finFET program rather than a mixed-provenance team. Employer attribution is high confidence for IBM; the specific site (Albany vs. Yorktown) is moderate confidence from the inventors' publication histories.

Unusual pattern to flag (carried forward from the prior summary): the recorded assignment shows inventor signing dates spanning 2012-01-16 to 2015-11-25 — i.e., one signer signed roughly three years and eleven months before the 2015-12-08 filing date, while the last signed ~2 weeks before filing. That long spread is not a typical single-filing assignment sheet. It is consistent with (a) a long-pending / re-filed application, or (b) an assignment instrument that swept in an earlier related application or a pre-existing obligation. Either way it is a data anomaly worth confirming against the assignment document text — but it is not evidence of inventor flight. There is no indication any inventor departed IBM around filing; the "all inventors leave within 12 months → fire-sale" precursor is not present.

Original assignee

International Business Machines Corporation (Armonk, New York) — named as original assignee on the issue record and, per all sources examined, still the current assignee. No company-level “Change of Name” is recorded for this chain (IBM has been “International Business Machines Corporation” throughout the relevant period).

• Primary line of business: IBM is a global technology company — enterprise hardware, hybrid cloud/software, and (at filing) a leading semiconductor R&D and manufacturing operation, including the Albany NanoTech finFET program in which all five inventors worked. This patent sits squarely in IBM's core semiconductor process technology, i.e., a strategic, not orphaned, asset.
• Did they ship a product embodying the claims? The claims recite a fabrication method (a gate-last replacement-metal-gate FinFET flow with post-dummy-gate-removal channel implantation + anneal). A method claim is practiced in the fab, not in a shipped part. IBM's 14nm/22nm-class FinFET foundry output (and its Albany NanoTech R&D line) is the relevant embodying activity, but there is no public evidence this specific process was used in a commercially sold IBM chip. Marking this unclear rather than asserting embodiment.
• Current status: Operating. IBM has not filed for bankruptcy and remains a going concern. Note the adjacent corporate event: IBM divested its Microelectronics semiconductor manufacturing business to GlobalFoundries (deal announced Oct 2014, closed July 2015) — a few months before this application was filed (2015-12-08). Critically, this patent did not transfer with the Microelectronics division; it remained with IBM, which is consistent with IBM retaining its R&D/patent estate while divesting fabs.

Assignment timeline

The chain contains exactly one recorded assignment — the original inventor→IBM assignment. There are no security agreements, no change-of-name recordings, no merger recordings, no license recordings, and no post-issuance transfers on this application or its patent.

• 2015-12-08 (recorded) — Reel 037237 / 0001
  • Conveyance: Assignment of (entire) interest — recorded text: “ASSIGNMENT OF ASSIGNMENT OF INTEREST”
  • Assignors: DORIS, BRUCE B.; HE, HONG; KANAKASABAPATHY, SIVANANDA K.; and others (Gauri Karve; Fee Li Lie) — signing dates 2012-01-16 to 2015-11-25
  • Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY
  • Correspondent of record: Not retrieved. The sources I could reach (Google Patents legal events, uspto.report) expose the reel/frame and conveyance text but not the recording correspondent's name/firm/address for this entry. I will not guess one. (IBM in-house filings of this era typically carry an IBM Intellectual Property Law correspondent of record, but I could not verify the name for reel 037237/0001 — treat that generalization as a lead to confirm at Assignment Center, not a finding.)
  • Context: Standard original-employment assignment (inventors → employer at filing). Not an acquisition, fire-sale, securitization, or asserter transfer.

Because the Assignment Center shows no records beyond the original assignment, that is itself the finding: IBM still owns the patent. This is corroborated by the maintenance-fee history on the patent's legal events — 4th-year fee paid 2019-10-16 and 8th-year fee paid 2023-10-17, both by the same “LARGE ENTITY” owner, with no fee-address change or assignee substitution event.

Method caveat: I did not independently confirm whether the two divisionals (US 9,515,141 and US 9,640,640, both filed 2016-04-22) carry any assignment of their own. If a later transfer exists in this family, it is at least as likely to appear on a divisional record as on the parent. That check remains open.

Timeline diagram

timeline
    title Ownership of US 9331148
    2012 : First inventor signs assignment
    2015 : Application filed 08 Dec
         : Assignment recorded reel 037237 frame 0001
    2016 : Patent issued 03 May
    2019 : 4th year maintenance fee paid
    2023 : 8th year maintenance fee paid
    2035 : Anticipated expiration

NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT. The sole assignee is International Business Machines Corporation (reel 037237/0001). No “IP / Holdings / Licensing / Ventures” suffix entity, no single-purpose LLC, no registered-agent-service address appears anywhere in the chain. Nothing to support a shell-transfer finding.

2. Known asserter in the chain — NOT PRESENT. The assignee (IBM) does not appear on any NPE/PAE list I compared against (Acacia, Marathon, Intellectual Ventures, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Spangenberg entities, etc.). No such entity is in the chain.

3. Repeat correspondent across the chain — UNCLEAR (data gap). There is only one recorded link, so recurrence cannot be assessed even in principle, and the correspondent of record for reel 037237/0001 was not retrievable from the sources I reached. Marked unclear, not “not present,” because I lack the underlying record — I will not assert the absence of a recurring facilitator I never observed.

4. Cascading transfers — NOT PRESENT. No chained assignments; a single link in 2015 and nothing after, so the “multiple LLCs in <24 months” pattern is inapplicable.

5. Pre-litigation transfer — NOT PRESENT. No infringement suit naming US 9,331,148 was found (district court, PTAB, or CAFC). There is therefore no transfer within 6 months of any suit, because there is no suit and no transfer.

6. Bankruptcy fire-sale — NOT PRESENT. IBM has not filed Chapter 7/11, and no bankruptcy-sale conveyance touches this patent. (The relevant IBM-side corporate event was the GlobalFoundries Microelectronics divestiture, which closed July 2015; this patent stayed with IBM — the inverse of a fire-sale.)

7. Privateering — NOT PRESENT. No operating-company-to-NPE transfer exists; IBM retained title and there is no downstream NPE asserting on IBM's behalf over this patent.

8. Defensive aggregator (anti-NPE) — NOT PRESENT. The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. It terminates at IBM itself. (Absence of aggregation is not itself a signal either way; noted for completeness.)

Verdict

Insufficient data — only the original assignment is of record.

Justification: the entire recorded chain for US 9,331,148 is a single link — reel 037237/0001, recorded 2015-12-08, conveying the inventors' interest to International Business Machines Corporation, with no subsequent assignment, security interest, license, or change of name, and maintenance fees paid by the same large-entity owner in 2019 and 2023. The rubric explicitly maps “only the original assignment” to Insufficient data, and that is the accurate label here — there is no post-issuance transfer history to score. Substantively, none of the eight NPE signals are present: the patent remains with an operating, non-bankrupt original assignee, and no assertion activity (litigation or PTAB) was found. If deeper confirmation is needed, the open items are (i) the correspondent of record on reel 037237/0001 and (ii) whether either divisional (US 9,515,141 / US 9,640,640) carries a separate assignment.

Verify at USPTO Assignment Center: https://assignmentcenter.uspto.gov/ (search patent number 9331148; also indexed at https://assignment.uspto.gov/patent/index.html). Reel/frame to request: 037237/0001.

Contradictions / caveats vs. prior sections

• No contradiction with the prior bibliographic summary — the “no reassignment of record found” conclusion in the earlier section is confirmed, and this section adds the reel/frame (037237/0001) and the inventor-signing-date spread as supporting detail.
• One unresolved item carried forward: the earlier summary flagged the 2012–2015 signing-date range and the ~5-month filing-to-grant gap as “unusual.” This section concurs and adds that the wide signing range most plausibly reflects a continuation/re-filing or a pre-existing assignment obligation, but I could not verify that from the assignment document text — it remains a lead, not a finding.

I'll verify the patent and research each cited reference. Let me start with targeted searches.

Let me research the remaining cited references.

Let me research the remaining cited references.

I've gathered what I can within the search budget. Below is the prior-art analysis for US 9,331,148 B1, built on the previously-generated verification section (which correctly identified the patent, its sole independent method claim 1, and its 9 cited references' companion set).

⚠️ Important framing note up front: The task asks which cited references "potentially anticipate" claims under §102. Having worked through the eleven references, my honest conclusion is that none of them anticipates claim 1 (or any claim) under §102, because every reference lacks at least one element of the ordered claim-1 flow — most notably the specific combination of (i) forming a conductive contact on the source/drain before (ii) stripping the dummy gate to expose the channel, then (iii) implanting ions in the channel region followed by (iv) annealing. These references are §103 obviousness-type art (background/context in the strained-FinFET and replacement-gate space), not §102 anticipating art. I flag this rather than manufacture anticipation mappings that the record does not support.

I also note the immediate caution: my retrieval budget was exhausted before I could pull the full text of several references (flagged below), so for those I rely on the authoritative citation metadata reproduced in the patent itself plus general knowledge, and I mark confidence levels explicitly.

1. Patent confirmation (building on the prior section)

The search confirmed exactly one match for the number 9331148 — US 9,331,148 B1, "FinFET device with channel strain," IBM, filed/priority 2015-12-08, granted 2016-05-03, App. 14/962,194 (uspto.report and Google Patents agree). No similar-number substitution was made. Accordingly, every reference below is prior art relative to the 2015-12-08 filing (all have publication dates well before 2015).

2. The eleven cited references — citations, dates, descriptions

These are the "Patent Citations (11)" of record. Dates below are as printed in the patent record (priority date / publication or issue date).

Note on the record's own flags: the Google Patents table marks items 6, 10, and 11 with an asterisk (cited by examiner) and the remainder without; I did not independently reconcile which of the eleven came from the examiner versus the applicant's IDS, so treat that distinction as unverified.

3. §102 anticipation analysis, claim-by-claim

Claim 1 (sole independent claim) requires, in order: (1) fin on substrate → (2) dummy gate stack → (3) remove a portion of exposed fin → (4) form source/drain on exposed fin → (5) form a conductive contact on the source/drain → (6) remove dummy gate to expose channel → (7) implant ions in the channel region → (8) anneal → (9) form gate stack over channel.

Finding: No cited reference anticipates claim 1. For each reference, at least one element is missing, and more than one is missing for most:

• US 7,335,545 (Amberwave, #1): Discloses relaxing strain by PAI (implant) and thermal anneal — the opposite polarity of the invention's stated goal (claims 2–3 add strain). It has no fin, no dummy-gate-then-contact sequencing, and no channel-located implant. Missing elements 2, 4, 5, 7 (in-channel), 9. No anticipation even of dependent claim 5 (fin strained at formation), because it is a planar SSOI substrate, not a fin. Relevant primarily to §103.
• US 2005/0266632 (Chen, #2): Mixed strained/non-strained transistor integration; silent on the claim-1 ordered replacement-gate + contact-before-gate-strip + channel-implant flow. Missing elements 5, 6, 7, 9. No anticipation.
• US 7,138,323 (Intel RMG, #3): Discloses replacement-metal-gate/planarization — supports elements 6 and 9 only. No fin-etch/S-D/contact-before-strip/channel-implant. No anticipation; §103 context for the gate-last scaffold.
• US 7,335,929 (TSMC, #4): Strained channel via lattice-mismatched SiGe in recesses and epitaxial source/drain. Touches element 4. No dummy-gate removal, no conductive contact before gate pull, no post-gate-removal channel implant/anneal. No anticipation.
• US 2006/0292776 (Jin, #5) and US 2007/0235818 (Anderson, #6): General strained-FET / dual-plane CMOS disclosures with no fin-last + channel-implant-after-dummy-gate-removal flow. No anticipation.
• US 7,871,877 (GlobalFoundries, #7): Closest art. Implant to create a strain layer, but expressly under the channel region — not in the channel as claim 1 and claim 4 (Ge ions) require, and it lacks the fin/dummy-gate/contact ordering. No anticipation of claim 1 or claim 4; strong §103 candidate for the core "implant-to-strain-the-channel" idea and for dependent claim 3 (implant increases channel strain).
• US 2012/0080722 (CAS, #8): Strained-channel formation; no claim-1 sequence disclosed. No anticipation.
• US 8,847,281 (Intel, #9): Strained high-mobility fin channels — relevant to claim 5 (strained fin at formation) and claim 8 (SiGe fin) conceptually, but not to the claim-1 flow. No anticipation.
• US 2014/0145242 (TSMC, #10): "Fin-last" FinFET — gate-last ordering for fins; supports element 9 context only. No anticipation.
• US 2015/0214051 (Samsung, #11): Generic semiconductor device/fabrication; nothing establishing the claim-1 combination. No anticipation.

Net: zero §102 anticipations. Where individual references do overlap, they map to dependent concepts rather than the full claim:

• Claim 2 (fin removal reduces channel strain) — background teaching in #1 (relaxation) and #4.
• Claim 3 (implant + anneal increases strain) — #1 (implant/anneal relaxation) and #7 (implant-formed strain layer under channel) as §103 art.
• Claim 4 (Ge ions) — #7 (implantation-based strain layer) and #4 (SiGe stressors) as §103 art; neither puts Ge ions in the channel after dummy-gate removal.
• Claim 5/8 (strained fin; SiGe fin) — #9 and #1.
• Claim 7 (anneal ≥ ~900 °C) — routine anneal parameters across #1, #3, #4; §103 art for the parameter itself.
• Claim 9 (lithographic patterning/etch) — ubiquitous.

4. Bottom line

• No single cited reference anticipates any claim of US 9,331,148; the patent's novelty sits in the ordered combination (contacts built before dummy-gate strip, then in-channel ion implant + anneal before replacement gate).
• The two references of real substantive interest are US 7,871,877 B2 (GlobalFoundries) — implantation to create a strain-inducing layer, albeit under the channel — and US 8,847,281 B2 (Intel) — strained fin channels. Together with the replacement-gate art (#3, #10), they form the likely §103 combination an examiner would assemble, not a §102 rejection.
• The remaining references (#2, #5, #6, #8, #11) read as general background in strained-FET/CMOS design and are cumulative.

5. Confidence and limitations

• High confidence on the list of eleven cited references and their citation data, because these come from the authoritative full patent text.
• High confidence on the §102 conclusion (no anticipation) and on the descriptions of #1, #3, #4 and the title-level characterization of the rest — those were verified against retrieved sources.
• Moderate-to-low confidence on the detailed substance of references #5, #6, #7, #8, #9, #10, #11: my tool budget expired before I could retrieve full text for these, so their descriptions rest on the record's titles plus general knowledge. In particular, my read of #7 (US 7,871,877) — that the strain-inducing layer is under the channel — is drawn from its title and should be re-verified against the specification before being relied on in any office action or invalidity contention.
• Not verified: which citations were examiner-cited vs. applicant-cited; and the internal content of the sister patents US 9,515,141 and US 9,640,640.

If you want, the next step would be a targeted retrieval of US 7,871,877, US 8,847,281, US 2014/0145242, and US 2015/0214051 to lock down their §§102/103 treatment with page-and-line citations.

I'll ground this § 103 analysis by verifying what the cited prior-art references actually disclose, rather than relying on titles alone.

Let me verify the remaining key cited references before finalizing the combination analysis.

Obviousness Analysis — US 9,331,148 B1 under 35 U.S.C. § 103

0. Scope, sources, and caveats

This analysis is built from (a) the authoritative full text of US 9,331,148 ("the '148 patent"), (b) the Prior Art / Citations (11) list on the patent page, and (c) verification searches I ran on the most load-bearing cited references. I flag verification status for each reference so you can weight the analysis appropriately:

Important scope point carried over from the prior summary: the issued claims of the '148 patent are all method claims (claim 1 independent; claims 2–9 dependent). The device aspect described in the specification's Summary ("channel region … includes implanted germanium ions that are operative to induce a strain") is not claimed here. So the entire § 103 inquiry reduces to the ordered process steps of claim 1.

I did not obtain full text for the title-only references. Where I rely on them, I say so and treat them as cumulative/confirmatory rather than load-bearing. Nothing below should be read as a legal conclusion; validity is ultimately a claim-construction-dependent and evidence-intensive question.

1. The claim 1 elements, as a chart

The alleged point of novelty is the combination and ordering of (f)→(g)→(h)→(i): implant-and-anneal the exposed channel after the dummy gate is pulled, in a fin-last, source/drain-and-contact-first flow. No single reference need disclose every step; the question is whether the combination was obvious.

2. The obviousness case

2.1 Primary reference — a fin-last / replacement-gate FinFET flow

US 2014/0145242 A1 (TSMC) is the strongest single anticipatory-in-spirit reference and is expressly in the '148 Prior Art list. It discloses a fin-last FinFET in which: a fin/strip is formed on a substrate; a dummy gate is formed over the fin; source/drain regions are formed on opposite sides of the dummy gate (including source/drain recesses and epitaxy); the dummy gate and dummy gate dielectric are removed to form an opening exposing the channel region; and a replacement channel region is formed, the reference stating the device "may have better performance due to the strain inducing and/or high mobility channel region." That discloses elements (a), (b), (c)/(d), (f), (i), and the motivation of strain/high-mobility.

The same family/flow (e.g., IBM/Chang, US 8,637,359 / US 2014/0117464, "Fin-Last Replacement Metal Gate FinFET") confirms this is a well-known architecture: dummy gate → S/D implant/recess/epi → dielectric filler → dummy gate removed → channel region defined → replacement gate formed. That corroborates that elements (a)–(f) and (i) were routine in the art by the '148's 2015-12-08 filing date.

US 7,138,323 B2 (Intel) — "Planarizing a semiconductor structure to form replacement metal gates" — is the title-level corroboration that a replacement-metal-gate (gate-last) process was standard prior art, supplying element (i) as a known technique.

2.2 Secondary reference — implant + anneal to (re)generate channel strain

US 7,871,877 B2 (GlobalFoundries) discloses the exact mechanism the '148 claims. Verified text: it "relates to methods … in which … a strain-inducing semiconductor material is formed below the respective channel region on the basis of an implantation process." It teaches "implanting a first ionic species … [having] the same valence and different covalent radius compared to silicon," then "performing an anneal process … to re-crystallize the silicon-based layer … in order to form a strained silicon-based material," and only then "forming a gate electrode structure above the silicon-based layer." Critically for the ordering question, '877 states the strain-inducing material may be introduced "at an appropriate process stage, for instance, prior to the fabrication of respective gate electrodes," explicitly framing implantation as insertable into a gate-last flow.

This supplies elements (g) implanting ions in the channel region and (h) annealing, and it supplies the reason why (strain → mobility → performance), which is the '148's entire stated purpose.

US 2012/0080722 A1 (CAS) independently supplies both the mechanism and, more importantly, the motivation and ordering. Verified text: it "removes the dummy gate stacks to form openings; and [forms] a tensile strained epitaxial layer in the opening of the NMOS transistor, and … a compressive strained epitaxial layer in the opening of the PMOS transistor." Its stated rationale: doing so "avoid[s] the strained semiconductor channel being exposed to high-temperature source/drain annealing" and "loss of strained … material can be avoided … the stress in the channel can be better maintained." That is precisely the problem recited in the '148 specification ("[t]he removal of portions of the fins … undesirably reduces (relaxes) the strain in the channel region"). '722 uses Ge-containing strained channels and a SiGe relaxed layer, which also touches dependent claims 4 and 8.

2.3 The two-reference combination that renders claim 1 obvious

Ground 1: US 2014/0145242 (TSMC) in view of US 7,871,877 (GlobalFoundries).

• '242 provides (a) fin, (b) dummy gate, (c)/(d) fin recess + S/D, (f) dummy-gate removal exposing the channel, and (i) a replacement gate/strained channel — i.e., a fin-last RMG flow whose channel is exposed at gate-pull.
• '877 provides (g) ion implantation (same-valence/different-covalent-radius species) and (h) anneal to form a strained region, together with the express teaching that this can be done before gate formation.
• '722 (if also applied) supplies the articulated reason to locate the strain-generating step after dummy-gate removal: to avoid the high-temperature S/D anneal relaxing the channel.

A person of ordinary skill in the art (POSITA) reading '242 and '877 together would arrive at claim 1's ordered steps with (e) "conductive contact on the source/drain" being the routine S/D contact formation that fin-last flows already address (the '242/self-aligned-contact art explicitly deals with contacting the S/D of a fin-last FinFET).

Ground 2: US 2012/0080722 (CAS) in view of US 7,871,877 (GF) and a FinFET reference (US 8,847,281 Intel or US 2014/0145242 TSMC).
'722 supplies gate-last + "form the strained channel region after dummy-gate removal to preserve strain"; '877 supplies the implant-and-anneal vehicle for creating that strain (rather than '722's epitaxial replacement channel); the FinFET reference supplies the fin/fin-recess architecture. This is arguably an even tighter fit on motivation, because '722's stated problem is identical to the '148's.

3. Motivation to combine (KSR factors)

The teaching–suggestion–motivation requirement is satisfied by several independent, overlapping rationales under KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007):

1. Same problem, same field. Both '877 and '722 address the same problem the '148 identifies — creating/preserving channel strain to raise carrier mobility in a scaled transistor. '722 literally names "strain … released in high-temperature steps" as the problem to solve.
2. Known, finite set of solutions. By the 2015 filing date, inducing channel strain by (i) implanting a lattice-mismatched species and annealing to recrystallize, and (ii) forming a strained channel after gate pull, were both known and the reference materials expressly note the "well-established manufacturing techniques" remain usable. Combining them is the predictable use of prior-art elements according to their known functions.
3. Design/process incentive flowing from the fin-last flow itself. The '242 fin-last flow creates the exposed-channel configuration. Once the channel is exposed after gate pull (element f), the natural and obvious place to inject strain engineering is precisely there — the '877 teaching that its implant may be placed "prior to the fabrication of respective gate electrodes" removes any structural barrier.
4. "Predictable results" / reasonable expectation of success. '877 states the implantation+anneal approach "substantiates … without negatively affecting any further process sequence," and '722 demonstrates a successful gate-last strained channel. A POSITA would reasonably expect the implant+anneal to restore strain lost during fin recess (which both the '148 spec and '722/'877 acknowledge occurs).

No teaching away is evident: '877 affirmatively locates its strain implant before the gate, and '722 affirmatively endorses forming the strained channel after dummy-gate removal. The references point in the same direction as the '148 claims rather than away from them.

4. The dependent claims

Applying the same references, every dependent claim follows:

Claims 4, 7, and 8 are the ones with the strongest independent-claim spillover. Claim 4 is nearly foreclosed by '877's explicit teaching of a same-valence/different-covalent-radius implanted species (Ge in Si) plus '722's Ge-channel disclosure. Claim 8 is supported by '722/'545. Claim 7 rests on the ordinary skill level (a 900 °C+ activation/recrystallization anneal) and is well supported by the general RTA practice described in the cited art.

5. Rebuttal considerations and honest uncertainties

• Element (e) — "conductive contact" before gate pull. The '148 requires the contact to be formed on the S/D before removing the dummy gate. My verified text for the TSMC '242 does not expressly recite forming an inter-level contact at that exact point (it recites S/D and self-aligned S/D contacting; silicide). This is the element I am least certain about from verified text, and it is where a patent owner would likely focus a secondary-consideration or "different order" argument. Confidence for this single element: moderate. A PACER/full-text pull of US 2014/0145242's complete specification (and its US 9,543,301 relative) would resolve it.
• Ground 1 uses '242 for element (f)+(i) while '877 is used only for (g)+(h). If a factfinder were to read '877 as limited to forming the strain region below (not in) the channel and before fin formation, a patent owner could argue no suggestion to relocate the implant to the post-gate-pull channel. '877's own text ("prior to the fabrication of respective gate electrodes") and '722 defeat that argument, but it is the main non-frivolous teaching-away theory.
• Title-only references. I did not obtain full text for US 7,138,323, US 7,335,545, US 2005/0266632, US 7,335,929, US 2006/0292776, US 2007/0235818, or US 2015/0214051. If the analysis is to be filed, each should be pulled and the specific paragraphs cited; my combination does not depend on them, and I have deliberately not asserted specific disclosures from their bodies.
• No litigation/PTAB caveat repeated: as noted previously, the prior verification found no IPR/PGR or district-court proceeding against this patent; conversely, there is no KSR-ERA prosecution record available here showing how the Examiner treated these references. Absence of an obviousness rejection on the record is not evidence of non-obviousness but would be worth confirming from the file wrapper (which I did not pull).

6. Bottom line

Claim 1 of US 9,331,148 is, on the cited art, a predictable combination of two known techniques placed in a known flow:

• a fin-last / replacement-metal-gate FinFET process (US 2014/0145242, corroborated by US 7,138,323 and the general RMG art) supplying "form fin → dummy gate → S/D → pull dummy gate → replacement gate"; and
• implant-and-anneal strain engineering of the channel (US 7,871,877, with US 2012/0080722 supplying the express motivation to do it after dummy-gate removal to avoid strain relaxation).

The '148 specification itself concedes the fin-etch/S-D steps relax channel strain and that pre-fin-lamination strain engineering is conventional — i.e., the inventor adopted the known solution (post-gate-pull implant + anneal) to the known problem. Under KSR, that is a strong prima facie § 103 case against claim 1, and the dependent claims (especially 3, 4, and 8) are met or rendered obvious by the same references. The principal factual gap to close before relying on this analysis is verification of the "conductive contact on the source/drain before gate removal" element and full-text confirmation of the title-only references.

Overall confidence: high for claims 3, 4, 6, 9; moderate-to-high for claims 1, 2, 5, 8; moderate for claim 7 (rests on the level of ordinary skill for the 900 °C anneal) and for claim 1's element (e).