Prior art — US Patent 9281314B1

Based on your request, here is a detailed analysis of the prior art cited on the face of U.S. Patent No. 9,281,314 B1.

Analysis of Prior Art Cited in U.S. Patent No. 9,281,314 B1

This analysis examines the prior art references cited by the USPTO examiner during the prosecution of the '314 patent. The core inventive concept of the '314 patent, as detailed in the independent claims, involves a non-volatile memory device and its manufacturing method. The key feature is the selective formation of a protective silicon nitride layer on the sidewalls of the word lines, but not on the sidewalls of the charge storage regions, which are instead insulated by an air gap. This is achieved using a sacrificial layer that is deposited and then etched back to a specific height before the nitride deposition.

The following is an assessment of the most relevant cited patents and their potential to anticipate the claims of the '314 patent under 35 U.S.C. § 102.

1. U.S. Patent No. 8,633,546 B2 (Lee et al.)

Full Citation: U.S. Patent No. 8,633,546 B2, "Semiconductor device and method for manufacturing the same," issued to Hynix Semiconductor Inc.
Filing Date: June 21, 2011
Issue Date: January 21, 2014
Description: The '546 patent describes a semiconductor device with air-gap spacers to reduce parasitic capacitance between gate structures (e.g., word lines). The method involves forming a gate pattern, depositing a liner oxide layer and a liner nitride layer over the gate pattern, and then forming spacers. A sacrificial layer is deposited and then removed to form the air gap between the gate structures.
Potential Relevance to '314 Patent Claims:
- The '546 patent discloses the use of both an oxide liner and a nitride liner on the sidewalls of a gate structure, as well as the formation of an air gap for isolation. This combination of materials and the use of an air gap are relevant to the general field of the '314 patent.
- However, the '546 patent does not teach the key inventive step of the '314 patent: the selective application of the nitride layer. In Lee et al., the nitride liner appears to be formed conformally over the entire gate stack sidewall, including the areas adjacent to what would be the charge storage region. It does not describe a process for intentionally removing or preventing the formation of this nitride layer at the lower portion of the memory cell stack while retaining it at the upper word line portion. Therefore, it would not anticipate the limitations of claims 1, 8, or 15, which all require this specific, differentiated sidewall structure.

2. U.S. Patent No. 8,664,710 B2 (Kim et al.)

Full Citation: U.S. Patent No. 8,664,710 B2, "Non-volatile memory device and method of fabricating the same," issued to Samsung Electronics Co., Ltd.
Filing Date: August 3, 2012
Issue Date: March 4, 2014
Description: This patent discloses a method for forming a NAND flash memory device with air gaps between word lines to reduce interference. The process involves forming gate stacks, depositing a spacer layer (such as silicon nitride), etching the spacer to form sidewall spacers, and then depositing a sacrificial layer. The sacrificial layer is then removed to create the air gap.
Potential Relevance to '314 Patent Claims:
- Similar to the '546 patent, Kim et al. teach the use of air gaps for insulation between word lines and the use of nitride spacers. The use of a sacrificial layer to form the air gap is also disclosed, which is an element of claim 15 of the '314 patent.
- However, the process described in the '710 patent is different. The nitride spacers are formed before the sacrificial layer is introduced. Furthermore, these nitride spacers appear to cover the entire sidewall of the gate stack, from top to bottom. The patent does not describe the '314 patent's specific structure of an oxide layer covering the entire sidewall, with a nitride layer covering only the upper portion of that oxide layer (adjacent to the word line). This key structural limitation is absent. Therefore, the '710 patent would not anticipate claims 1, 8, or 15.

3. U.S. Patent Application Publication No. 2008/0179679 A1 (Kim et al.)

Full Citation: U.S. Patent Application Publication No. US 2008/0179679 A1, "Nonvolatile memory device with air gap structure and method for fabricating the same," assigned to Hynix Semiconductor Inc.
Filing Date: January 22, 2008
Publication Date: July 31, 2008
Description: This publication describes forming a non-volatile memory device where air gaps are used to insulate word lines. The method involves creating gate structures, forming an etch stop layer (e.g., silicon nitride) and an insulating interlayer (e.g., silicon oxide) between them, and then selectively removing the insulating interlayer to create the air gaps.
Potential Relevance to '314 Patent Claims:
- This reference clearly discloses the use of air gaps for insulation between word lines in a memory array. It also mentions using both silicon oxide and silicon nitride layers as part of the structure.
- However, the structural arrangement and formation method are distinct from the '314 patent. The nitride layer in this application acts as an etch stop layer at the bottom of the trench between word lines, not as a selective protective layer on the upper sidewalls of the word lines. It does not teach the '314 patent's structure of an oxide-covered sidewall with nitride only on the portion adjacent to the word line. The method of using a sacrificial layer that is etched back to a specific level to mask the lower portion of the cell is not described. Therefore, this reference does not anticipate the claims of the '314 patent.

4. U.S. Patent No. 8,338,252 B2 (Yang)

Full Citation: U.S. Patent No. 8,338,252 B2, "Semiconductor memory device and method of fabricating the same," issued to Macronix International Co., Ltd.
Filing Date: March 9, 2011
Issue Date: December 25, 2012
Description: Yang describes a method of fabricating a memory device, focusing on the formation of self-aligned contacts and isolation structures. The process includes forming gate stacks, creating sidewall spacers, and using a "gap-fill" material that is subsequently etched back. The patent is concerned with preventing short-circuits and managing process complexity in scaled-down devices.
Potential Relevance to '314 Patent Claims:
- The '252 patent discusses fabricating gate stacks with sidewall spacers and using etch-back techniques, which are general processes also used in the '314 patent.
- However, the specific combination of materials and their final arrangement as claimed in the '314 patent is not disclosed. Yang does not teach forming an oxide liner followed by a selective nitride layer that is deliberately excluded from the area near the charge storage region. The purpose and structure of the sidewall materials in Yang are for creating contacts and general isolation, not for the specific charge-trapping prevention and word line protection taught in the '314 patent. Therefore, this patent does not anticipate the claims of the '314 patent.

Summary of Prior Art Analysis

The prior art references cited by the examiner during the prosecution of the '314 patent establish the context of semiconductor memory fabrication at the time. Key concepts such as using air gaps for insulation (Lee et al. '546, Kim et al. '710, Kim et al. '679), forming sidewall spacers made of oxide and nitride (Lee et al. '546, Kim et al. '710), and employing sacrificial layers and etch-back processes (Lee et al. '546, Kim et al. '710, Yang '252) were known in the art.

However, none of the cited references appear to disclose the unique combination recited in the independent claims of the '314 patent. The novelty of the '314 invention lies in the deliberate and selective placement of the silicon nitride layer. Specifically, the nitride covers the oxide on the sidewalls of the word lines but is absent from the oxide on the sidewalls of the charge storage regions. This distinction is crucial, as the patent's specification explains it is done to prevent charge trapping near the storage region, which can degrade device performance, while still protecting the metallic word line during subsequent processing steps.

The manufacturing method of claim 15, which uses a sacrificial layer that is precisely etched back to act as a mask for this selective nitride deposition, also appears to be absent from the cited prior art. Therefore, based on a review of the cited references, no single reference fully anticipates the structures or methods claimed in U.S. Patent No. 9,281,314 B1.