Obviousness

Analysis of Obviousness for U.S. Patent No. 9,281,314 B1

To: File
From: Senior Patent Analyst
Date: May 13, 2026
Subject: Obviousness Analysis of U.S. Patent No. 9,281,314 B1

---

1. Introduction and Scope

This report provides an analysis of the potential obviousness of the claims of U.S. Patent No. 9,281,314 B1 (hereafter, "the '314 patent") under 35 U.S.C. § 103. The analysis is based on prior art references cited during the patent's prosecution and other publicly available documents preceding the patent's priority date of October 10, 2014.

A Person Having Ordinary Skill in the Art (PHOSITA) at the time of the invention would be an engineer or scientist with a Master's degree in electrical engineering, materials science, or a related field, and 2-3 years of experience in semiconductor device fabrication, particularly in the area of non-volatile memory. Alternatively, a PHOSITA could have a Bachelor's degree and 5+ years of direct experience in the field. Such a person would be familiar with standard deposition, etching, and patterning techniques (e.g., CVD, PVD, RIE), as well as the structures and challenges of NAND flash memory, including inter-device interference and material properties of dielectrics like silicon oxide (SiO₂) and silicon nitride (SiN).

2. Core Inventive Concept of the '314 Patent

The central inventive concept of the '314 patent is a memory device structure and its fabrication method that selectively forms a protective silicon nitride layer on the sidewalls of the word lines, while intentionally omitting this nitride layer from the sidewalls of the underlying charge storage regions.

As detailed in the patent, this is achieved by:

1. Forming memory cell stacks, each including a charge storage region and a word line.
2. Depositing a conformal layer of silicon oxide over the entire stack sidewall.
3. Filling the gaps between stacks with a sacrificial material.
4. Recessing the sacrificial material to a level below the word lines but above the charge storage regions, thereby exposing only the upper portion of the oxide-covered sidewalls.
5. Depositing silicon nitride, which forms only on the exposed upper portions.
6. Removing the sacrificial material, leaving an air gap adjacent to the charge storage regions.

This structure aims to leverage the protective benefits of silicon nitride for the word line (e.g., tungsten) during subsequent processing steps, while avoiding the known problem of charge trapping associated with having silicon nitride adjacent to the charge storage layer, which can degrade memory cell performance (e.g., cause threshold voltage shifts). The resulting air gap provides excellent electrical isolation between adjacent word lines, addressing the issue of parasitic capacitance.

3. Prior Art References

Several prior art references, when combined, suggest that the claims of the '314 patent would have been obvious to a PHOSITA. The following references are particularly relevant:

• US 2011/0266611 A1 ("Son et al."): Teaches a method of fabricating a NAND flash memory device. It discloses forming word line stacks, depositing a liner oxide layer on the sidewalls, and then forming a silicon nitride spacer on the liner oxide. Critically, Son et al. teaches forming this nitride spacer along the entire sidewall of the word line stack, including the portion adjacent to the charge storage region. This reference establishes the foundational structure and use of oxide/nitride sidewalls in memory devices.
• US 2013/0200444 A1 ("Sato et al."): Addresses the problem of inter-wordline capacitance by forming air gaps. Sato et al. explicitly teaches a process of filling the space between word line stacks with a sacrificial layer (e.g., Spin-On Hardmask or SOH), recessing this sacrificial layer to a desired height, and then depositing a capping layer to seal the top, thereby creating an air gap after the sacrificial material is removed. This teaches the key process step used in the '314 patent to achieve selective material deposition.
• US 2011/0175168 A1 ("Lee et al."): Also describes a method for forming air gaps between conductive lines (such as word lines) to reduce parasitic capacitance. Lee et al. similarly discloses using a sacrificial layer that is deposited and then etched back, followed by the formation of a capping layer to define the air gap.

4. Obviousness Analysis of Key Claims

An analysis of the independent claims (1, 8, and 15) demonstrates that a PHOSITA would have found the claimed invention obvious by combining the teachings of these prior art references.

Argument for Obviousness: Son et al. in view of Sato et al.

a) Claim 1 and Claim 15 (Method Claims):

Claim 1 recites a method of forming a memory device by: (i) forming lines of memory cells with charge storage regions and control gates, and associated word lines; (ii) forming an oxide layer covering the sidewalls of both the charge storage regions and the word lines; and (iii) forming a nitride region adjacent to the oxide on the word line sidewalls but not adjacent to the oxide on the charge storage region sidewalls. Claim 15 further specifies the use of a sacrificial material that is etched back to enable this selective nitride formation, followed by removal of the sacrificial material to form air gaps.

A PHOSITA starting with the process described in Son et al. would form a memory stack with a full oxide/nitride sidewall. However, a PHOSITA would recognize a well-known problem with this structure: silicon nitride is a charge-trapping material. Placing it directly adjacent to the charge storage region (even with a thin oxide liner) can lead to threshold voltage (Vth) instability and degrade device reliability, a key concern in memory scaling. The '314 patent itself acknowledges this issue in its background description.

The motivation to solve this problem would lead the PHOSITA to seek a method for removing the nitride from the critical area near the charge storage region while retaining its protective benefits higher up on the word line. Sato et al. provides an explicit and well-understood solution for such localized processing. Sato et al. teaches the exact technique of depositing a sacrificial layer, recessing it to a specific height between features, and then performing a subsequent process step on the exposed upper portions.

It would have been a matter of routine engineering to apply the recessed sacrificial layer technique from Sato et al. to the structure of Son et al. The PHOSITA would:

1. Follow Son et al. to form the memory cell stacks and deposit the conformal oxide liner (as recited in claim 1).
2. Instead of immediately forming the nitride spacer of Son et al., the PHOSITA would apply the method of Sato et al. by filling the trenches with a sacrificial material and etching it back to expose the upper part of the word line stacks.
3. Proceed with depositing a silicon nitride layer, which would now only form on the exposed upper sidewalls.
4. Remove the sacrificial material, as taught by Sato et al. This would result in the structure of the '314 patent, where nitride protects the word line and an air gap provides isolation for the charge storage region.

This combination is not a result of hindsight, but rather a predictable application of a known processing technique (Sato et al.) to solve a known problem (nitride-induced charge trapping from a structure like that in Son et al.).

b) Claim 8 (Apparatus Claim):

Claim 8 describes the resulting memory device structure: lines of memory cells, word lines, first oxide regions on charge storage sidewalls, second oxide regions on word line sidewalls, nitride regions covering only the second oxide regions, and "electrical isolation regions other than silicon nitride" adjacent to the first oxide regions.

The structure described in claim 8 is the direct and inevitable result of the obvious-to-try process combination detailed above. By combining the teachings of Son et al. and Sato et al., a PHOSITA would arrive at a device with:

• Memory cell stacks (Son et al.).
• A silicon oxide liner on all sidewalls (Son et al.).
• A silicon nitride layer only on the upper portion of the sidewall, adjacent to the word line (Son et al.'s nitride layer, but with its location modified by Sato et al.'s process).
• An air gap where the sacrificial material was removed, which serves as the "electrical isolation region other than silicon nitride" adjacent to the charge storage region sidewalls (Sato et al.).

Therefore, the apparatus of claim 8 is rendered obvious by the combination of these references.

5. Conclusion

The claims of the '314 patent appear to be a combination of known elements from the prior art to solve a well-understood problem in the field. The use of an oxide/nitride sidewall structure was known (Son et al.). The problem of charge trapping by nitride near the active area of a transistor was also well-known. Furthermore, the technique of using a recessed sacrificial layer to selectively process the upper portions of a structure and/or to form an air gap was also explicitly taught (Sato et al., Lee et al.).

A person having ordinary skill in the art, when faced with the challenge of protecting word lines without introducing charge-trapping nitride near the storage layer, would have been motivated to combine the sacrificial layer technique of Sato et al. with the memory device structure of Son et al. This combination would lead directly to the method and apparatus claimed in the '314 patent with a reasonable expectation of success. Therefore, a strong case for obviousness under 35 U.S.C. § 103 exists for the independent claims of the '314 patent.