Derivative works

Defensive Publication: Advanced Sidewall Engineering for Semiconductor Devices

Publication Date: May 13, 2026
Reference: This disclosure builds upon the concepts described in U.S. Patent 9,281,314 B1.

Abstract: This document discloses several novel methods and structures for fabricating semiconductor devices, particularly non-volatile memory, by extending the principles of selective sidewall protection. The disclosed variations explore alternative materials, extreme operational parameters, cross-domain applications, integration with emerging technologies, and engineered failure modes. The purpose of this disclosure is to place these concepts into the public domain to foster innovation and prevent exclusive patenting of these incremental advancements.

Derivatives Based on Independent Claim 1: Method of Forming a Memory Device

1. Material & Component Substitution

• 1.1. High-k Dielectric Substitution for Oxide Layer

  • Enabling Description: A method for forming a memory device wherein the silicon oxide layer (532) is replaced with a high-k dielectric material such as hafnium oxide (HfO₂), aluminum oxide (Al₂O₃), or zirconium dioxide (ZrO₂). This layer is deposited using Atomic Layer Deposition (ALD) to ensure a conformal coating over the memory cell stack sidewalls (552, 554, 556, 558, 560). Following the high-k deposition, a silicon nitride (Si₃N₄) or boron nitride (BN) layer is selectively deposited adjacent to the word line (528) portion as described in the reference patent. The higher dielectric constant of the HfO₂ layer provides superior electrical isolation, reducing leakage current and allowing for a thinner physical layer, which is advantageous for device scaling.
  • Mermaid.js Diagram:

    graph TD
        A[Form Memory Cell Stack] --> B(Deposit Conformal HfO₂ Layer via ALD);
        B --> C{Apply Sacrificial Masking Layer};
        C --> D[Recess Etch Masking Layer to expose Word Line Sidewall];
        D --> E[Deposit SiN/BN Layer];
        E --> F[Remove Sacrificial Layer];
        F --> G[Form Air Gap Dielectric];
    

• 1.2. Carbon Nanotube (CNT) Conductive Word Lines

  • Enabling Description: A method where the word lines (528), typically tungsten, are replaced with a composite material comprising aligned carbon nanotubes (CNTs) embedded in a metallic or polysilicon matrix. This structure is formed by first growing a dense, vertically aligned forest of CNTs and then infilling the gaps with a conductive material via electroplating or chemical vapor deposition. This approach reduces RC delay due to the high conductivity and low capacitance of CNTs, improving device switching speeds. The subsequent oxide and nitride sidewall processes are then applied to this composite word line.
  • Mermaid.js Diagram:

    graph LR
        subgraph Word Line Formation
            A(Catalyst Deposition) --> B(CNT Growth via CVD) --> C(Infill with Tungsten/Polysilicon);
        end
        subgraph Sidewall Protection
            D(Deposit Oxide Layer) --> E(Apply & Etch Sacrificial Layer) --> F(Deposit Nitride Layer);
        end
        C --> D;
    

• 1.3. Polymer-Based Sacrificial Layer

  • Enabling Description: The sacrificial material (1002) is replaced with a spin-on organic polymer, such as a polyimide or a specialized block copolymer. This polymer is applied after the conformal oxide deposition (step 706) and can be precisely etched back using a plasma ashing process (e.g., O₂ plasma). The organic nature of the sacrificial material allows for a highly selective and residue-free removal using wet chemical stripping or plasma ashing, which does not attack the underlying oxide or the subsequently deposited nitride. This simplifies the removal step (910) and reduces the risk of damage to the memory cell structures.
  • Mermaid.js Diagram:

    sequenceDiagram
        participant Wafer
        participant Spin Coater
        participant Plasma Etcher
        participant CVD Chamber
        participant Wet Bench
    
        Wafer->>Spin Coater: Apply Polymer Sacrificial Layer
        Spin Coater-->>Wafer: Layer Formed
        Wafer->>Plasma Etcher: Etch Back Polymer to Expose Upper Sidewall
        Plasma Etcher-->>Wafer: Etch Complete
        Wafer->>CVD Chamber: Deposit Silicon Nitride
        CVD Chamber-->>Wafer: Nitride Spacer Formed
        Wafer->>Wet Bench: Strip Remaining Polymer
        Wet Bench-->>Wafer: Final Structure with Air Gap Precursor
    

• 1.4. Self-Assembling Block Copolymers for Dielectric Spacers

  • Enabling Description: Instead of a two-step process to form the oxide and nitride layers, a self-assembling block copolymer (BCP) is used. The BCP, such as polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA), is deposited over the memory stack. A thermal annealing process induces microphase separation, causing one polymer block to preferentially align along the word line region and the other along the charge storage region. Selective etching removes one block (e.g., PMMA), leaving behind a patterned polymer mask. This mask is used to selectively deposit silicon nitride only on the desired upper sidewall portion. The remaining BCP can then be stripped or used as part of the final dielectric structure.
  • Mermaid.js Diagram:

    graph TD
        A[Form Memory Stack] --> B[Deposit Block Copolymer];
        B --> C[Thermal Annealing for Phase Separation];
        C --> D[Selective Etching of One Polymer Block];
        D --> E[Deposit SiN on Exposed Sidewall];
        E --> F[Strip Remaining Polymer];
        F --> G[Final Structure];
    

• 1.5. Amorphous Carbon (a-C:H) Sacrificial Layer

  • Enabling Description: A hydrogenated amorphous carbon (a-C:H) layer is used as the sacrificial material (1002). This film is deposited via Plasma-Enhanced Chemical Vapor Deposition (PECVD) and exhibits excellent gap-fill properties. The a-C:H layer can be precisely etched back using an oxygen-based plasma. The key advantage is its extremely high etch selectivity relative to both SiO₂ and Si₃N₄, simplifying the etch-back (step 908) and removal (step 910) processes and minimizing damage to the permanent structures.
  • Mermaid.js Diagram:

    flowchart TD
        subgraph Process
            A(Deposit SiO2) --> B(Deposit a-C:H Sacrificial Layer) --> C(Etch Back a-C:H) --> D(Deposit Si3N4) --> E(Anisotropic Etch Si3N4) --> F(Strip a-C:H) --> G(Form Air Gap)
        end
    

2. Operational Parameter Expansion

• 2.1. Cryogenic Memory Application

  • Enabling Description: The described structure is optimized for operation at cryogenic temperatures (e.g., 77 K), for use in quantum computing or high-performance computing environments. The air gap (844) provides superior thermal isolation between word lines, minimizing thermal crosstalk in densely packed arrays operating at high frequencies. The silicon nitride (534) layer is engineered with a specific stoichiometry (e.g., silicon-rich) to minimize stress and prevent delamination or cracking during thermal cycling between room temperature and cryogenic temperatures. This ensures the mechanical integrity and electrical isolation of the word lines.
  • Mermaid.js Diagram:

    graph TD
        A[Standard Device] -->|Cryogenic Cycling| B(Thermal Stress);
        B --> C{Failure Modes};
        C -- Delamination --> D[Word Line Short];
        C -- Cracking --> E[Dielectric Breakdown];
    
        subgraph Cryogenic-Optimized Device
            F(Memory Stack) --> G(Conformal SiO2);
            G --> H(Stress-Compensated SiN on WL Sidewall);
            H --> I(Vacuum-Sealed Air Gap);
        end
    
        I --> J[Stable Cryogenic Operation];
    

• 2.2. High-Temperature Automotive/Industrial Application

  • Enabling Description: The memory device is fabricated for high-temperature environments (>150°C), such as automotive under-the-hood or industrial control systems. The word line material is a refractory metal silicide, such as tungsten silicide (WSiₓ) or molybdenum silicide (MoSi₂), to prevent electromigration at elevated temperatures. The silicon oxide (532) and silicon nitride (534) layers are deposited using a high-density plasma CVD (HDP-CVD) process to create dense, low-defect films with superior thermal stability and resistance to charge leakage at high temperatures. The air gap (844) enhances thermal isolation, preventing heat from one active word line from affecting the threshold voltage of adjacent memory cells.
  • Mermaid.js Diagram:

    graph TD
        subgraph Materials
            A[Substrate] --> B[Memory Cell Layers];
            B --> C[WSi₂ Word Line];
        end
        subgraph Process
            D[Form Stacks] --> E[Deposit HDP-CVD SiO₂];
            E --> F[Deposit HDP-CVD SiN on WL Sidewall];
            F --> G[Form Air Gap];
        end
        C --> D
        G --> H{High-Temp Operation > 150°C};
        H -- Prevents --> I[Electromigration];
        H -- Prevents --> J[Thermal Crosstalk];
    

3. Cross-Domain Application

• 3.1. MEMS Resonator Fabrication

  • Enabling Description: The method is adapted to fabricate high-frequency Micro-Electro-Mechanical Systems (MEMS) resonators. The "word lines" are analogous to drive/sense electrodes, and the "charge storage regions" are replaced by the resonating silicon beam. The silicon oxide (532) and selectively-placed silicon nitride (534) layers form a composite dielectric spacer that precisely defines the capacitive gap between the resonator and the electrodes. The air gap (844) is essential for allowing the beam to vibrate freely. The nitride protects the electrodes during the final hydrofluoric acid (HF) vapor release etch, which removes a sacrificial silicon dioxide layer to free the resonating beam.
  • Mermaid.js Diagram:

    graph TD
        A[Define MEMS Resonator Body & Electrodes] --> B[Deposit Conformal Oxide Layer];
        B --> C[Deposit & Pattern Sacrificial Layer];
        C --> D[Deposit Nitride on Electrode Sidewalls];
        D --> E[Remove Sacrificial Layer];
        E --> F[Vapor HF Release Etch];
        F --> G[Freestanding Resonator with Protected Electrodes];
    

• 3.2. Implantable Biomedical Sensors

  • Enabling Description: The structure is used to create a highly-isolated, multi-electrode neural probe. Each "word line" is a separate sensing electrode (e.g., platinum or iridium oxide), and the "memory cell" region is the insulating substrate. The silicon oxide (532) provides primary biocompatible insulation. The silicon nitride (534) is selectively applied to the upper portions of the electrode shanks, away from the active sensing tips, to provide robust protection against the corrosive saline environment of the body and prevent delamination during insertion. The air gap (844) minimizes capacitive cross-talk between adjacent electrode channels, improving the signal-to-noise ratio of recorded neural signals.
  • Mermaid.js Diagram:

    graph LR
        A(Substrate) --> B(Electrode Array);
        B --> C(Encapsulate in SiO2);
        C --> D(Protect Tips with Sacrificial Layer);
        D --> E(Deposit SiN on Shanks);
        E --> F(Remove Sacrificial Layer);
        F --> G{Implantable Probe};
        G -- Prevents --> H(Crosstalk);
        G -- Prevents --> I(Corrosion);
    

• 3.3. Advanced Photovoltaic Cell Manufacturing

  • Enabling Description: The method is applied to create high-efficiency, interdigitated back-contact (IBC) solar cells. The "word lines" and "memory cells" are analogous to the alternating n-type and p-type doped silicon regions on the back of the cell. After etching trenches to define these regions, a passivation layer of silicon oxide (532) is applied. A sacrificial layer is used to mask the p-type regions while a silicon nitride layer (534), which has excellent anti-reflective and surface passivation properties, is selectively deposited on the n-type regions. The air gap (844) between regions reduces surface recombination velocity and optical losses, thereby increasing the cell's overall efficiency.
  • Mermaid.js Diagram:

    graph TD
        A[Define N-type/P-type regions on Si wafer] --> B[Etch Trenches for Isolation];
        B --> C[Deposit Passivating SiO2 Layer];
        C --> D[Apply and Pattern Sacrificial Layer];
        D --> E[Selectively Deposit SiN on N-type Regions];
        E --> F[Remove Sacrificial Layer];
        F --> G[Deposit Metal Contacts];
        G --> H[Finished IBC Solar Cell];
    

4. Integration with Emerging Tech

• 4.1. AI-Optimized Etch and Deposition Process

  • Enabling Description: The fabrication process is integrated with a machine learning (ML) control system. In-situ metrology tools (e.g., ellipsometry, optical emission spectroscopy) monitor the thickness and composition of the oxide (532), sacrificial (1002), and nitride (534) layers in real-time. The ML model, trained on previous fabrication runs, dynamically adjusts process parameters such as gas flow rates, plasma power, and etch time to compensate for minor variations in chamber conditions or wafer properties. This ensures the height of the etched-back sacrificial layer and the thickness of the nitride sidewall are controlled with nanometer precision, maximizing device yield and performance consistency across the wafer.
  • Mermaid.js Diagram:

    sequenceDiagram
        participant Wafer
        participant ProcessChamber
        participant InSituSensors
        participant ML_Control_System
    
        loop Etch/Deposition Cycle
            ProcessChamber->>Wafer: Apply Process Gas/Plasma
            Wafer-->>InSituSensors: Provide Real-time Data (e.g., film thickness)
            InSituSensors->>ML_Control_System: Send Data
            ML_Control_System->>ML_Control_System: Analyze Data vs. Target
            ML_Control_System->>ProcessChamber: Adjust Parameters (e.g., time, power)
        end
    

• 4.2. IoT-Enabled Lifetime Monitoring

  • Enabling Description: The memory array incorporates embedded canary memory cells and wear-out sensors. These sensors are fabricated using the same oxide/nitride sidewall process but are designed to be more sensitive to charge trapping and breakdown. An on-chip IoT module periodically reads the threshold voltage shift and leakage current of these canary cells. This data is wirelessly transmitted to a central monitoring system, which uses predictive analytics to estimate the remaining useful life (RUL) of the memory device and schedule proactive data migration before a critical failure occurs. The selective nitride placement ensures the canary cells accurately reflect the degradation of the main array's charge storage regions, which are not covered by nitride.
  • Mermaid.js Diagram:

    graph TD
        subgraph MemoryDie
            A[Main Memory Array]
            B[Canary Cells (Sensitive)]
            C[IoT Readout & Tx Module]
        end
        A --- B
        B -- Vth, I_leak --> C
        C -- RUL Data --> D((Wireless Network))
        D --> E[Cloud Analytics Platform]
        E --> F[Predictive Maintenance Alert]
    

• 4.3. Blockchain-Verified Fabrication Ledger

  • Enabling Description: A secure, immutable record of the memory device's fabrication is created using blockchain technology. Critical process parameters from the AI-optimized control system (see 4.1), such as etch depth, layer thickness, and material batch numbers, are cryptographically hashed and recorded as transactions on a private blockchain. This creates a "digital twin" or "device passport" for each wafer. The selective application of the nitride layer is a key verifiable step. This allows for end-to-end traceability, guaranteeing the provenance and quality of memory devices used in high-security applications (e.g., military, aerospace), and preventing counterfeiting.
  • Mermaid.js Diagram:

    graph LR
        A[Fab Tool] -- Process Data --> B(On-Premise Server);
        B -- Hash Data --> C(Create Transaction);
        C -- Send to --> D(Blockchain Network);
        D -- Validate & Add --> E(Immutable Ledger);
        E -- Query via Device ID --> F(Retrieve Fab History);
    

5. The "Inverse" or Failure Mode

• 5.1. Programmable-Life Memory Device

  • Enabling Description: The silicon oxide layer (532) adjacent to the charge storage region (522) is intentionally fabricated with a controlled density of defects or is replaced by a material with a lower dielectric strength, such as a biodegradable polymer or a porous low-k dielectric. The silicon nitride layer (534) on the word line remains robust. This creates a device with a predictable wear-out mechanism. After a predetermined number of program/erase cycles, charge leakage through the weakened dielectric (region 532a) accelerates, rendering the memory cells unusable. This provides a built-in "end-of-life" for applications requiring secure data erasure or planned obsolescence. The lifetime is tuned by controlling the defect density or material properties of the lower sidewall dielectric.
  • Mermaid.js Diagram:

    stateDiagram-v2
        [*] --> Active
        Active --> Degraded: N P/E Cycles
        Degraded --> Failed: M P/E Cycles
        state Active {
            description Low charge leakage through engineered weak dielectric
        }
        state Degraded {
            description Increased bit error rate as charge leakage accelerates
        }
        state Failed {
            description Data retention time < operating time; device is unusable
        }
    

• 5.2. Fused-Link Anti-Tamper Memory

  • Enabling Description: The air gaps (844) between word lines are replaced with a conductive, low-melting-point material, such as a chalcogenide glass or a specific metal alloy, which is kept isolated by the thin silicon oxide layer (532a). The word lines are protected by the more robust silicon nitride (534). If an unauthorized attempt is made to physically probe or reverse-engineer the device, an on-chip sensor detects the intrusion and applies a high voltage pulse to a set of word lines. This pulse causes the low-melting-point material to flow or filament, creating a permanent short circuit between adjacent word lines and physically destroying the data in that section of the array. The nitride protects the word lines from the heat/current, ensuring the shorting action is confined to the data storage region.
  • Mermaid.js Diagram:

    sequenceDiagram
        participant Tamper_Sensor
        participant Voltage_Generator
        participant Word_Line
        participant Fusible_Material
    
        Tamper_Sensor->>Voltage_Generator: Detect Tamper Event
        activate Voltage_Generator
        Voltage_Generator->>Word_Line: Apply High Voltage Pulse
        activate Word_Line
        Word_Line->>Fusible_Material: Heat Transfer & Dielectric Breakdown
        activate Fusible_Material
        Fusible_Material->>Fusible_Material: Melts and Shorts Adjacent Lines
        deactivate Fusible_Material
        deactivate Word_Line
        deactivate Voltage_Generator
    

Combination Prior Art Scenarios

• 1. Combination with RISC-V Open-Source ISA:
  • Description: A system-on-chip (SoC) is designed using the open-source RISC-V instruction set architecture (ISA). This SoC integrates a non-volatile memory block fabricated using the method of claim 15. The memory controller, also designed with RISC-V principles, is specifically optimized to manage the unique wear and performance characteristics of the air-gap and selective-nitride memory cells. This combination provides a fully open-standard processing and storage solution, where the physical layout (per the patent) is tailored to the logical architecture (RISC-V), enhancing performance for edge computing devices where both power efficiency and data integrity are critical.
• 2. Combination with ONFI (Open NAND Flash Interface) Standard:
  • Description: The memory device described in claim 8 is packaged as a standard NAND flash chip. The chip's command and data interface is designed to be fully compliant with the Open NAND Flash Interface (ONFI) 5.0 specification. This allows the device, with its unique internal oxide/nitride/air-gap structure, to be used as a drop-in replacement for conventional NAND flash in any standard system, such as Solid-State Drives (SSDs). The device would report its characteristics via the ONFI "Read Parameter Page" command, but the underlying physical mechanism for achieving its high breakdown voltage and improved cell current would be derived from the '314 patent's teachings.
• 3. Combination with Universal Flash Storage (UFS) Protocol:
  • Description: A storage device, such as an embedded multimedia card (eMMC) or a removable memory card, is constructed using a memory array as described in the patent. The device's controller and physical interface adhere to the JEDEC Universal Flash Storage (UFS) standard. The UFS protocol's advanced features, such as command queuing and full-duplex operation, are leveraged to maximize the performance benefits gained from the enhanced cell current of the selectively-passivated memory cells. The combination of the UFS protocol's efficiency with the improved physical characteristics of the memory cells results in a storage device with higher sustained read/write speeds and lower latency compared to a UFS device using conventional flash memory.