US 9281314B1

A non-volatile storage device with an oxide/nitride sidewall is disclosed in U.S. Patent No. 9,281,314 B1. The patent, assigned to Palisade Technologies LLP, aims to improve the performance and reliability of memory devices by using a specific fabrication method.

Patent Details:

• Title: Non-volatile storage having oxide/nitride sidewall
• Assignee: Palisade Technologies LLP
• Inventors: Takashi Kashimura, Xiaolong Hu, Sayako Nagamine, Yusuke Yoshida, Hiroaki Iuchi, Akira Nakada, Kazutaka Yoshizawa
• Filing Date: October 10, 2014
• Issue Date: March 8, 2016
• Abstract: The patent describes non-volatile storage devices and methods for their fabrication. Sidewalls of memory cells and their associated word lines are covered with silicon oxide. A layer of silicon nitride is then applied over the silicon oxide adjacent to the word lines, which helps protect the word lines during the manufacturing process. Crucially, this silicon nitride layer does not cover the silicon oxide that is adjacent to the charge storage regions of the memory cells. This is intended to prevent performance degradation that can occur from charges becoming trapped in the silicon nitride near the charge storage area. One method to achieve this selective placement of silicon nitride involves using a sacrificial material.

Plain-Language Summary of Independent Claims:

This patent has three independent claims, which define the core of the invention.

Claim 1: This claim describes a method for making a memory device. The process involves creating lines of memory cells, where each cell has a region to store charge and a control gate. Word lines are then formed on top of these control gates. The key steps are:

1. Covering the sides of both the memory cells' charge storage regions and the word lines with an oxide layer.
2. Adding a nitride layer that only sits next to the oxide on the word lines, but not on the oxide next to the charge storage regions. This selective placement is the central innovation.

Claim 8: This claim details the structure of the memory device itself. It describes a device with:

1. Lines of memory cells, each containing a charge storage region and a control gate.
2. Word lines connected to the control gates.
3. An oxide layer covering the sides of both the charge storage regions and the word lines.
4. A nitride layer that only covers the oxide on the sides of the word lines.
5. A different type of electrical insulation, which is not silicon nitride, placed next to the oxide that covers the sides of the charge storage regions.

Claim 15: This claim outlines a more specific manufacturing process for a memory array. This method includes:

1. Creating stacks of memory cells, with each stack including memory cells and a tungsten word line.
2. Coating the sides of these stacks with silicon oxide.
3. Depositing a temporary "sacrificial" material between the stacks. This material is etched back so that it covers the lower part of the stacks (the memory cells) but leaves the upper part (the word lines) exposed.
4. Adding a silicon nitride layer to the exposed parts, which are the sidewalls of the silicon oxide next to the word lines.
5. Removing the sacrificial material, which leaves behind the silicon oxide on the memory cell stacks and the silicon nitride on the oxide next to the word lines.
6. Finally, creating air gaps between the memory cell stacks to provide electrical isolation.