US 8775857

I'll verify the patent details and check for any litigation/docket activity before summarizing.

Search results for US 8,775,857

Important caveat on scope: I searched for authoritative records on this specific number. I did not find any USPTO litigation/assignment records beyond what Google Patents surfaces, and I found no CAFC 2026 docket, appeal, IPR/PGR, or district-court case naming US 8,775,857. Given the strict rule about not fabricating, I am flagging that this reflects the absence of a hit in my searches, not affirmative proof that no such proceeding exists. Google Patents and Justia pages for the patent show no litigation section.

Also note a date inconsistency in the request: the prompt states "Current Date: April 26, 2026," while the authoritative fetched patent page is timestamped 2026-09-28. I used the supplied patent text as ground truth and treated the 2026 docket check as "as of the search date."

Bibliographic data (from the authoritative patent text)

Source: https://patents.google.com/patent/US8775857/en ; https://patents.justia.com/patent/[8775857](/patent/8775857)

Abstract (verbatim)

"A controller includes a clock control unit configured to provide a first output to test circuitry and a bypass unit configured to provide a second output to a further controller. The controller is configured to cause the bypass unit to output the second output and to optionally cause the clock control unit to output the first output."

Note: the issued abstract and issued claims diverge from the as-published pre-grant abstract/claims. The published application (US 2012/0166860 A1) claimed the "first output / second output" formulation; the issued claim 1 was materially rewritten to recite an input sequential selection signal, a clock bit unit, and a bypass unit responsive to that input. This is a meaningful prosecution-history point (see caveat below).

Plain-language overview of the independent claims (as issued)

Claim 1 — a controller (the basic building block).
A controller for a clock domain has four cooperating parts:

1. an input that receives an input sequential selection signal from a previous controller in a chain (a handshake/"you may proceed" token);
2. a clock bit unit that generates clock bit signals specifying which clock pulses to generate;
3. a clock control unit that takes those clock bit signals and produces a pulsed output containing exactly the specified clock pulses (this is the at-speed capture clock fed to test circuitry); and
4. a bypass unit that produces an output sequential selection signal destined for a further controller, where that output is generated in response to the received input sequential selection signal.

The novelty hook is the bypass path: the handshake can be forwarded onward without waiting for the internal shift-register "bubble" to propagate through the clock control unit — i.e., a controller that doesn't need to pulse can be skipped quickly.

Claim 12 — a chain of N controllers (N ≥ 2).
Same controller architecture as claim 1, but expressed as a chain. Each controller receives an input sequential selection signal from the previous controller, has a clock bit unit and a clock control unit producing a pulsed output, and a bypass unit that provides the output sequential selection signal to the next controller after the pulsed output is generated, in response to the received input sequential selection signal. This captures the sequential/one-domain-at-a-time capture scheme.

Claim 16 — a circuit testing unit (system-level claim).
A system comprising a control unit, at least one oscillator (e.g., PLL), and a chain of N ≥ 2 controllers. Each controller has:

• an input receiving the input sequential selection signal from the previous controller, a clock input, and a scan enable signal indicating multiple modes of operation;
• a control bit unit indicating which clock pulses to generate;
• a clock control unit that (a) in a first mode generates a pulsed output whose pulse widths equal the frequency of the clock input (at-speed capture pulses), and (b) in a second mode generates a controller output comprising the clock signal (shift mode);
• a bypass unit providing the output sequential selection signal to the next controller after generation of its pulsed output; and
• each subsequent controller receives, as an input, the output sequential selection signal from the bypass unit of the previous controller.

Dependent claims of note: claim 19 (depends on claim 1) recites that the clock control unit blocks pulsing of the pulsed output in response to the received input sequential selection signal; claim 20 (depends on 16) adds test circuitry associated with each of the N controllers; claims 17–18 add ATPG-sequence reception and an on-chip implementation.

Technical context (from the specification, for grounding)

The problem addressed: in multi-clock-domain ATPG, independent PLL-clocked OCCs pulse asynchronously, causing unpredictable peak/average power, IR-drop, and unreliable power estimation. The disclosed solution chains clock controllers so only one domain is active at a time, and adds a dynamic bypass so controllers not needed by a given test pattern are skipped (the spec states this roughly halves handshake propagation, from ~6 cycles to ~3 per bypassed controller). The bypass unit 510 is built from a NOR gate receiving the two chain-bit flip-flop outputs plus scan enable, feeding NAND gates together with the stability-unit output and shift-register output, then a synchronizing flip-flop 516 (Fig. 7; ¶¶0051, 0061).

Prior art cited on the face of the patent

• US 7,058,868 B2 — Broadcom, "Scan testing mode control of gated clock signals for memory devices"
• US 2005/0225361 A1 and US 7,245,168 B2 — Young-Chul Rhee / Samsung, "Clock selection circuit and digital processing system for reducing glitches"
• US 2010/0198991 A1 — Yokogawa Electric, "Duplexed field controller"

Notable later family members (continuations/follow-ons, same assignee)

US 8,917,123 B2; US 9,234,938 B2; US 9,264,049 B2 ("Synchronous on-chip clock controllers"); US 9,891,279 B2 ("Managing IR drop") — indicating an active STMicroelectronics OCC/DFT portfolio around this disclosure.

Uncertainties and items you should verify at the source

1. No CAFC 2026 docket found for 8,775,857. If your assignment requires a definitive docket negative, this should be confirmed on the CAFC CM/ECF and PACER/RECAP systems directly; my search did not surface any appeal or district-court case.
2. Prosecution-history divergence: the granted claim 1 is narrower than the published claim 1 (added "input sequential selection signal" and "clock bit unit" limitations). If claim scope/validity is at issue, pull the USPTO file wrapper (PatentCenter) for US 13/152,013 — I did not retrieve it.
3. Assignee chain: Google Patents lists original assignee STMicroelectronics Pvt. Ltd. and current assignee STMicroelectronics International N.V.; the 2014-03-31 reassignment record is consistent with this, but current ownership/inventor assignment should be confirmed via the USPTO Assignment database.
4. Approximate valuation figures appearing on third-party sites (e.g., patentleaderboard.com lists ~$2,866,000) are algorithmic estimates, not authoritative, and I would not rely on them.
5. I did not locate any ITC proceeding or reexamination/IPR regarding this patent in the searches performed.

Primary authoritative source used throughout: https://patents.google.com/patent/US8775857/en (full text, claims, and legal events supplied in the prompt).

I'll research litigation involving US patent 8775857 across patent litigation databases and court sources.

Let me search more specific litigation sources.

Let me search dedicated litigation databases directly.

Litigation Search Results for U.S. Patent No. 8,775,857

Finding: No litigation involving U.S. Patent No. 8,775,857 was identified in the sources searched.

What I searched

• General web/patent litigation queries ("8775857 litigation," "8,775,857 patent infringement case")
• Unified Patents litigation portal, RPX Insight, Docket Alarm, CourtListener/RECAP, and PTAB-related filings
• Litigation naming the patent owner/assignee (STMicroelectronics) or its title ("Sequential on-chip clock controller with dynamic bypass for multi-clock domain testing")

Results

No district court case (D. Del., E.D. Tex., W.D. Tex., N.D. Cal., or elsewhere), ITC Section 337 investigation, PTAB/IPR proceeding, or CAFC appeal asserting or challenging U.S. Patent No. 8,775,857 was found.

Two items surfaced that are not this patent and should not be conflated:

• A search snippet referencing "the '857 patent" in an AlmondNet litigation document — a different patent (the snippet provides no confirmation that it is 8,775,857, and the surrounding context concerns AlmondNet's ad-targeting portfolio).
• The Google Patents page for US8775857B2, which is the patent document itself, not a litigation record.

Context on the patent

• Patent: U.S. 8,775,857 B2 — "Sequential on-chip clock controller with dynamic bypass for multi-clock domain testing"
• Inventors: Shray Khullar; Swapnil Bahl
• Original assignee: STMicroelectronics Pvt. Ltd. → reassigned to STMicroelectronics International N.V. (2014)
• Priority: 2010-12-28 (Indian App. No. 3130/DEL/2010); filed 2011-06-02; granted 2014-07-08
• Status: Active; adjusted expiration 2032-03-15

This is a design-for-test (DFT)/ATPG clock-controller patent held by an operating semiconductor company. Its citation trail shows it is cited by later patents (e.g., LSI/Avago "Dynamic clock domain bypass for scan chains," Qualcomm, GlobalFoundries) rather than being asserted in litigation. Consistent with that, no infringement suits, IPRs, or other contested proceedings naming this patent were located.

Caveats

• Absence of evidence in the sources searched is not conclusive proof that no litigation exists. Litigation databases vary in completeness, and older or sealed matters may not be indexed.
• I did not have direct, confirmed access to the Unified Patents case list or PACER docket queries for this specific number within the tool limits, so this finding rests on the general patent-litigation sources above.
• If a definitive negative is required, the authoritative check is a PACER/RECAP docket search and the USPTO Patent Assignment/PTAB records for the "8,775,857" number and its family.

Bottom line: Based on the available information, there is no known litigation involving U.S. Patent No. 8,775,857.

I'll verify the structured data against live sources before reporting.

Proceedings overview

Zero AIA trial proceedings on file. The structured PTAB data block for US 8,775,857 states that the USPTO Open Data Portal returns no AIA trial proceedings — no IPR, no PGR, no CBM — as of the most recent ingest. My independent searching (Google Patents, Justia, FreePatentsOnline, PTAB-related mirrors, CourtListener-indexed material) surfaced no petition, institution decision, Final Written Decision, or Federal Circuit appeal naming U.S. Patent No. 8,775,857 (application 13/152,013, "Sequential on-chip clock controller with dynamic bypass for multi-clock domain testing," STMicroelectronics International N.V.).

Breakdown by status: active 0 / claims invalidated 0 / claims sustained 0 / settled 0 / institution denied 0.

Bottom-line defensive posture: this is an untested patent. There is no PTAB record to attack or rely on, no estoppel, and no claim-cancellation to point a defendant at. But the absence also means the patent has never been hardened (or narrowed) by an adverse PTAB ruling, and — conversely — no petitioner has yet been estopped, so the full § 102/§ 103 prior-art space remains open to the first challenger (subject to the § 315(b) clock below). Practically: the claims stand exactly as issued, all 20 of them.

Caution — do not confuse the shorthand "'877 patent." Searches for "877 patent" + PTAB return heavy, real activity on U.S. Patent No. 10,250,877 (InterDigital Madison Patent Holdings) in Amazon-filed IPRs, and on 6,534,805 C1 (IPR2020-01491, Qualcomm/AMD/STMicroelectronics v. Monterey Research). Neither is US 8,775,857. I confirmed those hits concern different patents, different owners, and different technology. Any docket citing "the '877 patent" in an InterDigital/Amazon or Monterey Research context is not this patent.

Proceedings

There is no proceeding number to report, and I will not invent one. No entry follows because the canonical list is empty.

Closest-item disambiguation (verified, not proceedings against this patent):

• IPR2021-00776 — Advanced Micro Devices, Inc. v. Monterey Research, LLC, FWD 2022-03-04, addressed U.S. Patent No. 6,534,805 C1, not 8,775,857. STMicroelectronics appears there only as a joined petitioner against Monterey Research. No relation to the patent at issue here.
• Forward-citation documents in the '857 record — US 2015/0002190 A1 (Tabula) and US 9,740,234 B1 (Qualcomm, "On-chip clock controller") — are citations, not PTAB filings.
• The forward-citing STMicroelectronics siblings US 8,917,123, US 9,264,049, US 9,234,938, and US 9,891,279 belong to the same OCC/ATPG technology family and cite this patent; I found no PTAB proceedings on them in this search either, but that is a separate question and I did not verify it exhaustively.

Strategic summary

Claim status. All claims 1–20 of US 8,775,857 are UNTESTED and intact — nothing canceled, nothing confirmed, nothing disclaimed. There is no certificate of correction, ex parte reexamination, or statutory disclaimer visible in the record I reviewed. The claim set breaks down as: independent claim 1 (controller: input for sequential selection signal, clock bit unit, clock control unit generating a pulsed output, bypass unit generating an output sequential selection signal); independent claim 12 (chain of N controllers); independent claim 16 (circuit testing unit with control unit, oscillator, chain of N controllers, control bit unit, clock control unit, bypass unit); and dependents 2–11, 13–15, 17–20. The narrowest useful reading for an accused infringer is that every independent claim requires both a clock/control-bit-driven pulsed output and a bypass unit emitting an output sequential selection signal to a downstream controller.

Estoppel landscape. Because no IPR/PGR was ever instituted, § 315(e)(2) estoppel is nonexistent — no party is barred from raising any ground in district court or the ITC. For a defendant being asserted against today: the entire prior-art field is available, unconstrained by § 325(d) estoppel-by-argument except as to art the examiner actually considered. The three prosecution-cited references — US 7,058,868 B2 (Broadcom, scan testing mode control of gated clock signals), US 2005/0225361 A1 / US 7,245,168 B2 (Samsung, clock selection with glitch reduction), and US 2010/0198991 A1 (Yokogawa, duplexed field controller) — are the obvious starting art, but re-running those exact references against the same claims invites a § 325(d) discretionary denial, so a first IPR should be built on different art or on materially new combinations.

Critical timing gate — § 315(b). A petition for IPR/PGR must be filed within one year of service of a complaint alleging infringement of this patent. If an accused infringer has already been served more than 12 months ago, that party is time-barred from the PTAB entirely and its only invalidity route is the district court/ITC. If service is recent, the clock is running and an IPR decision should be made early, not at expert-discovery time.

Pattern signals. No repeat-petitioner pattern (no petitioner at all). No PTAB appeal activity by the patent owner — none could exist. No defensive aggregator (e.g., Unified Patents) appears anywhere in the chain; the only assignee history is STMicroelectronics Pvt. Ltd. (2011-06-02) → STMicroelectronics International N.V. (2014-03-31). The patent is held by a large operating company, not a monetization entity, which is the most plausible explanation for the absence of IPRs: operating-company patents in a niche internal-DFT space are typically asserted only in cross-licensing negotiations or against direct competitors, and rarely draw unified-fee challenges.

Maintenance-fee risk to watch. Per the legal-events record: 4th-year fee paid 2017-12-26, 8th-year fee paid 2021-12-16, and a maintenance-fee reminder mailed 2026-02-23 for the 12th-year window. The 12-year fee comes due on/around 2026-07-08 (6-month grace through roughly 2027-01-08 with surcharge). A lapse there would moot the patent entirely — worth checking the current fee status on USPTO Patent Center before spending on invalidity work.

Recommended next steps

1. No PTAB activity exists on this patent. Say it plainly in any litigation-hold or opinion memo: there is no FWD to cite, no cancelation to rely on, and no institution decision to distinguish. Any memo citing "the '877 IPR" is almost certainly citing US 10,250,877 (InterDigital) or 6,534,805 — verify the patent number character-for-character before relying on it.
2. Check the § 315(b) date first. If your client was served with an infringement complaint more than one year ago, IPR/PGR is unavailable and you are litigating validity in court only. If not, calendar the one-year bar date immediately.
3. If you need a PTAB vehicle, docket a petition on new art not previously before the examiner — the three prosecution-cited references (US 7,058,868; US 7,245,168 / US 2005/0225361; US 2010/0198991) are the ones the examiner of record had, so build on art emphasizing the bypass unit / output sequential selection signal limitations of claims 1, 12, and 16 rather than re-running the examiner's art. Expect the trial-stage timeline to be: petition → institution decision by ~6 months → FWD within 1 year of institution (§ 316(a)(11)).
4. Verify the fee status. Confirm the 12th-year maintenance fee (reminder mailed 2026-02-23) has been paid on USPTO Patent Center. Historically, patents that go unchallenged at the PTAB and are near end-of-term sometimes lapse for non-payment — that outcome is cheaper for your client than any IPR. Link: https://patentcenter.uspto.gov and the patent page https://patents.google.com/patent/[US8775857B2](/patent/US8775857B2)/en.
5. Monitor, don't assume. The absence of PTAB activity is a signal of a quiet patent, not a weak one. A well-asserted or NPE-acquired version of this patent could attract an IPR at any time; set a periodic watch on PTAB E2E (https://ptacts.uspto.gov) for new filings naming U.S. Patent No. 8,775,857.

Confidence note: I have high confidence that no AIA trial proceeding against US 8,775,857 appears in the ODP structured data or in publicly indexed PTAB/CAFC material as of 2026-09-28. I have lower confidence in the negative as to unindexed, very recently filed petitions, and I could not verify the maintenance-fee payment status directly — both should be re-checked at the primary source.

I'll verify the assignment record details and cross-reference the assignees and correspondents.

Let me cross-check the 2016 reassignment signal and try to surface the correspondent of record.

Assignment & Ownership Reconstruction — U.S. Patent No. 8,775,857 B2

Source note: The reel/frame data below is taken from the legal-events record on the authoritative Google Patents full text (fetched 2026-09-28), which mirrors the USPTO Assignment Center records. I was unable within tool limits to retrieve the underlying USPTO assignment PDFs for reels 026380/0143 and 032560/0734, so the correspondent-of-record fields are not available to me and are reported as such rather than guessed. Verify at USPTO Assignment Center (legacy search at assignment.uspto.gov).

Inventors

• Both inventors executed the original assignment between 2011-05-29 and 2011-05-30, i.e. 2–4 days before the 2011-06-02 U.S. filing date (assignment text: "SIGNING DATES FROM 20110529 TO 20110530"). This is the ordinary corporate employee-invention pattern — rights were papered at the moment of filing, which is consistent with a captive R&D-portfolio practice, not a later buy-out.
• The work was done at STMicroelectronics Pvt. Ltd., Plot 1, Knowledge Park III, Greater Noida, UP, India — ST's principal non-European design centre (ST's Greater Noida site is certified to ISO 45001:2018 for "Design & Development of Semiconductor Products, Solutions and IT Applications," audit dated 2025-10-09, certificate cycle running to 2028-12-11 — ST/Bureau Veritas certificate).
• No unusual departure pattern is observable. Assignment records do not disclose inventor-side subsequent transfers, and there is no evidence in the record of either inventor departing the assignee inside 12 months of filing. I cannot confirm or refute departures from public data — treat this as "no signal," not "cleared."

Original assignee

Two different things must be kept separate, and the patent text itself creates the ambiguity:

• First-recorded assignee of the inventors' rights (reel 026380/0143, recorded 2011-06-02): STMicroelectronics Pvt. Ltd., India.
• Assignee named on the issued patent / current owner: STMicroelectronics International N.V. This is because the intra-group transfer (reel 032560/0734) was recorded 2014-03-31, roughly three months before grant on 2014-07-08, so the printed patent and Google's "Original Assignee" header both read STMicroelectronics International NV.

⚠️ Literal-record flag: The authoritative page states "Original Assignee: STMicroelectronics International NV." Read literally against the assignment history, that is the assignee at issue, not the assignee that first took the inventors' rights. The assignment record, not the front-page field, is the reliable source here.

Entity profile:

• STMicroelectronics International N.V. — Netherlands-incorporated ST group entity (Amsterdam registry), acting through a Swiss branch at Plan-les-Ouates, Geneva. Its status as ST's IP-holding/contracting vehicle is independently corroborated by a 2014 in-license/assignment agreement in which "STMicroelectronics International NV, société de droit néerlandais agissant … par le biais de sa branche suisse dont le siège social est situé à Plan-les-Ouates, Genève" takes rights from Grenoble INP and CNRS (legacy USPTO assignment reel 033380/0349). It is not a licensing-only shell; it is a wholly-owned financing/IP conduit of a public operating company.
• STMicroelectronics N.V. (the parent) is a publicly traded semiconductor manufacturer (NYSE: STM; Euronext Paris), ~$6.9B revenue in 2015, "more than 100,000 customers" — an operating company. Its products are system-on-chip devices whose scan/ATPG test architecture embodies the claimed on-chip clock controller; the claims are embodied in ST silicon rather than sold as a standalone product.
• Status: operating, solvent, not acquired, not in bankruptcy. ST India leadership transitioned in 2025 (Anand Kumar succeeded Vivek Sharma as India MD, Greater Noida HQ), indicating ongoing India operations — the opposite of a wind-down.

Assignment timeline

Two recorded assignments. No security agreements, licenses, releases, corrections, mergers, or change-of-name records appear.

2011-05-30 (executed; signing window 2011-05-29→05-30) / recorded 2011-06-02 — Reel 026380/0143

• Conveyance: Assignment
• Assignor: Shray Khullar; Swapnil Bahl (individual inventors)
• Assignee: STMicroelectronics Pvt. Ltd. (India)
• Correspondent: Not available in the retrieved record. I could not pull the reel 026380/0143 image within tool limits; do not treat the correspondent as absent — treat it as unretrieved. No recurrence flag can be made for this link.
• Context: Standard corporate employee-invention assignment executed at filing — the ordinary capture of employee IP by the operating employer.

2014-03-31 (executed/effective) / recorded 2014-03-31 — Reel 032560/0734

• Conveyance: Assignment
• Assignor: STMicroelectronics Pvt. Ltd.
• Assignee: STMicroelectronics International N.V. (Netherlands)
• Correspondent: Not available in the retrieved record. One contemporaneous, unrelated data point: an ST-side recording into the same N.V. entity four months later (reel 033380/0349, recorded 2014-07-22) carried correspondent Joanne M. Murphy, signature "/Joanne Murphy/". I cannot attribute that correspondent to reel 032560/0734, and I am not doing so — it is offered only as an indication of ST's mid-2014 recording practice. Absent the reel image, no repeat-correspondent finding is made.
• Context: Intra-group reorganization / IP consolidation, not a divestiture. Assignor and assignee are both ST group entities; consideration was internal ("ASSIGNMENT OF INTEREST;ASSIGNOR: STMICROELECTRONICS PVT. LTD."). The recorded transfer sits inside a broader ST pattern — third-party portfolio tables list many ST patents (from STMicroelectronics S.A., S.r.l., Inc., R&D Co. Ltd. Beijing, Russet SAS, Design and Application s.r.o.) with a 2016 reassignment year and no U.S. litigation, consistent with multi-year consolidation of group patents into the N.V. holding entity (KIPO portfolio table). I flag this as corroborating context only — US 8,775,857 itself has no 2016 record.

Post-issuance fee record (not assignments, but relevant to status):

• 2014-06-18 — Patent grant
• 2017-12-26 — 4th-year maintenance fee paid (large entity)
• 2021-12-16 — 8th-year maintenance fee paid (large entity)
• 2026-02-23 — Maintenance fee reminder mailed

⚠️ Status caveat: the 11.5-year fee falls due around early 2026 and the last event of record is the reminder, with no payment event yet indexed as of the 2026-09-28 fetch. Google shows the patent "Active" with adjusted expiration 2032-03-15 (20 years from filing plus term adjustment), but that reflects the statutory ceiling, not proof the fee was paid. Confirm the 12th-year payment before relying on enforceability through 2032.

No post-issuance assignment exists beyond the 2014 intra-group re-record. That is itself a finding: the patent has stayed inside the ST corporate family since 2011.

Timeline diagram

timeline
    title Ownership of US 8775857
    2010 : Priority application filed in India
    2011 : US application 13 152 013 filed
         : Inventors assign to STMicroelectronics Pvt Ltd
    2014 : Rights moved to STMicroelectronics International NV
         : Patent granted 8 July
    2017 : Fourth year maintenance fee paid
    2021 : Eighth year maintenance fee paid
    2026 : Maintenance fee reminder mailed

NPE / troll-pattern signals

Weak/additional observations (not scored as signals):

• IP-holding-entity consolidation — moving patents out of the Indian operating subsidiary into a Netherlands holding entity (reel 032560/0734) is a tax/treasury and portfolio-administration structure, common to large European chipmakers, not an NPE tell. Scored as neutral.
• No encumbrance of record — no security agreements, no recorded licenses/releases. Clean title in the ST family.

Verdict

Insufficient data (with an explicit negative finding on NPE status)

The prescribed taxonomy has no bucket for "operating company retained captive ownership and never asserted," which is precisely what the record shows: the chain runs inventors → STMicroelectronics Pvt. Ltd. (reel 026380/0143, recorded 2011-06-02) → STMicroelectronics International N.V. (reel 032560/0734, 2014-03-31), both ST group entities. The "Operating-company assertion" label is unavailable because its second prong — suit against actual competitors — is not met (no litigation found), and "Defensive / non-asserting" is unavailable because the chain does not terminate at RPX/AST/Unified. Substantively, every NPE signal I could test is "not present," and the one untestable signal (correspondent recurrence) is untestable purely because I could not retrieve the reel images. If forced into an NPE verdict, the answer is a firm no NPE indicators; the label "Insufficient data" reflects a taxonomy gap plus the two retrieval gaps flagged above (correspondent fields; 12th-year fee payment), not any suggestion of concealment in the chain.

Two items to close out for a definitive record: (1) pull the reel 026380/0143 and 032560/0734 images to capture the correspondent of record; (2) confirm the 11.5-year maintenance fee was paid after the 2026-02-23 reminder, since no payment event is yet of record.

Verify at: https://assignmentcenter.uspto.gov/ (search patent number 8775857) · https://assignment.uspto.gov/patent/index.html

I'll research the patent's cited prior art references and verify details across USPTO and other sources.

Prior-Art Analysis — U.S. Patent No. 8,775,857 B2

0. Patent identified (confirmation before analysis)

Before analyzing art, I confirm the record matches the number requested so that no similar-number contamination occurs:

Sources used. Google Patents (patents.google.com/patent/US8775857B2/en), Justia Patents (patents.justia.com/patent/8775857), FreePatentsOnline, Patents-Review, and Espacenet. These mirror and are derived from the USPTO bibliographic/citation record. I did not obtain a direct, live response from USPTO PatentCenter or the USPTO "Patent Public Search" (PatFT/AppFT) API within the tool limits, so the citation list below is the USPTO-sourced citation list as reproduced by those mirrors. If a definitive primary-source check is required, the USPTO Patent Public Search record for 8,775,857 and the file wrapper (IFW) "References Cited" should be pulled directly.

Note on the citation count. The record retrieved lists the citation block inconsistently: a "Citations (3)" block and a "Patent Citations (4)" block. The four entries are:

1. US 7,058,868 B2
2. US 2005/0225361 A1
3. US 7,245,168 B2
4. US 2010/0198991 A1

Entries 2 and 3 are the same family (US 2005/0225361 A1 is the pre-grant publication of US 7,245,168 B2). So the examiner effectively relied on three distinct prior-art families, not four. This is flagged rather than auto-corrected, per the operating rule.

1. Legal framework applied

U.S. 8,775,857 has a priority date of 2010-12-28, i.e. before the AIA first-inventor-to-file provisions took effect (2013-03-16). Pre-AIA 35 U.S.C. § 102 therefore governs.

• § 102(a): patented or described in a printed publication (US or foreign) before the applicant's date of invention.
• § 102(b): patented or described in a printed publication (US or foreign) more than one year before the U.S. filing date. Measured from the U.S. filing date of 2011-06-02, the § 102(b) bar date is 2010-06-02.
• § 102(e): described in a U.S. patent granted on an application filed before the applicant's invention, or in a U.S. application publication with an earlier effective filing date.
• Anticipation standard: a single reference must disclose every element of the claim, arranged as claimed (§ 102); missing any element defeats anticipation (that gap is instead an obviousness/§ 103 question).

A pre-AIA foreign priority date may be used to antedate § 102(a)/(e) art, but the § 102(b) one-year grace runs from the U.S. filing date unless the priority is perfected under § 119. I apply the 2010-06-02 § 102(b) bar date below, while noting the 2010-12-28 invention date for § 102(a)/(e).

2. The cited references at a glance

3. Reference-by-reference analysis

R1 — US 7,058,868 B2 (Guettaf / Broadcom)

Brief description. Discloses an integrated circuit having a "scan testing clock control circuit" (a latch plus two AND gates) and a "memory bypass enable" contact point. A scan-test-mode input and a memory-bypass-enable input determine whether a clock signal is allowed to reach a memory device during scan testing. In one mode the memory is prevented from receiving a clock; in another mode its clocking is controlled so memory contents change predictably. The design is asserted not to add timing delay to the normal clock path. See esp. claim 1 (IC with scan testing clock control circuit + memory bypass enable contact point) and claims 2–4 (latch + first/second AND gate structure).

Mapping to 8,775,857 claims.

• Potentially relevant to the generic concept of gating/withholding a clock under test control (analogous to the "clock control unit … pulsed output" of claim 1 and to the mode-select behavior recited in claim 16).
• Missing for claim 1: no "input … receive an input sequential selection signal from a previous controller"; no "clock bit unit generating clock bit signals specifying clock pulses"; no "bypass unit … provide an output sequential selection signal for application to a further controller." The "memory bypass enable" of R1 is a static external contact point, not a sequential-selection handshake passed controller-to-controller.
• Missing for claim 12/16: no chain of N controllers, no oscillator/control-unit combination as claimed, no sequential selection signal propagation.

§ 102 anticipation: No claim is anticipated. R1 has no multi-controller sequential-selection chain and no bypass unit forwarding a handshake to a next controller. It is usable only as § 103 background art for "clock gating in test mode."

R2 / R3 — US 2005/0225361 A1 and US 7,245,168 B2 (Rhee / Samsung) — one family

Brief description. A clock-selection circuit that selects between a first and second clock signal while reducing glitches. It has a first and second control circuit, first and second disable-signal generating circuits implemented as series-connected flip-flops clocked by the delayed clock signal, and a logic circuit (NAND) producing the output clock. A control signal (BYPASS) selects which clock is output; the enable/disable handshakes are synchronized to their respective clocks to avoid glitches. Key structure at claim 1: first/second control circuits generating clock control signals, first/second disable-signal generating circuits that delay the other control signal for a specified number of cycles of the delayed clock, and a logic gate combining the gated clocks.

Mapping to 8,775,857 claims.

• R2/R3 is the closest of the cited art on two specific structural themes: (a) glitch-free clock handover across clock domains using series flip-flops (analogous to the "stability unit" of claims 5–8 and the synchronous handover described in the 8,775,857 specification), and (b) a logic-gate network that gates/selects clock signals under control inputs.
• Missing for claim 1: no previous/further-controller "sequential selection signal"; no "clock bit unit generating clock bit signals specifying clock pulses." R2/R3 selects between two clock sources; it does not select or pulse a controller within a chain.
• Missing for claim 5–8: R2/R3's series flip-flops delay a clock-control signal for a fixed cycle count; they do not constitute a "first stability unit configured to receive [sequential selection information]" combined with a "second stability unit configured to receive scan enable information" fed into a "clock gating unit." The elements overlap in function but not in claimed arrangement.
• Missing for claim 12/16: no chain of controllers; no ATPG/scan-enable multi-mode controller output.

§ 102 anticipation: No claim is anticipated. R2 and R3 are § 103 candidate art, and R3 is redundant with R2 (same disclosure), so citing both adds no independent prior-art weight.

R4 — US 2010/0198991 A1 (Yokogawa) [granted US 8,060,769 B2]

Brief description. A duplexed (redundant) industrial field controller for a distributed control system. Two control units (CPU 2A/2B) alternate control authority; each has an "application clock." An update control unit bypasses the first update of the second application clock after control authority switches, if the first application clock is ahead of the second, so that the handover is smooth. Field: process control/network timing, not semiconductor test.

Mapping to 8,775,857 claims.

• The only linguistic overlap is the word "bypass" and the notion of a unit handing timing authority from one block to another.
• Missing for every claim: no scan enable, no clock bit unit/clock bit signals, no on-chip clock controller, no ATPG, no chain of N clock controllers, no "sequential selection signal," no pulsed capture clock. The "bypass" in R4 bypasses a clock update event in a redundant controller — an entirely different mechanism (no forwarding of a handshake signal to a successor controller).

§ 102 anticipation: No claim is anticipated. This is marginal art, likely cited to show the abstract idea of bypassing a clock/timing update on a handover; it does not disclose the claimed apparatus.

4. Anticipation matrix (§ 102)

Bottom line: none of the four cited references anticipates any claim of US 8,775,857 under § 102. Each lacks at least the distinctive core: a clock bit unit specifying clock pulses, a bypass unit that forwards an output sequential selection signal to a further controller, arranged in a chain of N sequential controllers. Anticipation fails on the "all elements in a single reference" requirement for every independent claim (1, 12, 16).

5. What the art is useful for (§ 103, and completeness)

• Best § 103 combination candidate: R1 (test-mode clock gating) in view of R2/R3 (glitch-free clock selection with synchronized series-flip-flop enable/disable handshakes). Even combined, they still do not teach or suggest forwarding a sequential selection handshake that dynamically bypasses an unused controller in a scan-capture chain — the point of the 8,775,857 dynamic-bypass feature — so a prima facie § 103 case would be difficult on this record.
• R4 contributes essentially nothing technical to the claimed subject matter.

6. Caveats and cross-references

• Consistency with the earlier "Litigation summary": No contradiction found. That section reported no litigation; this prior-art section independently confirms the examiner-cited art is ordinary DFT/clocking art. Nothing here implies any assertion activity.
• Later "Cited By" documents are not prior art to 8,775,857 in the normal sense. One deserves a caveat: US 2015/0002190 A1 (Tabula, Inc.) carries a priority date of 2010-04-02, which precedes the 2010-12-28 priority of 8,775,857, even though it appears in the "Cited By" list. If a challenger wanted to reach back further, that document (and its issued counterpart US 9,362,909 B2, Altera) should be checked on its own merits. It concerns reconfiguration power, so it is unlikely to be materially relevant, but the date overlap is flagged rather than ignored.
• Other potentially relevant non-cited art (outside the "citation" set the task asked me to enumerate) includes US 2011/0276849 A1 ("System, circuit, and device for asynchronously scan capturing multi-clock domains") and the same-inventor sibling patents US 8,381,051 / US 8,527,824 ("Testing of multi-clock domains"). These are noted for completeness; they were not among the four examiner citations analyzed above.
• Primary-source verification: the citation list here is the USPTO-sourced list as mirrored by Google Patents/Justia/FPO. Direct USPTO PatentCenter/IFW confirmation of the "References Cited" list was not performed within tool limits; dates and bibliographic data for R1–R4 were cross-checked against multiple sources and are internally consistent.

Final answer to the task

For US 8,775,857, the four listed citations collapse to three distinct prior-art families (R1 Guettaf/Broadcom; R2–R3 Rhee/Samsung; R4 Yokogawa). Under pre-AIA § 102:

• R1 (US 7,058,868 B2) — § 102(b) art; relevant to test-mode clock gating; anticipates none of claims 1, 5–20.
• R2 (US 2005/0225361 A1) / R3 (US 7,245,168 B2) — § 102(b) art (same family); relevant to glitch-free clock selection and synchronized enable handshakes; anticipate none of claims 1, 5–20.
• R4 (US 2010/0198991 A1 / US 8,060,769 B2) — § 102(a)/(e) art; relevant only to the abstract idea of bypassing a clock/timing update across redundant controllers; anticipates none of claims 1, 5–20.

No cited reference discloses the claimed combination of a clock bit unit, a pulsed-output clock control unit, and a bypass unit forwarding an output sequential selection signal to a further controller in a chain of N controllers. The cited art is, at most, § 103 background material.

I'll research the prior-art references listed on the patent page to ground the obviousness analysis.

Let me research the remaining cited references and the sequential clock controller context.

Let me search for prior art on sequential/chained on-chip clock controllers with handshake signals and bypass in chains.

Obviousness Analysis — U.S. Patent No. 8,775,857 B2

Under 35 U.S.C. § 103 (pre-AIA, KSR framework)

Note on governing law: The application was filed 2011‑06‑02 and claims priority to IN 3130/DEL/2010 (2010‑12‑28), i.e., before the March 16, 2013 AIA first‑to‑file cutoff. Pre‑AIA § 103(a) governs, and KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007) supplies the "expansive and flexible" obviousness standard.

Note on sources: This analysis is built from the prior‑art references listed in the Prior Art / Citations sections of the Google Patents page for US8775857 (https://patents.google.com/patent/US8775857/en): the four examiner‑cited references (US7058868B2; US20050225361A1; US7245168B2; US20100198991A1), plus the forward‑citation and "similar documents" listings used only for context (and flagged where they are not prior art). Where I could not verify a reference's full text, I say so.

1. The Patent's Claimed Subject Matter (what must be met)

The invention is an on‑chip clock controller (OCC) for multi‑clock‑domain at‑speed scan testing that adds a dynamic bypass so that a "sequential selection" handshake can skip controllers whose logic is not pulsed in a given ATPG pattern. The key independent claims:

• Claim 1 (controller): (a) an input receiving an input sequential selection signal from a previous controller; (b) a clock bit unit generating clock bit signals specifying clock pulses to generate; (c) a clock control unit receiving the clock bits and responsively generating a pulsed output comprising those pulses; and (d) a bypass unit providing an output sequential selection signal for a further controller, generated in response to the received input sequential selection signal.
• Claim 12 (chain of N controllers, N ≥ 2): same building blocks, with the bypass unit providing the output sequential selection signal after the pulsed output is generated, in response to the received input sequential selection signal.
• Claim 16 (circuit testing unit): control unit + oscillator + chain of N controllers, each having an input, a clock input, and a scan enable indicating multiple modes; a control bit unit; a clock control unit that (i) in a first mode generates pulses whose widths equal the frequency of the clock input and (ii) in a second mode generates a controller output comprising the clock signal; and a bypass unit providing the output sequential selection signal to a further controller after generation of the pulsed output.

Dependent claims add, inter alia: scan‑enable/clock‑enable control (cl. 2, 13), bypass fed from the clock control unit/previous controller/control unit (cl. 3–4), first/second stability units implemented as shift registers clocked at the controller operating frequency (cl. 5–7), a clock gating unit combining stability‑unit outputs (cl. 8), capture‑clock‑to‑logic‑block (cl. 9), sequential‑selection information as the output (cl. 10), output at operating frequency (cl. 11), bypassing a not‑required controller (cl. 14–15), and ATPG/on‑chip testing (cl. 17–20).

Person of ordinary skill in the art (POSITA): a BS in EE/computer engineering plus ~2–3 years in design‑for‑test (DFT)/ATPG and digital IC clock‑control design, familiar with scan‑enable‑based clock gating, OCC/PLL clock switching, and multi‑clock test.

2. The Relevant Prior Art on the Page

2.1 US7058868B2 — Guettaf (Broadcom), "Scan testing mode control of gated clock signals for memory devices"

• https://patents.google.com/patent/[US7058868](/patent/US7058868)
• Discloses an integrated circuit with a "scan testing clock control circuit" and a "memory bypass enable" input, in which the control circuit controls whether/how a clock pulse reaches a block (memory) during scan testing, gated by a scan enable (SE) and a bypass enable. Implementation is a latch + two AND gates; the bypass enable and scan‑test‑mode input determine whether the clock propagates; a multiplexer selects the scan‑test clock vs. the normal clock.
• Maps to: claim 1 element (b)/(c) (clock‑gating control of pulses responsive to scan‑enable/mode control), and the concept of a "bypass enable" that selectively disables pulsing of a block for a given test condition; claim 16's "first mode/second mode" clock selection (shift clock vs. capture clock).

2.2 US20050225361A1 / US7245168B2 — Rhee (Samsung), "Clock selection circuit … for reducing glitches"

• https://patents.justia.com/patent/[7245168](/patent/7245168)
• Discloses a clock selection circuit that selects one of first/second clocks as CLKOUT in response to a control/BYPASS signal, using first/second control circuits, disable‑signal generating circuits built from pluralities of series‑connected flip‑flops (delay chains), and a NAND logic gate, to effect a glitch‑free handover between clock domains.
• Maps to: claim 1 element (d)'s selection/hand‑over logic responding to a control input; dependent claims 5–7's stability units as shift registers (series flip‑flop delay elements clocked by the domain clock); and the specification's repeated emphasis on "glitch‑free implementation across clock domains."

2.3 US20100198991A1 — Yokogawa Electric, "Duplexed field controller"

• https://patents.google.com/patent/US20100198991
• Discloses first and second control units between which control authority is switchable, and an "update control unit" that bypasses an update of a second unit's clock/timing after a handoff, conditioned on the relative state of the two units; the reference/timer clock is transferred from the active unit to the standby unit, which then advances based on the transferred signal.
• Maps to: the abstract functional concept of a "bypass" of a unit's normal processing and a signal handed from one controller to the next, with the bypass decision made in response to a signal/state rather than by waiting for full processing. (Different field — industrial process control — so this is the weakest of the four for a § 103 combination; see § 5.)

2.4 Forward citations / similar documents (context only — NOT prior art to '857)

• US8812921B2 (LSI/Avago), "Dynamic clock domain bypass for scan chains," priority 2011‑10‑25 — post‑dates '857 and is a forward citation; it independently describes bypassing scan sub‑chains of inactive clock domains to cut test time and power (https://patents.google.com/patent/[US8812921](/patent/US8812921)). Not prior art, but evidence of the trajectory of the field.
• US2016/0349318A1, "Dynamic Clock Chain Bypass" (https://patents.justia.com/patent/20160349318) — a later filing describing an apparatus strikingly close to '857's claims (bypass flip‑flop + bypass multiplexer in a clock scan chain). Not prior art (2016), but notable as an independent later arrival at the same architecture.
• US9740234B1 (Qualcomm), "On‑chip clock controller" — priority 2016‑03‑31; not prior art.
• US20150002190A1 (Tabula), priority 2010‑04‑02 — predates '857 but concerns FPGA reconfiguration power, remote from OCC handshaking; not useful.
• EPO search report for a related European filing (EP 12 18 8947) lists, as category "A" background: EP 1 826 579 A1 (Syntest), US 2004/098687 A1 (Guettaf et al.), US 2010/188096 A1 (Waayers et al.), and Hetherington et al., "Logic BIST for Large Industrial Designs" (ITC 1999). I flag that I could not verify that EP 12 18 8947 is the same family, and these are category "A" (mere background) citations.

3. Proposed § 103 Combinations

Ground 1 — Claim 1 (and 2–4, 9–11) obvious over Guettaf (US7058868) in view of Rhee (US7245168 / US20050225361)

• Guettaf supplies a scan‑testing clock control circuit that receives a scan‑enable and a bypass‑enable and selects/gates clock pulses to a block, i.e., elements (b)/(c) and the mode‑selective clock output of claim 16. Guettaf's "memory bypass enable" establishes that bypass‑by‑control‑signal to selectively prevent a block being clocked was a known scan‑test technique.
• Rhee supplies the BYPASS‑controlled selection of one clock over another and, critically, the flip‑flop delay‑chain mechanism for glitch‑free handover between clock domains — the functional equivalent of the claimed bypass unit's controlled crossing between the input and output sequential selection signals, and of the stability units (shift‑register delay chains) of claims 5–7.
• Motivation / reasonable expectation: Both references are in the same field (scan/at‑speed testing and clock gating in digital processing systems). A POSITA seeking to (i) stop pulsing a domain not used by a test pattern (Guettaf) and (ii) guarantee a glitch‑free crossover of a control/handshake signal between asynchronous domains (Rhee) would predictably combine a clock‑control unit driven by clock bits with a control‑signal‑driven bypass/selection stage. KSR permits combining known elements for their known functions with predictable results.

Ground 2 — Claims 12 & 16 (the chain / testing‑unit claims) obvious over the sequential‑OCC chain (as described in '857's own FIG. 4–5 background) in view of Guettaf and Rhee

• The '857 specification itself describes, as the pre‑existing arrangement, a chain of sequential on‑chip clock controllers 306a…306n in which each controller receives a "sequential selection signal" from the previous controller and passes it to the next ("handshake"), with the bubble propagating through the shift registers (see "FIG. 4 shows a chain of sequential clock controllers … as used in some embodiments"). If treated as applicant‑admitted prior art / background, this discloses the input‑from‑previous‑controller / output‑to‑further‑controller handshake architecture of claims 1 and 12 and the "chain of N controllers" of claims 12/16.
• Against that baseline, the only added matter is the bypass unit that forwards the sequential selection signal directly (skipping the controller's shift‑register propagation) when the controller is not needed. Guettaf's bypass‑enable (skip clocking a block under a control condition) and Rhee's control‑driven, glitch‑free selection logic supply exactly that teaching applied to a chain element.
• Motivation: The specification itself states the problem expressly — unnecessary controllers in the chain "add to the scan test time," create "capture delays," and risk later controllers "not having been pulsed before the end of the capture mode"; and longer chains worsen peak power/IR‑drop. Bypassing unused chain elements to shorten a serial handshake is a routine, well‑understood optimization (cf. scan‑chain and JTAG bypass registers, and later LSI US8812921's "dynamic clock domain bypass"). The result (shorter capture, fewer pulses) is a predictable improvement of the same device, which is the classic KSR "obvious to try / design incentive" scenario.

Ground 3 — Claim 1 obvious over Yokogawa (US20100198991) in view of Guettaf

• Yokogawa discloses a "bypass" that skips a unit's normal update and hands the timing signal from one controller to the next, with the bypass decision responsive to a signal/state. Guettaf supplies the scan‑testing clock‑control context and clock bit/mode control.
• Motivation: The shared abstract problem — availing a following controller without waiting for full processing by the previous one — and the common use of bypass logic around a serial stage would suggest the substitution. (This ground is the weakest: Yokogawa is industrial process control, and a POSITA could argue non‑analogous art; see § 5.)

4. Dependent‑Claim Mapping (where each reference lands)

5. Weaknesses, Gaps, and Counter‑Arguments (why a § 103 challenge is not airtight)

1. No single cited reference teaches the chain with a "sequential selection" handshake between OCCs. The four examiner‑cited references are about (a) memory clock gating in scan (Guettaf), (b) glitch‑free clock multiplexing (Rhee), and (c) industrial duplexed control (Yokogawa). None shows a daisy‑chained, handshake‑propagated OCC. The "chain" concept appears in '857 only as background ("as used in some embodiments") — a soft admission that an accused infringer/defendant would need to shore up with independent prior art (e.g., Beck et al., DATE 2005; Furukawa et al., ITC 2006; Fan et al., ATS 2007 — the classic on‑chip‑clock‑control literature, which I saw cited in the related LSI patents but which is not on the '857 page).
2. The limiting amendment. Claim 1's language — the bypass unit generates the output sequential selection signal "in response to the received input sequential selection signal" — reads as an added limitation (compare the original Summary, which recites only "a bypass unit configured to provide a second output"). The examiner evidently found this responsive‑handshake feature absent from the art, so any § 103 ground must squarely teach a bypass path whose output is triggered by the incoming sequential selection signal, not merely a bypass that disables a clock.
3. The bypass unit's specific logic (FIG. 7: NOR 510 / NAND 512 / NAND 514 / FF 516, combining chain bits, scan enable, stability‑unit output, and the last shift‑register output) is quite specific and would need to be met element‑by‑element for a strong invalidity case; a POSITA could contest that Guettaf/Rhee render that exact feedback network obvious.
4. Claim 16's "pulse widths equal to a frequency of the clock input" is an awkwardly phrased limitation; construing it, and finding art that meets it, is non‑trivial.
5. Secondary considerations (Graham factors): I found no litigation/PTAB record for '857 (consistent with the earlier litigation section), so there is no adjudicated commercial‑success/industry‑praise evidence to weigh. The dense forward‑citation trail (10 citing families, including LSI/Avago, Qualcomm, GlobalFoundries) shows the concept was widely adopted afterward — which cuts both ways: it can support non‑obviousness/pioneering status, but the independent later arrivals at the same "dynamic clock chain bypass" architecture (LSI US8812921; the 2016 "Dynamic Clock Chain Bypass" application) also suggest the solution was within the ordinary skill level once the problem was recognized.
6. Analogous‑art risk: Yokogawa (process control) is the most vulnerable to a non‑analogous‑art attack; the Ground‑3 combination should be treated as a secondary/backup theory only.

6. Conclusion

• Defensible § 103 grounds exist for independent claims 1, 12, and 16 by combining the scan‑testing clock‑gating + bypass‑enable teaching of Guettaf (US7058868B2) with the control‑signal‑driven, glitch‑free clock selection/delay‑chain teaching of Rhee (US7245168B2 / US20050225361A1), and by treating the sequential‑OCC handshake chain (described as background in '857's own FIG. 4–5) as the starting point, with Yokogawa (US20100198991A1) as a supplementary teaching of "bypass a unit and hand the signal onward."
• Motivations to combine are strong and rooted in the patent's own stated problems: reduce scan‑capture test time, ensure later controllers are reached before capture ends, and lower peak/average test power and IR‑drop — all classic "improve a known device in a predictable way" rationales under KSR.
• The strongest non‑obviousness bulwark is the specific handshake‑responsive bypass unit (bypass triggered by the incoming sequential selection signal, with the specific FIG. 7 gating logic), which the four cited references do not clearly disclose. A rigorous invalidity position would therefore need additional prior art (the DATS/ITC/ATS on‑chip‑clock‑control literature, or a reference showing bypass‑by‑handshake in a serial controller chain) beyond what appears on the '857 Google Patents page.

Caveat: I did not have full‑text access to every reference, and I could not confirm the prosecution‑history amendments against the file wrapper. This is a technical obviousness assessment, not a legal opinion; a definitive § 103 conclusion should be validated against the complete file history and a full‑text prior‑art search.