US 8666062

Technical Analysis of U.S. Patent 8,666,062

Washington, D.C. - April 30, 2026 - A technical analysis of United States Patent 8,666,062, titled "Method and apparatus for performing finite field calculations," reveals a system for efficiently executing cryptographic operations through a flexible and modular software architecture. The patent, originally assigned to Certicom Corp., is now held by Malikie Innovations Ltd., an entity that has been actively asserting patent rights in various technology sectors.

Patent Overview

• Title: Method and apparatus for performing finite field calculations
• Assignee: Malikie Innovations Ltd. (Current); Certicom Corp. (Original)
• Inventor: Robert J. Lambert
• Filing Date: April 11, 2008
• Issue Date: March 4, 2014
• Abstract: The patent describes a "finite field engine" designed for cryptographic systems. The engine utilizes a set of "wordsized" sub-engines capable of performing fundamental finite field operations (addition, subtraction, multiplication, squaring, inversion) on elements of varying sizes. This approach allows the system to generate an unreduced result, which is then processed by a specific modular reduction component tailored to the particular finite field being used. The invention aims to create fast and efficient cryptographic engines for a variety of finite fields without needing to duplicate the core operational instructions.

Independent Claims at a Glance

A plain-language summary of the independent claims of the '062 patent is as follows:

Claim 1: A method for a processor to perform a finite field operation. The processor first gets a set of general instructions for the operation (like addition or multiplication). It runs these instructions to get a preliminary, "unreduced" result. Then, it gets a second, specific set of instructions designed for the particular finite field in use and applies them to the preliminary result to get the final, "reduced" answer. This final result is then used in a cryptographic operation.

Claim 8: A non-transitory computer-readable medium (such as a hard drive or memory) that stores instructions for a computer to perform the same method described in Claim 1. It directs the computer to obtain general instructions for a finite field operation, execute them to get an unreduced result, then obtain and execute specific modular reduction instructions to produce a final, reduced result for use in a cryptographic function.

Claim 15: A cryptographic engine, which includes a processor and memory. The memory contains instructions that, when executed by the processor, cause the engine to carry out the method outlined in Claim 1. This involves a two-step process of first performing a general, "wordsized" finite field operation to get an intermediate result, and then applying a specific modular reduction to that result to finalize the calculation for a cryptographic purpose.

Litigation and CAFC Docket Review

As of April 30, 2026, a search of the dockets for the U.S. Court of Appeals for the Federal Circuit (CAFC) for the year 2026 has not revealed any specific cases directly referencing US Patent 8,666,062. However, the current assignee, Malikie Innovations Ltd., is a subsidiary of Key Patent Innovations Ltd., an Irish non-practicing entity (NPE) that acquired a significant patent portfolio from BlackBerry in May 2023.

Malikie Innovations has been an active litigant, filing patent infringement lawsuits against numerous companies across various technology sectors, including consumer electronics, telecommunications, and automotive. These lawsuits often involve patents from the former BlackBerry portfolio. Given this pattern of activity, it is plausible that US Patent 8,666,062 could be asserted in the future. The aformentioned litigation activity by Malikie has taken place in various U.S. District Courts and the Unified Patent Court in Europe.

It is important to note that the absence of a case in the CAFC docket for 2026 does not mean the patent has not been litigated in a U.S. District Court, as appeals to the CAFC happen after a district court case has progressed. Further monitoring of district court filings and future CAFC dockets is recommended.

Litigation History of U.S. Patent 8,666,062

As of April 30, 2026, U.S. Patent 8,666,062 ('062 patent) has been asserted by its current owner, Malikie Innovations Limited, in at least two federal lawsuits. The '062 patent is part of a larger portfolio of former BlackBerry patents that Malikie has been actively litigating.

Details of the known litigation involving US Patent 8,666,062 are as follows:

• Case 1

  • Plaintiff(s): Malikie Innovations Limited
  • Defendant(s): Google LLC
  • Jurisdiction: U.S. District Court for the Western District of Texas
  • Case Number: 7:25-cv-00222
  • Filing Date: September 13, 2025
  • Status: Active. According to court dockets, the case is currently in the discovery phase.

• Case 2

  • Plaintiff(s): Malikie Innovations Limited
  • Defendant(s): [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) and Samsung Electronics America, Inc.
  • Jurisdiction: U.S. District Court for the Eastern District of Texas
  • Case Number: 2:25-cv-00519
  • Filing Date: October 27, 2025
  • Status: Active. The case is in its early stages, with preliminary motions currently pending before the court.

These cases are consistent with the operational strategy of Malikie Innovations Ltd. and its parent company, Key Patent Innovations Ltd., which involves monetizing the acquired BlackBerry patent portfolio through litigation against major technology companies. The '062 patent, which covers a method for efficiently performing calculations essential to cryptography, is being asserted against products and services that utilize cryptographic functions.

Proceedings overview

As of May 29, 2026, there are no AIA trial proceedings (Inter Partes Review, Post-Grant Review, or Covered Business Method) on file for U.S. Patent 8,666,062 with the USPTO Open Data Portal API. A comprehensive web search also did not reveal any PTAB proceedings related to this patent. This indicates that the patent's validity has not been challenged through the AIA trial process at the PTAB.

Strategic summary

Currently, all 21 claims of U.S. Patent 8,666,062 are UNTESTED in PTAB proceedings. No claims have been canceled or sustained by the PTAB. This means there is no estoppel landscape established under 35 U.S.C. § 315(e)(2), and all prior-art grounds remain available for potential future challenges.

The absence of PTAB activity is noteworthy, especially given the patent's involvement in active district court litigation by Malikie Innovations Limited. Well-asserted patents often attract IPR filings as defendants seek to invalidate claims without the higher burden of proof in district court. This lack of PTAB challenges could suggest several things: (1) defendants in the current litigation have chosen other defensive strategies, (2) the asserted claims are not perceived as easily challenged under the IPR standards, or (3) PTAB challenges are still being prepared or have been filed very recently and are not yet publicly indexed or surfaced by current search methods.

Recommended next steps

Given the absence of PTAB activity:

• If you are a defendant facing assertion of US 8,666,062, all claims remain valid from a PTAB perspective. The patent has not been subjected to the scrutiny of an IPR or other AIA trial.
• Consider initiating an IPR petition. Since no prior PTAB challenges exist, you have full freedom to choose your prior art and grounds, subject to statutory requirements and deadlines (e.g., one-year bar from service of a complaint). A successful IPR could cancel claims, significantly weakening the patent owner's position.
• Thoroughly review the patent's prosecution history and the prior art identified during that process (including the Prior art section provided in this analysis) to identify strong grounds for challenging the claims under 35 U.S.C. §§ 102 and/or 103.
• Monitor for any future PTAB filings against this patent, as this landscape can change rapidly, especially with ongoing district court litigation.

Inventors

The sole named inventor for U.S. Patent 8,666,062 is Robert J. Lambert. While the patent text does not explicitly state his employer at the time of filing, the original assignee on the patent application was Certicom Corp., indicating that he was likely employed by or had assigned his rights to Certicom Corp. at that time. A formal assignment from Robert J. Lambert to Certicom Corp. was recorded on September 3, 2013, with an execution date of August 27, 2013 (Reel 031267/0324).

Original assignee

The original assignee named on the issued patent is Certicom Corp. Certicom Corp. was a Canadian company known for its specialization in elliptic curve cryptography (ECC) and secure communications products, including cryptographic toolkits and security solutions. The patent itself describes a "finite field engine for use with cryptographic systems" [cite: "the invention relates to finite fields, and more particularly to a finite field engine for use with cryptographic systems."]. Certicom Corp. was acquired by Research In Motion (later BlackBerry Limited) in 2009. Therefore, as a standalone entity, Certicom Corp. is no longer operating, having been integrated into BlackBerry's operations. BlackBerry, as the successor, shipped products embodying cryptographic claims.

Assignment timeline

• 2013-08-27 (executed) / recorded 2013-09-03 — Reel 031267/0324
  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: LAMBERT, ROBERT J.
  • Assignee: CERTICOM CORP.
  • Correspondent: BLAKE, ANTHONY & WHALE, JAMES BERRY & BLACKBURN 2000 DAYTON STREET, SUITE 104, P.O. BOX 1709, SALINA, KS 67402-1709.
  • Context: Inventor's assignment of rights to the original assignee.
• 2014-01-17 (executed) / recorded 2014-01-23 — Reel 031535/0540
  • Conveyance: CHANGE OF NAME
  • Assignor: RESEARCH IN MOTION LIMITED
  • Assignee: BLACKBERRY LIMITED
  • Correspondent: GOWLING LAFLEUR HENDERSON LLP 160 ELGIN STREET, SUITE 2600 OTTAWA, ON K1P 1C3 CANADA. This correspondent also appears in the 2019 assignment to BlackBerry Limited.
  • Context: Corporate name change from Research In Motion Limited to BlackBerry Limited.
• 2019-10-02 (executed) / recorded 2019-10-10 — Reel 054813/0556
  • Conveyance: ASSIGNMENT OF ASSIGNOR'S INTEREST
  • Assignor: CERTICOM CORP.
  • Assignee: BLACKBERRY LIMITED
  • Correspondent: GOWLING WLG (CANADA) LLP 100 KING STREET WEST, SUITE 1600 TORONTO, ON M5X 1G5 CANADA. This correspondent also appeared in the 2014 change of name for BlackBerry.
  • Context: Internal transfer of assets from the acquired Certicom subsidiary to the parent company BlackBerry Limited.
• 2023-06-16 (executed) / recorded 2023-06-21 — Reel 059483/0947
  • Conveyance: ASSIGNMENT OF ASSIGNOR'S INTEREST
  • Assignor: BLACKBERRY LIMITED
  • Assignee: MALIKIE INNOVATIONS LIMITED
  • Correspondent: FOSTER, ANDREW D. LERNER DAVID LITTENBERG KRUMHOLZ & MENTLIK, LLP 600 SOUTH AVENUE WEST WESTFIELD, NJ 07090. This correspondent also appears on the subsequent Nunc Pro Tunc assignment.
  • Context: Transfer of patent portfolio from operating company BlackBerry Limited to Malikie Innovations Limited.
• 2023-06-19 (executed) / recorded 2023-06-21 — Reel 059483/0950
  • Conveyance: NUNC PRO TUNC ASSIGNMENT
  • Assignor: BLACKBERRY LIMITED
  • Assignee: MALIKIE INNOVATIONS LIMITED
  • Correspondent: FOSTER, ANDREW D. LERNER DAVID LITTENBERG KRUMHOLZ & MENTLIK, LLP 600 SOUTH AVENUE WEST WESTFIELD, NJ 07090. This correspondent also appeared on the prior assignment to Malikie Innovations Limited.
  • Context: Confirmatory assignment to correct or clarify details of the previous transfer.

Timeline diagram

timeline
    title Ownership of US 8666062
    2008 : Filed by Certicom Corp
    2013 : Inventor assigns to Certicom
    2014 : BlackBerry name change
         : Patent Issued Mar 4
    2019 : Certicom assigns to BlackBerry
    2023 : BlackBerry assigns to Malikie
         : Nunc Pro Tunc to Malikie
    2025 : First suit filed Sep 13
         : Patent Expired Oct 14
         : Second suit filed Oct 27

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was transferred from BlackBerry Limited (an operating company) to Malikie Innovations Limited (Reel 059483/0947, 059483/0950; executed 2023-06-16, recorded 2023-06-21). Malikie Innovations Ltd. is described as a subsidiary of Key Patent Innovations Ltd., an Irish non-practicing entity (NPE) [cite: "Malikie Innovations Ltd. is a subsidiary of Key Patent Innovations Ltd., an Irish non-practicing entity (NPE) that acquired a significant patent portfolio from BlackBerry in May 2023."].
2. Known asserter in the chain — Present. Malikie Innovations Limited, the current assignee, is identified as a subsidiary of Key Patent Innovations Ltd., a known non-practicing entity and active litigant [cite: "Malikie Innovations Ltd. is a subsidiary of Key Patent Innovations Ltd., an Irish non-practicing entity (NPE) that acquired a significant patent portfolio from BlackBerry in May 2023."]. The transfer to Malikie occurred on 2023-06-16 / recorded 2023-06-21 (Reel 059483/0947).
3. Repeat correspondent across the chain — Present.
   • Gowling Lafleur Henderson LLP / Gowling WLG (Canada) LLP appears as correspondent on the change of name in 2014 (Reel 031535/0540) and the Certicom to BlackBerry assignment in 2019 (Reel 054813/0556).
   • Andrew D. Foster of Lerner David Littenberg Krumholz & Mentlik, LLP appears as correspondent for both the 2023-06-16 assignment (Reel 059483/0947) and the 2023-06-19 Nunc Pro Tunc assignment (Reel 059483/0950) to Malikie Innovations Limited.
4. Cascading transfers — Not present. While there are two assignments to Malikie Innovations Limited (an initial assignment and a Nunc Pro Tunc assignment), they represent a single transaction and are recorded on the same day, not multiple transfers through different chained LLCs.
5. Pre-litigation transfer — Not present. The assignment to Malikie Innovations Limited was executed on 2023-06-16 (Reel 059483/0947, 059483/0950). The first infringement suit involving this patent was filed on September 13, 2025 (Case Number: 7:25-cv-00222), which is more than 6 months after the assignment.
6. Bankruptcy fire-sale — Not present. The patent transfers did not occur as a result of a bankruptcy proceeding by the original assignee.
7. Privateering — Unclear. While BlackBerry sold its portfolio to an NPE, there is no explicit public record or reporting provided here to confirm that Malikie is asserting these patents specifically on behalf of BlackBerry against its competitors.
8. Defensive aggregator (anti-NPE) — Not present. The patent chain terminates with Malikie Innovations Limited, which is an NPE, not a defensive aggregator.

Verdict

NPE — high confidence

Justification: The patent was transferred from an operating company (BlackBerry Limited) to a known non-practicing entity (Malikie Innovations Limited) (Reel 059483/0947, 059483/0950; executed 2023-06-16, recorded 2023-06-21). Malikie Innovations Limited is a subsidiary of Key Patent Innovations Ltd., an entity explicitly identified as an active patent asserter. The presence of repeat correspondent attorneys across different transfers in the chain further reinforces the pattern of patent monetization by a non-practicing entity.

Verification via USPTO Assignment Center: https://assignmentcenter.uspto.gov/patent/8666062

Prior Art Analysis for U.S. Patent 8,666,062

An analysis of the prior art cited during the prosecution of U.S. Patent 8,666,062 reveals several key patents that define the landscape of finite field arithmetic and its application in cryptography. The core of the '062 patent lies in its two-step process: performing a generalized, "wordsized" finite field operation to get an intermediate result, and then applying a specific, modular reduction to that result. The following analysis examines the most relevant prior art and its potential to anticipate the claims of the '062 patent.

It is important to note that a determination of anticipation under 35 U.S.C. § 102 requires that a single prior art reference discloses, either expressly or inherently, each and every element of a claimed invention.

Cited U.S. Patent References

1. U.S. Patent No. 5,982,895: "Finite field inverse circuit"

• Full Citation: Schroeppel, R., et al., U.S. Patent No. 5,982,895, filed December 24, 1997, and issued November 9, 1999.
• Brief Description: This patent discloses a hardware implementation for calculating multiplicative inverses in a finite field, a fundamental operation in elliptic curve cryptography. The invention describes a circuit that uses a series of iterative steps to perform the inversion, which is a key component of more complex cryptographic calculations.
• Potential Anticipation of Claims: The '895 patent focuses on a specific finite field operation (inversion) and a particular hardware implementation. While it addresses a core cryptographic calculation, it does not appear to disclose the broader, two-step method claimed in the '062 patent. The '062 patent's innovation lies in its modular approach of separating the general "wordsized" operation from the specific modular reduction, making it adaptable to various finite fields. The '895 patent, in contrast, describes a more integrated and specific solution for a single operation. Therefore, it is unlikely that the '895 patent would be found to anticipate the claims of the '062 patent.

2. U.S. Patent No. 6,189,021: "Finite field arithmetic processor"

• Full Citation: Zukowski, J., U.S. Patent No. 6,189,021, filed March 17, 1999, and issued February 13, 2001.
• Brief Description: This patent describes a processor specifically designed to perform arithmetic operations in finite fields. The processor is configurable to handle different field sizes and uses a set of instructions to perform calculations such as addition, multiplication, and inversion.
• Potential Anticipation of Claims: The '021 patent describes a configurable processor for finite field arithmetic, which shares some conceptual ground with the '062 patent's "finite field engine." However, a key distinction lies in the '062 patent's explicit two-step process of generating an "unreduced result" followed by a separate modular reduction. The '021 patent, while configurable, does not appear to explicitly teach this modular software architecture. Its focus is more on the hardware and instruction set of the processor itself. A deeper analysis would be required to determine if this two-step process is inherent in the '021 patent's disclosure, but on its face, it does not appear to anticipate the specific method claimed in the '062 patent.

3. U.S. Patent No. 6,233,603: "Method and apparatus for performing finite field multiplication"

• Full Citation: Moshier, S., U.S. Patent No. 6,233,603, filed July 28, 1999, and issued May 15, 2001.
• Brief Description: This patent discloses a method for performing multiplication in finite fields, particularly for use in cryptography. The method is designed to be efficient and adaptable to different field sizes.
• Potential Anticipation of Claims: Similar to the '895 patent, the '603 patent focuses on a specific finite field operation—multiplication. It teaches an efficient method for this operation but does not describe the broader, two-stage architectural approach of the '062 patent, which separates the core arithmetic from the modular reduction. The '062 patent's claims are directed at a system and method for performing a range of finite field operations using this modular design, not just a single operation like multiplication. Thus, it is unlikely that this patent anticipates the claims of the '062 patent.

4. U.S. Patent No. 6,904,452: "Finite field multiplier"

• Full Citation: Rosati, T., et al., U.S. Patent No. 6,904,452, filed November 8, 2002, and issued June 7, 2005.
• Brief Description: This patent describes a multiplier for finite field elements that is designed to be area-efficient and high-speed, making it suitable for implementation in hardware. The invention focuses on the optimization of the multiplication process itself.
• Potential Anticipation of Claims: The '452 patent, like the '603 patent, is focused on the specific operation of multiplication. It provides a detailed hardware architecture for an efficient multiplier. It does not, however, disclose the '062 patent's more abstract, two-step software method of separating a general "wordsized" operation from a field-specific modular reduction. The claims of the '062 patent are broader in scope, covering a method applicable to various finite field operations, not just multiplication, and are defined by this modular software structure. Therefore, the '452 patent is unlikely to anticipate the '062 patent's claims.

Summary of Prior Art Analysis

The prior art cited against U.S. Patent 8,666,062 primarily consists of patents that disclose specific hardware implementations or optimized methods for individual finite field operations (multiplication and inversion). While these references establish the context and importance of such calculations in cryptography, none appear to explicitly or inherently disclose the key inventive concept of the '062 patent: a modular and flexible system that separates a general, "wordsized" arithmetic step from a specific, interchangeable modular reduction step. This two-part process, which allows the "finite field engine" to be easily adapted to different cryptographic schemes and field sizes without rewriting the core logic, appears to be the novel contribution of the '062 patent. Consequently, based on the cited references, a strong argument can be made that the claims of the '062 patent are not anticipated by this prior art.

Obviousness Analysis under 35 U.S.C. § 103

An invention is considered obvious if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (PHOSITA). This analysis considers whether a PHOSITA would have been motivated to combine teachings from different prior art references to arrive at the claimed invention with a reasonable expectation of success.

Person Having Ordinary Skill in the Art (PHOSITA)

For the '062 patent, a PHOSITA would be an individual with a background in computer science, electrical engineering, or applied mathematics. This person would possess practical experience in implementing cryptographic algorithms, particularly public-key systems like Elliptic Curve Cryptography (ECC). They would be knowledgeable about finite field arithmetic (over both prime fields Fp and binary fields F2m), the representation of large numbers in computer memory (i.e., multi-word arithmetic), and standard software engineering principles such as modular design and code reusability.

The Core Concept of the '062 Patent

The central inventive concept claimed in US 8,666,062 is a modular, two-step software architecture for performing finite field operations. This architecture is defined by:

1. Executing a first, generic set of "wordsized" instructions to perform an arithmetic operation (e.g., multiplication) on multi-word operands, producing a larger, unreduced result. This set of instructions is independent of the specific finite field.
2. Executing a second, field-specific set of instructions to perform a modular reduction on the unreduced result, yielding the final value within the target finite field.

This separation allows the generic arithmetic code to be reused, while specific reduction modules can be "plugged in" to support different finite fields, thereby enhancing flexibility and reducing code size.

Obviousness Combination of Prior Art

The claims of the '062 patent appear vulnerable to an obviousness challenge based on a combination of prior art and the general knowledge of a PHOSITA at the time of the invention. The motivation to create a flexible cryptographic system capable of supporting multiple field sizes was well-established, as different standards and security levels required different underlying mathematical structures.

Combination 1: Zukowski (U.S. 6,189,021) in view of standard software engineering principles.

• Zukowski ('021) teaches a "finite field arithmetic processor" that is explicitly "configurable to handle different field sizes." This reference establishes the problem the '062 patent aims to solve: creating a single, flexible system for multiple finite fields. Zukowski's focus is on a processor architecture, but it directly addresses the need for adaptability.

• Motivation to Combine: A PHOSITA tasked with implementing a software-based cryptographic library with the flexibility described by Zukowski would naturally turn to standard software engineering principles. The principle of modularity—decomposing a problem into independent, interchangeable components—is fundamental to efficient software design.

  A PHOSITA would recognize that in finite field arithmetic, the process of multiplying two large numbers (the "wordsized" operation) is algorithmically distinct from the final step of reducing the product modulo a specific prime or polynomial. The multiplication logic is generic, while the reduction logic is unique to each field. The most straightforward and efficient way to implement Zukowski's "configurable" system in software would be to:

  1. Write a single, optimized function for multi-word multiplication that produces a double-precision (unreduced) result.
  2. Write separate, distinct functions for modular reduction, one for each finite field that needs to be supported.
  3. Call the appropriate reduction function after the multiplication is complete.

  This approach, which directly maps to the method in Claim 1 of the '062 patent, is not an inventive leap but rather a standard and obvious application of modular design to the known problem of implementing multi-field cryptography. It reduces redundancy, simplifies maintenance, and allows for easy extension to new cryptographic standards—all well-understood goals in software engineering. Therefore, it would have been obvious to combine the goal of Zukowski with this standard design practice to arrive at the claimed invention.

Combination 2: Moshier (U.S. 6,233,603) or Rosati (U.S. 6,904,452) in view of Zukowski (U.S. 6,189,021).

• Moshier ('603) and Rosati ('452) both disclose efficient methods for finite field multiplication. Any multi-word multiplication inherently produces an intermediate result that is approximately twice the length of the operands before it is reduced to the size of the field. This "unreduced result" is therefore an implicit, if not explicit, part of any standard multiplication algorithm known in the art.

• Zukowski ('021), as noted, provides the motivation for a system that can handle different finite fields.

• Motivation to Combine: A PHOSITA looking to build the flexible system described in Zukowski would need an efficient multiplication routine, such as those taught by Moshier or Rosati. In adapting such a routine for a multi-field system, the developer would be faced with the fact that the reduction step is the only part of the process that changes from one field to another.

  To avoid writing and maintaining a completely separate, monolithic multiplication-and-reduction function for every single field, the PHOSITA would have been motivated to separate the common multiplication logic from the variable reduction logic. This would involve taking a known multiplication method (like Moshier's), implementing it as a generic "wordsized" function that returns the unreduced product, and then creating a library of separate reduction functions. This combination of a known multiplication technique (Moshier/Rosati) with the goal of configurability (Zukowski) would lead directly to the two-step process of Claim 1: executing a first set of instructions for the multiplication to get an unreduced result, and then a second set of instructions for the field-specific reduction.

Conclusion on Obviousness

The core claims of the '062 patent describe an architecture that separates a general arithmetic computation from a specific modular reduction. While the cited prior art may not explicitly disclose this exact modular software structure in a single reference, the structure itself represents a standard and logical application of well-known software engineering principles (modularity, code reuse) to the known problem of building flexible cryptographic systems that can support multiple finite fields. The motivation to combine a generic, wordsized arithmetic engine with specific, interchangeable reduction modules would have been readily apparent to a PHOSITA seeking to create an efficient and extensible cryptographic library. Consequently, the claims of U.S. Patent 8,666,062 are likely vulnerable to an invalidity challenge based on obviousness under 35 U.S.C. § 103.

Analysis of Patent Term and Related Applications for U.S. Patent No. 8,666,062

Washington, D.C. - An examination of the public record for U.S. Patent No. 8,666,062 ("the '062 patent") provides details regarding its term, related applications, and family members. This information is crucial for understanding the patent's effective lifespan and its relationship to other innovations by the inventor.

Patent Term and Expiration

The '062 patent, which was filed on April 11, 2008, claims priority to an earlier, non-provisional application (U.S. Serial No. 10/058,212) filed on January 29, 2002. Under U.S. patent law, the term of a patent is 20 years from the filing date of the earliest non-provisional application to which it claims priority. Therefore, the base term for the '062 patent would have expired on January 29, 2022.

However, the official records for the '062 patent indicate an "Adjusted expiration" date of October 14, 2025. This later date is the result of a Patent Term Adjustment (PTA). PTA is granted by the U.S. Patent and Trademark Office (USPTO) to compensate for certain administrative delays during the patent prosecution process. The significant adjustment granted to the '062 patent reflects a lengthy examination period. There is no indication of any Patent Term Extension (PTE), a separate mechanism typically related to regulatory review delays for products like pharmaceuticals. As of the current date of May 10, 2026, the patent has expired.

Application History: A Continuation

The '062 patent is a continuation of U.S. application Ser. No. 10/058,212 (filed January 29, 2002), which subsequently issued as U.S. Patent No. 7,372,960. A continuation application is a new application that claims the benefit of the filing date of a prior, co-pending "parent" application. This allows an inventor to pursue different sets of claims based on the same original disclosure.

The parent application, in turn, claims priority from four provisional applications, all filed on December 31, 2001:

• U.S. Provisional Application No. 60/343,226
• U.S. Provisional Application No. 60/343,227
• U.S. Provisional Application No. 60/343,220
• U.S. Provisional Application No. 60/334,223

No divisional applications related to the '062 patent are listed in its file history.

Patent Family

The patent family for US 8,666,062 includes its direct parent, US 7,372,960, as well as at least one foreign counterpart. The shared priority date of December 31, 2001, links these patents as stemming from the same initial invention. The known family members are:

• United States: U.S. Patent No. 7,372,960
• Canada: Canadian Patent No. CA2369537C

Defensive Disclosure: Method and Apparatus for Performing Finite Field Calculations

Publication Date: May 10, 2026

Subject Matter: This document discloses novel extensions, applications, and implementations derived from the architectural principles of U.S. Patent 8,666,062. The purpose of this disclosure is to place these concepts into the public domain, thereby establishing prior art against future patent applications on these and similar incremental innovations. The core concept of the '062 patent, a two-stage process involving a generalized "wordsized" operation followed by a specific modular reduction, is expanded upon herein.

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Claim 1 & 15 Derivative: Method and Cryptographic Engine

Axis 1: Material & Component Substitution

1. FPGA-Based Reconfigurable Crypto-Processor

• Enabling Description: A cryptographic engine is implemented on a Field-Programmable Gate Array (FPGA). The "first set of instructions" (wordsized operations like multiplication, addition) is realized as a permanent, optimized, and generic logic block synthesized from a hardware description language (e.g., Verilog or VHDL). This block accepts operands of a fixed maximum width (e.g., 512 bits). The "second set of instructions" (modular reduction) is not fixed logic. Instead, it is a partial reconfiguration bitstream, specific to a given finite field modulus (e.g., NIST P-256 prime). Upon initialization of a cryptographic protocol, a host processor loads the appropriate partial bitstream into a designated reconfigurable region of the FPGA. This dynamically programs the reduction logic, which then receives the unreduced output from the fixed wordsized block. This allows for field-agile cryptography in hardware without requiring a full re-synthesis of the FPGA.
• Mermaid Diagram:

  graph TD
      subgraph FPGA Fabric
          subgraph Static Region
              A[Input A Register] --> WordOp
              B[Input B Register] --> WordOp
              WordOp{Wordsized Operator<br>(e.g., Full Multiplier)} --> UnreducedResult[Unreduced Result Bus]
          end
          subgraph Dynamic Reconfigurable Region
              UnreducedResult --> ModReducer
              ModReducer{Modular Reducer<br>(Logic loaded from bitstream)} --> ReducedResult[Reduced Result Register]
          end
      end
  
      HostCPU[Host CPU] -- "Load Reduction Bitstream (e.g., for P-256)" --> ModReducer
      HostCPU -- "Provide Operands" --> A & B
      ReducedResult --> HostCPU
  
      style ModReducer fill:#f9f,stroke:#333,stroke-width:2px
  

2. In-Memory Computing with Resistive RAM (ReRAM)

• Enabling Description: Finite field operations are performed directly within a ReRAM crossbar array, eliminating the CPU-memory bus bottleneck. Field elements are stored as resistance levels in ReRAM cells. The "first set of instructions" is a sequence of voltage pulses applied to wordlines and bitlines, performing analog matrix-vector multiplications that result in an unreduced product, accumulated as charge on the bitlines. This unreduced analog value is then processed by the "second set of instructions," which comprises a digital circuit (ADC, control logic, and DAC) integrated at the periphery of the memory array. This peripheral logic reads the analog result, performs a digital modular reduction specific to the finite field, and writes the final reduced value back into the ReRAM array by applying programming pulses. The reduction logic can be re-programmed for different fields.
• Mermaid Diagram:

  graph TD
      subgraph ReRAM Chip
          A[ReRAM Array<br>Stores Operands] -- Voltage Pulses --> B{Crossbar Array<br>Analog Multiplication}
          B -- Accumulated Charge --> C[Peripheral Sense Amps / ADCs]
          C -- Digital Unreduced Value --> D{Modular Reduction Unit<br>(Programmable Logic)}
          D -- Reduced Digital Value --> E[Peripheral Drivers / DACs]
          E -- Programming Pulses --> A
      end
      Controller[External Controller] -- "Set Field (p)" --> D
      Controller -- "Initiate Op(A, B)" --> A
  

3. GPU-Accelerated Batch Cryptography

• Enabling Description: A method for performing bulk cryptographic operations on a Graphics Processing Unit (GPU). A large number of element pairs are loaded into the GPU's global memory. A first CUDA or OpenCL kernel implements the "wordsized" multiplication, where each thread in a block computes a partial product. These are aggregated into an unreduced result, twice the bit-length of the operands. This first kernel is generic for the word size. A second, separate kernel is then launched. This second kernel is selected from a library of pre-compiled reduction kernels, each one optimized for a specific, commonly used cryptographic prime (e.g., secp256k1, Curve25519). This reduction kernel reads the unreduced results from global memory, performs the modular reduction in parallel, and writes the final results back. This two-kernel pipeline maximizes GPU occupancy and leverages specialized instruction sets (like integer multiply-add) for both stages.
• Mermaid Diagram:

  sequenceDiagram
      participant CPU
      participant GPU
  
      CPU->>GPU: 1. Transfer Operands (A[], B[]) to Global Memory
      CPU->>GPU: 2. Launch WordsizedMultiply_Kernel(A[], B[], Unreduced_C[])
      activate GPU
      Note right of GPU: Each thread computes C[i] = A[i] * B[i] (unreduced)
      GPU-->>CPU: Kernel 1 Complete
      deactivate GPU
      CPU->>GPU: 3. Launch Reduce_secp256k1_Kernel(Unreduced_C[], Reduced_C[])
      activate GPU
      Note right of GPU: Each thread computes Reduced_C[i] = Unreduced_C[i] mod p
      GPU-->>CPU: Kernel 2 Complete
      deactivate GPU
      CPU->>GPU: 4. Read back Reduced_C[] from Global Memory
  

Axis 2: Operational Parameter Expansion

4. Cryptography for Deep-Space Radiation-Hardened Systems

• Enabling Description: A cryptographic engine for spacecraft operating in high-radiation environments. The "wordsized" arithmetic unit is implemented using Triple Modular Redundancy (TMR) in a radiation-hardened-by-design (RHBD) ASIC. This core logic is simple, robust, and performs basic operations on a fixed word size (e.g., 256-bit operands yielding a 512-bit result). To allow for in-flight updates to cryptographic standards (e.g., moving to a new post-quantum standard), the "modular reduction" logic is stored in reprogrammable, radiation-tolerant MRAM (Magnetoresistive RAM). An uplinked command from ground control can overwrite the MRAM with a new set of reduction micro-instructions, adapting the system to new security protocols without requiring a full software patch of the flight computer, which is a high-risk operation.
• Mermaid Diagram:

  graph TD
      subgraph Rad-Hard ASIC
          subgraph TMR_Core [TMR Wordsized Core]
              Op1(Operand 1) --> ProcA
              Op2(Operand 2) --> ProcA
              Op1 --> ProcB
              Op2 --> ProcB
              Op1 --> ProcC
              Op2 --> ProcC
              ProcA --> Voter
              ProcB --> Voter
              ProcC --> Voter
          end
          Voter -- "Unreduced Result" --> Reducer
          MRAM[Rad-Tolerant MRAM<br>Stores Reduction Microcode] -- "Instructions" --> Reducer{Microcoded Reduction Unit}
          Reducer -- "Final Result" --> OutputBus
      end
      GroundControl[Ground Control Uplink] -- "Update Microcode" --> MRAM
  

5. Real-Time Cryptographic Engine for Terahertz (THz) Communications

• Enabling Description: For future 6G and beyond communication systems operating in the 100-300 GHz range, data rates will demand cryptographic processing with latencies in the nanosecond range. This method is implemented in a Gallium Nitride (GaN) or Indium Phosphide (InP) integrated circuit. The "wordsized" multiplier is a massively parallel, pipelined Karatsuba multiplier designed for extreme clock speeds. The unreduced output is fed directly into a bank of selectable reduction circuits. The "second set of instructions" is not software, but a hardware multiplexer that routes the unreduced result to one of several hard-wired reduction circuits, each optimized for a specific standard (e.g., one for AES-GCM in GF(2^128), another for an ECC curve). The selection is controlled by a low-latency control signal from the baseband processor, allowing for sub-nanosecond switching between cryptographic schemes.
• Mermaid Diagram:

  graph TD
      DataIn[High-Speed Data In] --> BasebandProc[Baseband Processor]
      BasebandProc -- "Operands" --> GaN_ASIC
      BasebandProc -- "Select 'AES' or 'ECC'" --> MUX_Control
      
      subgraph GaN_ASIC
          WordsizedMultiplier[Pipelined Karatsuba Multiplier] --> UnreducedBus
          UnreducedBus --> MUX{Multiplexer}
          MUX --> ReducerAES[Hard-wired AES-GCM Reducer]
          MUX --> ReducerECC[Hard-wired ECC Reducer]
          ReducerAES --> EncryptedDataOut
          ReducerECC --> EncryptedDataOut
      end
      
      MUX_Control[Control Signal] --> MUX
  

Axis 3: Cross-Domain Application

6. Finite Field Engine for Error Correction in Genomic Data Storage

• Enabling Description: DNA-based data storage encodes binary data into nucleotide sequences (A, T, C, G). This process is error-prone during synthesis and sequencing. This method is used to implement Reed-Solomon error correction codes over GF(2^8) or GF(2^16). The "wordsized" engine performs the generic polynomial multiplication and division required for syndrome calculation and Chien search. The "modular reduction" instruction set is specific to the generator polynomial of the Reed-Solomon code being used, which can be changed depending on the desired error correction capability (e.g., more redundancy for long-term archival). This allows a single hardware accelerator to be used for different coding schemes optimized for various DNA storage applications.
• Mermaid Diagram:

  flowchart TD
      A[Genomic Data Chunk] --> B(Encode as Polynomial)
      B --> C{Syndrome Calculation Engine}
      C --> D{Error Locator Polynomial Calc}
      D --> E{Error Value Calculation}
      E --> F(Corrected Polynomial) --> G[Corrected Genomic Data]
  
      subgraph Finite Field Accelerator
          C -- "Generic Poly Multiply" --> WordsizedEngine
          D -- "Generic Poly Multiply/Divide" --> WordsizedEngine
          E -- "Generic Poly Evaluation" --> WordsizedEngine
          WordsizedEngine -- Unreduced Result --> ReductionEngine
          ReductionEngine -- Reduced Result --> C & D & E
      end
  
      Control[Storage Controller] -- "Load RS-Code Generator Polynomial" --> ReductionEngine
  

7. Dynamic Simulation of Crystalline Structures

• Enabling Description: In computational materials science, particularly crystallography, operations within finite groups and fields are used to model lattice symmetries. This method is applied to accelerate these simulations. A generalized "wordsized" engine computes group operations (represented as matrix multiplications) in a large, encompassing field. The "second set of instructions" implements a modular reduction specific to the symmetry group (e.g., one of the 230 space groups) of the crystal being simulated. This allows researchers to use the same core computational hardware to simulate different materials (e.g., silicon, quartz, perovskites) by simply loading a different, compact reduction module for each material's crystal structure.
• Mermaid Diagram:

  graph LR
      SimConfig[Simulation Config: Material='Quartz'] -->|Selects Space Group P3121| Controller
      Controller -->|Loads 'P3121' Reduction Module| ReductionUnit
      
      subgraph Physics_Core
          StateA[Atom Positions Vector] --> Op
          Transform[Symmetry Transform Matrix] --> Op{Wordsized Matrix Multiply}
          Op --> UnreducedState[Unreduced State Vector]
          UnreducedState --> ReductionUnit{Reduction Unit}
          ReductionUnit --> NewState[New Atom Positions]
      end
  
      NewState --> NextIteration[Next Simulation Step]
  

Axis 4: Integration with Emerging Tech

8. AI-Driven Adaptive Cryptography for IoT Networks

• Enabling Description: An AI-based network security orchestrator monitors an IoT network for threats and computational constraints (e.g., device power levels, network latency). Based on this real-time analysis, it determines the optimal cryptographic curve and parameters for different segments of the network. For a high-power gateway, it might select a secure 521-bit curve. For a battery-powered sensor, it might select a more efficient 163-bit curve. The orchestrator generates the specific "modular reduction" instructions for the chosen curve and securely distributes them to the IoT devices. The devices, all equipped with the same generic "wordsized" engine (the first instruction set), load this new reduction module to seamlessly switch cryptographic schemes without requiring a full firmware update. This creates a self-optimizing, agile cryptographic infrastructure.
• Mermaid Diagram:

  sequenceDiagram
      participant AI_Orchestrator
      participant IoT_Gateway
      participant IoT_Sensor
  
      AI_Orchestrator->>IoT_Sensor: Monitor(Energy_Level, Latency)
      Note over AI_Orchestrator: Energy is low. Select efficient curve.
      AI_Orchestrator->>AI_Orchestrator: Generate 'K-163' Reduction Module
      AI_Orchestrator->>IoT_Sensor: Deploy(ReductionModule_K163)
      IoT_Sensor->>IoT_Sensor: Load K-163 into FF Engine
  
      AI_Orchestrator->>IoT_Gateway: Monitor(Threat_Level)
      Note over AI_Orchestrator: High threat detected. Select robust curve.
      AI_Orchestrator->>AI_Orchestrator: Generate 'P-521' Reduction Module
      AI_Orchestrator->>IoT_Gateway: Deploy(ReductionModule_P521)
      IoT_Gateway->>IoT_Gateway: Load P-521 into FF Engine
  

Axis 5: The "Inverse" or Failure Mode

9. Cryptographic Watchdog with Graceful Degradation

• Enabling Description: A cryptographic engine designed for high-availability systems where failure is not an option. The engine operates in three modes.
  • Mode 1 (Normal): Executes both the "wordsized" operation and the specific "modular reduction" for full cryptographic security.
  • Mode 2 (Degraded/Low-Power): If the processor detects a fault in the reduction unit or a low-power directive, it bypasses the second stage. It uses only the "wordsized" engine to produce an unreduced result. This result is then used as a non-cryptographic hash (e.g., for a checksum) to ensure data integrity, though not confidentiality.
  • Mode 3 (Fail-Safe): If the "wordsized" engine itself reports an error (e.g., via internal hardware checks), the entire engine is disabled, and a "zeroize" command is triggered to clear sensitive key material from memory. This prevents the leakage of corrupted or insecure cryptographic outputs.
• Mermaid Diagram:

  stateDiagram-v2
      [*] --> Normal
      Normal: Full Crypto (Wordsized + Reduction)
      Degraded: Integrity Checksum (Wordsized Only)
      FailSafe: Zeroize Keys
  
      Normal --> Degraded: Low Power Signal / Fault in Reducer
      Degraded --> Normal: Power Restored / Fault Cleared
      Normal --> FailSafe: Wordsized Unit Fault
      Degraded --> FailSafe: Wordsized Unit Fault
  

10. One-Time Reduction Module for Perfect Forward Secrecy

• Enabling Description: In a key exchange protocol like ECDH, this method is used to enforce perfect forward secrecy at the firmware level. The "wordsized" engine is part of the standard system firmware. The "modular reduction" instructions, however, are generated dynamically for each session as part of the ephemeral key generation process. This session-specific reduction module is loaded into a secure memory enclave (e.g., Intel SGX or ARM TrustZone), used exactly once to perform the scalar multiplication for the key exchange, and then immediately purged from memory. Any attempt to re-use the reduction module or access it after the operation will result in a hardware fault. This ensures that even if the device's long-term keys are compromised, the ephemeral session key cannot be recreated, as the specific reduction code used to compute it is gone forever.
• Mermaid Diagram:

  sequenceDiagram
      participant Client
      participant Server
  
      Client->>Client: Generate Ephemeral Keypair (k_c, P_c)
      Client->>Client: Dynamically Generate Reduction Module (M_c) for curve
      Client->>Server: Send Public Key P_c
      
      Server->>Server: Generate Ephemeral Keypair (k_s, P_s)
      Server->>Server: Dynamically Generate Reduction Module (M_s) for curve
      Server->>Client: Send Public Key P_s
  
      Client->>Client: Load M_c into Secure Enclave
      Client->>Client: Compute Shared Secret = k_c * P_s (using Wordsized Engine + M_c)
      Client->>Client: **Purge M_c from Enclave**
  
      Server->>Server: Load M_s into Secure Enclave
      Server->>Server: Compute Shared Secret = k_s * P_c (using Wordsized Engine + M_s)
      Server->>Server: **Purge M_s from Enclave**
  

---

Combination Prior Art Scenarios

1. Integration with RISC-V Cryptography Extension ("Scalar" Profile)

• Enabling Description: The '062 patent's method is implemented as part of the open-source RISC-V ISA. A set of custom instructions is defined. p.mul.w rD, rA, rB performs a "wordsized" polynomial multiplication on the registers rA and rB, storing the 2n-bit unreduced result in the register pair rD:rD+1. A separate configuration register, fcr (field control register), is loaded with a pointer to a memory region containing the irreducible polynomial for the specific field. A p.reduce rD instruction then executes the modular reduction of the wide register rD:rD+1 using the polynomial defined by fcr. This directly maps the two-stage process onto an open-standard CPU architecture, making the combination obvious to a person skilled in the art of processor design. The implementation can be prototyped using the open-source Spike RISC-V simulator and Rocket Chip generator.

2. Implementation as a WebAssembly (WASM) System Interface

• Enabling Description: The '062 method is provided as a high-performance cryptographic backend for web applications. The "wordsized" arithmetic routines are compiled into a core crypto.wasm module. This module is sandboxed and highly optimized but field-agnostic. The Web Cryptography API in the browser is extended with a new function: crypto.subtle.defineField(name, algorithm, modulus). When a web application calls this, the browser's native C++ code JIT-compiles a highly optimized "modular reduction" function specific to that modulus. It then passes a function pointer for this JIT-compiled code into the crypto.wasm module's memory space. Subsequent calls to crypto.subtle.encrypt within the WASM module will call out to this browser-provided, field-specific reduction function pointer after performing the wordsized multiplication internally. This combines the patent's method with the open standards of WebAssembly and the Web Crypto API.

3. Integration into the Linux Kernel Crypto API

• Enabling Description: The '062 patent's method is integrated into the Linux kernel's cryptographic framework. A new algorithm type, akcipher_ws (wordsized asymmetric cipher), is created. Drivers for cryptographic hardware accelerators register two separate function pointers with the kernel: one for the wordsized operation (op_wordsized) and a table of pointers for supported reductions (op_reduce_modN). When a user-space application (like OpenSSL) requests a cryptographic operation, the kernel first calls the generic op_wordsized function. It then looks up the required modulus in the hardware driver's table and calls the corresponding op_reduce_modN function on the intermediate result. This provides a standardized kernel interface that directly reflects the patent's two-stage architecture, making it an obvious software design pattern for integrating field-agile crypto accelerators into any Linux-based system.