US 8489837

US Patent 8,489,837 — Concise Summary

Search caveat: I ran live web searches against Google Patents, FreePatentsOnline, Docket Alarm, CourtListener, CAFC docket feeds, and PTAB records. I could not directly query USPTO Patent Center/PAIR content programmatically, so bibliographic data below is corroborated by Google Patents (full-text record), FreePatentsOnline, and IPR filing documents (IPR2017-00548), which are consistent with one another. No 2026 CAFC docket entry specifically naming patent 8,489,837 was found in the search results (see litigation note below).

Bibliographic data (high confidence)

Abstract (verbatim)

"According to certain aspects, a memory module is provided having at least one output configured to be operatively coupled to a memory controller of a host computer system. The memory module can be configured to operate in at least two modes comprising an initialization mode during which the memory module executes at least one initialization sequence and an operational mode. The memory module may include a controller circuit configured to cause the memory module to enter the initialization mode. The memory module may also include a notification circuit configured to drive the at least one output while the memory module is in the initialization mode to provide at least one notification signal to the memory controller indicating at least one status of the at least one initialization sequence."

Plain-language overview of each independent claim

• Claim 1 (apparatus — memory module). A memory module having at least one output wired to the host system's memory controller. The module has two modes: an initialization mode (where it runs one or more initialization/training sequences) and an operational mode. A controller circuit puts the module into initialization mode, and a notification circuit drives the output during initialization to send the memory controller a notification signal reporting the status of the initialization sequence. The notification signal is specifically required to trigger the memory controller to execute an interrupt routine (this interrupt-triggering feature is the distinguishing limitation of claim 1).

  • Dependent claims add: status = completion of initialization (2); status = execution in progress (3); output coupled to an interrupt of the memory controller (4); output is an error-out pin (5); driving to a first state (executing) or second state (complete) (6); coupling to a second memory module's output and wired-OR behavior (7–9), with states including a logic level and a high-impedance state (9).

• Claim 10 (method — module-side signaling). A method of using a first memory module whose output is coupled to a memory controller: (a) cause the module to enter initialization mode; (b) drive the output to a first state while the module is executing an initialization sequence; and (c) upon completion, drive the output to a second state different from the first, done so as to trigger the memory controller to execute an interrupt routine.

  • Dependent claims add: first state = logic level, second state = high-impedance (11); output coupled to an interrupt (12); output is an error-out pin (13); optional second memory module with parallel first/third and second/fourth state signaling (14); outputs shared on a common bus to one controller input (15) or on separate inputs (16).

• Claim 17 (method — notification output). A method of using a memory module whose output is coupled to a memory controller: (a) provide the module (initialization mode + operational mode); (b) cause the module to enter initialization mode; and (c) output a notification signal from the output indicating that the module has completed the initialization sequence, with the signal triggering the memory controller to execute an interrupt routine.

  • Dependent claim 18 adds that the notification signal is output via an error-out pin.

Technology in one sentence: The patent solves the problem of a memory controller (MCH) having to guess or blindly wait for a DIMM/LRDIMM's local controller to finish initialization/training — instead of polling a status register (SMBus) or inserting a fixed standby period, the module actively drives an output (advantageously a JEDEC error-out pin, used in an open-drain/wired-OR arrangement across multiple modules) to signal completion, which can trigger an interrupt so the host continues promptly.

Litigation / proceeding notes (what the searches showed)

• PTAB: IPR2017-00548 — SK hynix Inc. v. Netlist, Inc., inter partes review of U.S. Patent 8,489,837 (petition filed 2016; docket entries through Feb. 2018). Google Patents metadata lists a PTAB final written decision for this IPR.
• District Court/ITC: The '837 patent was among six Netlist patents asserted against SK hynix in the ITC (Inv. 337-TA-1023) and in C.D. Cal. case 8:16-cv-01605; also listed in a W.D. Tex. case (6:20-cv-00194). A CAFC appeal (18-1676) is associated with the family/litigation per Google Patents.
• CAFC 2026: I found no 2026 CAFC docket specifically identifying U.S. Patent 8,489,837. The 2026 Federal Circuit activity located involved other Netlist patents (e.g., appeal 25-1378 argued Dec. 5, 2025, affirmed under Fed. Cir. R. 36 with mandate issued Jan. 15, 2026 — relating to different Netlist patents; and 24-2203 argued Mar. 6, 2026). If you need confirmation of whether any 2026 CAFC matter cites the '837 patent, that would require a targeted PACER/CAFC docket search beyond what these searches returned.

Uncertainty note

• The "Expired – Fee Related" status and adjusted-expiration date come from Google Patents' legal-status display; I did not independently verify maintenance-fee status in USPTO records.
• I could not verify CAFC 2026 docket activity for this specific patent number; absence of results in these searches is not proof that no such docket exists.

Known litigation involving U.S. Patent No. 8,489,837 ("the '837 patent")

Based on searches of the Stanford NPE Litigation Database, Unified Patents, PTAB dockets, CourtListener, and Netlist's own disclosures, the '837 patent has been involved in the following matters, all stemming from Netlist's enforcement campaign against SK hynix (note: Netlist is the patent owner/assignee; the patent is invalidated in PTAB, which has driven most of the related litigation):

1. Netlist, Inc. v. SK hynix Inc., SK hynix America Inc., and SK Hynix Memory Solutions Inc. — C.D. Cal.

• Case No.: 8:16-cv-01605-JLS-JCG (Central District of California)
• Filing date: August 31, 2016
• Plaintiff: Netlist, Inc.
• Defendants: SK hynix Inc., SK hynix America Inc., SK Hynix Memory Solutions Inc.
• Asserted patents: Six Netlist patents, including U.S. Patent No. 8,489,837 ('837), plus 8,756,364, 8,516,185, 8,001,434, 8,359,501, and 8,689,064 (DDR4 LRDIMM/RDIMM products)
• Status/Outcome: Netlist's infringement claims were stayed on July 17, 2017 pending IPRs. SK hynix's RAND counterclaims proceeded separately. After the PTAB invalidated the asserted claims of the '837 patent (see below) and the Federal Circuit affirmed, the '837 patent was effectively dead; the case was ultimately dismissed/closed (stipulated dismissal and report on determination on the docket, with the case closed by about 2021).

2. Certain Memory Modules and Components Thereof, and Products Containing Same — U.S. International Trade Commission

• Investigation No.: 337-TA-1023
• Complaint filed: September 1, 2016 (investigation instituted October 7, 2016)
• Complainant: Netlist, Inc.
• Respondents: SK hynix Inc., SK hynix America Inc., SK Hynix Memory Solutions Inc.
• Asserted patents: The same six patents as the CDCA case, including the '837 patent
• Status/Outcome: The ALJ's Final Initial Determination (Nov. 14, 2017) found no violation of § 337 (no infringement of any asserted patent, including the '837 patent) and no invalidity shown by SK hynix. The Commission's final determination (January 16, 2018) affirmed no violation and terminated the investigation. Netlist's appeal of the ITC final determination was later found moot at the CAFC in light of the PTAB invalidity affirmances.

3. SK hynix Inc., SK hynix America Inc., and SK Hynix Memory Solutions Inc. v. Netlist, Inc. — PTAB

• Case No.: IPR2017-00548 (Patent Trial and Appeal Board)
• Petition filed: December 30, 2016
• Petitioners: SK hynix Inc., SK hynix America Inc., SK Hynix Memory Solutions Inc.
• Patent Owner: Netlist, Inc.
• Claims challenged/instituted: Claims 1–3, 5, and 6 of the '837 patent
• Institution decision: May 15, 2017
• Final Written Decision: May 3, 2018 — all instituted claims (1–3, 5, 6) held unpatentable under 35 U.S.C. § 103(a) as obvious over LeClerg (US 2005/0071580 A1) and Lee (US 2005/0193161 A1), and over LeClerg, Lee, and Kim (US 8,359,521 B2)
• Status: Final Written Decision; the Board's invalidity ruling was affirmed by the Federal Circuit (Rule 36 summary affirmance), per Netlist's own December 13, 2019 press release and later SK hynix filings describing the '837 patent as invalidated with the affirmance on appeal.

4. Netlist, Inc. v. SK hynix Inc., et al. — Court of Appeals for the Federal Circuit

• Case No.: 18-1676 (per the litigation data associated with this patent on Google Patents/Unified Patents)
• Parties: Netlist, Inc. (appellant) v. SK hynix entities (appellees)
• Subject: Federal Circuit appeal relating to the ITC/PTAB outcomes involving the '837 patent and related patents
• Status/Outcome: Per Netlist's December 13, 2019 announcement, the CAFC affirmed the PTAB invalidity decisions (via Rule 36) for related patents and found the appeal of the ITC's Inv. 337-TA-1023 final determination moot in light of those affirmances. I could not independently confirm from the search results whether 18-1676 was the ITC-final-determination appeal versus the PTAB appeal, so this specific docket should be verified on PACER/CAFC if precision on that point matters.

5. Netlist, Inc. v. SK hynix Inc., et al. — W.D. Tex.

• Case No.: 6:20-cv-00194 (Western District of Texas)
• Filed: 2020 (exact filing date not confirmed in the search results)
• Parties: Netlist, Inc. v. SK hynix Inc., et al.
• Relation to '837: This case is listed in litigation datasets associated with the '837 patent family. However, briefing within the case reflects that the '837 patent had already been invalidated by the PTAB and affirmed on appeal — SK hynix argued the '837 patent "was never litigated in California—and it never will be." I could not confirm from the available results whether the '837 patent was actually asserted in this W.D. Tex. action (the case appears to center on other Netlist patents, including a '623 patent). Verify the operative complaints on PACER before relying on this one.

Bottom line

• The '837 patent was asserted by Netlist against SK hynix in C.D. Cal. (8:16-cv-01605) and ITC Inv. 337-TA-1023 (filed 2016).
• The PTAB in IPR2017-00548 invalidated claims 1–3, 5, and 6 (Final Written Decision May 3, 2018), and the Federal Circuit affirmed — effectively ending the district court and ITC enforcement cases (no infringement finding ever issued).
• The CAFC appeal 18-1676 and W.D. Tex. 6:20-cv-00194 are the other dockets associated with this patent in litigation databases; their exact scope vis-à-vis the '837 patent should be confirmed on PACER if you need certainty.

Caveat: My search reached its step limit before I could pull PACER/CAFC docket sheets for cases 18-1676 and 6:20-cv-00194. The party names, filing dates, and current statuses above for those two dockets are drawn from secondary litigation databases and court-document snippets; I have high confidence in items 1–3 (CDCA case, ITC investigation, and IPR2017-00548) and moderate confidence on the precise mapping of items 4–5.

I'll research the PTAB proceedings on US Patent 8,489,837, starting from the canonical ODP data (which shows none on file) but flagging and investigating any surfaced proceedings — particularly the IPR2017-00548 matter identified in the patent record.

I've confirmed IPR2017-00548. Now let me dig into the FWD details, check for any appeal to the Federal Circuit, and confirm whether any other AIA proceedings targeted the '837 patent itself (as opposed to its continuations like 9,535,623 or 10,474,595).

I have the core IPR2017-00548 details. Now let me verify (a) whether the FWD was appealed to the Federal Circuit, and (b) whether any additional IPR/PGR petitions were filed directly against the '837 patent itself.

Proceedings overview

The USPTO Open Data Portal block in this prompt states "no AIA trial proceedings on file" — but that ingest is demonstrably stale. Live PTAB records confirm one completed inter partes review directly on US 8,489,837: IPR2017-00548 (SK hynix v. Netlist), which went all the way to a Final Written Decision invalidating every claim it challenged (claims 1, 2, 3, 5, and 6). Status breakdown: 0 active · 1 claims-invalidated · 0 settled · 0 institution-denied. The defensive bottom line: the apparatus claim that is the heart of this patent — claim 1, plus its challenged dependents — is canceled and gone; a demand letter built on claims 1–3, 5, or 6 has no surviving basis in the patent. Only the untested method claims (independent claims 10 and 17, with their dependents) remain as potential (and never-PTAB-tested) enforcement vehicles.

Flag on the canonical data: The structured "PTAB proceedings on file" block conflicts with primary-source evidence. USPTO PTAB Final Written Decision, Paper 25 in IPR2017-00548 (dated 2018-05-03), confirms the proceeding exists, its caption, panel, grounds, and outcome. Treat the ODP block as incomplete for this patent.

IPR2017-00548 — SK hynix Inc., SK hynix America Inc., and SK hynix Memory Solutions Inc. v. Netlist, Inc.

• Type: Inter Partes Review
• Filed: 2016-12-30 (filing date accorded 2017-01-09)
• Status: Final Written Decision entered 2018-05-03 — all instituted claims found unpatentable (proceeding concluded; no settlement)
• Judge panel: Stephen C. Siu (author of the FWD), Matthew R. Clements, Sheila F. McShane
• Petition grounds: Claims 1–3, 5, and 6 challenged under 35 U.S.C. § 103(a):
  1. Claims 1–3 and 6 over U.S. Pat. Publ. 2005/0071580 A1 ("LeClerg," Ex. 1005) in view of U.S. Pat. Publ. 2005/0193161 A1 ("Lee," Ex. 1007); and
  2. Claims 1–3, 5, and 6 over LeClerg + Lee + U.S. Patent 8,359,521 B2 ("Kim," Ex. 1008).
• Institution decision: Instituted on 2017-05-15 (Paper 7) on all requested claims and both grounds, the panel finding a reasonable likelihood that the claims were obvious over LeClerg + Lee (claims 1–3, 6) and LeClerg + Lee + Kim (claims 1–3, 5, 6).
• Final Written Decision: Issued 2018-05-03 (Paper 25). The Board held: "we determine that Petitioner met its burden of showing, by a preponderance of the evidence, that claims 1–3, 5, and 6 of the '837 patent are unpatentable." The Board applied the broadest reasonable construction, rejected Netlist's narrowing construction of "mode" (noting its own expert conceded the proposal departed from ordinary meaning), and found LeClerg disclosed initialization-status messaging to the memory controller and Lee supplied the interrupt-routine trigger; Kim supplied the error-out pin for claim 5. Canceled: claims 1, 2, 3, 5, 6.
• Settlement / termination: None — the parties litigated through oral hearing (2018-02-14) and FWD. No settlement terms exist.
• Appeal: I found no direct evidence that the IPR2017-00548 FWD itself was appealed to the Federal Circuit in my searches. The related CAFC appeal 18-1676, Netlist, Inc. v. ITC (appealing the ITC's no-violation determination in Inv. No. 337-TA-1023 — the very ITC investigation that had asserted the '837 against SK hynix) was dismissed as moot on 2019-12-12 in light of the Federal Circuit's Rule 36 affirmances in Netlist v. SK hynix, Nos. 18-2123 and 18-2357 (which affirmed PTAB invalidity determinations on other Netlist patents). Netlist's own 2019-12-13 press release confirms the PTAB invalidity rulings were affirmed and the ITC appeal became moot.
• Defensive value: This is the single most valuable defensive fact available on this patent. Claims 1–3, 5, and 6 — including independent apparatus claim 1 and the error-out-pin claim (5) — were canceled in a final, un-appealed (so far as the record shows) FWD. No infringement theory built on claim 1 or its challenged dependents can survive; asserting them today would be sanction-bait. For links: FWD at Docket Alarm (IPR2017-00548, Paper 25, 2018-05-03); moot order at CourtListener (Netlist, Inc. v. ITC, No. 18-1676, Dec. 12, 2019).

Strategic summary

Which claims are CANCELED vs. SUSTAINED vs. UNTESTED. The IPR challenged only claims 1, 2, 3, 5, and 6, and all five were canceled in the 2018-05-03 FWD. That kills the entire apparatus-claim axis of the patent: claim 1 (the only apparatus independent claim), claim 2 (status = completion), claim 3 (status = execution), claim 5 (error-out pin), and claim 6 (first/second state signaling). No claim was "sustained" — the Board found against the patent owner on every instituted claim. Untested by any PTAB trial are claims 4, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, and 18. Practically, however, claims 4, 7, 8, and 9 are orphaned dependents — claim 4 depends from canceled claim 1, and claims 7–9 depend (directly or via claim 7) from canceled claim 6 — so they incorporate canceled limitations and are not meaningfully assertable. The only truly live, never-tested claims are the method claims: independent claim 10 (with dependents 11–16) and independent claim 17 (with dependent 18) — including the method versions of the error-out-pin signaling (claims 13 and 18). A patentee enforcing today must rely on those method claims, which have never faced a PTAB merits test.

Estoppel landscape. Under 35 U.S.C. § 315(e), only SK hynix (and its privies/real parties in interest) are estopped from re-asserting grounds raised or reasonably available in IPR2017-00548 — and only as to the claims that were in that trial (claims 1–3, 5, 6). Those claims are canceled anyway, so the estoppel is largely academic for SK hynix. Critically, a new defendant is not estopped at all: the surviving method claims (10–18) and the orphaned dependents (4, 7–9) were never the subject of a final written decision, and no estoppel attaches to claims that were not in the trial. The prior art that worked before — LeClerg (2005/0071580), Lee (2005/0193161), and Kim (8,359,521) — remains freely available to any new challenger, and the FWD's claim constructions and obviousness reasoning are persuasive authority a new petitioner can build on. One caution: those references were heavily developed in this IPR, so a new petition should pair them with a Sotera-type stipulation and be alert to § 325(d) if relying on substantially the same art already of record.

Pattern signals. SK hynix filed this IPR as part of a coordinated wave — simultaneously challenging sibling Netlist patents in IPR2017-00549 (8,756,364), IPR2017-00560 (8,689,064), and IPR2017-00587 (8,671,243), all heard in a combined 2018-02-14 oral hearing — and later filed IPR2018-00303 against the '837's continuation child, 9,535,623, and IPR2020-01042 against 10,474,595. Netlist has been a serial ITC/EDTX litigant and has lost the PTAB battles on this family's earliest patents; it did not secure a favorable PTAB outcome on the '837. No defensive aggregator (e.g., Unified Patents) filed on the '837 itself — the Unified Patents links on the Google Patents record are litigation-data annotations only. Samsung's later IPR2025-00001 cites the '837 only as an exhibit/prior art, not as a challenged patent. Netlist's patent-owner litigation posture (ITC 337-TA-1023, C.D. Cal. 8:16-cv-01605, W.D. Tex. 6:20-cv-00194) has not translated into PTAB wins on this patent — the one time the '837 was tried at the PTAB, it lost everything challenged.

Recommended next steps

• If you are a defendant facing assertion of the '837 today, lead with the FWD. Get IPR2017-00548, Paper 25 (2018-05-03) — freely available via Docket Alarm and the USPTO PTAB (PTABE2E/PTACTS) — and quote its dispositve language: claims 1–3, 5, and 6 "are unpatentable." Since the USPTO issues a certificate canceling claims after FWD, verify the certificate in USPTO records, but the FWD itself is the operative document. If the demand cites claim 1, 2, 3, 5, or 6 — or dependents 4, 7–9 that trace to canceled claims — there is no colorable infringement theory; move to dismiss / seek fees under § 285 if the patentee persists.
• If the demand pivots to method claims 10–18, those are untested and you cannot rely on the IPR alone. You are not estopped; consider a fresh IPR on claims 10–18 using the same LeClerg/Lee/Kim art (which the FWD already found sufficient to render the parallel apparatus limitations obvious) plus any additional art, and/or raise invalidity under § 103 in district court. Be mindful of the § 315(b) one-year bar from service of the complaint and of § 325(d) given the art's prior Office consideration.
• No active PTAB proceeding is pending, so there are no near-term institution-decision, oral-hearing, or FWD deadlines to track on this patent. The single completed IPR ended at FWD on 2018-05-03, well over a year ago.
• If you are SK hynix or a privy, you are estopped on claims 1–3, 5, 6 under § 315(e)(2) — but those claims are canceled, so the estoppel imposes no practical handicap; you may also have res judicata-type arguments in the district court and ITC matters based on the FWD and the mooted CAFC appeal.
• Verify two open items in USPTO/CAFC records directly (beyond what web search returned): (1) whether Netlist filed a notice of appeal of the IPR2017-00548 FWD itself under 35 U.S.C. § 141(c) — my searches found none, but absence of search results is not proof; and (2) the maintenance-fee/expiration status of the patent, since Google Patents' "Expired – Fee Related" label with a 2031 adjusted expiration is internally inconsistent and unverified.

Bottom line for a defendant: The patent's principal claims — the ones a memory-module patent assertion would be built on — are dead (claims 1–3, 5, 6 canceled by IPR2017-00548, FWD 2018-05-03). Only the never-tested method claims 10–18 survive on paper, and any new challenger remains free to attack them.

I was unable to query the USPTO Assignment Center directly before hitting my tool-call limit, so the chain below is reconstructed from (a) Google Patents' legal-events feed for US 8,489,837 (which mirrors USPTO assignment-record data), (b) Netlist SEC filings (8-Ks of July 18, 2013 and Feb. 17, 2015; 10-Q exhibits), and (c) a PTAB exhibit (Docket Alarm, IPR2026-00017, Ex. 2006) showing one Netlist→SVIC security-interest cover page. Exact reel/frame values for most entries are not verified and are marked as such; where I do not know a value I say so rather than guess.

Inventors

No unusual inventor-side signals. This is not a case where a portfolio fire-sale is foreshadowed by inventor departures.

Original assignee

• Netlist, Inc. (Delaware corp., Irvine, CA; NYSE American: NLST) is the entity named on the issued patent and the assignee of the inventor's interest.
• Products: Netlist designs and sells memory modules — including its NVvault™ (NAND/DRAM hybrid) line and DDR3/LRDIMM products — so it is an operating company with products, not a paper entity. The '837 claims (handshaking during LR-DIMM-style initialization) relate to its memory-module technology.
• Current status: Still operating (public), and still an active patent litigant (e.g., later cases against Samsung and SK hynix). The '837 itself was invalidated in IPR2017-00548 (FWD May 3, 2018, affirmed by the Federal Circuit) and shows "Expired – Fee Related" status; Netlist remains the owner of record.

Assignment timeline

USPTO Assignment Center could not be directly searched in this session. The records below are the ones surfaced by Google Patents' legal-events feed for the '837 (which draws from recorded USPTO conveyances) plus SEC/PTAB corroboration. No ownership (title) transfer away from Netlist appears anywhere in the record — every post-issuance conveyance is a creditor's security agreement or its termination/release, which does not change title.

1. 2010-10-19 (recorded) — Reel/frame not verified

   • Conveyance: Assignment of Assignors Interest (inventor → company)
   • Assignor: Hyun Lee
   • Assignee: Netlist, Inc.
   • Correspondent: not available in my sources
   • Context: Standard pre-issuance assignment from the sole inventor to his employer.

2. 2013-07-18 (executed and recorded same date per Google Patents) — Reel/frame not verified

   • Conveyance: Security Agreement (IP collateral grant)
   • Assignor/Grantor: Netlist, Inc.
   • Assignee/Secured Party: DBD Credit Funding LLC (Delaware LLC; Fortress Investment Group affiliate)
   • Correspondent: not available in my sources
   • Context: Debt collateral, not a sale. Corroborated by Netlist's July 18, 2013 8-K: a Loan and Security Agreement with DBD Credit Funding LLC (Fortress), including a contemporaneous Intellectual Property Security Agreement pledging Netlist's patent portfolio, plus a Patent Monetization Side Letter giving the lender a share of future patent-monetization revenue. Netlist retained title.

3. 2015-11-20 (recorded; agreement dated 2015-11-18) — Reel 037150 / Frame 0897 (per PTAB IPR2026-00017 Ex. 2006 cover page; I could not confirm this specific reel/frame covers the '837 as opposed to sibling patents — treat as probable but unverified)

   • Conveyance: Security Interest (IP collateral grant)
   • Assignor/Grantor: Netlist, Inc.
   • Assignee/Secured Party: SVIC No. 28 New Technology Business Investment L.L.P. (Korean LLP; a Samsung Venture Investment Corp. fund)
   • Correspondent: DLA Piper LLP — submitter Troy Zander; e-mail contact susan.reynholds@dlapiper.com; attorney docket 350916-9 (from the Ex. 2006 cover page; agreement file titled "Netlist – Project Neptune – IP Security Agreement")
   • Context: Debt collateral, not a sale. A new secured loan (codename "Project Neptune") replacing/refinancing the Fortress facility. SEC filings (intercreditor agreements with Silicon Valley Bank and TR Global Funding V LLC) corroborate the November 2015 SVIC financing and the pledge of Netlist's patent portfolio as collateral.

4. 2015-12-03 (recorded) — Reel/frame not verified

   • Conveyance: Termination of Intellectual Property Security Agreement
   • Assignor: DBD Credit Funding LLC (releasing party)
   • Assignee: Netlist, Inc. (released debtor)
   • Correspondent: not available in my sources
   • Context: Release of the 2013 Fortress/DBD lien, consistent with the SVIC refinancing (Netlist's Feb. 17, 2015 8-K already showed Fortress Credit Opportunities I LP as successor to DBD).

5. 2023-11-20 (recorded) — Reel/frame not verified

   • Conveyance: Release by Secured Party
   • Assignor: SVIC No. 28 New Technology Business Investment L.L.P. (releasing party)
   • Assignee: Netlist, Inc. (released debtor)
   • Correspondent: not available in my sources
   • Context: Release of the 2015 SVIC lien — i.e., the final creditor's interest in the '837 was cleared, leaving Netlist as sole owner with no encumbrances of record shown.

Bottom line on the record: no shell-entity, NPE, or aggregator ever took title. The only non-inventor "assignees" are two secured lenders (DBD/Fortress in 2013; SVIC in 2015), and both liens were later released. This is a standard debtor-creditor collateral pattern, not an ownership chain. (Caveat: I could not rule out additional recorded security interests — e.g., Silicon Valley Bank or TR Global Funding V LLC filings touching the '837 — because I could not run the Assignment Center query; Google Patents' event list for the '837 shows only the five events above.)

Timeline diagram

timeline
    title Ownership of US 8489837
    2009 : Provisional filed Jun 12
    2010 : Utility filed Jun 14
         : Assigned by Hyun Lee to Netlist Inc
    2013 : Patent issued Jul 16
         : DBD Credit Funding lien granted Jul 18
    2015 : SVIC No 28 lien granted Nov 20
         : DBD lien terminated Dec 3
    2016 : SK hynix suit filed Aug 31
    2017 : IPR2017-00548 instituted May 15
    2018 : PTAB invalidates claims May 3
    2023 : SVIC lien released Nov 20

NPE / troll-pattern signals

1. Shell-entity transfer — not present. No assignment ever moved the '837 from Netlist to an "IP / Licensing / Holdings" LLC. DBD Credit Funding LLC (2013-07-18) and SVIC No. 28 (2015-11-20) took only security interests under loan agreements (per Netlist's 8-Ks and the recorded "Security Interest / Security Agreement" conveyances); both were released (2015-12-03 and 2023-11-20). A creditor's lien is not a shell transfer.

2. Known asserter in the chain — not present. The asserter is Netlist itself — an operating memory-module company, not an entity on NPE lists (Acacia, Marathon, IV, Wi-LAN, Conversant, etc.). The lenders (Fortress/DBD and SVIC/Samsung Venture) are financial institutions, not patent asserters. (Side note worth flagging, though not an NPE signal: SVIC is a Samsung Venture Investment Corp. fund, and Samsung later became a Netlist adversary — but the SVIC lien was a conventional secured loan, not privateering.)

3. Repeat correspondent across the chain — unclear. My only correspondent data point is DLA Piper (Troy Zander / attorney docket 350916-9) on the 2015 SVIC filing. I could not retrieve correspondents for the inventor assignment, the DBD agreement, or the two releases, so I cannot test for a recurring recording attorney. This signal is unverified, not affirmative.

4. Cascading transfers — not present. No chained LLC-to-LLC conveyances exist; the five recorded events are one inventor assignment, two liens, and two releases, spread over 13 years.

5. Pre-litigation transfer — not present. Netlist owned the patent continuously from issuance (July 16, 2013) and filed suit against SK hynix in its own name (C.D. Cal. 8:16-cv-01605, filed Aug. 31, 2016; ITC Inv. 337-TA-1023, complaint filed Sept. 1, 2016). No transfer occurred in the six months before suit, and none was needed — the plaintiff already held title.

6. Bankruptcy fire-sale — not present. Netlist has not been in bankruptcy; the 2013 and 2015 liens were ordinary secured borrowings (Fortress and SVIC), not § 363 asset sales.

7. Privateering — not present. Netlist asserted the '837 directly against a competitor (SK hynix) in its own name; there is no SEC or press evidence of a transfer to a fronting NPE.

8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. It terminates at Netlist, the original operating assignee — with the patent neutralized instead by PTAB invalidity (IPR2017-00548, FWD May 3, 2018) and expiration.

Verdict

Operating-company assertion

Netlist, Inc. — the original assignee and current owner of record — is an operating memory-module company that shipped products in the relevant field and asserted the '837 against a direct competitor, SK hynix, in its own name (C.D. Cal. 8:16-cv-01605, filed 2016-08-31; ITC 337-TA-1023, filed 2016-09-01). The only post-issuance conveyances are 2013 and 2015 security agreements to lenders DBD Credit Funding LLC (Fortress) and SVIC No. 28 (both later released in 2015 and 2023), which never transferred title and therefore do not constitute shell transfers, cascades, or privateering. There is no NPE in the chain, no pre-litigation transfer, and no defensive aggregator; the absence of any ownership migration is itself the controlling fact.

Verification link: search patent number 8489837 at https://assignmentcenter.uspto.gov/ (patent assignment search). Reel/frame values not independently confirmed in this session except the probable SVIC entry at 037150/0897; the five-event chain above matches Google Patents' legal-events feed for the '837 and Netlist's SEC disclosures.

I'll research the prior-art citations of US 8,489,837 directly. Let me run several targeted searches.

Let me pull the actual front-page citation list for the '837 patent itself.

Let me try to retrieve the '837 patent's own front-page reference list directly.

I hit my search-step limit while trying to pull the '837's own front page verbatim, so before giving you the reference-by-reference breakdown, I need to be precise about what I could and could not retrieve — per the operating rules, I will not fabricate a citation list.

Source / confidence caveat (important)

What the search returned for "8489837": Live queries against Google Patents (patents.google.com/patent/US8489837), FreePatentsOnline (freepatentsonline.com/8489837.html), and the PTAB/IPR record confirmed the patent and its bibliographic data. The Google Patents record for the '837 says "Prior art keywords: memory module, memory, output, initialization, state."

What I could NOT retrieve: the '837's own printed "(56) References Cited" block, verbatim, from its front page (the fetched Google Patents/FreePatentsOnline text jumped from the claims to the family/priority tables and did not include the 56 block). I also did not retrieve any foreign patent documents or NPL citations printed on the '837's face page.

What I did retrieve instead: the (56) reference lists printed on the continuation members of the same family — US 9,535,623 B1 (filed 2016-06-01) and US 9,858,218 B1 (filed 2016-04-01), whose specifications are continuations of the '837 and which carry forward the original examiner-cited art plus later art. Treat the list below as the family's citation record, not as a verbatim read of the '837 face page. The individual entries dated after June 2010 (e.g., the 2010/2011 publications) cannot have been on the '837's 2013 front page and are almost certainly additions made during prosecution of the later continuations — I flag those.

For the substantive prior-art question, the authoritative source is not the face page at all — it is the adjudicated record of IPR2017-00548, discussed in Section 3.

1. Front-page / family "References Cited" — U.S. Patent Documents

Drawn from the (56) blocks of US 9,535,623 and US 9,858,218 (family members; see caveat). Dates are the printed publication/grant dates.

U.S. Patent Application Publications (from the same family (56) blocks):

I could not retrieve a foreign-patent-documents or "Other Publications" block for the '837; if the face page has one, it was not surfaced.

2. The most relevant prior art, ranked

Tier 1 — the three references that actually defeated the patent (Tier 1 = adjudicated):

1. US 2005/0071580 A1 — LeClerg et al., "Distributed memory initialization and test," published 2005-03-31. (Its granted counterpart US 7,539,909 B2, issued 2009-05-26, is also on the family's face page.)
2. US 2005/0193161 A1 — Lee et al., published 2005-09-01.
3. US 8,359,521 B2 — Kim et al., issued 2013-01-15 (open-drain shared error-feedback pin).

Tier 2 — relevant-but-not-dispositive: US 7,093,715 (Poisner), US 7,489,163 (Goodnow), US 7,586,350 (Chung), US 2007/0214347 (Rothman), US 2008/0256281 (Fahr).

Applicant-cited / incorporated by reference: US 2006/0062047 A1 (Bhakta) and US 2006/0262586 A1 (Solomon) — cited in the '837 specification as the baseline memory-module architecture.

3. § 102 vs. § 103 — the key legal point you asked about

No cited reference was held to anticipate the '837 under § 102. Every reference above was applied in § 103 obviousness combinations, not as a § 102 anticipatory reference. That distinction matters for your question:

• LeClerg (US 2005/0071580 A1 / US 7,539,909 B2) — alone, does NOT anticipate claim 1. It discloses nearly every element of claim 1 — module-local initialization/training, a controller that causes initialization mode, and status messaging ("Initialization Status"/"Completed" vs. "Not Completed") back to the memory controller over an upstream channel. But it discloses query/response status polling, not notification-driven interrupt triggering — i.e., it lacks claim 1's final limitation ("wherein the at least one notification signal triggers the memory controller to execute an interrupt routine") and claim 10's/17's trigger element. So LeClerg's potential § 102 exposure is limited to claim elements, and it was used as the primary § 103 reference for claims 1, 2, 3, and 6.

  • If one (incorrectly) ignored the interrupt limitation, LeClerg reads squarely on claims 2 and 3 (status = completion; status = execution) and on claim 6 (first state = executing, second state = complete). But claims 2 and 3 depend from claim 1, so they inherit the interrupt limitation and are not anticipated by LeClerg standing alone.

• Lee (US 2005/0193161 A1) — used for the single missing limitation. It discloses an interrupt handler that triggers an interrupt routine in response to a received interrupt signal. It supplies claim 1's (and claims 10/17's) interrupt-routine-triggering element; it has no independent § 102 read on the memory-module claims because it does not disclose a memory module in an initialization mode.

• Kim (US 8,359,521 B2) — the reference for claim 5. It discloses a shared, open-drain, wired-OR "error feedback" pin on memory devices/modules — the JEDEC-style error-out pin of claim 5 (and claim 13/18 in the method claims). By itself it does not anticipate claim 5, because claim 5 depends from claim 1 and requires the initialization-mode notification; it was applied in the § 103 combination LeClerg + Lee + Kim for claims 1–3, 5, and 6.

The PTAB's actual holdings (from IPR2017-00548, FWD 2018-05-03):

• Claims 1–3 and 6 unpatentable under § 103(a) over LeClerg + Lee.
• Claims 1–3, 5, and 6 unpatentable under § 103(a) over LeClerg + Lee + Kim.
• The Federal Circuit affirmed (Rule 36).

Method claims 10–18 were never challenged in the IPR, so no official § 102 or § 103 ruling exists for them. On the merits, the identical mapping would apply (LeClerg for the module-side driving/reporting, Lee for the interrupt trigger, Kim for the high-impedance/error-out-pin dependent claims 11–13 and 18) — but that is my analysis, not an adjudicated finding.

4. Related-family § 103 use of face-page art (for completeness)

During prosecution of the sibling continuation US 10,474,595 (a child of the '837), a later examiner rejected claims 1–20 under § 103(a) over Tanguay (US 2010/0042778 A1) in view of Roohparvar (US 2003/0115427 A1) — both of which appear on the family citation record above. Also, claims in the continuations were rejected for nonstatutory double patenting over claims 1–18 of US 8,489,837 itself (the '837 thus operates as a family reference against its own continuations, not as prior art against itself). Source: Declaration of Dr. Donald Alpert regarding US 10,474,595, filed in the PTAB record (ptacts.uspto.gov).

Bottom line

• The most relevant prior art for US 8,489,837 is, in order: (1) LeClerg, US 2005/0071580 A1 (pub. 2005-03-31; granted as US 7,539,909 B2, 2009-05-26); (2) Lee, US 2005/0193161 A1 (pub. 2005-09-01); and (3) Kim, US 8,359,521 B2 (issued 2013-01-15). All three predate the June 12, 2009 priority date and were the references that invalidated the challenged claims.
• Strictly under § 102, none of the cited references anticipates an independent claim: LeClerg lacks the interrupt-triggering limitation (claim 1) and the method counterparts (claims 10, 17); Kim lacks the initialization-mode notification context. The operative legal theory was § 103, and the adjudicated result was invalidation of claims 1, 2, 3, 5, and 6.
• Caveat on my citation list: I could not retrieve the '837's own printed (56) block verbatim; the reference table in Section 1 is reconstructed from the front pages of the co-pending continuations US 9,535,623 and US 9,858,218, which share the '837 specification. If you need the '837's face-page citations exactly (including any foreign documents and NPL), the primary source to pull is the front page of the US 8,489,837 B1 PDF (patentimages/Patent Public Search) or the USPTO Patent Center file wrapper — I was unable to read that block directly before hitting my search limit, and I did not substitute the continuation lists for it without saying so.

Preliminary note on sources

The user prompt references a "Prior Art section of this page," but no such section was actually included in the message. To ground this analysis I instead pulled the authoritative prior-art record from the PTAB proceeding that actually adjudicated obviousness of US 8,489,837 — IPR2017-00548 (SK hynix Inc., SK hynix America Inc., and SK Hynix Memory Solutions Inc. v. Netlist, Inc.) — including the Petition, Patent Owner Response, Petitioner's Reply, and the Final Written Decision (May 3, 2018), as well as the underlying references themselves. That record is the best available "prior art section" for this patent and is highly reliable: the PTAB held every instituted claim (1, 2, 3, 5, and 6) unpatentable under 35 U.S.C. § 103(a), and the Federal Circuit affirmed (Rule 36). Key sources:

• PTAB Final Written Decision, IPR2017-00548, Paper 25 (May 3, 2018) — https://www.docketalarm.com/cases/PTAB/IPR2017-00548/Inter_Partes_Review_of_U.S._Pat._8489837/05-03-2018-Board/Termination_Decision_Document-25-Final_Written_Decision/
• Petition for IPR, Paper 1 (Dec. 30, 2016) — https://www.docketalarm.com/cases/PTAB/IPR2017-00548/Inter_Partes_Review_of_U.S._Pat._8489837/12-30-2016-Petitioner/Petition-1-Petition_for_Inter_Partes_Review/
• LeClerg, US 2005/0071580 A1 (published Mar. 31, 2005); Lee, US 2005/0193161 A1 (published Sept. 1, 2005); Kim, US 8,359,521 B2.

Legal framework

Obviousness under 35 U.S.C. § 103 asks whether the claimed subject matter as a whole would have been obvious to a person of ordinary skill in the art (POSITA) at the time of invention (here, priority date June 12, 2009). Under Graham v. John Deere and KSR Int'l Co. v. Teleflex, that inquiry turns on: (1) the scope and content of the prior art; (2) differences between the prior art and the claims; (3) the level of ordinary skill; and (4) secondary considerations. A combination of familiar elements is obvious when a POSITA would have had a reason to combine them "according to known methods" to achieve "predictable results," and the combination yields no more than the predictable working of its known parts. The IPR applied these standards (under the Board's broadest-reasonable-construction rubric) and found the claims obvious by a preponderance of the evidence.

The prior-art references

LeClerg (Ex. 1005) — US 2005/0071580 A1, "Distributed memory initialization and test" (published Mar. 31, 2005; well before the June 2009 priority date).
LeClerg discloses a computer system with a processor, memory controller, and multiple memory modules that carry out their own initialization/test procedures. Key teachings used in the obviousness analysis:

• Each memory module includes an initialization/test controller (e.g., element 304) that controls module-local initialization, stores initialization-related information, and writes status to registers.
• Upon receiving an initialization command from the processor or memory controller, the module executes an initialization procedure/sequence (Fig. 5: receive module-init command → initialize registers → initialize memory locations → indicate process completion).
• The module has a normal/operational mode in which the memory controller issues read/write commands to the module.
• The module communicates status back to the memory controller over an upstream channel (bus interface 302; channels 210/212), and the messages sent to the memory controller "can include initialization and/or test status messages," including an "Initialization Status" (Completed/Not Completed) response to an "Initialization Status Query." (¶¶ 34, 35, 88, 91.)

Lee (Ex. 1007) — US 2005/0193161 A1 (published Sept. 1, 2005).
Lee discloses a memory system in which the processor/memory controller includes an interrupt handler (148) that receives an interrupt signal (142); the interrupt signal triggers an interrupt routine at the processor. Lee supplies the one limitation the Board found LeClerg to lack in claim 1: notification-driven (rather than polling/query-driven) triggering of an interrupt routine.

Kim (Ex. 1019/1003) — US 8,359,521 B2, "Providing a memory device having a shared error feedback pin."
Kim discloses adding an error pin to each memory device in a module and connecting ("dotting") those device-level error pins, via an open-drain arrangement, to a single error-out/error-feedback pin that is "available on many industry standard modules." An OR-gate combines parity-error and CRC-error indications to drive the gate of the open-drain transistor so that the shared pin is asserted if any connected device asserts an error. Kim therefore teaches the industry-standard error-out pin and the open-drain/wired-OR mechanism for reporting status/error from multiple devices on one line.

Primary obviousness ground: Claims 1–3 and 6 over LeClerg + Lee

Claim 1 — element-by-element

Why the combination is obvious. The Board found that LeClerg discloses all of claim 1 except interrupt-routine triggering, and that Lee teaches triggering an interrupt routine in response to a memory-related signal in a memory system. The two references are in the same field (memory systems/initialization), and the modification is a simple substitution of one well-known notification mechanism (interrupt) for another (status-query/polling) — precisely the "polling vs. notifying" design choice the '837 specification itself describes as conventional. A POSITA seeking to avoid the inefficiency of register polling (which the '837 patent itself criticizes at col. 3) would naturally route LeClerg's status message to Lee's interrupt handler. The result is the predictable combination of a module-generated completion signal with a standard processor interrupt.

Netlist's arguments against this ground — (a) that LeClerg's initialization and normal operations occur in the same "normal power" mode and therefore do not teach distinct "modes," and (b) that LeClerg notifies "the processor" rather than "the memory controller" — were rejected:

• The claims and specification say nothing about power levels; under the broadest reasonable construction, "initialization mode" is simply "a mode during which initialization occurs."
• LeClerg discloses no direct module-to-processor connection; status is conveyed over the upstream channel to the memory controller, and LeClerg's own expert admitted the upstream communication to the memory controller "could include initialization status messages."

Claim 2 — "at least one status comprises completion of the at least one initialization sequence"

LeClerg's "Initialization Status" message includes a "Completed" state — the module explicitly "indicates process completion" at the end of its Fig. 5 sequence. Same combination; obvious for the same reasons.

Claim 3 — "at least one status comprises execution of the at least one initialization sequence"

LeClerg's "Not Completed" status indicates the sequence is still executing. Alternatively (and more robustly, per the alternate ground below), in LeClerg combined with Kim's active-low open-drain pin, an asserted (low) output during the initialization sequence means "in progress / not completed." Obvious.

Claim 6 — "notification circuit configured to drive the at least one output to a first state indicative of execution … or to a second state indicative of completion"

LeClerg's Completed/Not-Completed message dichotomy maps directly onto "executing" vs. "complete." Where the output is implemented with Kim's open-drain transistor (below), driving the gate high pulls the output low ("executing/first state") and releasing the gate to a high-impedance state lets the controller's pull-up drive the line high ("complete/second state"). Obvious.

Secondary ground: Claims 1–3, 5, and 6 over LeClerg + Lee + Kim

Claim 5 — "the at least one output comprises an error-out pin of the memory module"

Kim supplies the missing limitation. Kim expressly teaches adding an error pin to memory devices and connecting the device pins to an existing error pin available on industry-standard modules — i.e., the JEDEC-style error-out pin the '837 specification relies on (col. 8–9). The claim recites only that the output "comprises an error-out pin," with no added structure or function, so the addition is a trivial selection of a known, standard pin.

Motivation to combine LeClerg with Kim. The record identified several concrete, non-hindsight reasons a POSITA would add Kim's open-drain error-out pin scheme to LeClerg:

1. Known technique, known purpose, predictable result. Open-drain/wired-OR status reporting from multiple memory devices on a single line was a well-known, simple technique for conveying error/status information.
2. LeClerg already points to an error channel. LeClerg discloses a channel between the module and the memory controller "over which error information is sent," which a POSITA would understand is physically implemented as a pin.
3. LeClerg already wants both status values. LeClerg discloses the desirability of sending both "Not Completed" and "Completed" messages to notify the host of module-initialization status — a two-state signal that is "efficiently implemented with the open drain configuration as disclosed by Kim."
4. Design efficiency. Kim's open-drain sharing "simplif[ies] the design of the system and sav[es] pins on the various integrated circuits connected to the bus," and permits the memory controller to monitor the progress of multiple modules (including non-homogeneous DIMM mixes) on one line — the very multi-module wired-OR behavior the '837 specification describes at col. 10–11.

Netlist argued claim 5 was non-obvious because (in its view) Kim's error pin was for error reporting, not initialization status, and because combining the references required improper hindsight. The Board disagreed: the claim language does not require any particular function for the error-out pin, and repurposing an existing standard pin to carry a status signal during initialization — while preserving its error function in normal operation — is exactly the kind of simple repurposing of a known hardware resource that § 103 treats as obvious.

Claims 3 and 6 via Kim (independent of Lee)

The PTAB record additionally shows that LeClerg + Kim (with or without Lee) renders claims 3, 5, and 6 obvious: in LeClerg's system modified with Kim's open-drain output pin, an active (asserted) signal on the pin in response to an initialization command indicates the sequence has "Not Completed" (execution in progress — claim 3), and driving the transistor's gate high vs. low yields the first (low/impedance, executing) and second (released/high-impedance, completed) states — claim 6.

Claims 10 and 17 (method claims) — observation

Claims 10 and 17 recite the mirror-image methods (module-side driving of the output to first/second states; outputting a notification signal indicating completion), each with the same "triggers the memory controller to execute an interrupt routine" limitation. The IPR petition challenged only claims 1, 2, 3, 5, and 6, so the Board never formally ruled on claims 10 and 17. On the merits, however, the identical element mapping would apply: LeClerg discloses the module executing an initialization sequence and reporting completion/status to the memory controller, and Lee supplies the interrupt-triggering mechanism; dependent claims 11–13 and 18 add only the high-impedance state and the error-out pin, both taught by Kim. A POSITA applying the same motivation analysis would have had the same reason to find these method claims obvious.

Secondary considerations

The IPR record contains no persuasive evidence of secondary indicia of non-obviousness (long-felt need, commercial success, copying, unexpected results) sufficient to overcome the strong prima facie case. The '837 specification itself concedes the field's problems (blind waiting, inefficient polling) and characterizes "notifying" as a known alternative to polling — undermining any argument that the claimed concept was a paradigm shift rather than an obvious design choice.

Conclusion

The instituted claims of US 8,489,837 — claims 1, 2, 3, 5, and 6 — were held unpatentable under 35 U.S.C. § 103(a) in IPR2017-00548, and that decision was affirmed by the Federal Circuit:

• Claims 1–3 and 6: obvious over LeClerg (US 2005/0071580 A1) in view of Lee (US 2005/0193161 A1) — LeClerg teaches distributed module-local initialization with status messaging to the memory controller; Lee teaches the missing interrupt-routine-triggering mechanism.
• Claims 1–3, 5, and 6: obvious over LeClerg + Lee + Kim (US 8,359,521 B2) — Kim teaches the industry-standard open-drain error-out pin and the wired-OR sharing technique, which a POSITA would have been motivated to add to LeClerg's status-reporting scheme to efficiently signal Completed/Not-Completed status from one or more modules on a single line.

The Board's reasoning on motivation tracks the classic KSR analysis: the references are analogous art in the same field; each element was known; the combination uses known techniques for their known purposes with predictable results; and Netlist's contrary arguments (modes, notification "to the processor," error-pin repurposing) were rejected as inconsistent with the broadest reasonable claim construction and the references' actual disclosures. There is accordingly a strong, adjudicated § 103 case against the challenged claims, and the same reasoning would apply with equal force to the unchallenged method claims 10 and 17.

Confidence note: The substance above is drawn from the IPR2017-00548 record (Petition, Patent Owner Response, Petitioner's Reply, Final Written Decision) and the reference disclosures themselves, which I verified via live search. I did not independently re-derive every element mapping from the raw LeClerg/Lee/Kim PDFs, but the Board's final written decision — an authoritative adjudication on a complete record, affirmed on appeal — is the highest-confidence source available on this question.